1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Multi-class for logical operators.
18 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
19 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
20 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
21 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
23 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
24 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
25 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
29 // Multi-class for compare ops.
30 let isCompare = 1 in {
31 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
32 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
33 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
34 [(set (i1 PredRegs:$dst),
35 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
37 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
38 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
39 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
40 [(set (i1 PredRegs:$dst),
41 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
44 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
45 let CextOpcode = CextOp in {
46 let InputType = "reg" in
47 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
48 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
49 [(set (i1 PredRegs:$dst),
50 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
52 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
53 opExtentBits = 10, InputType = "imm" in
54 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
55 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
56 [(set (i1 PredRegs:$dst),
57 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
61 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
62 let CextOpcode = CextOp in {
63 let InputType = "reg" in
64 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
65 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
66 [(set (i1 PredRegs:$dst),
67 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
69 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
70 opExtentBits = 9, InputType = "imm" in
71 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
72 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
73 [(set (i1 PredRegs:$dst),
74 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
78 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
79 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
80 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
81 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
82 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
86 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
87 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
88 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
90 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
95 //===----------------------------------------------------------------------===//
96 // ALU32/ALU (Instructions with register-register form)
97 //===----------------------------------------------------------------------===//
98 multiclass ALU32_Pbase<string mnemonic, bit isNot,
101 let PNewValue = !if(isPredNew, "new", "") in
102 def NAME : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
104 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
105 ") $dst = ")#mnemonic#"($src2, $src3)",
109 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
110 let PredSense = !if(PredNot, "false", "true") in {
111 defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
113 defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
117 let InputType = "reg" in
118 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
119 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
120 let isPredicable = 1 in
121 def NAME : ALU32_rr<(outs IntRegs:$dst),
122 (ins IntRegs:$src1, IntRegs:$src2),
123 "$dst = "#mnemonic#"($src1, $src2)",
124 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
125 (i32 IntRegs:$src2)))]>;
127 let neverHasSideEffects = 1, isPredicated = 1 in {
128 defm Pt : ALU32_Pred<mnemonic, 0>;
129 defm NotPt : ALU32_Pred<mnemonic, 1>;
134 let isCommutable = 1 in {
135 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
136 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
137 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
138 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
141 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
143 //===----------------------------------------------------------------------===//
144 // ALU32/ALU (ADD with register-immediate form)
145 //===----------------------------------------------------------------------===//
146 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
147 let PNewValue = !if(isPredNew, "new", "") in
148 def NAME : ALU32_ri<(outs IntRegs:$dst),
149 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
150 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
151 ") $dst = ")#mnemonic#"($src2, #$src3)",
155 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
156 let PredSense = !if(PredNot, "false", "true") in {
157 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
159 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
163 let isExtendable = 1, InputType = "imm" in
164 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
165 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
166 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
168 def NAME : ALU32_ri<(outs IntRegs:$dst),
169 (ins IntRegs:$src1, s16Ext:$src2),
170 "$dst = "#mnemonic#"($src1, #$src2)",
171 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
172 (s16ExtPred:$src2)))]>;
174 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
175 neverHasSideEffects = 1, isPredicated = 1 in {
176 defm Pt : ALU32ri_Pred<mnemonic, 0>;
177 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
182 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
184 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
185 CextOpcode = "OR", InputType = "imm" in
186 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
187 (ins IntRegs:$src1, s10Ext:$src2),
188 "$dst = or($src1, #$src2)",
189 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
190 s10ExtPred:$src2))]>, ImmRegRel;
192 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
195 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
198 InputType = "imm", CextOpcode = "AND" in
199 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
200 (ins IntRegs:$src1, s10Ext:$src2),
201 "$dst = and($src1, #$src2)",
202 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
203 s10ExtPred:$src2))]>, ImmRegRel;
205 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
207 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
209 let neverHasSideEffects = 1 in
210 def NOP : ALU32_rr<(outs), (ins),
214 // Rd32=sub(#s10,Rs32)
215 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
216 CextOpcode = "SUB", InputType = "imm" in
217 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
218 (ins s10Ext:$src1, IntRegs:$src2),
219 "$dst = sub(#$src1, $src2)",
220 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
224 multiclass TFR_Pred<bit PredNot> {
225 let PredSense = !if(PredNot, "false", "true") in {
226 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
227 (ins PredRegs:$src1, IntRegs:$src2),
228 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
231 let PNewValue = "new" in
232 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
233 (ins PredRegs:$src1, IntRegs:$src2),
234 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
239 let InputType = "reg", neverHasSideEffects = 1 in
240 multiclass TFR_base<string CextOp> {
241 let CextOpcode = CextOp, BaseOpcode = CextOp in {
242 let isPredicable = 1 in
243 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
247 let isPredicated = 1 in {
248 defm Pt : TFR_Pred<0>;
249 defm NotPt : TFR_Pred<1>;
254 multiclass TFR64_Pred<bit PredNot> {
255 let PredSense = !if(PredNot, "false", "true") in {
256 def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst),
257 (ins PredRegs:$src1, DoubleRegs:$src2),
258 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
261 let PNewValue = "new" in
262 def _cdn#NAME : ALU32_rr<(outs DoubleRegs:$dst),
263 (ins PredRegs:$src1, DoubleRegs:$src2),
264 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
269 let InputType = "reg", neverHasSideEffects = 1 in
270 multiclass TFR64_base<string CextOp> {
271 let CextOpcode = CextOp, BaseOpcode = CextOp in {
272 let isPredicable = 1 in
273 def NAME : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
277 let isPredicated = 1 in {
278 defm Pt : TFR64_Pred<0>;
279 defm NotPt : TFR64_Pred<1>;
285 multiclass TFRI_Pred<bit PredNot> {
286 let PredSense = !if(PredNot, "false", "true") in {
287 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
288 (ins PredRegs:$src1, s12Ext:$src2),
289 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
293 let PNewValue = "new" in
294 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
295 (ins PredRegs:$src1, s12Ext:$src2),
296 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
301 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
302 multiclass TFRI_base<string CextOp> {
303 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
304 let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
305 isReMaterializable = 1 in
306 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
308 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
310 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
311 isPredicated = 1 in {
312 defm Pt : TFRI_Pred<0>;
313 defm NotPt : TFRI_Pred<1>;
318 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
319 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
320 defm TFR64 : TFR64_base<"TFR64">, ImmRegRel, PredNewRel;
322 // Transfer control register.
323 let neverHasSideEffects = 1 in
324 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
327 //===----------------------------------------------------------------------===//
329 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
338 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
339 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
341 def HexagonWrapperCombineII :
342 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
343 def HexagonWrapperCombineRR :
344 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
346 // Combines the two integer registers SRC1 and SRC2 into a double register.
347 let isPredicable = 1 in
348 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1,
350 "$dst = combine($src1, $src2)",
351 [(set (i64 DoubleRegs:$dst),
352 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
353 (i32 IntRegs:$src2))))]>;
355 // Rd=combine(Rt.[HL], Rs.[HL])
356 class COMBINE_halves<string A, string B>: ALU32_rr<(outs IntRegs:$dst),
359 "$dst = combine($src1."# A #", $src2."# B #")", []>;
361 let isPredicable = 1 in {
362 def COMBINE_hh : COMBINE_halves<"H", "H">;
363 def COMBINE_hl : COMBINE_halves<"H", "L">;
364 def COMBINE_lh : COMBINE_halves<"L", "H">;
365 def COMBINE_ll : COMBINE_halves<"L", "L">;
368 def : Pat<(i32 (trunc (i64 (srl (i64 DoubleRegs:$a), (i32 16))))),
369 (COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
370 (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;
372 // Combines the two immediates SRC1 and SRC2 into a double register.
373 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
374 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
375 "$dst = combine(#$src1, #$src2)",
376 [(set (i64 DoubleRegs:$dst),
377 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
379 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
380 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
383 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
386 "$dst = vmux($src1, $src2, $src3)",
389 let CextOpcode = "MUX", InputType = "reg" in
390 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
391 IntRegs:$src2, IntRegs:$src3),
392 "$dst = mux($src1, $src2, $src3)",
393 [(set (i32 IntRegs:$dst),
394 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
395 (i32 IntRegs:$src3))))]>, ImmRegRel;
397 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
398 CextOpcode = "MUX", InputType = "imm" in
399 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
401 "$dst = mux($src1, #$src2, $src3)",
402 [(set (i32 IntRegs:$dst),
403 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
404 (i32 IntRegs:$src3))))]>, ImmRegRel;
406 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
407 CextOpcode = "MUX", InputType = "imm" in
408 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
410 "$dst = mux($src1, $src2, #$src3)",
411 [(set (i32 IntRegs:$dst),
412 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
413 s8ExtPred:$src3)))]>, ImmRegRel;
415 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
416 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
418 "$dst = mux($src1, #$src2, #$src3)",
419 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
421 s8ImmPred:$src3)))]>;
424 let isPredicable = 1 in
425 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
426 "$dst = aslh($src1)",
427 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
429 let isPredicable = 1 in
430 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
431 "$dst = asrh($src1)",
432 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
435 let isPredicable = 1 in
436 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
437 "$dst = sxtb($src1)",
438 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
440 let isPredicable = 1 in
441 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
442 "$dst = sxth($src1)",
443 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
446 let isPredicable = 1, neverHasSideEffects = 1 in
447 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
448 "$dst = zxtb($src1)",
451 let isPredicable = 1, neverHasSideEffects = 1 in
452 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
453 "$dst = zxth($src1)",
455 //===----------------------------------------------------------------------===//
457 //===----------------------------------------------------------------------===//
460 //===----------------------------------------------------------------------===//
462 //===----------------------------------------------------------------------===//
464 // Conditional combine.
465 let neverHasSideEffects = 1, isPredicated = 1 in
466 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
468 "if ($src1) $dst = combine($src2, $src3)",
471 let neverHasSideEffects = 1, isPredicated = 1 in
472 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
473 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
474 "if (!$src1) $dst = combine($src2, $src3)",
477 let neverHasSideEffects = 1, isPredicated = 1 in
478 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
479 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
480 "if ($src1.new) $dst = combine($src2, $src3)",
483 let neverHasSideEffects = 1, isPredicated = 1 in
484 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
485 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
486 "if (!$src1.new) $dst = combine($src2, $src3)",
490 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
491 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
492 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
493 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
494 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
495 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
496 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
498 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
500 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
502 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
504 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
506 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
508 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
510 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
512 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
514 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
515 "$dst = tstbit($src1, $src2)",
516 [(set (i1 PredRegs:$dst),
517 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
519 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
520 "$dst = tstbit($src1, $src2)",
521 [(set (i1 PredRegs:$dst),
522 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
524 //===----------------------------------------------------------------------===//
526 //===----------------------------------------------------------------------===//
529 //===----------------------------------------------------------------------===//
531 //===----------------------------------------------------------------------===//
533 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
535 "$dst = add($src1, $src2)",
536 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
537 (i64 DoubleRegs:$src2)))]>;
542 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
543 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
544 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
546 // Logical operations.
547 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
549 "$dst = and($src1, $src2)",
550 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
551 (i64 DoubleRegs:$src2)))]>;
553 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
555 "$dst = or($src1, $src2)",
556 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
557 (i64 DoubleRegs:$src2)))]>;
559 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
561 "$dst = xor($src1, $src2)",
562 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
563 (i64 DoubleRegs:$src2)))]>;
566 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
567 "$dst = max($src2, $src1)",
568 [(set (i32 IntRegs:$dst),
569 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
570 (i32 IntRegs:$src1))),
571 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
573 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
574 "$dst = maxu($src2, $src1)",
575 [(set (i32 IntRegs:$dst),
576 (i32 (select (i1 (setult (i32 IntRegs:$src2),
577 (i32 IntRegs:$src1))),
578 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
580 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
582 "$dst = max($src2, $src1)",
583 [(set (i64 DoubleRegs:$dst),
584 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
585 (i64 DoubleRegs:$src1))),
586 (i64 DoubleRegs:$src1),
587 (i64 DoubleRegs:$src2))))]>;
589 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
591 "$dst = maxu($src2, $src1)",
592 [(set (i64 DoubleRegs:$dst),
593 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
594 (i64 DoubleRegs:$src1))),
595 (i64 DoubleRegs:$src1),
596 (i64 DoubleRegs:$src2))))]>;
599 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
600 "$dst = min($src2, $src1)",
601 [(set (i32 IntRegs:$dst),
602 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
603 (i32 IntRegs:$src1))),
604 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
606 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
607 "$dst = minu($src2, $src1)",
608 [(set (i32 IntRegs:$dst),
609 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
610 (i32 IntRegs:$src1))),
611 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
613 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
615 "$dst = min($src2, $src1)",
616 [(set (i64 DoubleRegs:$dst),
617 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
618 (i64 DoubleRegs:$src1))),
619 (i64 DoubleRegs:$src1),
620 (i64 DoubleRegs:$src2))))]>;
622 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
624 "$dst = minu($src2, $src1)",
625 [(set (i64 DoubleRegs:$dst),
626 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
627 (i64 DoubleRegs:$src1))),
628 (i64 DoubleRegs:$src1),
629 (i64 DoubleRegs:$src2))))]>;
632 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
634 "$dst = sub($src1, $src2)",
635 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
636 (i64 DoubleRegs:$src2)))]>;
638 // Subtract halfword.
640 //===----------------------------------------------------------------------===//
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
648 //===----------------------------------------------------------------------===//
650 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
663 // Logical reductions on predicates.
665 // Looping instructions.
667 // Pipelined looping instructions.
669 // Logical operations on predicates.
670 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
671 "$dst = and($src1, $src2)",
672 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
673 (i1 PredRegs:$src2)))]>;
675 let neverHasSideEffects = 1 in
676 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
678 "$dst = and($src1, !$src2)",
681 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
682 "$dst = any8($src1)",
685 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
686 "$dst = all8($src1)",
689 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
691 "$dst = vitpack($src1, $src2)",
694 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
697 "$dst = valignb($src1, $src2, $src3)",
700 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
703 "$dst = vspliceb($src1, $src2, $src3)",
706 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
707 "$dst = mask($src1)",
710 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
712 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
714 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
715 "$dst = or($src1, $src2)",
716 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
717 (i1 PredRegs:$src2)))]>;
719 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
720 "$dst = xor($src1, $src2)",
721 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
722 (i1 PredRegs:$src2)))]>;
725 // User control register transfer.
726 //===----------------------------------------------------------------------===//
728 //===----------------------------------------------------------------------===//
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
735 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
736 def JMP : JInst< (outs),
737 (ins brtarget:$offset),
743 let isBranch = 1, isTerminator=1, Defs = [PC],
744 isPredicated = 1 in {
745 def JMP_c : JInst< (outs),
746 (ins PredRegs:$src, brtarget:$offset),
747 "if ($src) jump $offset",
748 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
752 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
753 isPredicated = 1 in {
754 def JMP_cNot : JInst< (outs),
755 (ins PredRegs:$src, brtarget:$offset),
756 "if (!$src) jump $offset",
760 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
761 isPredicated = 1 in {
762 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
763 "if ($pred) jump $dst",
767 // Jump to address conditioned on new predicate.
769 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
770 isPredicated = 1 in {
771 def JMP_cdnPt : JInst< (outs),
772 (ins PredRegs:$src, brtarget:$offset),
773 "if ($src.new) jump:t $offset",
778 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
779 isPredicated = 1 in {
780 def JMP_cdnNotPt : JInst< (outs),
781 (ins PredRegs:$src, brtarget:$offset),
782 "if (!$src.new) jump:t $offset",
787 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
788 isPredicated = 1 in {
789 def JMP_cdnPnt : JInst< (outs),
790 (ins PredRegs:$src, brtarget:$offset),
791 "if ($src.new) jump:nt $offset",
796 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
797 isPredicated = 1 in {
798 def JMP_cdnNotPnt : JInst< (outs),
799 (ins PredRegs:$src, brtarget:$offset),
800 "if (!$src.new) jump:nt $offset",
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
807 //===----------------------------------------------------------------------===//
809 //===----------------------------------------------------------------------===//
810 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
811 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
813 // Jump to address from register.
814 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
815 Defs = [PC], Uses = [R31] in {
816 def JMPR: JRInst<(outs), (ins),
821 // Jump to address from register.
822 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
823 Defs = [PC], Uses = [R31] in {
824 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
825 "if ($src1) jumpr r31",
829 // Jump to address from register.
830 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
831 Defs = [PC], Uses = [R31] in {
832 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
833 "if (!$src1) jumpr r31",
837 //===----------------------------------------------------------------------===//
839 //===----------------------------------------------------------------------===//
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 // Load -- MEMri operand
846 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
847 bit isNot, bit isPredNew> {
848 let PNewValue = !if(isPredNew, "new", "") in
849 def NAME : LDInst2<(outs RC:$dst),
850 (ins PredRegs:$src1, MEMri:$addr),
851 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
852 ") ")#"$dst = "#mnemonic#"($addr)",
856 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
857 let PredSense = !if(PredNot, "false", "true") in {
858 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
860 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
864 let isExtendable = 1, neverHasSideEffects = 1 in
865 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
866 bits<5> ImmBits, bits<5> PredImmBits> {
868 let CextOpcode = CextOp, BaseOpcode = CextOp in {
869 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
871 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
872 "$dst = "#mnemonic#"($addr)",
875 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
876 isPredicated = 1 in {
877 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
878 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
883 let addrMode = BaseImmOffset, isMEMri = "true" in {
884 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
885 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
886 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
887 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
888 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
889 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
892 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
893 (LDrib ADDRriS11_0:$addr) >;
895 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
896 (LDriub ADDRriS11_0:$addr) >;
898 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
899 (LDrih ADDRriS11_1:$addr) >;
901 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
902 (LDriuh ADDRriS11_1:$addr) >;
904 def : Pat < (i32 (load ADDRriS11_2:$addr)),
905 (LDriw ADDRriS11_2:$addr) >;
907 def : Pat < (i64 (load ADDRriS11_3:$addr)),
908 (LDrid ADDRriS11_3:$addr) >;
911 // Load - Base with Immediate offset addressing mode
912 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
913 bit isNot, bit isPredNew> {
914 let PNewValue = !if(isPredNew, "new", "") in
915 def NAME : LDInst2<(outs RC:$dst),
916 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
917 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
918 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
922 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
924 let PredSense = !if(PredNot, "false", "true") in {
925 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
927 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
931 let isExtendable = 1, neverHasSideEffects = 1 in
932 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
933 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
934 bits<5> PredImmBits> {
936 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
937 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
938 isPredicable = 1, AddedComplexity = 20 in
939 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
940 "$dst = "#mnemonic#"($src1+#$offset)",
943 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
944 isPredicated = 1 in {
945 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
946 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
951 let addrMode = BaseImmOffset in {
952 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
954 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
956 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
958 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
960 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
962 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
966 let AddedComplexity = 20 in {
967 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
968 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
970 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
971 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
973 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
974 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
976 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
977 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
979 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
980 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
982 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
983 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
986 let neverHasSideEffects = 1 in
987 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
988 (ins globaladdress:$global, u16Imm:$offset),
989 "$dst = memd(#$global+$offset)",
993 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
994 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
995 (ins globaladdress:$global),
996 "$dst = memd(#$global)",
1000 //===----------------------------------------------------------------------===//
1001 // Post increment load
1002 // Make sure that in post increment load, the first operand is always the post
1003 // increment operand.
1004 //===----------------------------------------------------------------------===//
1006 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1007 bit isNot, bit isPredNew> {
1008 let PNewValue = !if(isPredNew, "new", "") in
1009 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1010 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1011 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1012 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1017 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1018 Operand ImmOp, bit PredNot> {
1019 let PredSense = !if(PredNot, "false", "true") in {
1020 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1022 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1023 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1027 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1030 let BaseOpcode = "POST_"#BaseOp in {
1031 let isPredicable = 1 in
1032 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1033 (ins IntRegs:$src1, ImmOp:$offset),
1034 "$dst = "#mnemonic#"($src1++#$offset)",
1038 let isPredicated = 1 in {
1039 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1040 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1045 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1046 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1048 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1050 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1052 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1054 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1056 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1060 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1061 (i32 (LDrib ADDRriS11_0:$addr)) >;
1063 // Load byte any-extend.
1064 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1065 (i32 (LDrib ADDRriS11_0:$addr)) >;
1067 // Indexed load byte any-extend.
1068 let AddedComplexity = 20 in
1069 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1070 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1072 let neverHasSideEffects = 1 in
1073 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
1074 (ins globaladdress:$global, u16Imm:$offset),
1075 "$dst = memb(#$global+$offset)",
1079 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1080 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1081 (ins globaladdress:$global),
1082 "$dst = memb(#$global)",
1086 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1087 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1088 (ins globaladdress:$global),
1089 "$dst = memub(#$global)",
1093 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1094 (i32 (LDrih ADDRriS11_1:$addr))>;
1096 let AddedComplexity = 20 in
1097 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1098 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1100 let neverHasSideEffects = 1 in
1101 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1102 (ins globaladdress:$global, u16Imm:$offset),
1103 "$dst = memh(#$global+$offset)",
1107 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1108 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1109 (ins globaladdress:$global),
1110 "$dst = memh(#$global)",
1114 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1115 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1116 (ins globaladdress:$global),
1117 "$dst = memuh(#$global)",
1121 let AddedComplexity = 10 in
1122 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1123 (i32 (LDriub ADDRriS11_0:$addr))>;
1125 let AddedComplexity = 20 in
1126 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1127 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1129 let neverHasSideEffects = 1 in
1130 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1131 (ins globaladdress:$global, u16Imm:$offset),
1132 "$dst = memub(#$global+$offset)",
1136 // Load unsigned halfword.
1137 let neverHasSideEffects = 1 in
1138 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1139 (ins globaladdress:$global, u16Imm:$offset),
1140 "$dst = memuh(#$global+$offset)",
1145 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1146 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1147 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1149 "Error; should not emit",
1153 let neverHasSideEffects = 1 in
1154 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1155 (ins globaladdress:$global, u16Imm:$offset),
1156 "$dst = memw(#$global+$offset)",
1160 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1161 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1162 (ins globaladdress:$global),
1163 "$dst = memw(#$global)",
1167 // Deallocate stack frame.
1168 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1169 def DEALLOCFRAME : LDInst2<(outs), (ins),
1174 // Load and unpack bytes to halfwords.
1175 //===----------------------------------------------------------------------===//
1177 //===----------------------------------------------------------------------===//
1179 //===----------------------------------------------------------------------===//
1181 //===----------------------------------------------------------------------===//
1182 //===----------------------------------------------------------------------===//
1184 //===----------------------------------------------------------------------===//
1186 //===----------------------------------------------------------------------===//
1188 //===----------------------------------------------------------------------===//
1189 //===----------------------------------------------------------------------===//
1191 //===----------------------------------------------------------------------===//
1193 //===----------------------------------------------------------------------===//
1195 //===----------------------------------------------------------------------===//
1196 // Multiply and use lower result.
1198 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1199 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1200 "$dst =+ mpyi($src1, #$src2)",
1201 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1202 u8ExtPred:$src2))]>;
1205 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1206 "$dst =- mpyi($src1, #$src2)",
1207 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1208 u8ImmPred:$src2)))]>;
1211 // s9 is NOT the same as m9 - but it works.. so far.
1212 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1213 // depending on the value of m9. See Arch Spec.
1214 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1215 CextOpcode = "MPYI", InputType = "imm" in
1216 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1217 "$dst = mpyi($src1, #$src2)",
1218 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1219 s9ExtPred:$src2))]>, ImmRegRel;
1222 let CextOpcode = "MPYI", InputType = "reg" in
1223 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1224 "$dst = mpyi($src1, $src2)",
1225 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1226 (i32 IntRegs:$src2)))]>, ImmRegRel;
1229 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1230 CextOpcode = "MPYI_acc", InputType = "imm" in
1231 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1232 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1233 "$dst += mpyi($src2, #$src3)",
1234 [(set (i32 IntRegs:$dst),
1235 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1236 (i32 IntRegs:$src1)))],
1237 "$src1 = $dst">, ImmRegRel;
1240 let CextOpcode = "MPYI_acc", InputType = "reg" in
1241 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1242 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1243 "$dst += mpyi($src2, $src3)",
1244 [(set (i32 IntRegs:$dst),
1245 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1246 (i32 IntRegs:$src1)))],
1247 "$src1 = $dst">, ImmRegRel;
1250 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1251 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1252 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1253 "$dst -= mpyi($src2, #$src3)",
1254 [(set (i32 IntRegs:$dst),
1255 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1256 u8ExtPred:$src3)))],
1259 // Multiply and use upper result.
1260 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1261 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1263 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1264 "$dst = mpy($src1, $src2)",
1265 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1266 (i32 IntRegs:$src2)))]>;
1268 // Rd=mpy(Rs,Rt):rnd
1270 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1271 "$dst = mpyu($src1, $src2)",
1272 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1273 (i32 IntRegs:$src2)))]>;
1275 // Multiply and use full result.
1277 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1278 "$dst = mpyu($src1, $src2)",
1279 [(set (i64 DoubleRegs:$dst),
1280 (mul (i64 (anyext (i32 IntRegs:$src1))),
1281 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1284 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1285 "$dst = mpy($src1, $src2)",
1286 [(set (i64 DoubleRegs:$dst),
1287 (mul (i64 (sext (i32 IntRegs:$src1))),
1288 (i64 (sext (i32 IntRegs:$src2)))))]>;
1290 // Multiply and accumulate, use full result.
1291 // Rxx[+-]=mpy(Rs,Rt)
1293 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1294 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1295 "$dst += mpy($src2, $src3)",
1296 [(set (i64 DoubleRegs:$dst),
1297 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1298 (i64 (sext (i32 IntRegs:$src3)))),
1299 (i64 DoubleRegs:$src1)))],
1303 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1304 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1305 "$dst -= mpy($src2, $src3)",
1306 [(set (i64 DoubleRegs:$dst),
1307 (sub (i64 DoubleRegs:$src1),
1308 (mul (i64 (sext (i32 IntRegs:$src2))),
1309 (i64 (sext (i32 IntRegs:$src3))))))],
1312 // Rxx[+-]=mpyu(Rs,Rt)
1314 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1315 IntRegs:$src2, IntRegs:$src3),
1316 "$dst += mpyu($src2, $src3)",
1317 [(set (i64 DoubleRegs:$dst),
1318 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1319 (i64 (anyext (i32 IntRegs:$src3)))),
1320 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1323 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1324 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1325 "$dst -= mpyu($src2, $src3)",
1326 [(set (i64 DoubleRegs:$dst),
1327 (sub (i64 DoubleRegs:$src1),
1328 (mul (i64 (anyext (i32 IntRegs:$src2))),
1329 (i64 (anyext (i32 IntRegs:$src3))))))],
1333 let InputType = "reg", CextOpcode = "ADD_acc" in
1334 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1335 IntRegs:$src2, IntRegs:$src3),
1336 "$dst += add($src2, $src3)",
1337 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1338 (i32 IntRegs:$src3)),
1339 (i32 IntRegs:$src1)))],
1340 "$src1 = $dst">, ImmRegRel;
1342 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1343 InputType = "imm", CextOpcode = "ADD_acc" in
1344 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1345 IntRegs:$src2, s8Ext:$src3),
1346 "$dst += add($src2, #$src3)",
1347 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1348 s8_16ExtPred:$src3),
1349 (i32 IntRegs:$src1)))],
1350 "$src1 = $dst">, ImmRegRel;
1352 let CextOpcode = "SUB_acc", InputType = "reg" in
1353 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1354 IntRegs:$src2, IntRegs:$src3),
1355 "$dst -= add($src2, $src3)",
1356 [(set (i32 IntRegs:$dst),
1357 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1358 (i32 IntRegs:$src3))))],
1359 "$src1 = $dst">, ImmRegRel;
1361 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1362 CextOpcode = "SUB_acc", InputType = "imm" in
1363 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1364 IntRegs:$src2, s8Ext:$src3),
1365 "$dst -= add($src2, #$src3)",
1366 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1367 (add (i32 IntRegs:$src2),
1368 s8_16ExtPred:$src3)))],
1369 "$src1 = $dst">, ImmRegRel;
1371 //===----------------------------------------------------------------------===//
1373 //===----------------------------------------------------------------------===//
1375 //===----------------------------------------------------------------------===//
1377 //===----------------------------------------------------------------------===//
1378 //===----------------------------------------------------------------------===//
1380 //===----------------------------------------------------------------------===//
1382 //===----------------------------------------------------------------------===//
1384 //===----------------------------------------------------------------------===//
1385 //===----------------------------------------------------------------------===//
1387 //===----------------------------------------------------------------------===//
1389 //===----------------------------------------------------------------------===//
1391 //===----------------------------------------------------------------------===//
1392 //===----------------------------------------------------------------------===//
1394 //===----------------------------------------------------------------------===//
1396 //===----------------------------------------------------------------------===//
1398 //===----------------------------------------------------------------------===//
1400 /// Assumptions::: ****** DO NOT IGNORE ********
1401 /// 1. Make sure that in post increment store, the zero'th operand is always the
1402 /// post increment operand.
1403 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1406 // Store doubleword.
1408 let neverHasSideEffects = 1 in
1409 def STrid_GP : STInst2<(outs),
1410 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1411 "memd(#$global+$offset) = $src",
1415 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1416 def STd_GP : STInst2<(outs),
1417 (ins globaladdress:$global, DoubleRegs:$src),
1418 "memd(#$global) = $src",
1422 //===----------------------------------------------------------------------===//
1423 // Post increment store
1424 //===----------------------------------------------------------------------===//
1426 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1427 bit isNot, bit isPredNew> {
1428 let PNewValue = !if(isPredNew, "new", "") in
1429 def NAME : STInst2PI<(outs IntRegs:$dst),
1430 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1431 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1432 ") ")#mnemonic#"($src2++#$offset) = $src3",
1437 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1438 Operand ImmOp, bit PredNot> {
1439 let PredSense = !if(PredNot, "false", "true") in {
1440 defm _c#NAME# : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1442 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1443 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1447 let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1448 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1451 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1452 let isPredicable = 1 in
1453 def NAME : STInst2PI<(outs IntRegs:$dst),
1454 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1455 #mnemonic#"($src1++#$offset) = $src2",
1459 let isPredicated = 1 in {
1460 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1461 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1466 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1467 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1468 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1470 let isNVStorable = 0 in
1471 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1473 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1474 s4_3ImmPred:$offset),
1475 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1477 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1478 s4_3ImmPred:$offset),
1479 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1481 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1482 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1484 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1485 s4_3ImmPred:$offset),
1486 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1488 //===----------------------------------------------------------------------===//
1489 // multiclass for the store instructions with MEMri operand.
1490 //===----------------------------------------------------------------------===//
1491 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1493 let PNewValue = !if(isPredNew, "new", "") in
1494 def NAME : STInst2<(outs),
1495 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1496 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1497 ") ")#mnemonic#"($addr) = $src2",
1501 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1502 let PredSense = !if(PredNot, "false", "true") in {
1503 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1506 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1507 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1511 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1512 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1513 bits<5> ImmBits, bits<5> PredImmBits> {
1515 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1516 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1518 def NAME : STInst2<(outs),
1519 (ins MEMri:$addr, RC:$src),
1520 mnemonic#"($addr) = $src",
1523 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1524 isPredicated = 1 in {
1525 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1526 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1531 let addrMode = BaseImmOffset, isMEMri = "true" in {
1532 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1533 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1534 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1536 let isNVStorable = 0 in
1537 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1540 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1541 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1543 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1544 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1546 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1547 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1549 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1550 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1553 //===----------------------------------------------------------------------===//
1554 // multiclass for the store instructions with base+immediate offset
1556 //===----------------------------------------------------------------------===//
1557 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1558 bit isNot, bit isPredNew> {
1559 let PNewValue = !if(isPredNew, "new", "") in
1560 def NAME : STInst2<(outs),
1561 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1562 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1563 ") ")#mnemonic#"($src2+#$src3) = $src4",
1567 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1569 let PredSense = !if(PredNot, "false", "true"), isPredicated = 1 in {
1570 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1573 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1574 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1578 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1579 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1580 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1581 bits<5> PredImmBits> {
1583 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1584 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1586 def NAME : STInst2<(outs),
1587 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1588 mnemonic#"($src1+#$src2) = $src3",
1591 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1592 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1593 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1598 let addrMode = BaseImmOffset, InputType = "reg" in {
1599 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1600 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1601 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1602 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1603 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1604 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1605 let isNVStorable = 0 in
1606 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1607 u6_3Ext, 14, 9>, AddrModeRel;
1610 let AddedComplexity = 10 in {
1611 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1612 s11_0ExtPred:$offset)),
1613 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1614 (i32 IntRegs:$src1))>;
1616 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1617 s11_1ExtPred:$offset)),
1618 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1619 (i32 IntRegs:$src1))>;
1621 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1622 s11_2ExtPred:$offset)),
1623 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1624 (i32 IntRegs:$src1))>;
1626 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1627 s11_3ExtPred:$offset)),
1628 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1629 (i64 DoubleRegs:$src1))>;
1632 // memb(gp+#u16:0)=Rt
1633 let neverHasSideEffects = 1 in
1634 def STrib_GP : STInst2<(outs),
1635 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1636 "memb(#$global+$offset) = $src",
1641 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1642 def STb_GP : STInst2<(outs),
1643 (ins globaladdress:$global, IntRegs:$src),
1644 "memb(#$global) = $src",
1648 let neverHasSideEffects = 1 in
1649 def STrih_GP : STInst2<(outs),
1650 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1651 "memh(#$global+$offset) = $src",
1655 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1656 def STh_GP : STInst2<(outs),
1657 (ins globaladdress:$global, IntRegs:$src),
1658 "memh(#$global) = $src",
1662 // memh(Rx++#s4:1)=Rt.H
1666 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1667 def STriw_pred : STInst2<(outs),
1668 (ins MEMri:$addr, PredRegs:$src1),
1669 "Error; should not emit",
1672 let neverHasSideEffects = 1 in
1673 def STriw_GP : STInst2<(outs),
1674 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1675 "memw(#$global+$offset) = $src",
1679 let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
1680 def STw_GP : STInst2<(outs),
1681 (ins globaladdress:$global, IntRegs:$src),
1682 "memw(#$global) = $src",
1686 // Allocate stack frame.
1687 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1688 def ALLOCFRAME : STInst2<(outs),
1690 "allocframe(#$amt)",
1693 //===----------------------------------------------------------------------===//
1695 //===----------------------------------------------------------------------===//
1697 //===----------------------------------------------------------------------===//
1699 //===----------------------------------------------------------------------===//
1701 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1702 "$dst = not($src1)",
1703 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1706 // Sign extend word to doubleword.
1707 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1708 "$dst = sxtw($src1)",
1709 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1710 //===----------------------------------------------------------------------===//
1712 //===----------------------------------------------------------------------===//
1714 //===----------------------------------------------------------------------===//
1716 //===----------------------------------------------------------------------===//
1718 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1719 "$dst = clrbit($src1, #$src2)",
1720 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1722 (shl 1, u5ImmPred:$src2))))]>;
1724 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1725 "$dst = clrbit($src1, #$src2)",
1728 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1729 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1730 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1733 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1734 "$dst = setbit($src1, #$src2)",
1735 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1736 (shl 1, u5ImmPred:$src2)))]>;
1738 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1739 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1740 "$dst = setbit($src1, #$src2)",
1743 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1744 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1747 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1748 "$dst = setbit($src1, #$src2)",
1749 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1750 (shl 1, u5ImmPred:$src2)))]>;
1752 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1753 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1754 "$dst = togglebit($src1, #$src2)",
1757 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1758 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1760 // Predicate transfer.
1761 let neverHasSideEffects = 1 in
1762 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1763 "$dst = $src1 /* Should almost never emit this. */",
1766 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1767 "$dst = $src1 /* Should almost never emit this. */",
1768 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1769 //===----------------------------------------------------------------------===//
1771 //===----------------------------------------------------------------------===//
1773 //===----------------------------------------------------------------------===//
1775 //===----------------------------------------------------------------------===//
1776 // Shift by immediate.
1777 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1778 "$dst = asr($src1, #$src2)",
1779 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1780 u5ImmPred:$src2))]>;
1782 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1783 "$dst = asr($src1, #$src2)",
1784 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1785 u6ImmPred:$src2))]>;
1787 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1788 "$dst = asl($src1, #$src2)",
1789 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1790 u5ImmPred:$src2))]>;
1792 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1793 "$dst = asl($src1, #$src2)",
1794 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1795 u6ImmPred:$src2))]>;
1797 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1798 "$dst = lsr($src1, #$src2)",
1799 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1800 u5ImmPred:$src2))]>;
1802 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1803 "$dst = lsr($src1, #$src2)",
1804 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1805 u6ImmPred:$src2))]>;
1807 // Shift by immediate and add.
1808 let AddedComplexity = 100 in
1809 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1811 "$dst = addasl($src1, $src2, #$src3)",
1812 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1813 (shl (i32 IntRegs:$src2),
1814 u3ImmPred:$src3)))]>;
1816 // Shift by register.
1817 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1818 "$dst = asl($src1, $src2)",
1819 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1820 (i32 IntRegs:$src2)))]>;
1822 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1823 "$dst = asr($src1, $src2)",
1824 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1825 (i32 IntRegs:$src2)))]>;
1827 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1828 "$dst = lsl($src1, $src2)",
1829 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1830 (i32 IntRegs:$src2)))]>;
1832 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1833 "$dst = lsr($src1, $src2)",
1834 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1835 (i32 IntRegs:$src2)))]>;
1837 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1838 "$dst = asl($src1, $src2)",
1839 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1840 (i32 IntRegs:$src2)))]>;
1842 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1843 "$dst = lsl($src1, $src2)",
1844 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1845 (i32 IntRegs:$src2)))]>;
1847 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1849 "$dst = asr($src1, $src2)",
1850 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1851 (i32 IntRegs:$src2)))]>;
1853 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1855 "$dst = lsr($src1, $src2)",
1856 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1857 (i32 IntRegs:$src2)))]>;
1859 //===----------------------------------------------------------------------===//
1861 //===----------------------------------------------------------------------===//
1863 //===----------------------------------------------------------------------===//
1865 //===----------------------------------------------------------------------===//
1866 //===----------------------------------------------------------------------===//
1868 //===----------------------------------------------------------------------===//
1870 //===----------------------------------------------------------------------===//
1872 //===----------------------------------------------------------------------===//
1873 //===----------------------------------------------------------------------===//
1875 //===----------------------------------------------------------------------===//
1877 //===----------------------------------------------------------------------===//
1879 //===----------------------------------------------------------------------===//
1881 //===----------------------------------------------------------------------===//
1883 //===----------------------------------------------------------------------===//
1884 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1885 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1888 let hasSideEffects = 1, isSolo = 1 in
1889 def BARRIER : SYSInst<(outs), (ins),
1891 [(HexagonBARRIER)]>;
1893 //===----------------------------------------------------------------------===//
1895 //===----------------------------------------------------------------------===//
1897 // TFRI64 - assembly mapped.
1898 let isReMaterializable = 1 in
1899 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1901 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1903 // Pseudo instruction to encode a set of conditional transfers.
1904 // This instruction is used instead of a mux and trades-off codesize
1905 // for performance. We conduct this transformation optimistically in
1906 // the hope that these instructions get promoted to dot-new transfers.
1907 let AddedComplexity = 100, isPredicated = 1 in
1908 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1911 "Error; should not emit",
1912 [(set (i32 IntRegs:$dst),
1913 (i32 (select (i1 PredRegs:$src1),
1914 (i32 IntRegs:$src2),
1915 (i32 IntRegs:$src3))))]>;
1916 let AddedComplexity = 100, isPredicated = 1 in
1917 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1918 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1919 "Error; should not emit",
1920 [(set (i32 IntRegs:$dst),
1921 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1922 s12ImmPred:$src3)))]>;
1924 let AddedComplexity = 100, isPredicated = 1 in
1925 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1926 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1927 "Error; should not emit",
1928 [(set (i32 IntRegs:$dst),
1929 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1930 (i32 IntRegs:$src3))))]>;
1932 let AddedComplexity = 100, isPredicated = 1 in
1933 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1934 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1935 "Error; should not emit",
1936 [(set (i32 IntRegs:$dst),
1937 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1938 s12ImmPred:$src3)))]>;
1940 // Generate frameindex addresses.
1941 let isReMaterializable = 1 in
1942 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1943 "$dst = add($src1)",
1944 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1949 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1950 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1951 "loop0($offset, #$src2)",
1955 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1956 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1957 "loop0($offset, $src2)",
1961 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1962 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1963 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
1968 // Support for generating global address.
1969 // Taken from X86InstrInfo.td.
1970 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1974 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1975 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
1977 // HI/LO Instructions
1978 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1979 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1980 "$dst.l = #LO($global)",
1983 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1984 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1985 "$dst.h = #HI($global)",
1988 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1989 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1990 "$dst.l = #LO($imm_value)",
1994 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1995 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1996 "$dst.h = #HI($imm_value)",
1999 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2000 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2001 "$dst.l = #LO($jt)",
2004 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2005 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2006 "$dst.h = #HI($jt)",
2010 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2011 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2012 "$dst.l = #LO($label)",
2015 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2016 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2017 "$dst.h = #HI($label)",
2020 // This pattern is incorrect. When we add small data, we should change
2021 // this pattern to use memw(#foo).
2022 // This is for sdata.
2023 let isMoveImm = 1 in
2024 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2025 "$dst = CONST32(#$global)",
2026 [(set (i32 IntRegs:$dst),
2027 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2029 // This is for non-sdata.
2030 let isReMaterializable = 1, isMoveImm = 1 in
2031 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2032 "$dst = CONST32(#$global)",
2033 [(set (i32 IntRegs:$dst),
2034 (HexagonCONST32 tglobaladdr:$global))]>;
2036 let isReMaterializable = 1, isMoveImm = 1 in
2037 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2038 "$dst = CONST32(#$jt)",
2039 [(set (i32 IntRegs:$dst),
2040 (HexagonCONST32 tjumptable:$jt))]>;
2042 let isReMaterializable = 1, isMoveImm = 1 in
2043 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2044 "$dst = CONST32(#$global)",
2045 [(set (i32 IntRegs:$dst),
2046 (HexagonCONST32_GP tglobaladdr:$global))]>;
2048 let isReMaterializable = 1, isMoveImm = 1 in
2049 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2050 "$dst = CONST32(#$global)",
2051 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2053 let isReMaterializable = 1, isMoveImm = 1 in
2054 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2055 "$dst = CONST32($label)",
2056 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2058 let isReMaterializable = 1, isMoveImm = 1 in
2059 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2060 "$dst = CONST64(#$global)",
2061 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2063 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2064 "$dst = xor($dst, $dst)",
2065 [(set (i1 PredRegs:$dst), 0)]>;
2067 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2068 "$dst = mpy($src1, $src2)",
2069 [(set (i32 IntRegs:$dst),
2070 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2071 (i64 (sext (i32 IntRegs:$src2))))),
2074 // Pseudo instructions.
2075 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2077 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2078 SDTCisVT<1, i32> ]>;
2080 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2081 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2083 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2084 [SDNPHasChain, SDNPOutGlue]>;
2086 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2088 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2089 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2091 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2092 // Optional Flag and Variable Arguments.
2093 // Its 1 Operand has pointer type.
2094 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2095 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2097 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2098 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2099 "Should never be emitted",
2100 [(callseq_start timm:$amt)]>;
2103 let Defs = [R29, R30, R31], Uses = [R29] in {
2104 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2105 "Should never be emitted",
2106 [(callseq_end timm:$amt1, timm:$amt2)]>;
2109 let isCall = 1, neverHasSideEffects = 1,
2110 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2111 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2112 def CALL : JInst<(outs), (ins calltarget:$dst),
2116 // Call subroutine from register.
2117 let isCall = 1, neverHasSideEffects = 1,
2118 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2119 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2120 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2126 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2127 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2128 "jump $dst // TAILCALL", []>;
2130 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2131 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2132 "jump $dst // TAILCALL", []>;
2135 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2136 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2137 "jumpr $dst // TAILCALL", []>;
2139 // Map call instruction.
2140 def : Pat<(call (i32 IntRegs:$dst)),
2141 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2142 def : Pat<(call tglobaladdr:$dst),
2143 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2144 def : Pat<(call texternalsym:$dst),
2145 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2147 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2148 (TCRETURNtg tglobaladdr:$dst)>;
2149 def : Pat<(HexagonTCRet texternalsym:$dst),
2150 (TCRETURNtext texternalsym:$dst)>;
2151 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2152 (TCRETURNR (i32 IntRegs:$dst))>;
2154 // Atomic load and store support
2155 // 8 bit atomic load
2156 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2157 (i32 (LDub_GP tglobaladdr:$global))>,
2160 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2161 u16ImmPred:$offset)),
2162 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2165 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2166 (i32 (LDriub ADDRriS11_0:$src1))>;
2168 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2169 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2173 // 16 bit atomic load
2174 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2175 (i32 (LDuh_GP tglobaladdr:$global))>,
2178 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2179 u16ImmPred:$offset)),
2180 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2183 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2184 (i32 (LDriuh ADDRriS11_1:$src1))>;
2186 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2187 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2191 // 32 bit atomic load
2192 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2193 (i32 (LDw_GP tglobaladdr:$global))>,
2196 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2197 u16ImmPred:$offset)),
2198 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2201 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2202 (i32 (LDriw ADDRriS11_2:$src1))>;
2204 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2205 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2208 // 64 bit atomic load
2209 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2210 (i64 (LDd_GP tglobaladdr:$global))>,
2213 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2214 u16ImmPred:$offset)),
2215 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2218 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2219 (i64 (LDrid ADDRriS11_3:$src1))>;
2221 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2222 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2225 // 64 bit atomic store
2226 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2227 (i64 DoubleRegs:$src1)),
2228 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2231 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2232 u16ImmPred:$offset),
2233 (i64 DoubleRegs:$src1)),
2234 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2235 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2237 // 8 bit atomic store
2238 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2239 (i32 IntRegs:$src1)),
2240 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2243 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2244 u16ImmPred:$offset),
2245 (i32 IntRegs:$src1)),
2246 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2247 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2249 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2250 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2252 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2253 (i32 IntRegs:$src1)),
2254 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2255 (i32 IntRegs:$src1))>;
2258 // 16 bit atomic store
2259 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2260 (i32 IntRegs:$src1)),
2261 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2264 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2265 u16ImmPred:$offset),
2266 (i32 IntRegs:$src1)),
2267 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2268 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2270 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2271 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2273 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2274 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2275 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2276 (i32 IntRegs:$src1))>;
2279 // 32 bit atomic store
2280 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2281 (i32 IntRegs:$src1)),
2282 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2285 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2286 u16ImmPred:$offset),
2287 (i32 IntRegs:$src1)),
2288 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2289 (i32 IntRegs:$src1))>,
2292 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2293 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2295 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2296 (i32 IntRegs:$src1)),
2297 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2298 (i32 IntRegs:$src1))>;
2303 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2304 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2306 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2307 (i64 DoubleRegs:$src1)),
2308 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2309 (i64 DoubleRegs:$src1))>;
2311 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2312 def : Pat <(and (i32 IntRegs:$src1), 65535),
2313 (ZXTH (i32 IntRegs:$src1))>;
2315 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2316 def : Pat <(and (i32 IntRegs:$src1), 255),
2317 (ZXTB (i32 IntRegs:$src1))>;
2319 // Map Add(p1, true) to p1 = not(p1).
2320 // Add(p1, false) should never be produced,
2321 // if it does, it got to be mapped to NOOP.
2322 def : Pat <(add (i1 PredRegs:$src1), -1),
2323 (NOT_p (i1 PredRegs:$src1))>;
2325 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2326 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2327 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2328 (i32 IntRegs:$src3),
2329 (i32 IntRegs:$src4)),
2330 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2331 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2332 Requires<[HasV2TOnly]>;
2334 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2335 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2336 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2339 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2340 // => r0 = TFR_condset_ri(p0, r1, #i)
2341 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2342 (i32 IntRegs:$src3)),
2343 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2344 s12ImmPred:$src2))>;
2346 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2347 // => r0 = TFR_condset_ir(p0, #i, r1)
2348 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2349 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2350 (i32 IntRegs:$src2)))>;
2352 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2353 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2354 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2356 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2357 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2358 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2360 // Map from store(globaladdress + x) -> memd(#foo + x).
2361 let AddedComplexity = 100 in
2362 def : Pat <(store (i64 DoubleRegs:$src1),
2363 (add (HexagonCONST32_GP tglobaladdr:$global),
2364 u16ImmPred:$offset)),
2365 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2366 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2368 // Map from store(globaladdress) -> memd(#foo).
2369 let AddedComplexity = 100 in
2370 def : Pat <(store (i64 DoubleRegs:$src1),
2371 (HexagonCONST32_GP tglobaladdr:$global)),
2372 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2375 // Map from store(globaladdress + x) -> memw(#foo + x).
2376 let AddedComplexity = 100 in
2377 def : Pat <(store (i32 IntRegs:$src1),
2378 (add (HexagonCONST32_GP tglobaladdr:$global),
2379 u16ImmPred:$offset)),
2380 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2383 // Map from store(globaladdress) -> memw(#foo + 0).
2384 let AddedComplexity = 100 in
2385 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2386 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2388 // Map from store(globaladdress) -> memw(#foo).
2389 let AddedComplexity = 100 in
2390 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2391 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2394 // Map from store(globaladdress + x) -> memh(#foo + x).
2395 let AddedComplexity = 100 in
2396 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2397 (add (HexagonCONST32_GP tglobaladdr:$global),
2398 u16ImmPred:$offset)),
2399 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2402 // Map from store(globaladdress) -> memh(#foo).
2403 let AddedComplexity = 100 in
2404 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2405 (HexagonCONST32_GP tglobaladdr:$global)),
2406 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2409 // Map from store(globaladdress + x) -> memb(#foo + x).
2410 let AddedComplexity = 100 in
2411 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2412 (add (HexagonCONST32_GP tglobaladdr:$global),
2413 u16ImmPred:$offset)),
2414 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2417 // Map from store(globaladdress) -> memb(#foo).
2418 let AddedComplexity = 100 in
2419 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2420 (HexagonCONST32_GP tglobaladdr:$global)),
2421 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2424 // Map from load(globaladdress + x) -> memw(#foo + x).
2425 let AddedComplexity = 100 in
2426 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2427 u16ImmPred:$offset))),
2428 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2431 // Map from load(globaladdress) -> memw(#foo).
2432 let AddedComplexity = 100 in
2433 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2434 (i32 (LDw_GP tglobaladdr:$global))>,
2437 // Map from load(globaladdress + x) -> memd(#foo + x).
2438 let AddedComplexity = 100 in
2439 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2440 u16ImmPred:$offset))),
2441 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2444 // Map from load(globaladdress) -> memw(#foo + 0).
2445 let AddedComplexity = 100 in
2446 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2447 (i64 (LDd_GP tglobaladdr:$global))>,
2450 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2451 let AddedComplexity = 100 in
2452 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2453 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2456 // Map from load(globaladdress + x) -> memh(#foo + x).
2457 let AddedComplexity = 100 in
2458 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2459 u16ImmPred:$offset))),
2460 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2463 // Map from load(globaladdress + x) -> memh(#foo + x).
2464 let AddedComplexity = 100 in
2465 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2466 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2469 // Map from load(globaladdress + x) -> memuh(#foo + x).
2470 let AddedComplexity = 100 in
2471 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2472 u16ImmPred:$offset))),
2473 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2476 // Map from load(globaladdress) -> memuh(#foo).
2477 let AddedComplexity = 100 in
2478 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2479 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2482 // Map from load(globaladdress) -> memh(#foo).
2483 let AddedComplexity = 100 in
2484 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2485 (i32 (LDh_GP tglobaladdr:$global))>,
2488 // Map from load(globaladdress) -> memuh(#foo).
2489 let AddedComplexity = 100 in
2490 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2491 (i32 (LDuh_GP tglobaladdr:$global))>,
2494 // Map from load(globaladdress + x) -> memb(#foo + x).
2495 let AddedComplexity = 100 in
2496 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2497 u16ImmPred:$offset))),
2498 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2501 // Map from load(globaladdress + x) -> memb(#foo + x).
2502 let AddedComplexity = 100 in
2503 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2504 u16ImmPred:$offset))),
2505 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2508 // Map from load(globaladdress + x) -> memub(#foo + x).
2509 let AddedComplexity = 100 in
2510 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2511 u16ImmPred:$offset))),
2512 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2515 // Map from load(globaladdress) -> memb(#foo).
2516 let AddedComplexity = 100 in
2517 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2518 (i32 (LDb_GP tglobaladdr:$global))>,
2521 // Map from load(globaladdress) -> memb(#foo).
2522 let AddedComplexity = 100 in
2523 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2524 (i32 (LDb_GP tglobaladdr:$global))>,
2527 // Map from load(globaladdress) -> memub(#foo).
2528 let AddedComplexity = 100 in
2529 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2530 (i32 (LDub_GP tglobaladdr:$global))>,
2533 // When the Interprocedural Global Variable optimizer realizes that a
2534 // certain global variable takes only two constant values, it shrinks the
2535 // global to a boolean. Catch those loads here in the following 3 patterns.
2536 let AddedComplexity = 100 in
2537 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2538 (i32 (LDb_GP tglobaladdr:$global))>,
2541 let AddedComplexity = 100 in
2542 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2543 (i32 (LDb_GP tglobaladdr:$global))>,
2546 let AddedComplexity = 100 in
2547 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2548 (i32 (LDub_GP tglobaladdr:$global))>,
2551 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2552 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2553 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2555 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2556 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2557 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2559 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2560 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2561 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2562 subreg_loreg))))))>;
2564 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2565 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2566 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2567 subreg_loreg))))))>;
2569 // We want to prevent emitting pnot's as much as possible.
2570 // Map brcond with an unsupported setcc to a JMP_cNot.
2571 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2573 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2576 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2578 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2580 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2581 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2583 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2584 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2586 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2588 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2590 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2592 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2594 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2596 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2599 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2601 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2604 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2606 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2609 // Map from a 64-bit select to an emulated 64-bit mux.
2610 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2611 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2612 (i64 DoubleRegs:$src3)),
2613 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2614 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2616 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2618 (i32 (MUX_rr (i1 PredRegs:$src1),
2619 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2621 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2622 subreg_loreg))))))>;
2624 // Map from a 1-bit select to logical ops.
2625 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2626 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2627 (i1 PredRegs:$src3)),
2628 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2629 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2631 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2632 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2633 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2635 // Map for truncating from 64 immediates to 32 bit immediates.
2636 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2637 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2639 // Map for truncating from i64 immediates to i1 bit immediates.
2640 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2641 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2644 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2645 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2646 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2649 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2650 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2651 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2653 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2654 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2655 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2658 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2659 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2660 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2663 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2664 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2665 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2667 let AddedComplexity = 100 in
2668 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2670 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2671 (STb_GP tglobaladdr:$global, (TFRI 1))>,
2674 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2675 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2676 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2678 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2679 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2680 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2682 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2683 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2684 // Better way to do this?
2685 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2686 (i64 (SXTW (i32 IntRegs:$src1)))>;
2688 // Map cmple -> cmpgt.
2689 // rs <= rt -> !(rs > rt).
2690 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2691 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2693 // rs <= rt -> !(rs > rt).
2694 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2695 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2697 // Rss <= Rtt -> !(Rss > Rtt).
2698 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2699 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2701 // Map cmpne -> cmpeq.
2702 // Hexagon_TODO: We should improve on this.
2703 // rs != rt -> !(rs == rt).
2704 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2705 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
2707 // Map cmpne(Rs) -> !cmpeqe(Rs).
2708 // rs != rt -> !(rs == rt).
2709 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2710 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2712 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2713 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2714 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2716 // Map cmpne(Rss) -> !cmpew(Rss).
2717 // rs != rt -> !(rs == rt).
2718 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2719 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2720 (i64 DoubleRegs:$src2)))))>;
2722 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2723 // rs >= rt -> !(rt > rs).
2724 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2725 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2727 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
2728 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
2730 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2731 // rss >= rtt -> !(rtt > rss).
2732 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2733 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2734 (i64 DoubleRegs:$src1)))))>;
2736 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2737 // rs < rt -> !(rs >= rt).
2738 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2739 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
2741 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2742 // rs < rt -> rt > rs.
2743 // We can let assembler map it, or we can do in the compiler itself.
2744 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2745 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2747 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2748 // rss < rtt -> (rtt > rss).
2749 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2750 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2752 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2753 // rs < rt -> rt > rs.
2754 // We can let assembler map it, or we can do in the compiler itself.
2755 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2756 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2758 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2759 // rs < rt -> rt > rs.
2760 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2761 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2763 // Generate cmpgeu(Rs, #u8)
2764 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
2765 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2767 // Generate cmpgtu(Rs, #u9)
2768 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
2769 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
2771 // Map from Rs >= Rt -> !(Rt > Rs).
2772 // rs >= rt -> !(rt > rs).
2773 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2774 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2776 // Map from Rs >= Rt -> !(Rt > Rs).
2777 // rs >= rt -> !(rt > rs).
2778 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2779 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2781 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2782 // Map from (Rs <= Rt) -> !(Rs > Rt).
2783 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2784 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2786 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2787 // Map from (Rs <= Rt) -> !(Rs > Rt).
2788 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2789 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2793 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2794 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2797 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2798 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2800 // Convert sign-extended load back to load and sign extend.
2802 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2803 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2805 // Convert any-extended load back to load and sign extend.
2807 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2808 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2810 // Convert sign-extended load back to load and sign extend.
2812 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2813 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2815 // Convert sign-extended load back to load and sign extend.
2817 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2818 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2823 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2824 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2827 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2828 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2832 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2833 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2837 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2838 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2841 let AddedComplexity = 20 in
2842 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2843 s11_0ExtPred:$offset))),
2844 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2845 s11_0ExtPred:$offset)))>,
2849 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2850 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2853 let AddedComplexity = 20 in
2854 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2855 s11_1ExtPred:$offset))),
2856 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2857 s11_1ExtPred:$offset)))>,
2861 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2862 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2865 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2866 (i32 (LDriw ADDRriS11_0:$src1))>;
2868 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2869 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2870 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2872 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2873 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2874 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2876 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2877 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2878 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2881 // Any extended 64-bit load.
2882 // anyext i32 -> i64
2883 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2884 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2887 // When there is an offset we should prefer the pattern below over the pattern above.
2888 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2889 // So this complexity below is comfortably higher to allow for choosing the below.
2890 // If this is not done then we generate addresses such as
2891 // ********************************************
2892 // r1 = add (r0, #4)
2893 // r1 = memw(r1 + #0)
2895 // r1 = memw(r0 + #4)
2896 // ********************************************
2897 let AddedComplexity = 100 in
2898 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2899 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2900 s11_2ExtPred:$offset)))>,
2903 // anyext i16 -> i64.
2904 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2905 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2908 let AddedComplexity = 20 in
2909 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2910 s11_1ExtPred:$offset))),
2911 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2912 s11_1ExtPred:$offset)))>,
2915 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2916 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2917 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2920 // Multiply 64-bit unsigned and use upper result.
2921 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2936 (COMBINE_rr (TFRI 0),
2942 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2944 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2945 subreg_loreg)))), 32)),
2947 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2948 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2949 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2950 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2951 32)), subreg_loreg)))),
2952 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2953 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2955 // Multiply 64-bit signed and use upper result.
2956 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2960 (COMBINE_rr (TFRI 0),
2970 (COMBINE_rr (TFRI 0),
2976 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2978 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2979 subreg_loreg)))), 32)),
2981 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2982 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2983 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2984 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2985 32)), subreg_loreg)))),
2986 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2987 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2989 // Hexagon specific ISD nodes.
2990 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2991 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2992 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2993 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2994 SDTHexagonADJDYNALLOC>;
2995 // Needed to tag these instructions for stack layout.
2996 let usesCustomInserter = 1 in
2997 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2999 "$dst = add($src1, #$src2)",
3000 [(set (i32 IntRegs:$dst),
3001 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3002 s16ImmPred:$src2))]>;
3004 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3005 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3006 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3008 [(set (i32 IntRegs:$dst),
3009 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3011 let AddedComplexity = 100 in
3012 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3013 (COPY (i32 IntRegs:$src1))>;
3015 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3016 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3018 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3019 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3021 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3023 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3025 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3026 (i32 (CONST32_set_jt tjumptable:$dst))>;
3030 // Multi-class for logical operators :
3031 // Shift by immediate/register and accumulate/logical
3032 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3033 def _ri : SInst_acc<(outs IntRegs:$dst),
3034 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3035 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3036 [(set (i32 IntRegs:$dst),
3037 (OpNode2 (i32 IntRegs:$src1),
3038 (OpNode1 (i32 IntRegs:$src2),
3039 u5ImmPred:$src3)))],
3042 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3043 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3044 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3045 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3046 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3050 // Multi-class for logical operators :
3051 // Shift by register and accumulate/logical (32/64 bits)
3052 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3053 def _rr : SInst_acc<(outs IntRegs:$dst),
3054 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3055 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3056 [(set (i32 IntRegs:$dst),
3057 (OpNode2 (i32 IntRegs:$src1),
3058 (OpNode1 (i32 IntRegs:$src2),
3059 (i32 IntRegs:$src3))))],
3062 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3063 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3064 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3065 [(set (i64 DoubleRegs:$dst),
3066 (OpNode2 (i64 DoubleRegs:$src1),
3067 (OpNode1 (i64 DoubleRegs:$src2),
3068 (i32 IntRegs:$src3))))],
3073 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3074 let AddedComplexity = 100 in
3075 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3076 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3077 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3078 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3081 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3082 let AddedComplexity = 100 in
3083 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3084 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3085 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3086 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3089 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3090 let AddedComplexity = 100 in
3091 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3094 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3095 xtype_xor_imm<"asl", shl>;
3097 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3098 xtype_xor_imm<"lsr", srl>;
3100 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3101 defm LSL : basic_xtype_reg<"lsl", shl>;
3103 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3104 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3105 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3107 //===----------------------------------------------------------------------===//
3108 // V3 Instructions +
3109 //===----------------------------------------------------------------------===//
3111 include "HexagonInstrInfoV3.td"
3113 //===----------------------------------------------------------------------===//
3114 // V3 Instructions -
3115 //===----------------------------------------------------------------------===//
3117 //===----------------------------------------------------------------------===//
3118 // V4 Instructions +
3119 //===----------------------------------------------------------------------===//
3121 include "HexagonInstrInfoV4.td"
3123 //===----------------------------------------------------------------------===//
3124 // V4 Instructions -
3125 //===----------------------------------------------------------------------===//
3127 //===----------------------------------------------------------------------===//
3128 // V5 Instructions +
3129 //===----------------------------------------------------------------------===//
3131 include "HexagonInstrInfoV5.td"
3133 //===----------------------------------------------------------------------===//
3134 // V5 Instructions -
3135 //===----------------------------------------------------------------------===//