1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonImmediates.td"
17 //===----------------------------------------------------------------------===//
18 // Hexagon Instruction Predicate Definitions.
19 //===----------------------------------------------------------------------===//
20 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
21 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
22 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
23 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
24 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
25 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
26 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
27 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
28 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
31 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
32 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
33 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
34 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
35 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
36 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
37 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
38 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
39 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
42 def MEMrr : Operand<i32> {
43 let PrintMethod = "printMEMrrOperand";
44 let MIOperandInfo = (ops IntRegs, IntRegs);
48 def MEMri : Operand<i32> {
49 let PrintMethod = "printMEMriOperand";
50 let MIOperandInfo = (ops IntRegs, IntRegs);
53 def MEMri_s11_2 : Operand<i32>,
54 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
55 let PrintMethod = "printMEMriOperand";
56 let MIOperandInfo = (ops IntRegs, s11Imm);
59 def FrameIndex : Operand<i32> {
60 let PrintMethod = "printFrameIndexOperand";
61 let MIOperandInfo = (ops IntRegs, s11Imm);
64 let PrintMethod = "printGlobalOperand" in
65 def globaladdress : Operand<i32>;
67 let PrintMethod = "printJumpTable" in
68 def jumptablebase : Operand<i32>;
70 def brtarget : Operand<OtherVT>;
71 def calltarget : Operand<i32>;
73 def bblabel : Operand<i32>;
74 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
76 def symbolHi32 : Operand<i32> {
77 let PrintMethod = "printSymbolHi";
79 def symbolLo32 : Operand<i32> {
80 let PrintMethod = "printSymbolLo";
83 // Multi-class for logical operators.
84 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
85 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
86 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
87 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
88 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
90 [(set IntRegs:$dst, (OpNode s10Imm:$b, IntRegs:$c))]>;
93 // Multi-class for compare ops.
94 let isCompare = 1 in {
95 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
96 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
97 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
98 [(set PredRegs:$dst, (OpNode DoubleRegs:$b, DoubleRegs:$c))]>;
100 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
101 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
102 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
103 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
106 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
107 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
108 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
109 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
110 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
111 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
112 [(set PredRegs:$dst, (OpNode IntRegs:$b, s10ImmPred:$c))]>;
115 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
116 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
117 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
118 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
119 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
120 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
121 [(set PredRegs:$dst, (OpNode IntRegs:$b, u9ImmPred:$c))]>;
124 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
125 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
126 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
127 [(set PredRegs:$dst, (OpNode IntRegs:$b, u8ImmPred:$c))]>;
130 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
131 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
132 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
133 [(set PredRegs:$dst, (OpNode IntRegs:$b, s8ImmPred:$c))]>;
137 //===----------------------------------------------------------------------===//
139 //===----------------------------------------------------------------------===//
141 //===----------------------------------------------------------------------===//
142 // http://qualnet.qualcomm.com/~erich/v1/htmldocs/index.html
143 // http://qualnet.qualcomm.com/~erich/v2/htmldocs/index.html
144 // http://qualnet.qualcomm.com/~erich/v3/htmldocs/index.html
145 // http://qualnet.qualcomm.com/~erich/v4/htmldocs/index.html
146 // http://qualnet.qualcomm.com/~erich/v5/htmldocs/index.html
147 //===----------------------------------------------------------------------===//
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 let isPredicable = 1 in
154 def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
155 (ins IntRegs:$src1, IntRegs:$src2),
156 "$dst = add($src1, $src2)",
157 [(set IntRegs:$dst, (add IntRegs:$src1, IntRegs:$src2))]>;
159 let isPredicable = 1 in
160 def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
161 (ins IntRegs:$src1, s16Imm:$src2),
162 "$dst = add($src1, #$src2)",
163 [(set IntRegs:$dst, (add IntRegs:$src1, s16ImmPred:$src2))]>;
165 // Logical operations.
166 let isPredicable = 1 in
167 def XOR_rr : ALU32_rr<(outs IntRegs:$dst),
168 (ins IntRegs:$src1, IntRegs:$src2),
169 "$dst = xor($src1, $src2)",
170 [(set IntRegs:$dst, (xor IntRegs:$src1, IntRegs:$src2))]>;
172 let isPredicable = 1 in
173 def AND_rr : ALU32_rr<(outs IntRegs:$dst),
174 (ins IntRegs:$src1, IntRegs:$src2),
175 "$dst = and($src1, $src2)",
176 [(set IntRegs:$dst, (and IntRegs:$src1, IntRegs:$src2))]>;
178 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
179 (ins IntRegs:$src1, s8Imm:$src2),
180 "$dst = or($src1, #$src2)",
181 [(set IntRegs:$dst, (or IntRegs:$src1, s8ImmPred:$src2))]>;
183 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
186 [(set IntRegs:$dst, (not IntRegs:$src1))]>;
188 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
189 (ins IntRegs:$src1, s10Imm:$src2),
190 "$dst = and($src1, #$src2)",
191 [(set IntRegs:$dst, (and IntRegs:$src1, s10ImmPred:$src2))]>;
193 let isPredicable = 1 in
194 def OR_rr : ALU32_rr<(outs IntRegs:$dst),
195 (ins IntRegs:$src1, IntRegs:$src2),
196 "$dst = or($src1, $src2)",
197 [(set IntRegs:$dst, (or IntRegs:$src1, IntRegs:$src2))]>;
200 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
202 [(set IntRegs:$dst, (ineg IntRegs:$src1))]>;
204 let neverHasSideEffects = 1 in
205 def NOP : ALU32_rr<(outs), (ins),
210 let isPredicable = 1 in
211 def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
212 (ins IntRegs:$src1, IntRegs:$src2),
213 "$dst = sub($src1, $src2)",
214 [(set IntRegs:$dst, (sub IntRegs:$src1, IntRegs:$src2))]>;
216 // Transfer immediate.
217 let isReMaterializable = 1, isPredicable = 1 in
218 def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
220 [(set IntRegs:$dst, s16ImmPred:$src1)]>;
222 // Transfer register.
223 let neverHasSideEffects = 1, isPredicable = 1 in
224 def TFR : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1),
228 // Transfer control register.
229 let neverHasSideEffects = 1 in
230 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
243 let isPredicable = 1, neverHasSideEffects = 1 in
244 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
245 (ins IntRegs:$src1, IntRegs:$src2),
246 "$dst = combine($src1, $src2)",
249 let neverHasSideEffects = 1 in
250 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
251 (ins s8Imm:$src1, s8Imm:$src2),
252 "$dst = combine(#$src1, #$src2)",
256 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
259 "$dst = vmux($src1, $src2, $src3)",
262 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
263 IntRegs:$src2, IntRegs:$src3),
264 "$dst = mux($src1, $src2, $src3)",
265 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
268 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
270 "$dst = mux($src1, #$src2, $src3)",
271 [(set IntRegs:$dst, (select PredRegs:$src1,
272 s8ImmPred:$src2, IntRegs:$src3))]>;
274 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
276 "$dst = mux($src1, $src2, #$src3)",
277 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
280 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
282 "$dst = mux($src1, #$src2, #$src3)",
283 [(set IntRegs:$dst, (select PredRegs:$src1, s8ImmPred:$src2,
287 let isPredicable = 1 in
288 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
289 "$dst = aslh($src1)",
290 [(set IntRegs:$dst, (shl 16, IntRegs:$src1))]>;
292 let isPredicable = 1 in
293 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
294 "$dst = asrh($src1)",
295 [(set IntRegs:$dst, (sra 16, IntRegs:$src1))]>;
298 let isPredicable = 1 in
299 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
300 "$dst = sxtb($src1)",
301 [(set IntRegs:$dst, (sext_inreg IntRegs:$src1, i8))]>;
303 let isPredicable = 1 in
304 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
305 "$dst = sxth($src1)",
306 [(set IntRegs:$dst, (sext_inreg IntRegs:$src1, i16))]>;
309 let isPredicable = 1, neverHasSideEffects = 1 in
310 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
311 "$dst = zxtb($src1)",
314 let isPredicable = 1, neverHasSideEffects = 1 in
315 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
316 "$dst = zxth($src1)",
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
325 //===----------------------------------------------------------------------===//
328 let neverHasSideEffects = 1, isPredicated = 1 in
329 def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
330 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
331 "if ($src1) $dst = add($src2, #$src3)",
334 let neverHasSideEffects = 1, isPredicated = 1 in
335 def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
336 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
337 "if (!$src1) $dst = add($src2, #$src3)",
340 let neverHasSideEffects = 1, isPredicated = 1 in
341 def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
342 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
343 "if ($src1.new) $dst = add($src2, #$src3)",
346 let neverHasSideEffects = 1, isPredicated = 1 in
347 def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
348 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
349 "if (!$src1.new) $dst = add($src2, #$src3)",
352 let neverHasSideEffects = 1, isPredicated = 1 in
353 def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
354 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
355 "if ($src1) $dst = add($src2, $src3)",
358 let neverHasSideEffects = 1, isPredicated = 1 in
359 def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
360 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
361 "if (!$src1) $dst = add($src2, $src3)",
364 let neverHasSideEffects = 1, isPredicated = 1 in
365 def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
366 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
367 "if ($src1.new) $dst = add($src2, $src3)",
370 let neverHasSideEffects = 1, isPredicated = 1 in
371 def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
372 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
373 "if (!$src1.new) $dst = add($src2, $src3)",
377 // Conditional combine.
379 let neverHasSideEffects = 1, isPredicated = 1 in
380 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
381 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
382 "if ($src1) $dst = combine($src2, $src3)",
385 let neverHasSideEffects = 1, isPredicated = 1 in
386 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
387 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
388 "if (!$src1) $dst = combine($src2, $src3)",
391 let neverHasSideEffects = 1, isPredicated = 1 in
392 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
393 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
394 "if ($src1.new) $dst = combine($src2, $src3)",
397 let neverHasSideEffects = 1, isPredicated = 1 in
398 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
399 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
400 "if (!$src1.new) $dst = combine($src2, $src3)",
403 // Conditional logical operations.
405 let isPredicated = 1 in
406 def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
407 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
408 "if ($src1) $dst = xor($src2, $src3)",
411 let isPredicated = 1 in
412 def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
413 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
414 "if (!$src1) $dst = xor($src2, $src3)",
417 let isPredicated = 1 in
418 def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
419 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
420 "if ($src1.new) $dst = xor($src2, $src3)",
423 let isPredicated = 1 in
424 def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
425 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
426 "if (!$src1.new) $dst = xor($src2, $src3)",
429 let isPredicated = 1 in
430 def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
431 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
432 "if ($src1) $dst = and($src2, $src3)",
435 let isPredicated = 1 in
436 def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
437 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
438 "if (!$src1) $dst = and($src2, $src3)",
441 let isPredicated = 1 in
442 def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
443 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
444 "if ($src1.new) $dst = and($src2, $src3)",
447 let isPredicated = 1 in
448 def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
449 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
450 "if (!$src1.new) $dst = and($src2, $src3)",
453 let isPredicated = 1 in
454 def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
455 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
456 "if ($src1) $dst = or($src2, $src3)",
459 let isPredicated = 1 in
460 def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
461 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
462 "if (!$src1) $dst = or($src2, $src3)",
465 let isPredicated = 1 in
466 def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
468 "if ($src1.new) $dst = or($src2, $src3)",
471 let isPredicated = 1 in
472 def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
473 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
474 "if (!$src1.new) $dst = or($src2, $src3)",
478 // Conditional subtract.
480 let isPredicated = 1 in
481 def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
482 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
483 "if ($src1) $dst = sub($src2, $src3)",
486 let isPredicated = 1 in
487 def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
488 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
489 "if (!$src1) $dst = sub($src2, $src3)",
492 let isPredicated = 1 in
493 def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
494 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
495 "if ($src1.new) $dst = sub($src2, $src3)",
498 let isPredicated = 1 in
499 def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
500 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
501 "if (!$src1.new) $dst = sub($src2, $src3)",
505 // Conditional transfer.
507 let neverHasSideEffects = 1, isPredicated = 1 in
508 def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
509 "if ($src1) $dst = $src2",
512 let neverHasSideEffects = 1, isPredicated = 1 in
513 def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
515 "if (!$src1) $dst = $src2",
518 let neverHasSideEffects = 1, isPredicated = 1 in
519 def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
520 "if ($src1) $dst = #$src2",
523 let neverHasSideEffects = 1, isPredicated = 1 in
524 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
526 "if (!$src1) $dst = #$src2",
529 let neverHasSideEffects = 1, isPredicated = 1 in
530 def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
532 "if ($src1.new) $dst = $src2",
535 let neverHasSideEffects = 1, isPredicated = 1 in
536 def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
538 "if (!$src1.new) $dst = $src2",
541 let neverHasSideEffects = 1, isPredicated = 1 in
542 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
544 "if ($src1.new) $dst = #$src2",
547 let neverHasSideEffects = 1, isPredicated = 1 in
548 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
550 "if (!$src1.new) $dst = #$src2",
554 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
555 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
556 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
557 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
558 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
559 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
560 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
561 //===----------------------------------------------------------------------===//
563 //===----------------------------------------------------------------------===//
565 //===----------------------------------------------------------------------===//
567 //===----------------------------------------------------------------------===//
568 // Vector add halfwords
570 // Vector averagehalfwords
572 // Vector subtract halfwords
573 //===----------------------------------------------------------------------===//
575 //===----------------------------------------------------------------------===//
578 //===----------------------------------------------------------------------===//
580 //===----------------------------------------------------------------------===//
582 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
584 "$dst = add($src1, $src2)",
585 [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
586 DoubleRegs:$src2))]>;
591 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
592 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
593 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
595 // Logical operations.
596 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
598 "$dst = and($src1, $src2)",
599 [(set DoubleRegs:$dst, (and DoubleRegs:$src1,
600 DoubleRegs:$src2))]>;
602 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
604 "$dst = or($src1, $src2)",
605 [(set DoubleRegs:$dst, (or DoubleRegs:$src1, DoubleRegs:$src2))]>;
607 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
609 "$dst = xor($src1, $src2)",
610 [(set DoubleRegs:$dst, (xor DoubleRegs:$src1,
611 DoubleRegs:$src2))]>;
614 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
615 "$dst = max($src2, $src1)",
616 [(set IntRegs:$dst, (select (i1 (setlt IntRegs:$src2,
618 IntRegs:$src1, IntRegs:$src2))]>;
621 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
622 "$dst = min($src2, $src1)",
623 [(set IntRegs:$dst, (select (i1 (setgt IntRegs:$src2,
625 IntRegs:$src1, IntRegs:$src2))]>;
628 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
630 "$dst = sub($src1, $src2)",
631 [(set DoubleRegs:$dst, (sub DoubleRegs:$src1,
632 DoubleRegs:$src2))]>;
634 // Subtract halfword.
636 // Transfer register.
637 let neverHasSideEffects = 1 in
638 def TFR_64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
641 //===----------------------------------------------------------------------===//
643 //===----------------------------------------------------------------------===//
645 //===----------------------------------------------------------------------===//
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 //===----------------------------------------------------------------------===//
653 //===----------------------------------------------------------------------===//
655 //===----------------------------------------------------------------------===//
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
661 //===----------------------------------------------------------------------===//
663 //===----------------------------------------------------------------------===//
665 //===----------------------------------------------------------------------===//
667 //===----------------------------------------------------------------------===//
669 //===----------------------------------------------------------------------===//
671 //===----------------------------------------------------------------------===//
673 //===----------------------------------------------------------------------===//
675 //===----------------------------------------------------------------------===//
677 //===----------------------------------------------------------------------===//
679 //===----------------------------------------------------------------------===//
681 //===----------------------------------------------------------------------===//
683 //===----------------------------------------------------------------------===//
685 //===----------------------------------------------------------------------===//
687 //===----------------------------------------------------------------------===//
688 // Logical reductions on predicates.
690 // Looping instructions.
692 // Pipelined looping instructions.
694 // Logical operations on predicates.
695 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
696 "$dst = and($src1, $src2)",
697 [(set PredRegs:$dst, (and PredRegs:$src1, PredRegs:$src2))]>;
699 let neverHasSideEffects = 1 in
700 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
702 "$dst = and($src1, !$src2)",
705 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
706 "$dst = any8($src1)",
709 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
710 "$dst = all8($src1)",
713 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
715 "$dst = vitpack($src1, $src2)",
718 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
721 "$dst = valignb($src1, $src2, $src3)",
724 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
727 "$dst = vspliceb($src1, $src2, $src3)",
730 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
731 "$dst = mask($src1)",
734 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
736 [(set PredRegs:$dst, (not PredRegs:$src1))]>;
738 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
739 "$dst = or($src1, $src2)",
740 [(set PredRegs:$dst, (or PredRegs:$src1, PredRegs:$src2))]>;
742 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
743 "$dst = xor($src1, $src2)",
744 [(set PredRegs:$dst, (xor PredRegs:$src1, PredRegs:$src2))]>;
747 // User control register transfer.
748 //===----------------------------------------------------------------------===//
750 //===----------------------------------------------------------------------===//
753 //===----------------------------------------------------------------------===//
755 //===----------------------------------------------------------------------===//
757 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
758 def JMP : JInst< (outs),
759 (ins brtarget:$offset),
765 let isBranch = 1, isTerminator=1, Defs = [PC],
766 isPredicated = 1 in {
767 def JMP_c : JInst< (outs),
768 (ins PredRegs:$src, brtarget:$offset),
769 "if ($src) jump $offset",
770 [(brcond PredRegs:$src, bb:$offset)]>;
774 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
775 isPredicated = 1 in {
776 def JMP_cNot : JInst< (outs),
777 (ins PredRegs:$src, brtarget:$offset),
778 "if (!$src) jump $offset",
782 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
783 isPredicated = 1 in {
784 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
785 "if ($pred) jump $dst",
789 // Jump to address conditioned on new predicate.
791 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
792 isPredicated = 1 in {
793 def JMP_cdnPt : JInst< (outs),
794 (ins PredRegs:$src, brtarget:$offset),
795 "if ($src.new) jump:t $offset",
800 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
801 isPredicated = 1 in {
802 def JMP_cdnNotPt : JInst< (outs),
803 (ins PredRegs:$src, brtarget:$offset),
804 "if (!$src.new) jump:t $offset",
809 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
810 isPredicated = 1 in {
811 def JMP_cdnPnt : JInst< (outs),
812 (ins PredRegs:$src, brtarget:$offset),
813 "if ($src.new) jump:nt $offset",
818 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
819 isPredicated = 1 in {
820 def JMP_cdnNotPnt : JInst< (outs),
821 (ins PredRegs:$src, brtarget:$offset),
822 "if (!$src.new) jump:nt $offset",
825 //===----------------------------------------------------------------------===//
827 //===----------------------------------------------------------------------===//
829 //===----------------------------------------------------------------------===//
831 //===----------------------------------------------------------------------===//
832 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
833 [SDNPHasChain, SDNPOptInGlue]>;
835 // Jump to address from register.
836 let isReturn = 1, isTerminator = 1, isBarrier = 1,
837 Defs = [PC], Uses = [R31] in {
838 def JMPR: JRInst<(outs), (ins),
843 // Jump to address from register.
844 let isReturn = 1, isTerminator = 1, isBarrier = 1,
845 Defs = [PC], Uses = [R31] in {
846 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
847 "if ($src1) jumpr r31",
851 // Jump to address from register.
852 let isReturn = 1, isTerminator = 1, isBarrier = 1,
853 Defs = [PC], Uses = [R31] in {
854 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
855 "if (!$src1) jumpr r31",
859 //===----------------------------------------------------------------------===//
861 //===----------------------------------------------------------------------===//
863 //===----------------------------------------------------------------------===//
865 //===----------------------------------------------------------------------===//
867 /// Make sure that in post increment load, the first operand is always the post
868 /// increment operand.
871 let isPredicable = 1 in
872 def LDrid : LDInst<(outs DoubleRegs:$dst),
874 "$dst = memd($addr)",
875 [(set DoubleRegs:$dst, (load ADDRriS11_3:$addr))]>;
877 let isPredicable = 1, AddedComplexity = 20 in
878 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
879 (ins IntRegs:$src1, s11_3Imm:$offset),
880 "$dst=memd($src1+#$offset)",
881 [(set DoubleRegs:$dst, (load (add IntRegs:$src1,
882 s11_3ImmPred:$offset)))]>;
884 let mayLoad = 1, neverHasSideEffects = 1 in
885 def LDrid_GP : LDInst<(outs DoubleRegs:$dst),
886 (ins globaladdress:$global, u16Imm:$offset),
887 "$dst=memd(#$global+$offset)",
890 let mayLoad = 1, neverHasSideEffects = 1 in
891 def LDd_GP : LDInst<(outs DoubleRegs:$dst),
892 (ins globaladdress:$global),
893 "$dst=memd(#$global)",
896 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
897 def POST_LDrid : LDInstPI<(outs DoubleRegs:$dst, IntRegs:$dst2),
898 (ins IntRegs:$src1, s4Imm:$offset),
899 "$dst = memd($src1++#$offset)",
903 // Load doubleword conditionally.
904 let mayLoad = 1, neverHasSideEffects = 1 in
905 def LDrid_cPt : LDInst<(outs DoubleRegs:$dst),
906 (ins PredRegs:$src1, MEMri:$addr),
907 "if ($src1) $dst = memd($addr)",
911 let mayLoad = 1, neverHasSideEffects = 1 in
912 def LDrid_cNotPt : LDInst<(outs DoubleRegs:$dst),
913 (ins PredRegs:$src1, MEMri:$addr),
914 "if (!$src1) $dst = memd($addr)",
917 let mayLoad = 1, neverHasSideEffects = 1 in
918 def LDrid_indexed_cPt : LDInst<(outs DoubleRegs:$dst),
919 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
920 "if ($src1) $dst=memd($src2+#$src3)",
923 let mayLoad = 1, neverHasSideEffects = 1 in
924 def LDrid_indexed_cNotPt : LDInst<(outs DoubleRegs:$dst),
925 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
926 "if (!$src1) $dst=memd($src2+#$src3)",
929 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
930 def POST_LDrid_cPt : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
931 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
932 "if ($src1) $dst1 = memd($src2++#$src3)",
936 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
937 def POST_LDrid_cNotPt : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
938 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
939 "if (!$src1) $dst1 = memd($src2++#$src3)",
943 let mayLoad = 1, neverHasSideEffects = 1 in
944 def LDrid_cdnPt : LDInst<(outs DoubleRegs:$dst),
945 (ins PredRegs:$src1, MEMri:$addr),
946 "if ($src1.new) $dst = memd($addr)",
949 let mayLoad = 1, neverHasSideEffects = 1 in
950 def LDrid_cdnNotPt : LDInst<(outs DoubleRegs:$dst),
951 (ins PredRegs:$src1, MEMri:$addr),
952 "if (!$src1.new) $dst = memd($addr)",
955 let mayLoad = 1, neverHasSideEffects = 1 in
956 def LDrid_indexed_cdnPt : LDInst<(outs DoubleRegs:$dst),
957 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
958 "if ($src1.new) $dst=memd($src2+#$src3)",
961 let mayLoad = 1, neverHasSideEffects = 1 in
962 def LDrid_indexed_cdnNotPt : LDInst<(outs DoubleRegs:$dst),
963 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
964 "if (!$src1.new) $dst=memd($src2+#$src3)",
969 let isPredicable = 1 in
970 def LDrib : LDInst<(outs IntRegs:$dst),
972 "$dst = memb($addr)",
973 [(set IntRegs:$dst, (sextloadi8 ADDRriS11_0:$addr))]>;
975 def LDrib_ae : LDInst<(outs IntRegs:$dst),
977 "$dst = memb($addr)",
978 [(set IntRegs:$dst, (extloadi8 ADDRriS11_0:$addr))]>;
980 // Indexed load byte.
981 let isPredicable = 1, AddedComplexity = 20 in
982 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
983 (ins IntRegs:$src1, s11_0Imm:$offset),
984 "$dst=memb($src1+#$offset)",
985 [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,
986 s11_0ImmPred:$offset)))]>;
989 // Indexed load byte any-extend.
990 let AddedComplexity = 20 in
991 def LDrib_ae_indexed : LDInst<(outs IntRegs:$dst),
992 (ins IntRegs:$src1, s11_0Imm:$offset),
993 "$dst=memb($src1+#$offset)",
994 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
995 s11_0ImmPred:$offset)))]>;
997 let mayLoad = 1, neverHasSideEffects = 1 in
998 def LDrib_GP : LDInst<(outs IntRegs:$dst),
999 (ins globaladdress:$global, u16Imm:$offset),
1000 "$dst=memb(#$global+$offset)",
1003 let mayLoad = 1, neverHasSideEffects = 1 in
1004 def LDb_GP : LDInst<(outs IntRegs:$dst),
1005 (ins globaladdress:$global),
1006 "$dst=memb(#$global)",
1009 let mayLoad = 1, neverHasSideEffects = 1 in
1010 def LDub_GP : LDInst<(outs IntRegs:$dst),
1011 (ins globaladdress:$global),
1012 "$dst=memub(#$global)",
1015 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1016 def POST_LDrib : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1017 (ins IntRegs:$src1, s4Imm:$offset),
1018 "$dst = memb($src1++#$offset)",
1022 // Load byte conditionally.
1023 let mayLoad = 1, neverHasSideEffects = 1 in
1024 def LDrib_cPt : LDInst<(outs IntRegs:$dst),
1025 (ins PredRegs:$src1, MEMri:$addr),
1026 "if ($src1) $dst = memb($addr)",
1029 let mayLoad = 1, neverHasSideEffects = 1 in
1030 def LDrib_cNotPt : LDInst<(outs IntRegs:$dst),
1031 (ins PredRegs:$src1, MEMri:$addr),
1032 "if (!$src1) $dst = memb($addr)",
1035 let mayLoad = 1, neverHasSideEffects = 1 in
1036 def LDrib_indexed_cPt : LDInst<(outs IntRegs:$dst),
1037 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1038 "if ($src1) $dst = memb($src2+#$src3)",
1041 let mayLoad = 1, neverHasSideEffects = 1 in
1042 def LDrib_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1043 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1044 "if (!$src1) $dst = memb($src2+#$src3)",
1047 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1048 def POST_LDrib_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1049 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1050 "if ($src1) $dst1 = memb($src2++#$src3)",
1054 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1055 def POST_LDrib_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1056 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1057 "if (!$src1) $dst1 = memb($src2++#$src3)",
1061 let mayLoad = 1, neverHasSideEffects = 1 in
1062 def LDrib_cdnPt : LDInst<(outs IntRegs:$dst),
1063 (ins PredRegs:$src1, MEMri:$addr),
1064 "if ($src1.new) $dst = memb($addr)",
1067 let mayLoad = 1, neverHasSideEffects = 1 in
1068 def LDrib_cdnNotPt : LDInst<(outs IntRegs:$dst),
1069 (ins PredRegs:$src1, MEMri:$addr),
1070 "if (!$src1.new) $dst = memb($addr)",
1073 let mayLoad = 1, neverHasSideEffects = 1 in
1074 def LDrib_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1075 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1076 "if ($src1.new) $dst = memb($src2+#$src3)",
1079 let mayLoad = 1, neverHasSideEffects = 1 in
1080 def LDrib_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1081 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1082 "if (!$src1.new) $dst = memb($src2+#$src3)",
1087 let isPredicable = 1 in
1088 def LDrih : LDInst<(outs IntRegs:$dst),
1090 "$dst = memh($addr)",
1091 [(set IntRegs:$dst, (sextloadi16 ADDRriS11_1:$addr))]>;
1093 let isPredicable = 1, AddedComplexity = 20 in
1094 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
1095 (ins IntRegs:$src1, s11_1Imm:$offset),
1096 "$dst=memh($src1+#$offset)",
1097 [(set IntRegs:$dst, (sextloadi16 (add IntRegs:$src1,
1098 s11_1ImmPred:$offset)))] >;
1100 def LDrih_ae : LDInst<(outs IntRegs:$dst),
1102 "$dst = memh($addr)",
1103 [(set IntRegs:$dst, (extloadi16 ADDRriS11_1:$addr))]>;
1105 let AddedComplexity = 20 in
1106 def LDrih_ae_indexed : LDInst<(outs IntRegs:$dst),
1107 (ins IntRegs:$src1, s11_1Imm:$offset),
1108 "$dst=memh($src1+#$offset)",
1109 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
1110 s11_1ImmPred:$offset)))] >;
1112 let mayLoad = 1, neverHasSideEffects = 1 in
1113 def LDrih_GP : LDInst<(outs IntRegs:$dst),
1114 (ins globaladdress:$global, u16Imm:$offset),
1115 "$dst=memh(#$global+$offset)",
1118 let mayLoad = 1, neverHasSideEffects = 1 in
1119 def LDh_GP : LDInst<(outs IntRegs:$dst),
1120 (ins globaladdress:$global),
1121 "$dst=memh(#$global)",
1124 let mayLoad = 1, neverHasSideEffects = 1 in
1125 def LDuh_GP : LDInst<(outs IntRegs:$dst),
1126 (ins globaladdress:$global),
1127 "$dst=memuh(#$global)",
1131 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1132 def POST_LDrih : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1133 (ins IntRegs:$src1, s4Imm:$offset),
1134 "$dst = memh($src1++#$offset)",
1138 // Load halfword conditionally.
1139 let mayLoad = 1, neverHasSideEffects = 1 in
1140 def LDrih_cPt : LDInst<(outs IntRegs:$dst),
1141 (ins PredRegs:$src1, MEMri:$addr),
1142 "if ($src1) $dst = memh($addr)",
1145 let mayLoad = 1, neverHasSideEffects = 1 in
1146 def LDrih_cNotPt : LDInst<(outs IntRegs:$dst),
1147 (ins PredRegs:$src1, MEMri:$addr),
1148 "if (!$src1) $dst = memh($addr)",
1151 let mayLoad = 1, neverHasSideEffects = 1 in
1152 def LDrih_indexed_cPt : LDInst<(outs IntRegs:$dst),
1153 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1154 "if ($src1) $dst = memh($src2+#$src3)",
1157 let mayLoad = 1, neverHasSideEffects = 1 in
1158 def LDrih_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1159 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1160 "if (!$src1) $dst = memh($src2+#$src3)",
1163 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1164 def POST_LDrih_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1165 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1166 "if ($src1) $dst1 = memh($src2++#$src3)",
1170 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1171 def POST_LDrih_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1172 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1173 "if (!$src1) $dst1 = memh($src2++#$src3)",
1177 let mayLoad = 1, neverHasSideEffects = 1 in
1178 def LDrih_cdnPt : LDInst<(outs IntRegs:$dst),
1179 (ins PredRegs:$src1, MEMri:$addr),
1180 "if ($src1.new) $dst = memh($addr)",
1183 let mayLoad = 1, neverHasSideEffects = 1 in
1184 def LDrih_cdnNotPt : LDInst<(outs IntRegs:$dst),
1185 (ins PredRegs:$src1, MEMri:$addr),
1186 "if (!$src1.new) $dst = memh($addr)",
1189 let mayLoad = 1, neverHasSideEffects = 1 in
1190 def LDrih_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1191 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1192 "if ($src1.new) $dst = memh($src2+#$src3)",
1195 let mayLoad = 1, neverHasSideEffects = 1 in
1196 def LDrih_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1197 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1198 "if (!$src1.new) $dst = memh($src2+#$src3)",
1201 // Load unsigned byte.
1202 let isPredicable = 1 in
1203 def LDriub : LDInst<(outs IntRegs:$dst),
1205 "$dst = memub($addr)",
1206 [(set IntRegs:$dst, (zextloadi8 ADDRriS11_0:$addr))]>;
1208 let isPredicable = 1 in
1209 def LDriubit : LDInst<(outs IntRegs:$dst),
1211 "$dst = memub($addr)",
1212 [(set IntRegs:$dst, (zextloadi1 ADDRriS11_0:$addr))]>;
1214 let isPredicable = 1, AddedComplexity = 20 in
1215 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
1216 (ins IntRegs:$src1, s11_0Imm:$offset),
1217 "$dst=memub($src1+#$offset)",
1218 [(set IntRegs:$dst, (zextloadi8 (add IntRegs:$src1,
1219 s11_0ImmPred:$offset)))]>;
1221 let AddedComplexity = 20 in
1222 def LDriubit_indexed : LDInst<(outs IntRegs:$dst),
1223 (ins IntRegs:$src1, s11_0Imm:$offset),
1224 "$dst=memub($src1+#$offset)",
1225 [(set IntRegs:$dst, (zextloadi1 (add IntRegs:$src1,
1226 s11_0ImmPred:$offset)))]>;
1228 def LDriub_ae : LDInst<(outs IntRegs:$dst),
1230 "$dst = memub($addr)",
1231 [(set IntRegs:$dst, (extloadi8 ADDRriS11_0:$addr))]>;
1234 let AddedComplexity = 20 in
1235 def LDriub_ae_indexed : LDInst<(outs IntRegs:$dst),
1236 (ins IntRegs:$src1, s11_0Imm:$offset),
1237 "$dst=memub($src1+#$offset)",
1238 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
1239 s11_0ImmPred:$offset)))]>;
1241 let mayLoad = 1, neverHasSideEffects = 1 in
1242 def LDriub_GP : LDInst<(outs IntRegs:$dst),
1243 (ins globaladdress:$global, u16Imm:$offset),
1244 "$dst=memub(#$global+$offset)",
1247 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1248 def POST_LDriub : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1249 (ins IntRegs:$src1, s4Imm:$offset),
1250 "$dst = memub($src1++#$offset)",
1254 // Load unsigned byte conditionally.
1255 let mayLoad = 1, neverHasSideEffects = 1 in
1256 def LDriub_cPt : LDInst<(outs IntRegs:$dst),
1257 (ins PredRegs:$src1, MEMri:$addr),
1258 "if ($src1) $dst = memub($addr)",
1261 let mayLoad = 1, neverHasSideEffects = 1 in
1262 def LDriub_cNotPt : LDInst<(outs IntRegs:$dst),
1263 (ins PredRegs:$src1, MEMri:$addr),
1264 "if (!$src1) $dst = memub($addr)",
1267 let mayLoad = 1, neverHasSideEffects = 1 in
1268 def LDriub_indexed_cPt : LDInst<(outs IntRegs:$dst),
1269 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1270 "if ($src1) $dst = memub($src2+#$src3)",
1273 let mayLoad = 1, neverHasSideEffects = 1 in
1274 def LDriub_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1275 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1276 "if (!$src1) $dst = memub($src2+#$src3)",
1279 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1280 def POST_LDriub_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1281 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1282 "if ($src1) $dst1 = memub($src2++#$src3)",
1286 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1287 def POST_LDriub_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1288 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1289 "if (!$src1) $dst1 = memub($src2++#$src3)",
1293 let mayLoad = 1, neverHasSideEffects = 1 in
1294 def LDriub_cdnPt : LDInst<(outs IntRegs:$dst),
1295 (ins PredRegs:$src1, MEMri:$addr),
1296 "if ($src1.new) $dst = memub($addr)",
1299 let mayLoad = 1, neverHasSideEffects = 1 in
1300 def LDriub_cdnNotPt : LDInst<(outs IntRegs:$dst),
1301 (ins PredRegs:$src1, MEMri:$addr),
1302 "if (!$src1.new) $dst = memub($addr)",
1305 let mayLoad = 1, neverHasSideEffects = 1 in
1306 def LDriub_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1307 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1308 "if ($src1.new) $dst = memub($src2+#$src3)",
1311 let mayLoad = 1, neverHasSideEffects = 1 in
1312 def LDriub_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1313 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1314 "if (!$src1.new) $dst = memub($src2+#$src3)",
1317 // Load unsigned halfword.
1318 let isPredicable = 1 in
1319 def LDriuh : LDInst<(outs IntRegs:$dst),
1321 "$dst = memuh($addr)",
1322 [(set IntRegs:$dst, (zextloadi16 ADDRriS11_1:$addr))]>;
1324 // Indexed load unsigned halfword.
1325 let isPredicable = 1, AddedComplexity = 20 in
1326 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
1327 (ins IntRegs:$src1, s11_1Imm:$offset),
1328 "$dst=memuh($src1+#$offset)",
1329 [(set IntRegs:$dst, (zextloadi16 (add IntRegs:$src1,
1330 s11_1ImmPred:$offset)))]>;
1332 def LDriuh_ae : LDInst<(outs IntRegs:$dst),
1334 "$dst = memuh($addr)",
1335 [(set IntRegs:$dst, (extloadi16 ADDRriS11_1:$addr))]>;
1338 // Indexed load unsigned halfword any-extend.
1339 let AddedComplexity = 20 in
1340 def LDriuh_ae_indexed : LDInst<(outs IntRegs:$dst),
1341 (ins IntRegs:$src1, s11_1Imm:$offset),
1342 "$dst=memuh($src1+#$offset)",
1343 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
1344 s11_1ImmPred:$offset)))] >;
1346 let mayLoad = 1, neverHasSideEffects = 1 in
1347 def LDriuh_GP : LDInst<(outs IntRegs:$dst),
1348 (ins globaladdress:$global, u16Imm:$offset),
1349 "$dst=memuh(#$global+$offset)",
1352 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1353 def POST_LDriuh : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1354 (ins IntRegs:$src1, s4Imm:$offset),
1355 "$dst = memuh($src1++#$offset)",
1359 // Load unsigned halfword conditionally.
1360 let mayLoad = 1, neverHasSideEffects = 1 in
1361 def LDriuh_cPt : LDInst<(outs IntRegs:$dst),
1362 (ins PredRegs:$src1, MEMri:$addr),
1363 "if ($src1) $dst = memuh($addr)",
1366 let mayLoad = 1, neverHasSideEffects = 1 in
1367 def LDriuh_cNotPt : LDInst<(outs IntRegs:$dst),
1368 (ins PredRegs:$src1, MEMri:$addr),
1369 "if (!$src1) $dst = memuh($addr)",
1372 let mayLoad = 1, neverHasSideEffects = 1 in
1373 def LDriuh_indexed_cPt : LDInst<(outs IntRegs:$dst),
1374 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1375 "if ($src1) $dst = memuh($src2+#$src3)",
1378 let mayLoad = 1, neverHasSideEffects = 1 in
1379 def LDriuh_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1380 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1381 "if (!$src1) $dst = memuh($src2+#$src3)",
1384 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1385 def POST_LDriuh_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1386 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1387 "if ($src1) $dst1 = memuh($src2++#$src3)",
1391 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1392 def POST_LDriuh_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1393 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1394 "if (!$src1) $dst1 = memuh($src2++#$src3)",
1398 let mayLoad = 1, neverHasSideEffects = 1 in
1399 def LDriuh_cdnPt : LDInst<(outs IntRegs:$dst),
1400 (ins PredRegs:$src1, MEMri:$addr),
1401 "if ($src1.new) $dst = memuh($addr)",
1404 let mayLoad = 1, neverHasSideEffects = 1 in
1405 def LDriuh_cdnNotPt : LDInst<(outs IntRegs:$dst),
1406 (ins PredRegs:$src1, MEMri:$addr),
1407 "if (!$src1.new) $dst = memuh($addr)",
1410 let mayLoad = 1, neverHasSideEffects = 1 in
1411 def LDriuh_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1412 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1413 "if ($src1.new) $dst = memuh($src2+#$src3)",
1416 let mayLoad = 1, neverHasSideEffects = 1 in
1417 def LDriuh_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1418 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1419 "if (!$src1.new) $dst = memuh($src2+#$src3)",
1424 let isPredicable = 1 in
1425 def LDriw : LDInst<(outs IntRegs:$dst),
1426 (ins MEMri:$addr), "$dst = memw($addr)",
1427 [(set IntRegs:$dst, (load ADDRriS11_2:$addr))]>;
1430 let mayLoad = 1, Defs = [R10,R11] in
1431 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1433 "Error; should not emit",
1437 let isPredicable = 1, AddedComplexity = 20 in
1438 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
1439 (ins IntRegs:$src1, s11_2Imm:$offset),
1440 "$dst=memw($src1+#$offset)",
1441 [(set IntRegs:$dst, (load (add IntRegs:$src1,
1442 s11_2ImmPred:$offset)))]>;
1444 let mayLoad = 1, neverHasSideEffects = 1 in
1445 def LDriw_GP : LDInst<(outs IntRegs:$dst),
1446 (ins globaladdress:$global, u16Imm:$offset),
1447 "$dst=memw(#$global+$offset)",
1450 let mayLoad = 1, neverHasSideEffects = 1 in
1451 def LDw_GP : LDInst<(outs IntRegs:$dst),
1452 (ins globaladdress:$global),
1453 "$dst=memw(#$global)",
1456 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1457 def POST_LDriw : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1458 (ins IntRegs:$src1, s4Imm:$offset),
1459 "$dst = memw($src1++#$offset)",
1463 // Load word conditionally.
1465 let mayLoad = 1, neverHasSideEffects = 1 in
1466 def LDriw_cPt : LDInst<(outs IntRegs:$dst),
1467 (ins PredRegs:$src1, MEMri:$addr),
1468 "if ($src1) $dst = memw($addr)",
1471 let mayLoad = 1, neverHasSideEffects = 1 in
1472 def LDriw_cNotPt : LDInst<(outs IntRegs:$dst),
1473 (ins PredRegs:$src1, MEMri:$addr),
1474 "if (!$src1) $dst = memw($addr)",
1477 let mayLoad = 1, neverHasSideEffects = 1 in
1478 def LDriw_indexed_cPt : LDInst<(outs IntRegs:$dst),
1479 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1480 "if ($src1) $dst=memw($src2+#$src3)",
1483 let mayLoad = 1, neverHasSideEffects = 1 in
1484 def LDriw_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1485 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1486 "if (!$src1) $dst=memw($src2+#$src3)",
1489 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1490 def POST_LDriw_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1491 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1492 "if ($src1) $dst1 = memw($src2++#$src3)",
1496 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1497 def POST_LDriw_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1498 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1499 "if (!$src1) $dst1 = memw($src2++#$src3)",
1503 let mayLoad = 1, neverHasSideEffects = 1 in
1504 def LDriw_cdnPt : LDInst<(outs IntRegs:$dst),
1505 (ins PredRegs:$src1, MEMri:$addr),
1506 "if ($src1.new) $dst = memw($addr)",
1509 let mayLoad = 1, neverHasSideEffects = 1 in
1510 def LDriw_cdnNotPt : LDInst<(outs IntRegs:$dst),
1511 (ins PredRegs:$src1, MEMri:$addr),
1512 "if (!$src1.new) $dst = memw($addr)",
1515 let mayLoad = 1, neverHasSideEffects = 1 in
1516 def LDriw_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1517 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1518 "if ($src1.new) $dst=memw($src2+#$src3)",
1521 let mayLoad = 1, neverHasSideEffects = 1 in
1522 def LDriw_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1523 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1524 "if (!$src1.new) $dst=memw($src2+#$src3)",
1527 // Deallocate stack frame.
1528 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1529 def DEALLOCFRAME : LDInst<(outs), (ins i32imm:$amt1),
1534 // Load and unpack bytes to halfwords.
1535 //===----------------------------------------------------------------------===//
1537 //===----------------------------------------------------------------------===//
1539 //===----------------------------------------------------------------------===//
1541 //===----------------------------------------------------------------------===//
1542 //===----------------------------------------------------------------------===//
1544 //===----------------------------------------------------------------------===//
1546 //===----------------------------------------------------------------------===//
1548 //===----------------------------------------------------------------------===//
1549 //===----------------------------------------------------------------------===//
1551 //===----------------------------------------------------------------------===//
1553 //===----------------------------------------------------------------------===//
1555 //===----------------------------------------------------------------------===//
1556 // Multiply and use lower result.
1558 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1559 "$dst =+ mpyi($src1, #$src2)",
1560 [(set IntRegs:$dst, (mul IntRegs:$src1, u8ImmPred:$src2))]>;
1563 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1564 "$dst =- mpyi($src1, #$src2)",
1566 (mul IntRegs:$src1, n8ImmPred:$src2))]>;
1569 // s9 is NOT the same as m9 - but it works.. so far.
1570 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1571 // depending on the value of m9. See Arch Spec.
1572 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1573 "$dst = mpyi($src1, #$src2)",
1574 [(set IntRegs:$dst, (mul IntRegs:$src1, s9ImmPred:$src2))]>;
1577 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1578 "$dst = mpyi($src1, $src2)",
1579 [(set IntRegs:$dst, (mul IntRegs:$src1, IntRegs:$src2))]>;
1582 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1583 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1584 "$dst += mpyi($src2, #$src3)",
1586 (add (mul IntRegs:$src2, u8ImmPred:$src3), IntRegs:$src1))],
1590 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1591 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1592 "$dst += mpyi($src2, $src3)",
1594 (add (mul IntRegs:$src2, IntRegs:$src3), IntRegs:$src1))],
1598 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1599 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1600 "$dst -= mpyi($src2, #$src3)",
1602 (sub IntRegs:$src1, (mul IntRegs:$src2, u8ImmPred:$src3)))],
1605 // Multiply and use upper result.
1606 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1607 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1609 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1610 "$dst = mpy($src1, $src2)",
1611 [(set IntRegs:$dst, (mulhs IntRegs:$src1, IntRegs:$src2))]>;
1613 // Rd=mpy(Rs,Rt):rnd
1615 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1616 "$dst = mpyu($src1, $src2)",
1617 [(set IntRegs:$dst, (mulhu IntRegs:$src1, IntRegs:$src2))]>;
1619 // Multiply and use full result.
1621 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1622 "$dst = mpyu($src1, $src2)",
1623 [(set DoubleRegs:$dst, (mul (i64 (anyext IntRegs:$src1)),
1624 (i64 (anyext IntRegs:$src2))))]>;
1627 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1628 "$dst = mpy($src1, $src2)",
1629 [(set DoubleRegs:$dst, (mul (i64 (sext IntRegs:$src1)),
1630 (i64 (sext IntRegs:$src2))))]>;
1633 // Multiply and accumulate, use full result.
1634 // Rxx[+-]=mpy(Rs,Rt)
1636 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1637 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1638 "$dst += mpy($src2, $src3)",
1639 [(set DoubleRegs:$dst,
1640 (add (mul (i64 (sext IntRegs:$src2)), (i64 (sext IntRegs:$src3))),
1641 DoubleRegs:$src1))],
1645 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1646 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1647 "$dst -= mpy($src2, $src3)",
1648 [(set DoubleRegs:$dst,
1649 (sub DoubleRegs:$src1,
1650 (mul (i64 (sext IntRegs:$src2)), (i64 (sext IntRegs:$src3)))))],
1653 // Rxx[+-]=mpyu(Rs,Rt)
1655 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1656 IntRegs:$src2, IntRegs:$src3),
1657 "$dst += mpyu($src2, $src3)",
1658 [(set DoubleRegs:$dst, (add (mul (i64 (anyext IntRegs:$src2)),
1659 (i64 (anyext IntRegs:$src3))),
1660 DoubleRegs:$src1))],"$src1 = $dst">;
1663 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1664 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1665 "$dst += mpyu($src2, $src3)",
1666 [(set DoubleRegs:$dst,
1667 (sub DoubleRegs:$src1,
1668 (mul (i64 (anyext IntRegs:$src2)),
1669 (i64 (anyext IntRegs:$src3)))))],
1673 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1674 IntRegs:$src2, IntRegs:$src3),
1675 "$dst += add($src2, $src3)",
1676 [(set IntRegs:$dst, (add (add IntRegs:$src2, IntRegs:$src3),
1680 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1681 IntRegs:$src2, s8Imm:$src3),
1682 "$dst += add($src2, #$src3)",
1683 [(set IntRegs:$dst, (add (add IntRegs:$src2, s8ImmPred:$src3),
1687 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1688 IntRegs:$src2, IntRegs:$src3),
1689 "$dst -= add($src2, $src3)",
1690 [(set IntRegs:$dst, (sub IntRegs:$src1, (add IntRegs:$src2,
1694 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1695 IntRegs:$src2, s8Imm:$src3),
1696 "$dst -= add($src2, #$src3)",
1697 [(set IntRegs:$dst, (sub IntRegs:$src1,
1698 (add IntRegs:$src2, s8ImmPred:$src3)))],
1701 //===----------------------------------------------------------------------===//
1703 //===----------------------------------------------------------------------===//
1705 //===----------------------------------------------------------------------===//
1707 //===----------------------------------------------------------------------===//
1708 //===----------------------------------------------------------------------===//
1710 //===----------------------------------------------------------------------===//
1712 //===----------------------------------------------------------------------===//
1714 //===----------------------------------------------------------------------===//
1715 //===----------------------------------------------------------------------===//
1717 //===----------------------------------------------------------------------===//
1719 //===----------------------------------------------------------------------===//
1721 //===----------------------------------------------------------------------===//
1722 //===----------------------------------------------------------------------===//
1724 //===----------------------------------------------------------------------===//
1726 //===----------------------------------------------------------------------===//
1728 //===----------------------------------------------------------------------===//
1730 /// Assumptions::: ****** DO NOT IGNORE ********
1731 /// 1. Make sure that in post increment store, the zero'th operand is always the
1732 /// post increment operand.
1733 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1736 // Store doubleword.
1737 let isPredicable = 1 in
1738 def STrid : STInst<(outs),
1739 (ins MEMri:$addr, DoubleRegs:$src1),
1740 "memd($addr) = $src1",
1741 [(store DoubleRegs:$src1, ADDRriS11_3:$addr)]>;
1743 // Indexed store double word.
1744 let AddedComplexity = 10, isPredicable = 1 in
1745 def STrid_indexed : STInst<(outs),
1746 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
1747 "memd($src1+#$src2) = $src3",
1748 [(store DoubleRegs:$src3,
1749 (add IntRegs:$src1, s11_3ImmPred:$src2))]>;
1751 let mayStore = 1, neverHasSideEffects = 1 in
1752 def STrid_GP : STInst<(outs),
1753 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1754 "memd(#$global+$offset) = $src",
1757 let hasCtrlDep = 1, isPredicable = 1 in
1758 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1759 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1760 "memd($src2++#$offset) = $src1",
1762 (post_store DoubleRegs:$src1, IntRegs:$src2, s4_3ImmPred:$offset))],
1765 // Store doubleword conditionally.
1766 // if ([!]Pv) memd(Rs+#u6:3)=Rtt
1767 // if (Pv) memd(Rs+#u6:3)=Rtt
1768 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1769 def STrid_cPt : STInst<(outs),
1770 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1771 "if ($src1) memd($addr) = $src2",
1774 // if (!Pv) memd(Rs+#u6:3)=Rtt
1775 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1776 def STrid_cNotPt : STInst<(outs),
1777 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1778 "if (!$src1) memd($addr) = $src2",
1781 // if (Pv) memd(Rs+#u6:3)=Rtt
1782 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1783 def STrid_indexed_cPt : STInst<(outs),
1784 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1786 "if ($src1) memd($src2+#$src3) = $src4",
1789 // if (!Pv) memd(Rs+#u6:3)=Rtt
1790 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1791 def STrid_indexed_cNotPt : STInst<(outs),
1792 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1794 "if (!$src1) memd($src2+#$src3) = $src4",
1797 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1798 // if (Pv) memd(Rx++#s4:3)=Rtt
1799 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1800 def POST_STdri_cPt : STInstPI<(outs IntRegs:$dst),
1801 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1803 "if ($src1) memd($src3++#$offset) = $src2",
1807 // if (!Pv) memd(Rx++#s4:3)=Rtt
1808 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,
1810 def POST_STdri_cNotPt : STInstPI<(outs IntRegs:$dst),
1811 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1813 "if (!$src1) memd($src3++#$offset) = $src2",
1819 // memb(Rs+#s11:0)=Rt
1820 let isPredicable = 1 in
1821 def STrib : STInst<(outs),
1822 (ins MEMri:$addr, IntRegs:$src1),
1823 "memb($addr) = $src1",
1824 [(truncstorei8 IntRegs:$src1, ADDRriS11_0:$addr)]>;
1826 let AddedComplexity = 10, isPredicable = 1 in
1827 def STrib_indexed : STInst<(outs),
1828 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1829 "memb($src1+#$src2) = $src3",
1830 [(truncstorei8 IntRegs:$src3, (add IntRegs:$src1,
1831 s11_0ImmPred:$src2))]>;
1833 // memb(gp+#u16:0)=Rt
1834 let mayStore = 1, neverHasSideEffects = 1 in
1835 def STrib_GP : STInst<(outs),
1836 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1837 "memb(#$global+$offset) = $src",
1840 let mayStore = 1, neverHasSideEffects = 1 in
1841 def STb_GP : STInst<(outs),
1842 (ins globaladdress:$global, IntRegs:$src),
1843 "memb(#$global) = $src",
1846 // memb(Rx++#s4:0)=Rt
1847 let hasCtrlDep = 1, isPredicable = 1 in
1848 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1851 "memb($src2++#$offset) = $src1",
1853 (post_truncsti8 IntRegs:$src1, IntRegs:$src2,
1854 s4_0ImmPred:$offset))],
1857 // Store byte conditionally.
1858 // if ([!]Pv) memb(Rs+#u6:0)=Rt
1859 // if (Pv) memb(Rs+#u6:0)=Rt
1860 let mayStore = 1, neverHasSideEffects = 1 in
1861 def STrib_cPt : STInst<(outs),
1862 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1863 "if ($src1) memb($addr) = $src2",
1866 // if (!Pv) memb(Rs+#u6:0)=Rt
1867 let mayStore = 1, neverHasSideEffects = 1 in
1868 def STrib_cNotPt : STInst<(outs),
1869 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1870 "if (!$src1) memb($addr) = $src2",
1873 // if (Pv) memb(Rs+#u6:0)=Rt
1874 let mayStore = 1, neverHasSideEffects = 1 in
1875 def STrib_indexed_cPt : STInst<(outs),
1876 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1877 "if ($src1) memb($src2+#$src3) = $src4",
1880 // if (!Pv) memb(Rs+#u6:0)=Rt
1881 let mayStore = 1, neverHasSideEffects = 1 in
1882 def STrib_indexed_cNotPt : STInst<(outs),
1883 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1884 "if (!$src1) memb($src2+#$src3) = $src4",
1887 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1888 // if (Pv) memb(Rx++#s4:0)=Rt
1889 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1890 def POST_STbri_cPt : STInstPI<(outs IntRegs:$dst),
1891 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1892 "if ($src1) memb($src3++#$offset) = $src2",
1895 // if (!Pv) memb(Rx++#s4:0)=Rt
1896 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1897 def POST_STbri_cNotPt : STInstPI<(outs IntRegs:$dst),
1898 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1899 "if (!$src1) memb($src3++#$offset) = $src2",
1904 // memh(Rs+#s11:1)=Rt
1905 let isPredicable = 1 in
1906 def STrih : STInst<(outs),
1907 (ins MEMri:$addr, IntRegs:$src1),
1908 "memh($addr) = $src1",
1909 [(truncstorei16 IntRegs:$src1, ADDRriS11_1:$addr)]>;
1912 let AddedComplexity = 10, isPredicable = 1 in
1913 def STrih_indexed : STInst<(outs),
1914 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1915 "memh($src1+#$src2) = $src3",
1916 [(truncstorei16 IntRegs:$src3, (add IntRegs:$src1,
1917 s11_1ImmPred:$src2))]>;
1919 let mayStore = 1, neverHasSideEffects = 1 in
1920 def STrih_GP : STInst<(outs),
1921 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1922 "memh(#$global+$offset) = $src",
1925 let mayStore = 1, neverHasSideEffects = 1 in
1926 def STh_GP : STInst<(outs),
1927 (ins globaladdress:$global, IntRegs:$src),
1928 "memh(#$global) = $src",
1931 // memh(Rx++#s4:1)=Rt.H
1932 // memh(Rx++#s4:1)=Rt
1933 let hasCtrlDep = 1, isPredicable = 1 in
1934 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1935 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1936 "memh($src2++#$offset) = $src1",
1938 (post_truncsti16 IntRegs:$src1, IntRegs:$src2,
1939 s4_1ImmPred:$offset))],
1942 // Store halfword conditionally.
1943 // if ([!]Pv) memh(Rs+#u6:1)=Rt
1944 // if (Pv) memh(Rs+#u6:1)=Rt
1945 let mayStore = 1, neverHasSideEffects = 1 in
1946 def STrih_cPt : STInst<(outs),
1947 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1948 "if ($src1) memh($addr) = $src2",
1951 // if (!Pv) memh(Rs+#u6:1)=Rt
1952 let mayStore = 1, neverHasSideEffects = 1 in
1953 def STrih_cNotPt : STInst<(outs),
1954 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1955 "if (!$src1) memh($addr) = $src2",
1958 // if (Pv) memh(Rs+#u6:1)=Rt
1959 let mayStore = 1, neverHasSideEffects = 1 in
1960 def STrih_indexed_cPt : STInst<(outs),
1961 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1962 "if ($src1) memh($src2+#$src3) = $src4",
1965 // if (!Pv) memh(Rs+#u6:1)=Rt
1966 let mayStore = 1, neverHasSideEffects = 1 in
1967 def STrih_indexed_cNotPt : STInst<(outs),
1968 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1969 "if (!$src1) memh($src2+#$src3) = $src4",
1972 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1973 // if (Pv) memh(Rx++#s4:1)=Rt
1974 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1975 def POST_SThri_cPt : STInstPI<(outs IntRegs:$dst),
1976 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1977 "if ($src1) memh($src3++#$offset) = $src2",
1980 // if (!Pv) memh(Rx++#s4:1)=Rt
1981 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1982 def POST_SThri_cNotPt : STInstPI<(outs IntRegs:$dst),
1983 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1984 "if (!$src1) memh($src3++#$offset) = $src2",
1990 let Defs = [R10,R11] in
1991 def STriw_pred : STInst<(outs),
1992 (ins MEMri:$addr, PredRegs:$src1),
1993 "Error; should not emit",
1996 // memw(Rs+#s11:2)=Rt
1997 let isPredicable = 1 in
1998 def STriw : STInst<(outs),
1999 (ins MEMri:$addr, IntRegs:$src1),
2000 "memw($addr) = $src1",
2001 [(store IntRegs:$src1, ADDRriS11_2:$addr)]>;
2003 let AddedComplexity = 10, isPredicable = 1 in
2004 def STriw_indexed : STInst<(outs),
2005 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2006 "memw($src1+#$src2) = $src3",
2007 [(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>;
2009 let mayStore = 1, neverHasSideEffects = 1 in
2010 def STriw_GP : STInst<(outs),
2011 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2012 "memw(#$global+$offset) = $src",
2015 let hasCtrlDep = 1, isPredicable = 1 in
2016 def POST_STwri : STInstPI<(outs IntRegs:$dst),
2017 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
2018 "memw($src2++#$offset) = $src1",
2020 (post_store IntRegs:$src1, IntRegs:$src2, s4_2ImmPred:$offset))],
2023 // Store word conditionally.
2024 // if ([!]Pv) memw(Rs+#u6:2)=Rt
2025 // if (Pv) memw(Rs+#u6:2)=Rt
2026 let mayStore = 1, neverHasSideEffects = 1 in
2027 def STriw_cPt : STInst<(outs),
2028 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2029 "if ($src1) memw($addr) = $src2",
2032 // if (!Pv) memw(Rs+#u6:2)=Rt
2033 let mayStore = 1, neverHasSideEffects = 1 in
2034 def STriw_cNotPt : STInst<(outs),
2035 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2036 "if (!$src1) memw($addr) = $src2",
2039 // if (Pv) memw(Rs+#u6:2)=Rt
2040 let mayStore = 1, neverHasSideEffects = 1 in
2041 def STriw_indexed_cPt : STInst<(outs),
2042 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2043 "if ($src1) memw($src2+#$src3) = $src4",
2046 // if (!Pv) memw(Rs+#u6:2)=Rt
2047 let mayStore = 1, neverHasSideEffects = 1 in
2048 def STriw_indexed_cNotPt : STInst<(outs),
2049 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2050 "if (!$src1) memw($src2+#$src3) = $src4",
2053 // if ([!]Pv) memw(Rx++#s4:2)=Rt
2054 // if (Pv) memw(Rx++#s4:2)=Rt
2055 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
2056 def POST_STwri_cPt : STInstPI<(outs IntRegs:$dst),
2057 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2058 "if ($src1) memw($src3++#$offset) = $src2",
2061 // if (!Pv) memw(Rx++#s4:2)=Rt
2062 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
2063 def POST_STwri_cNotPt : STInstPI<(outs IntRegs:$dst),
2064 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2065 "if (!$src1) memw($src3++#$offset) = $src2",
2070 // Allocate stack frame.
2071 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
2072 def ALLOCFRAME : STInst<(outs),
2074 "allocframe(#$amt)",
2077 //===----------------------------------------------------------------------===//
2079 //===----------------------------------------------------------------------===//
2081 //===----------------------------------------------------------------------===//
2083 //===----------------------------------------------------------------------===//
2085 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2086 "$dst = not($src1)",
2087 [(set DoubleRegs:$dst, (not DoubleRegs:$src1))]>;
2090 // Sign extend word to doubleword.
2091 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2092 "$dst = sxtw($src1)",
2093 [(set DoubleRegs:$dst, (sext IntRegs:$src1))]>;
2094 //===----------------------------------------------------------------------===//
2096 //===----------------------------------------------------------------------===//
2098 //===----------------------------------------------------------------------===//
2100 //===----------------------------------------------------------------------===//
2101 //===----------------------------------------------------------------------===//
2103 //===----------------------------------------------------------------------===//
2106 //===----------------------------------------------------------------------===//
2108 //===----------------------------------------------------------------------===//
2109 //===----------------------------------------------------------------------===//
2111 //===----------------------------------------------------------------------===//
2113 //===----------------------------------------------------------------------===//
2115 //===----------------------------------------------------------------------===//
2116 //===----------------------------------------------------------------------===//
2118 //===----------------------------------------------------------------------===//
2120 //===----------------------------------------------------------------------===//
2122 //===----------------------------------------------------------------------===//
2123 // Predicate transfer.
2124 let neverHasSideEffects = 1 in
2125 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2126 "$dst = $src1 // Should almost never emit this",
2129 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2130 "$dst = $src1 // Should almost never emit!",
2131 [(set PredRegs:$dst, (trunc IntRegs:$src1))]>;
2132 //===----------------------------------------------------------------------===//
2134 //===----------------------------------------------------------------------===//
2136 //===----------------------------------------------------------------------===//
2138 //===----------------------------------------------------------------------===//
2139 // Shift by immediate.
2140 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2141 "$dst = asr($src1, #$src2)",
2142 [(set IntRegs:$dst, (sra IntRegs:$src1, u5ImmPred:$src2))]>;
2144 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2145 "$dst = asr($src1, #$src2)",
2146 [(set DoubleRegs:$dst, (sra DoubleRegs:$src1, u6ImmPred:$src2))]>;
2148 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2149 "$dst = asl($src1, #$src2)",
2150 [(set IntRegs:$dst, (shl IntRegs:$src1, u5ImmPred:$src2))]>;
2152 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2153 "$dst = lsr($src1, #$src2)",
2154 [(set IntRegs:$dst, (srl IntRegs:$src1, u5ImmPred:$src2))]>;
2156 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2157 "$dst = lsr($src1, #$src2)",
2158 [(set DoubleRegs:$dst, (srl DoubleRegs:$src1, u6ImmPred:$src2))]>;
2160 def LSRd_ri_acc : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2163 "$dst += lsr($src2, #$src3)",
2164 [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
2165 (srl DoubleRegs:$src2,
2166 u6ImmPred:$src3)))],
2169 // Shift by immediate and accumulate.
2170 def ASR_rr_acc : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1,
2173 "$dst += asr($src2, $src3)",
2174 [], "$src1 = $dst">;
2176 // Shift by immediate and add.
2177 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2179 "$dst = addasl($src1, $src2, #$src3)",
2180 [(set IntRegs:$dst, (add IntRegs:$src1,
2182 u3ImmPred:$src3)))]>;
2184 // Shift by register.
2185 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2186 "$dst = asl($src1, $src2)",
2187 [(set IntRegs:$dst, (shl IntRegs:$src1, IntRegs:$src2))]>;
2189 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2190 "$dst = asr($src1, $src2)",
2191 [(set IntRegs:$dst, (sra IntRegs:$src1, IntRegs:$src2))]>;
2194 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2195 "$dst = lsr($src1, $src2)",
2196 [(set IntRegs:$dst, (srl IntRegs:$src1, IntRegs:$src2))]>;
2198 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2199 "$dst = lsl($src1, $src2)",
2200 [(set DoubleRegs:$dst, (shl DoubleRegs:$src1, IntRegs:$src2))]>;
2202 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2204 "$dst = asr($src1, $src2)",
2205 [(set DoubleRegs:$dst, (sra DoubleRegs:$src1, IntRegs:$src2))]>;
2207 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2209 "$dst = lsr($src1, $src2)",
2210 [(set DoubleRegs:$dst, (srl DoubleRegs:$src1, IntRegs:$src2))]>;
2212 //===----------------------------------------------------------------------===//
2214 //===----------------------------------------------------------------------===//
2216 //===----------------------------------------------------------------------===//
2218 //===----------------------------------------------------------------------===//
2219 //===----------------------------------------------------------------------===//
2221 //===----------------------------------------------------------------------===//
2223 //===----------------------------------------------------------------------===//
2225 //===----------------------------------------------------------------------===//
2226 //===----------------------------------------------------------------------===//
2228 //===----------------------------------------------------------------------===//
2230 //===----------------------------------------------------------------------===//
2232 //===----------------------------------------------------------------------===//
2234 //===----------------------------------------------------------------------===//
2236 //===----------------------------------------------------------------------===//
2237 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2238 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2241 let hasSideEffects = 1 in
2242 def BARRIER : STInst<(outs), (ins),
2244 [(HexagonBARRIER)]>;
2246 //===----------------------------------------------------------------------===//
2248 //===----------------------------------------------------------------------===//
2250 // TFRI64 - assembly mapped.
2251 let isReMaterializable = 1 in
2252 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2254 [(set DoubleRegs:$dst, s8Imm64Pred:$src1)]>;
2256 // Pseudo instruction to encode a set of conditional transfers.
2257 // This instruction is used instead of a mux and trades-off codesize
2258 // for performance. We conduct this transformation optimistically in
2259 // the hope that these instructions get promoted to dot-new transfers.
2260 let AddedComplexity = 100 in
2261 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2264 "Error; should not emit",
2265 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
2268 let AddedComplexity = 100 in
2269 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2270 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2271 "Error; should not emit",
2273 (select PredRegs:$src1, IntRegs:$src2, s12ImmPred:$src3))]>;
2275 let AddedComplexity = 100 in
2276 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2277 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2278 "Error; should not emit",
2280 (select PredRegs:$src1, s12ImmPred:$src2, IntRegs:$src3))]>;
2282 let AddedComplexity = 100 in
2283 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2284 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2285 "Error; should not emit",
2286 [(set IntRegs:$dst, (select PredRegs:$src1,
2288 s12ImmPred:$src3))]>;
2290 // Generate frameindex addresses.
2291 let isReMaterializable = 1 in
2292 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2293 "$dst = add($src1)",
2294 [(set IntRegs:$dst, ADDRri:$src1)]>;
2299 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2300 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2301 "loop0($offset, #$src2)",
2305 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2306 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2307 "loop0($offset, $src2)",
2311 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2312 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2313 def ENDLOOP0 : CRInst<(outs), (ins brtarget:$offset),
2318 // Support for generating global address.
2319 // Taken from X86InstrInfo.td.
2320 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
2322 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2323 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2325 // This pattern is incorrect. When we add small data, we should change
2326 // this pattern to use memw(#foo).
2327 let isMoveImm = 1 in
2328 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2329 "$dst = CONST32(#$global)",
2331 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2333 let isReMaterializable = 1, isMoveImm = 1 in
2334 def CONST32_set : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2335 "$dst = CONST32(#$global)",
2337 (HexagonCONST32 tglobaladdr:$global))]>;
2339 let isReMaterializable = 1, isMoveImm = 1 in
2340 def CONST32_set_jt : LDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2341 "$dst = CONST32(#$jt)",
2343 (HexagonCONST32 tjumptable:$jt))]>;
2345 let isReMaterializable = 1, isMoveImm = 1 in
2346 def CONST32GP_set : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2347 "$dst = CONST32(#$global)",
2349 (HexagonCONST32_GP tglobaladdr:$global))]>;
2351 let isReMaterializable = 1, isMoveImm = 1 in
2352 def CONST32_Int_Real : LDInst<(outs IntRegs:$dst), (ins i32imm:$global),
2353 "$dst = CONST32(#$global)",
2354 [(set IntRegs:$dst, imm:$global) ]>;
2356 let isReMaterializable = 1, isMoveImm = 1 in
2357 def CONST32_Label : LDInst<(outs IntRegs:$dst), (ins bblabel:$label),
2358 "$dst = CONST32($label)",
2359 [(set IntRegs:$dst, (HexagonCONST32 bbl:$label))]>;
2361 let isReMaterializable = 1, isMoveImm = 1 in
2362 def CONST64_Int_Real : LDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
2363 "$dst = CONST64(#$global)",
2364 [(set DoubleRegs:$dst, imm:$global) ]>;
2366 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2367 "$dst = xor($dst, $dst)",
2368 [(set PredRegs:$dst, 0)]>;
2370 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2371 "$dst = mpy($src1, $src2)",
2373 (trunc (i64 (srl (i64 (mul (i64 (sext IntRegs:$src1)),
2374 (i64 (sext IntRegs:$src2)))),
2377 // Pseudo instructions.
2378 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2380 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2381 SDTCisVT<1, i32> ]>;
2383 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2384 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2386 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2387 [SDNPHasChain, SDNPOutGlue]>;
2389 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2391 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2392 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2394 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2395 // Optional Flag and Variable Arguments.
2396 // Its 1 Operand has pointer type.
2397 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2398 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2400 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2401 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2402 "Should never be emitted",
2403 [(callseq_start timm:$amt)]>;
2406 let Defs = [R29, R30, R31], Uses = [R29] in {
2407 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2408 "Should never be emitted",
2409 [(callseq_end timm:$amt1, timm:$amt2)]>;
2412 let isCall = 1, neverHasSideEffects = 1,
2413 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2414 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2415 def CALL : JInst<(outs), (ins calltarget:$dst, variable_ops),
2419 // Call subroutine from register.
2420 let isCall = 1, neverHasSideEffects = 1,
2421 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2422 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2423 def CALLR : JRInst<(outs), (ins IntRegs:$dst, variable_ops),
2429 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2430 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2431 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2432 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst, variable_ops),
2433 "jump $dst // TAILCALL", []>;
2435 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2436 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2437 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2438 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst, variable_ops),
2439 "jump $dst // TAILCALL", []>;
2442 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2443 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2444 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2445 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst, variable_ops),
2446 "jumpr $dst // TAILCALL", []>;
2448 // Map call instruction.
2449 def : Pat<(call IntRegs:$dst),
2450 (CALLR IntRegs:$dst)>, Requires<[HasV2TOnly]>;
2451 def : Pat<(call tglobaladdr:$dst),
2452 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2453 def : Pat<(call texternalsym:$dst),
2454 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2456 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2457 (TCRETURNtg tglobaladdr:$dst)>;
2458 def : Pat<(HexagonTCRet texternalsym:$dst),
2459 (TCRETURNtext texternalsym:$dst)>;
2460 def : Pat<(HexagonTCRet IntRegs:$dst),
2461 (TCRETURNR IntRegs:$dst)>;
2463 // Map from r0 = and(r1, 65535) to r0 = zxth(r1).
2464 def : Pat <(and IntRegs:$src1, 65535),
2465 (ZXTH IntRegs:$src1)>;
2467 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2468 def : Pat <(and IntRegs:$src1, 255),
2469 (ZXTB IntRegs:$src1)>;
2471 // Map Add(p1, true) to p1 = not(p1).
2472 // Add(p1, false) should never be produced,
2473 // if it does, it got to be mapped to NOOP.
2474 def : Pat <(add PredRegs:$src1, -1),
2475 (NOT_p PredRegs:$src1)>;
2477 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2478 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2479 def : Pat <(select (i1 (setlt IntRegs:$src1, IntRegs:$src2)), IntRegs:$src3,
2481 (TFR_condset_rr (CMPLTrr IntRegs:$src1, IntRegs:$src2), IntRegs:$src4,
2482 IntRegs:$src3)>, Requires<[HasV2TOnly]>;
2484 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2485 def : Pat <(select (not PredRegs:$src1), s8ImmPred:$src2, s8ImmPred:$src3),
2486 (TFR_condset_ii PredRegs:$src1, s8ImmPred:$src3, s8ImmPred:$src2)>;
2488 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2489 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2490 (JMP_cNot PredRegs:$src1, bb:$offset)>;
2492 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2493 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2494 (AND_pnotp PredRegs:$src1, PredRegs:$src2)>;
2496 // Map from store(globaladdress + x) -> memd(#foo + x).
2497 let AddedComplexity = 100 in
2498 def : Pat <(store DoubleRegs:$src1,
2499 (add (HexagonCONST32_GP tglobaladdr:$global),
2500 u16ImmPred:$offset)),
2501 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset, DoubleRegs:$src1)>;
2503 // Map from store(globaladdress) -> memd(#foo + 0).
2504 let AddedComplexity = 100 in
2505 def : Pat <(store DoubleRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2506 (STrid_GP tglobaladdr:$global, 0, DoubleRegs:$src1)>;
2508 // Map from store(globaladdress + x) -> memw(#foo + x).
2509 let AddedComplexity = 100 in
2510 def : Pat <(store IntRegs:$src1, (add (HexagonCONST32_GP tglobaladdr:$global),
2511 u16ImmPred:$offset)),
2512 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2514 // Map from store(globaladdress) -> memw(#foo + 0).
2515 let AddedComplexity = 100 in
2516 def : Pat <(store IntRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2517 (STriw_GP tglobaladdr:$global, 0, IntRegs:$src1)>;
2519 // Map from store(globaladdress) -> memw(#foo + 0).
2520 let AddedComplexity = 100 in
2521 def : Pat <(store IntRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2522 (STriw_GP tglobaladdr:$global, 0, IntRegs:$src1)>;
2524 // Map from store(globaladdress + x) -> memh(#foo + x).
2525 let AddedComplexity = 100 in
2526 def : Pat <(truncstorei16 IntRegs:$src1,
2527 (add (HexagonCONST32_GP tglobaladdr:$global),
2528 u16ImmPred:$offset)),
2529 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2531 // Map from store(globaladdress) -> memh(#foo).
2532 let AddedComplexity = 100 in
2533 def : Pat <(truncstorei16 IntRegs:$src1,
2534 (HexagonCONST32_GP tglobaladdr:$global)),
2535 (STh_GP tglobaladdr:$global, IntRegs:$src1)>;
2537 // Map from store(globaladdress + x) -> memb(#foo + x).
2538 let AddedComplexity = 100 in
2539 def : Pat <(truncstorei8 IntRegs:$src1,
2540 (add (HexagonCONST32_GP tglobaladdr:$global),
2541 u16ImmPred:$offset)),
2542 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2544 // Map from store(globaladdress) -> memb(#foo).
2545 let AddedComplexity = 100 in
2546 def : Pat <(truncstorei8 IntRegs:$src1,
2547 (HexagonCONST32_GP tglobaladdr:$global)),
2548 (STb_GP tglobaladdr:$global, IntRegs:$src1)>;
2550 // Map from load(globaladdress + x) -> memw(#foo + x).
2551 let AddedComplexity = 100 in
2552 def : Pat <(load (add (HexagonCONST32_GP tglobaladdr:$global),
2553 u16ImmPred:$offset)),
2554 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2556 // Map from load(globaladdress) -> memw(#foo + 0).
2557 let AddedComplexity = 100 in
2558 def : Pat <(load (HexagonCONST32_GP tglobaladdr:$global)),
2559 (LDw_GP tglobaladdr:$global)>;
2561 // Map from load(globaladdress + x) -> memd(#foo + x).
2562 let AddedComplexity = 100 in
2563 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2564 u16ImmPred:$offset))),
2565 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2567 // Map from load(globaladdress) -> memw(#foo + 0).
2568 let AddedComplexity = 100 in
2569 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2570 (LDd_GP tglobaladdr:$global)>;
2573 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress + 0), Pd = Rd.
2574 let AddedComplexity = 100 in
2575 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2576 (TFR_PdRs (LDrib_GP tglobaladdr:$global, 0))>;
2578 // Map from load(globaladdress + x) -> memh(#foo + x).
2579 let AddedComplexity = 100 in
2580 def : Pat <(sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2581 u16ImmPred:$offset)),
2582 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2584 // Map from load(globaladdress) -> memh(#foo + 0).
2585 let AddedComplexity = 100 in
2586 def : Pat <(sextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2587 (LDrih_GP tglobaladdr:$global, 0)>;
2589 // Map from load(globaladdress + x) -> memuh(#foo + x).
2590 let AddedComplexity = 100 in
2591 def : Pat <(zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2592 u16ImmPred:$offset)),
2593 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2595 // Map from load(globaladdress) -> memuh(#foo + 0).
2596 let AddedComplexity = 100 in
2597 def : Pat <(zextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2598 (LDriuh_GP tglobaladdr:$global, 0)>;
2600 // Map from load(globaladdress + x) -> memuh(#foo + x).
2601 let AddedComplexity = 100 in
2602 def : Pat <(extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2603 u16ImmPred:$offset)),
2604 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2606 // Map from load(globaladdress) -> memuh(#foo + 0).
2607 let AddedComplexity = 100 in
2608 def : Pat <(extloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2609 (LDriuh_GP tglobaladdr:$global, 0)>;
2610 // Map from load(globaladdress + x) -> memub(#foo + x).
2611 let AddedComplexity = 100 in
2612 def : Pat <(zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2613 u16ImmPred:$offset)),
2614 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2616 // Map from load(globaladdress) -> memuh(#foo + 0).
2617 let AddedComplexity = 100 in
2618 def : Pat <(zextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2619 (LDriub_GP tglobaladdr:$global, 0)>;
2621 // Map from load(globaladdress + x) -> memb(#foo + x).
2622 let AddedComplexity = 100 in
2623 def : Pat <(sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2624 u16ImmPred:$offset)),
2625 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2627 // Map from load(globaladdress) -> memb(#foo).
2628 let AddedComplexity = 100 in
2629 def : Pat <(extloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2630 (LDb_GP tglobaladdr:$global)>;
2632 // Map from load(globaladdress) -> memb(#foo).
2633 let AddedComplexity = 100 in
2634 def : Pat <(sextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2635 (LDb_GP tglobaladdr:$global)>;
2637 // Map from load(globaladdress) -> memub(#foo).
2638 let AddedComplexity = 100 in
2639 def : Pat <(zextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2640 (LDub_GP tglobaladdr:$global)>;
2642 // When the Interprocedural Global Variable optimizer realizes that a
2643 // certain global variable takes only two constant values, it shrinks the
2644 // global to a boolean. Catch those loads here in the following 3 patterns.
2645 let AddedComplexity = 100 in
2646 def : Pat <(extloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2647 (LDb_GP tglobaladdr:$global)>;
2649 let AddedComplexity = 100 in
2650 def : Pat <(sextloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2651 (LDb_GP tglobaladdr:$global)>;
2653 let AddedComplexity = 100 in
2654 def : Pat <(zextloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2655 (LDub_GP tglobaladdr:$global)>;
2657 // Map from load(globaladdress) -> memh(#foo).
2658 let AddedComplexity = 100 in
2659 def : Pat <(extloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2660 (LDh_GP tglobaladdr:$global)>;
2662 // Map from load(globaladdress) -> memh(#foo).
2663 let AddedComplexity = 100 in
2664 def : Pat <(sextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2665 (LDh_GP tglobaladdr:$global)>;
2667 // Map from load(globaladdress) -> memuh(#foo).
2668 let AddedComplexity = 100 in
2669 def : Pat <(zextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2670 (LDuh_GP tglobaladdr:$global)>;
2672 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2673 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2674 (AND_rr (LDrib ADDRriS11_0:$addr), (TFRI 0x1))>;
2676 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2677 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i32)),
2678 (i64 (SXTW (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg)))>;
2680 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2681 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i16)),
2682 (i64 (SXTW (SXTH (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2684 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2685 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i8)),
2686 (i64 (SXTW (SXTB (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2688 // We want to prevent emiting pnot's as much as possible.
2689 // Map brcond with an unsupported setcc to a JMP_cNot.
2690 def : Pat <(brcond (i1 (setne IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2691 (JMP_cNot (CMPEQrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2693 def : Pat <(brcond (i1 (setne IntRegs:$src1, s10ImmPred:$src2)), bb:$offset),
2694 (JMP_cNot (CMPEQri IntRegs:$src1, s10ImmPred:$src2), bb:$offset)>;
2696 def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 -1))), bb:$offset),
2697 (JMP_cNot PredRegs:$src1, bb:$offset)>;
2699 def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 0))), bb:$offset),
2700 (JMP_c PredRegs:$src1, bb:$offset)>;
2702 def : Pat <(brcond (i1 (setlt IntRegs:$src1, s8ImmPred:$src2)), bb:$offset),
2703 (JMP_cNot (CMPGEri IntRegs:$src1, s8ImmPred:$src2), bb:$offset)>;
2705 def : Pat <(brcond (i1 (setlt IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2706 (JMP_c (CMPLTrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2708 def : Pat <(brcond (i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)),
2710 (JMP_cNot (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1),
2713 def : Pat <(brcond (i1 (setule IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2714 (JMP_cNot (CMPGTUrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2716 def : Pat <(brcond (i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)),
2718 (JMP_cNot (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2),
2721 // Map from a 64-bit select to an emulated 64-bit mux.
2722 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2723 def : Pat <(select PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
2725 (MUX_rr PredRegs:$src1,
2726 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg),
2727 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_hireg)),
2728 (MUX_rr PredRegs:$src1,
2729 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_loreg),
2730 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_loreg)))>;
2732 // Map from a 1-bit select to logical ops.
2733 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2734 def : Pat <(select PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),
2735 (OR_pp (AND_pp PredRegs:$src1, PredRegs:$src2),
2736 (AND_pp (NOT_p PredRegs:$src1), PredRegs:$src3))>;
2738 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2739 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2740 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2742 // Map for truncating from 64 immediates to 32 bit immediates.
2743 def : Pat<(i32 (trunc DoubleRegs:$src)),
2744 (i32 (EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))>;
2746 // Map for truncating from i64 immediates to i1 bit immediates.
2747 def : Pat<(i1 (trunc DoubleRegs:$src)),
2748 (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>;
2750 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2751 def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr),
2752 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2755 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2756 def : Pat<(truncstorei16 DoubleRegs:$src, ADDRriS11_0:$addr),
2757 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2760 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2761 def : Pat<(truncstorei32 DoubleRegs:$src, ADDRriS11_0:$addr),
2762 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2765 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2766 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2767 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2769 let AddedComplexity = 100 in
2770 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2772 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2773 (STb_GP tglobaladdr:$global, (TFRI 1))>;
2776 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2777 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2778 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2780 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2781 def : Pat<(store PredRegs:$src1, ADDRriS11_2:$addr),
2782 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii PredRegs:$src1, 1, 0)) )>;
2784 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2785 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2786 // Better way to do this?
2787 def : Pat<(i64 (anyext IntRegs:$src1)),
2788 (i64 (SXTW IntRegs:$src1))>;
2790 // Map cmple -> cmpgt.
2791 // rs <= rt -> !(rs > rt).
2792 def : Pat<(i1 (setle IntRegs:$src1, s10ImmPred:$src2)),
2793 (i1 (NOT_p (CMPGTri IntRegs:$src1, s10ImmPred:$src2)))>;
2795 // rs <= rt -> !(rs > rt).
2796 def : Pat<(i1 (setle IntRegs:$src1, IntRegs:$src2)),
2797 (i1 (NOT_p (CMPGTrr IntRegs:$src1, IntRegs:$src2)))>;
2799 // Rss <= Rtt -> !(Rss > Rtt).
2800 def : Pat<(i1 (setle DoubleRegs:$src1, DoubleRegs:$src2)),
2801 (i1 (NOT_p (CMPGT64rr DoubleRegs:$src1, DoubleRegs:$src2)))>;
2803 // Map cmpne -> cmpeq.
2804 // Hexagon_TODO: We should improve on this.
2805 // rs != rt -> !(rs == rt).
2806 def : Pat <(i1 (setne IntRegs:$src1, s10ImmPred:$src2)),
2807 (i1 (NOT_p(i1 (CMPEQri IntRegs:$src1, s10ImmPred:$src2))))>;
2809 // Map cmpne(Rs) -> !cmpeqe(Rs).
2810 // rs != rt -> !(rs == rt).
2811 def : Pat <(i1 (setne IntRegs:$src1, IntRegs:$src2)),
2812 (i1 (NOT_p(i1 (CMPEQrr IntRegs:$src1, IntRegs:$src2))))>;
2814 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2815 def : Pat <(i1 (setne PredRegs:$src1, PredRegs:$src2)),
2816 (i1 (XOR_pp PredRegs:$src1, PredRegs:$src2))>;
2818 // Map cmpne(Rss) -> !cmpew(Rss).
2819 // rs != rt -> !(rs == rt).
2820 def : Pat <(i1 (setne DoubleRegs:$src1, DoubleRegs:$src2)),
2821 (i1 (NOT_p(i1 (CMPEHexagon4rr DoubleRegs:$src1, DoubleRegs:$src2))))>;
2823 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2824 // rs >= rt -> !(rt > rs).
2825 def : Pat <(i1 (setge IntRegs:$src1, IntRegs:$src2)),
2826 (i1 (NOT_p(i1 (CMPGTrr IntRegs:$src2, IntRegs:$src1))))>;
2828 def : Pat <(i1 (setge IntRegs:$src1, s8ImmPred:$src2)),
2829 (i1 (CMPGEri IntRegs:$src1, s8ImmPred:$src2))>;
2831 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2832 // rss >= rtt -> !(rtt > rss).
2833 def : Pat <(i1 (setge DoubleRegs:$src1, DoubleRegs:$src2)),
2834 (i1 (NOT_p(i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))))>;
2836 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2837 // rs < rt -> !(rs >= rt).
2838 def : Pat <(i1 (setlt IntRegs:$src1, s8ImmPred:$src2)),
2839 (i1 (NOT_p (CMPGEri IntRegs:$src1, s8ImmPred:$src2)))>;
2841 // Map cmplt(Rs, Rt) -> cmplt(Rs, Rt).
2842 // rs < rt -> rs < rt. Let assembler map it.
2843 def : Pat <(i1 (setlt IntRegs:$src1, IntRegs:$src2)),
2844 (i1 (CMPLTrr IntRegs:$src2, IntRegs:$src1))>;
2846 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2847 // rss < rtt -> (rtt > rss).
2848 def : Pat <(i1 (setlt DoubleRegs:$src1, DoubleRegs:$src2)),
2849 (i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))>;
2851 // Map from cmpltu(Rs, Rd) -> !cmpgtu(Rs, Rd - 1).
2852 // rs < rt -> rt > rs.
2853 def : Pat <(i1 (setult IntRegs:$src1, IntRegs:$src2)),
2854 (i1 (CMPGTUrr IntRegs:$src2, IntRegs:$src1))>;
2856 // Map from cmpltu(Rss, Rdd) -> !cmpgtu(Rss, Rdd - 1).
2857 // rs < rt -> rt > rs.
2858 def : Pat <(i1 (setult DoubleRegs:$src1, DoubleRegs:$src2)),
2859 (i1 (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1))>;
2861 // Map from Rs >= Rt -> !(Rt > Rs).
2862 // rs >= rt -> !(rt > rs).
2863 def : Pat <(i1 (setuge IntRegs:$src1, IntRegs:$src2)),
2864 (i1 (NOT_p (CMPGTUrr IntRegs:$src2, IntRegs:$src1)))>;
2866 // Map from Rs >= Rt -> !(Rt > Rs).
2867 // rs >= rt -> !(rt > rs).
2868 def : Pat <(i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)),
2869 (i1 (NOT_p (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1)))>;
2871 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2872 // Map from (Rs <= Rt) -> !(Rs > Rt).
2873 def : Pat <(i1 (setule IntRegs:$src1, IntRegs:$src2)),
2874 (i1 (NOT_p (CMPGTUrr IntRegs:$src1, IntRegs:$src2)))>;
2876 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2877 // Map from (Rs <= Rt) -> !(Rs > Rt).
2878 def : Pat <(i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)),
2879 (i1 (NOT_p (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2)))>;
2883 def : Pat <(i32 (sext PredRegs:$src1)),
2884 (i32 (MUX_ii PredRegs:$src1, -1, 0))>;
2886 // Convert sign-extended load back to load and sign extend.
2888 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2889 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2891 // Convert any-extended load back to load and sign extend.
2893 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2894 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2896 // Convert sign-extended load back to load and sign extend.
2898 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2899 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2901 // Convert sign-extended load back to load and sign extend.
2903 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2904 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2909 def : Pat <(i32 (zext PredRegs:$src1)),
2910 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2913 def : Pat <(i64 (zext PredRegs:$src1)),
2914 (i64 (COMBINE_rr (TFRI 0), (MUX_ii PredRegs:$src1, 1, 0)))>;
2917 def : Pat <(i64 (zext IntRegs:$src1)),
2918 (i64 (COMBINE_rr (TFRI 0), IntRegs:$src1))>;
2921 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2922 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
2925 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2926 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
2929 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2930 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2932 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2933 (i32 (LDriw ADDRriS11_0:$src1))>;
2935 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2936 def : Pat <(i32 (zext PredRegs:$src1)),
2937 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2939 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2940 def : Pat <(i32 (anyext PredRegs:$src1)),
2941 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2943 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2944 def : Pat <(i64 (anyext PredRegs:$src1)),
2945 (i64 (SXTW (i32 (MUX_ii PredRegs:$src1, 1, 0))))>;
2948 // Any extended 64-bit load.
2949 // anyext i32 -> i64
2950 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2951 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2953 // anyext i16 -> i64.
2954 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2955 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
2957 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2958 def : Pat<(i64 (zext IntRegs:$src1)),
2959 (i64 (COMBINE_rr (TFRI 0), IntRegs:$src1))>;
2961 // Multiply 64-bit unsigned and use upper result.
2962 def : Pat <(mulhu DoubleRegs:$src1, DoubleRegs:$src2),
2963 (MPYU64_acc(COMBINE_rr (TFRI 0),
2965 (LSRd_ri(MPYU64_acc(MPYU64_acc(COMBINE_rr (TFRI 0),
2966 (EXTRACT_SUBREG (LSRd_ri(MPYU64
2967 (EXTRACT_SUBREG DoubleRegs:$src1,
2969 (EXTRACT_SUBREG DoubleRegs:$src2,
2971 32) ,subreg_loreg)),
2972 (EXTRACT_SUBREG DoubleRegs:$src1,
2974 (EXTRACT_SUBREG DoubleRegs:$src2,
2976 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
2977 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)),
2979 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg),
2980 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)
2983 // Multiply 64-bit signed and use upper result.
2984 def : Pat <(mulhs DoubleRegs:$src1, DoubleRegs:$src2),
2985 (MPY64_acc(COMBINE_rr (TFRI 0),
2987 (LSRd_ri(MPY64_acc(MPY64_acc(COMBINE_rr (TFRI 0),
2988 (EXTRACT_SUBREG (LSRd_ri(MPYU64
2989 (EXTRACT_SUBREG DoubleRegs:$src1,
2991 (EXTRACT_SUBREG DoubleRegs:$src2,
2993 32) ,subreg_loreg)),
2994 (EXTRACT_SUBREG DoubleRegs:$src1,
2996 (EXTRACT_SUBREG DoubleRegs:$src2,
2998 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
2999 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)),
3001 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg),
3002 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)
3005 // Hexagon specific ISD nodes.
3006 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3007 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3008 SDTHexagonADJDYNALLOC>;
3009 // Needed to tag these instructions for stack layout.
3010 let usesCustomInserter = 1 in
3011 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3013 "$dst = add($src1, #$src2)",
3014 [(set IntRegs:$dst, (Hexagon_ADJDYNALLOC IntRegs:$src1,
3015 s16ImmPred:$src2))]>;
3017 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, []>;
3018 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3019 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3021 [(set IntRegs:$dst, (Hexagon_ARGEXTEND IntRegs:$src1))]>;
3023 let AddedComplexity = 100 in
3024 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND IntRegs:$src1), i16)),
3025 (TFR IntRegs:$src1)>;
3028 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3029 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3031 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3032 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3034 [(HexagonBR_JT IntRegs:$src)]>;
3035 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3037 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3038 (CONST32_set_jt tjumptable:$dst)>;
3041 //===----------------------------------------------------------------------===//
3042 // V3 Instructions +
3043 //===----------------------------------------------------------------------===//
3045 include "HexagonInstrInfoV3.td"
3047 //===----------------------------------------------------------------------===//
3048 // V3 Instructions -
3049 //===----------------------------------------------------------------------===//
3051 //===----------------------------------------------------------------------===//
3052 // V4 Instructions +
3053 //===----------------------------------------------------------------------===//
3055 include "HexagonInstrInfoV4.td"
3057 //===----------------------------------------------------------------------===//
3058 // V4 Instructions -
3059 //===----------------------------------------------------------------------===//