1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 //===----------------------------------------------------------------------===//
19 // Multi-class for logical operators.
20 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
21 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
22 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
23 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
25 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
26 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
27 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
31 // Multi-class for compare ops.
32 let isCompare = 1 in {
33 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
34 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
35 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
36 [(set (i1 PredRegs:$dst),
37 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
40 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
41 let CextOpcode = CextOp in {
42 let InputType = "reg" in
43 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
44 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
45 [(set (i1 PredRegs:$dst),
46 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
48 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
49 opExtentBits = 10, InputType = "imm" in
50 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
51 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
52 [(set (i1 PredRegs:$dst),
53 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
57 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
58 let CextOpcode = CextOp in {
59 let InputType = "reg" in
60 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
61 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
62 [(set (i1 PredRegs:$dst),
63 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
65 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
66 opExtentBits = 9, InputType = "imm" in
67 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
68 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
69 [(set (i1 PredRegs:$dst),
70 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
74 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
75 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
76 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
77 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
78 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
83 //===----------------------------------------------------------------------===//
84 // ALU32/ALU (Instructions with register-register form)
85 //===----------------------------------------------------------------------===//
86 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
87 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
89 def HexagonWrapperCombineII :
90 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
92 def HexagonWrapperCombineRR :
93 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
95 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
96 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
98 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
99 "$Rd = "#mnemonic#"($Rs, $Rt)",
100 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
101 let isCommutable = IsComm;
102 let BaseOpcode = mnemonic#_rr;
103 let CextOpcode = mnemonic;
111 let Inst{26-24} = MajOp;
112 let Inst{23-21} = MinOp;
113 let Inst{20-16} = !if(OpsRev,Rt,Rs);
114 let Inst{12-8} = !if(OpsRev,Rs,Rt);
118 let hasSideEffects = 0, hasNewValue = 1 in
119 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
120 bit OpsRev, bit PredNot, bit PredNew>
121 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
122 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
123 "$Rd = "#mnemonic#"($Rs, $Rt)",
124 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
125 let isPredicated = 1;
126 let isPredicatedFalse = PredNot;
127 let isPredicatedNew = PredNew;
128 let BaseOpcode = mnemonic#_rr;
129 let CextOpcode = mnemonic;
138 let Inst{26-24} = MajOp;
139 let Inst{23-21} = MinOp;
140 let Inst{20-16} = !if(OpsRev,Rt,Rs);
141 let Inst{13} = PredNew;
142 let Inst{12-8} = !if(OpsRev,Rs,Rt);
143 let Inst{7} = PredNot;
148 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
150 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
151 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
152 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
153 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
156 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
157 bit OpsRev, bit IsComm> {
158 let isPredicable = 1 in
159 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
160 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
163 let isCodeGenOnly = 0 in
164 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
166 // Pats for instruction selection.
167 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
168 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
169 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
171 def: BinOp32_pat<add, A2_add, i32>;
173 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
175 let isPredicatedNew = isPredNew in
176 def NAME : ALU32_rr<(outs RC:$dst),
177 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
178 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
179 ") $dst = ")#mnemonic#"($src2, $src3)",
183 multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
184 let isPredicatedFalse = PredNot in {
185 defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
187 defm _cdn#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 1>;
191 let InputType = "reg" in
192 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
193 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
194 let isPredicable = 1 in
195 def NAME : ALU32_rr<(outs IntRegs:$dst),
196 (ins IntRegs:$src1, IntRegs:$src2),
197 "$dst = "#mnemonic#"($src1, $src2)",
198 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
199 (i32 IntRegs:$src2)))]>;
201 let neverHasSideEffects = 1, isPredicated = 1 in {
202 defm Pt : ALU32_Pred<mnemonic, IntRegs, 0>;
203 defm NotPt : ALU32_Pred<mnemonic, IntRegs, 1>;
208 let isCommutable = 1 in {
209 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
210 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
211 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
214 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
216 // Combines the two integer registers SRC1 and SRC2 into a double register.
217 let isPredicable = 1 in
218 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
219 (ins IntRegs:$src1, IntRegs:$src2),
220 "$dst = combine($src1, $src2)",
221 [(set (i64 DoubleRegs:$dst),
222 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
223 (i32 IntRegs:$src2))))]>;
225 multiclass Combine_base {
226 let BaseOpcode = "combine" in {
227 def NAME : T_Combine;
228 let neverHasSideEffects = 1, isPredicated = 1 in {
229 defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
230 defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
235 defm COMBINE_rr : Combine_base, PredNewRel;
237 // Combines the two immediates SRC1 and SRC2 into a double register.
238 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
239 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
240 "$dst = combine(#$src1, #$src2)",
241 [(set (i64 DoubleRegs:$dst),
242 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
244 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
245 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
247 //===----------------------------------------------------------------------===//
248 // ALU32/ALU (ADD with register-immediate form)
249 //===----------------------------------------------------------------------===//
250 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
251 let isPredicatedNew = isPredNew in
252 def NAME : ALU32_ri<(outs IntRegs:$dst),
253 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
254 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
255 ") $dst = ")#mnemonic#"($src2, #$src3)",
259 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
260 let isPredicatedFalse = PredNot in {
261 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
263 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
267 let isExtendable = 1, InputType = "imm" in
268 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
269 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
270 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
272 def NAME : ALU32_ri<(outs IntRegs:$dst),
273 (ins IntRegs:$src1, s16Ext:$src2),
274 "$dst = "#mnemonic#"($src1, #$src2)",
275 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
276 (s16ExtPred:$src2)))]>;
278 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
279 neverHasSideEffects = 1, isPredicated = 1 in {
280 defm Pt : ALU32ri_Pred<mnemonic, 0>;
281 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
286 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
288 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
289 CextOpcode = "OR", InputType = "imm" in
290 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
291 (ins IntRegs:$src1, s10Ext:$src2),
292 "$dst = or($src1, #$src2)",
293 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
294 s10ExtPred:$src2))]>, ImmRegRel;
296 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
297 InputType = "imm", CextOpcode = "AND" in
298 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
299 (ins IntRegs:$src1, s10Ext:$src2),
300 "$dst = and($src1, #$src2)",
301 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
302 s10ExtPred:$src2))]>, ImmRegRel;
305 let neverHasSideEffects = 1, isCodeGenOnly = 0 in
306 def NOP : ALU32_rr<(outs), (ins),
310 // Rd32=sub(#s10,Rs32)
311 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
312 CextOpcode = "SUB", InputType = "imm" in
313 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
314 (ins s10Ext:$src1, IntRegs:$src2),
315 "$dst = sub(#$src1, $src2)",
316 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
319 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
320 def : Pat<(not (i32 IntRegs:$src1)),
321 (SUB_ri -1, (i32 IntRegs:$src1))>;
323 // Rd = neg(Rs) gets mapped to Rd=sub(#0, Rs).
324 // Pattern definition for 'neg' was not necessary.
326 multiclass TFR_Pred<bit PredNot> {
327 let isPredicatedFalse = PredNot in {
328 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
329 (ins PredRegs:$src1, IntRegs:$src2),
330 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
333 let isPredicatedNew = 1 in
334 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
335 (ins PredRegs:$src1, IntRegs:$src2),
336 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
341 let InputType = "reg", neverHasSideEffects = 1 in
342 multiclass TFR_base<string CextOp> {
343 let CextOpcode = CextOp, BaseOpcode = CextOp in {
344 let isPredicable = 1 in
345 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
349 let isPredicated = 1 in {
350 defm Pt : TFR_Pred<0>;
351 defm NotPt : TFR_Pred<1>;
356 class T_TFR64_Pred<bit PredNot, bit isPredNew>
357 : ALU32_rr<(outs DoubleRegs:$dst),
358 (ins PredRegs:$src1, DoubleRegs:$src2),
359 !if(PredNot, "if (!$src1", "if ($src1")#
360 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
367 let Inst{27-24} = 0b1101;
368 let Inst{13} = isPredNew;
369 let Inst{7} = PredNot;
371 let Inst{6-5} = src1;
372 let Inst{20-17} = src2{4-1};
374 let Inst{12-9} = src2{4-1};
378 multiclass TFR64_Pred<bit PredNot> {
379 let isPredicatedFalse = PredNot in {
380 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
382 let isPredicatedNew = 1 in
383 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
387 let neverHasSideEffects = 1 in
388 multiclass TFR64_base<string BaseName> {
389 let BaseOpcode = BaseName in {
390 let isPredicable = 1 in
391 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
392 (ins DoubleRegs:$src1),
398 let Inst{27-23} = 0b01010;
400 let Inst{20-17} = src1{4-1};
402 let Inst{12-9} = src1{4-1};
406 let isPredicated = 1 in {
407 defm Pt : TFR64_Pred<0>;
408 defm NotPt : TFR64_Pred<1>;
413 multiclass TFRI_Pred<bit PredNot> {
414 let isMoveImm = 1, isPredicatedFalse = PredNot in {
415 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
416 (ins PredRegs:$src1, s12Ext:$src2),
417 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
421 let isPredicatedNew = 1 in
422 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
423 (ins PredRegs:$src1, s12Ext:$src2),
424 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
429 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
430 multiclass TFRI_base<string CextOp> {
431 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
432 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
433 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
434 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
436 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
438 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
439 isPredicated = 1 in {
440 defm Pt : TFRI_Pred<0>;
441 defm NotPt : TFRI_Pred<1>;
446 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
447 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
448 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
450 // Transfer control register.
451 let neverHasSideEffects = 1 in
452 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
455 //===----------------------------------------------------------------------===//
457 //===----------------------------------------------------------------------===//
460 //===----------------------------------------------------------------------===//
462 //===----------------------------------------------------------------------===//
464 let neverHasSideEffects = 1 in
465 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
466 (ins s8Imm:$src1, s8Imm:$src2),
467 "$dst = combine(#$src1, #$src2)",
471 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
474 "$dst = vmux($src1, $src2, $src3)",
477 let CextOpcode = "MUX", InputType = "reg" in
478 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
479 IntRegs:$src2, IntRegs:$src3),
480 "$dst = mux($src1, $src2, $src3)",
481 [(set (i32 IntRegs:$dst),
482 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
483 (i32 IntRegs:$src3))))]>, ImmRegRel;
485 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
486 CextOpcode = "MUX", InputType = "imm" in
487 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
489 "$dst = mux($src1, #$src2, $src3)",
490 [(set (i32 IntRegs:$dst),
491 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
492 (i32 IntRegs:$src3))))]>, ImmRegRel;
494 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
495 CextOpcode = "MUX", InputType = "imm" in
496 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
498 "$dst = mux($src1, $src2, #$src3)",
499 [(set (i32 IntRegs:$dst),
500 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
501 s8ExtPred:$src3)))]>, ImmRegRel;
503 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
504 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
506 "$dst = mux($src1, #$src2, #$src3)",
507 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
509 s8ImmPred:$src3)))]>;
511 // ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
512 multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
513 let isPredicatedNew = isPredNew in
514 def NAME : ALU32Inst<(outs IntRegs:$dst),
515 (ins PredRegs:$src1, IntRegs:$src2),
516 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
517 ") $dst = ")#mnemonic#"($src2)">,
521 multiclass ALU32_2op_Pred<string mnemonic, bit PredNot> {
522 let isPredicatedFalse = PredNot in {
523 defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
525 defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
529 multiclass ALU32_2op_base<string mnemonic> {
530 let BaseOpcode = mnemonic in {
531 let isPredicable = 1, neverHasSideEffects = 1 in
532 def NAME : ALU32Inst<(outs IntRegs:$dst),
534 "$dst = "#mnemonic#"($src1)">;
536 let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
537 neverHasSideEffects = 1 in {
538 defm Pt_V4 : ALU32_2op_Pred<mnemonic, 0>;
539 defm NotPt_V4 : ALU32_2op_Pred<mnemonic, 1>;
544 defm ASLH : ALU32_2op_base<"aslh">, PredNewRel;
545 defm ASRH : ALU32_2op_base<"asrh">, PredNewRel;
546 defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
547 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
548 defm ZXTB : ALU32_2op_base<"zxtb">, PredNewRel;
549 defm ZXTH : ALU32_2op_base<"zxth">, PredNewRel;
551 def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
552 (ASLH IntRegs:$src1)>;
554 def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
555 (ASRH IntRegs:$src1)>;
557 def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
558 (SXTB IntRegs:$src1)>;
560 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
561 (SXTH IntRegs:$src1)>;
563 //===----------------------------------------------------------------------===//
565 //===----------------------------------------------------------------------===//
568 //===----------------------------------------------------------------------===//
570 //===----------------------------------------------------------------------===//
573 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
574 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
575 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
577 // SDNode for converting immediate C to C-1.
578 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
579 // Return the byte immediate const-1 as an SDNode.
580 int32_t imm = N->getSExtValue();
581 return XformSToSM1Imm(imm);
584 // SDNode for converting immediate C to C-1.
585 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
586 // Return the byte immediate const-1 as an SDNode.
587 uint32_t imm = N->getZExtValue();
588 return XformUToUM1Imm(imm);
591 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
593 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
595 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
597 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
599 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
601 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
603 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
605 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
607 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
608 "$dst = tstbit($src1, $src2)",
609 [(set (i1 PredRegs:$dst),
610 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
612 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
613 "$dst = tstbit($src1, $src2)",
614 [(set (i1 PredRegs:$dst),
615 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
617 //===----------------------------------------------------------------------===//
619 //===----------------------------------------------------------------------===//
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
626 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
628 "$dst = add($src1, $src2)",
629 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
630 (i64 DoubleRegs:$src2)))]>;
635 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
636 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
637 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
639 // Logical operations.
640 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
642 "$dst = and($src1, $src2)",
643 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
644 (i64 DoubleRegs:$src2)))]>;
646 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
648 "$dst = or($src1, $src2)",
649 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
650 (i64 DoubleRegs:$src2)))]>;
652 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
654 "$dst = xor($src1, $src2)",
655 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
656 (i64 DoubleRegs:$src2)))]>;
659 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
660 "$dst = max($src2, $src1)",
661 [(set (i32 IntRegs:$dst),
662 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
663 (i32 IntRegs:$src1))),
664 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
666 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
667 "$dst = maxu($src2, $src1)",
668 [(set (i32 IntRegs:$dst),
669 (i32 (select (i1 (setult (i32 IntRegs:$src2),
670 (i32 IntRegs:$src1))),
671 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
673 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
675 "$dst = max($src2, $src1)",
676 [(set (i64 DoubleRegs:$dst),
677 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
678 (i64 DoubleRegs:$src1))),
679 (i64 DoubleRegs:$src1),
680 (i64 DoubleRegs:$src2))))]>;
682 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
684 "$dst = maxu($src2, $src1)",
685 [(set (i64 DoubleRegs:$dst),
686 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
687 (i64 DoubleRegs:$src1))),
688 (i64 DoubleRegs:$src1),
689 (i64 DoubleRegs:$src2))))]>;
692 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
693 "$dst = min($src2, $src1)",
694 [(set (i32 IntRegs:$dst),
695 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
696 (i32 IntRegs:$src1))),
697 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
699 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
700 "$dst = minu($src2, $src1)",
701 [(set (i32 IntRegs:$dst),
702 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
703 (i32 IntRegs:$src1))),
704 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
706 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
708 "$dst = min($src2, $src1)",
709 [(set (i64 DoubleRegs:$dst),
710 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
711 (i64 DoubleRegs:$src1))),
712 (i64 DoubleRegs:$src1),
713 (i64 DoubleRegs:$src2))))]>;
715 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
717 "$dst = minu($src2, $src1)",
718 [(set (i64 DoubleRegs:$dst),
719 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
720 (i64 DoubleRegs:$src1))),
721 (i64 DoubleRegs:$src1),
722 (i64 DoubleRegs:$src2))))]>;
725 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
727 "$dst = sub($src1, $src2)",
728 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
729 (i64 DoubleRegs:$src2)))]>;
731 // Subtract halfword.
733 //===----------------------------------------------------------------------===//
735 //===----------------------------------------------------------------------===//
737 //===----------------------------------------------------------------------===//
739 //===----------------------------------------------------------------------===//
741 //===----------------------------------------------------------------------===//
743 //===----------------------------------------------------------------------===//
745 //===----------------------------------------------------------------------===//
747 //===----------------------------------------------------------------------===//
749 //===----------------------------------------------------------------------===//
751 //===----------------------------------------------------------------------===//
753 //===----------------------------------------------------------------------===//
755 //===----------------------------------------------------------------------===//
756 // Logical reductions on predicates.
758 // Looping instructions.
760 // Pipelined looping instructions.
762 // Logical operations on predicates.
763 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
764 "$dst = and($src1, $src2)",
765 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
766 (i1 PredRegs:$src2)))]>;
768 let neverHasSideEffects = 1 in
769 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
771 "$dst = and($src1, !$src2)",
774 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
775 "$dst = any8($src1)",
778 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
779 "$dst = all8($src1)",
782 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
784 "$dst = vitpack($src1, $src2)",
787 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
790 "$dst = valignb($src1, $src2, $src3)",
793 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
796 "$dst = vspliceb($src1, $src2, $src3)",
799 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
800 "$dst = mask($src1)",
803 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
805 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
807 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
808 "$dst = or($src1, $src2)",
809 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
810 (i1 PredRegs:$src2)))]>;
812 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
813 "$dst = xor($src1, $src2)",
814 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
815 (i1 PredRegs:$src2)))]>;
818 // User control register transfer.
819 //===----------------------------------------------------------------------===//
821 //===----------------------------------------------------------------------===//
823 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
824 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
825 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone,
828 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
829 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
831 let InputType = "imm", isBarrier = 1, isPredicable = 1,
832 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
833 opExtentBits = 24, isCodeGenOnly = 0 in
834 class T_JMP <dag InsDag, list<dag> JumpList = []>
835 : JInst<(outs), InsDag,
836 "jump $dst" , JumpList> {
841 let Inst{27-25} = 0b100;
842 let Inst{24-16} = dst{23-15};
843 let Inst{13-1} = dst{14-2};
846 let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
847 Defs = [PC], isPredicated = 1, opExtentBits = 17 in
848 class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
849 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
850 !if(PredNot, "if (!$src", "if ($src")#
851 !if(isPredNew, ".new) ", ") ")#"jump"#
852 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
855 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
856 let isPredicatedFalse = PredNot;
857 let isPredicatedNew = isPredNew;
863 let Inst{27-24} = 0b1100;
864 let Inst{21} = PredNot;
865 let Inst{12} = !if(isPredNew, isTak, zero);
866 let Inst{11} = isPredNew;
868 let Inst{23-22} = dst{16-15};
869 let Inst{20-16} = dst{14-10};
870 let Inst{13} = dst{9};
871 let Inst{7-1} = dst{8-2};
874 let isBarrier = 1, Defs = [PC], isPredicable = 1, InputType = "reg" in
875 class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
876 : JRInst<(outs ), InsDag,
882 let Inst{27-21} = 0b0010100;
883 let Inst{20-16} = dst;
886 let Defs = [PC], isPredicated = 1, InputType = "reg" in
887 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
888 JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
889 !if(PredNot, "if (!$src", "if ($src")#
890 !if(isPredNew, ".new) ", ") ")#"jumpr"#
891 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
894 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
895 let isPredicatedFalse = PredNot;
896 let isPredicatedNew = isPredNew;
902 let Inst{27-22} = 0b001101;
903 let Inst{21} = PredNot;
904 let Inst{20-16} = dst;
905 let Inst{12} = !if(isPredNew, isTak, zero);
906 let Inst{11} = isPredNew;
908 let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
909 let validSubTargets = !if(isPredNew, HasV3SubT, HasV2SubT);
912 multiclass JMP_Pred<bit PredNot> {
913 def _#NAME : T_JMP_c<PredNot, 0, 0>;
915 def _#NAME#new_t : T_JMP_c<PredNot, 1, 1>; // taken
916 def _#NAME#new_nt : T_JMP_c<PredNot, 1, 0>; // not taken
919 multiclass JMP_base<string BaseOp> {
920 let BaseOpcode = BaseOp in {
921 def NAME : T_JMP<(ins brtarget:$dst), [(br bb:$dst)]>;
922 defm t : JMP_Pred<0>;
923 defm f : JMP_Pred<1>;
927 multiclass JMPR_Pred<bit PredNot> {
928 def NAME: T_JMPr_c<PredNot, 0, 0>;
930 def NAME#new_tV3 : T_JMPr_c<PredNot, 1, 1>; // taken
931 def NAME#new_ntV3 : T_JMPr_c<PredNot, 1, 0>; // not taken
934 multiclass JMPR_base<string BaseOp> {
935 let BaseOpcode = BaseOp in {
937 defm _t : JMPR_Pred<0>;
938 defm _f : JMPR_Pred<1>;
942 let isTerminator = 1, neverHasSideEffects = 1 in {
944 defm JMP : JMP_base<"JMP">, PredNewRel;
946 let isBranch = 1, isIndirectBranch = 1 in
947 defm JMPR : JMPR_base<"JMPr">, PredNewRel;
949 let isReturn = 1, isCodeGenOnly = 1 in
950 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
956 def : Pat <(brcond (i1 PredRegs:$src1), bb:$offset),
957 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
959 // A return through builtin_eh_return.
960 let isReturn = 1, isTerminator = 1, isBarrier = 1, neverHasSideEffects = 1,
961 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
962 def EH_RETURN_JMPR : T_JMPr;
964 def : Pat<(eh_return),
965 (EH_RETURN_JMPR (i32 R31))>;
967 def : Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
968 (JMPR (i32 IntRegs:$dst))>;
970 def : Pat<(brind (i32 IntRegs:$dst)),
971 (JMPR (i32 IntRegs:$dst))>;
973 //===----------------------------------------------------------------------===//
975 //===----------------------------------------------------------------------===//
977 //===----------------------------------------------------------------------===//
979 //===----------------------------------------------------------------------===//
981 // Load -- MEMri operand
982 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
983 bit isNot, bit isPredNew> {
984 let isPredicatedNew = isPredNew in
985 def NAME : LDInst2<(outs RC:$dst),
986 (ins PredRegs:$src1, MEMri:$addr),
987 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
988 ") ")#"$dst = "#mnemonic#"($addr)",
992 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
993 let isPredicatedFalse = PredNot in {
994 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
996 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1000 let isExtendable = 1, neverHasSideEffects = 1 in
1001 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1002 bits<5> ImmBits, bits<5> PredImmBits> {
1004 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1005 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1007 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
1008 "$dst = "#mnemonic#"($addr)",
1011 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1012 isPredicated = 1 in {
1013 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
1014 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
1019 let addrMode = BaseImmOffset, isMEMri = "true" in {
1020 let accessSize = ByteAccess in {
1021 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
1022 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
1025 let accessSize = HalfWordAccess in {
1026 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
1027 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
1030 let accessSize = WordAccess in
1031 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
1033 let accessSize = DoubleWordAccess in
1034 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
1037 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
1038 (LDrib ADDRriS11_0:$addr) >;
1040 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
1041 (LDriub ADDRriS11_0:$addr) >;
1043 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
1044 (LDrih ADDRriS11_1:$addr) >;
1046 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
1047 (LDriuh ADDRriS11_1:$addr) >;
1049 def : Pat < (i32 (load ADDRriS11_2:$addr)),
1050 (LDriw ADDRriS11_2:$addr) >;
1052 def : Pat < (i64 (load ADDRriS11_3:$addr)),
1053 (LDrid ADDRriS11_3:$addr) >;
1056 // Load - Base with Immediate offset addressing mode
1057 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1058 bit isNot, bit isPredNew> {
1059 let isPredicatedNew = isPredNew in
1060 def NAME : LDInst2<(outs RC:$dst),
1061 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
1062 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1063 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
1067 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1069 let isPredicatedFalse = PredNot in {
1070 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1072 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1076 let isExtendable = 1, neverHasSideEffects = 1 in
1077 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1078 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1079 bits<5> PredImmBits> {
1081 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1082 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1083 isPredicable = 1, AddedComplexity = 20 in
1084 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1085 "$dst = "#mnemonic#"($src1+#$offset)",
1088 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1089 isPredicated = 1 in {
1090 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
1091 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
1096 let addrMode = BaseImmOffset in {
1097 let accessSize = ByteAccess in {
1098 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1099 11, 6>, AddrModeRel;
1100 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1101 11, 6>, AddrModeRel;
1103 let accessSize = HalfWordAccess in {
1104 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1105 12, 7>, AddrModeRel;
1106 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1107 12, 7>, AddrModeRel;
1109 let accessSize = WordAccess in
1110 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1111 13, 8>, AddrModeRel;
1113 let accessSize = DoubleWordAccess in
1114 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1115 14, 9>, AddrModeRel;
1118 let AddedComplexity = 20 in {
1119 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1120 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1122 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1123 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1125 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1126 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1128 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1129 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1131 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1132 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1134 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1135 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1138 //===----------------------------------------------------------------------===//
1139 // Post increment load
1140 //===----------------------------------------------------------------------===//
1142 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1143 bit isNot, bit isPredNew> {
1144 let isPredicatedNew = isPredNew in
1145 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1146 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1147 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1148 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1153 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1154 Operand ImmOp, bit PredNot> {
1155 let isPredicatedFalse = PredNot in {
1156 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1158 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1159 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1163 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1166 let BaseOpcode = "POST_"#BaseOp in {
1167 let isPredicable = 1 in
1168 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1169 (ins IntRegs:$src1, ImmOp:$offset),
1170 "$dst = "#mnemonic#"($src1++#$offset)",
1174 let isPredicated = 1 in {
1175 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1176 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1181 let hasCtrlDep = 1, neverHasSideEffects = 1, addrMode = PostInc in {
1182 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1184 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1186 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1188 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1190 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1192 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1196 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1197 (i32 (LDrib ADDRriS11_0:$addr)) >;
1199 // Load byte any-extend.
1200 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1201 (i32 (LDrib ADDRriS11_0:$addr)) >;
1203 // Indexed load byte any-extend.
1204 let AddedComplexity = 20 in
1205 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1206 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1208 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1209 (i32 (LDrih ADDRriS11_1:$addr))>;
1211 let AddedComplexity = 20 in
1212 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1213 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1215 let AddedComplexity = 10 in
1216 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1217 (i32 (LDriub ADDRriS11_0:$addr))>;
1219 let AddedComplexity = 20 in
1220 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1221 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1224 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1225 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1226 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1228 "Error; should not emit",
1231 // Deallocate stack frame.
1232 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1233 def DEALLOCFRAME : LDInst2<(outs), (ins),
1238 // Load and unpack bytes to halfwords.
1239 //===----------------------------------------------------------------------===//
1241 //===----------------------------------------------------------------------===//
1243 //===----------------------------------------------------------------------===//
1245 //===----------------------------------------------------------------------===//
1246 //===----------------------------------------------------------------------===//
1248 //===----------------------------------------------------------------------===//
1250 //===----------------------------------------------------------------------===//
1252 //===----------------------------------------------------------------------===//
1253 //===----------------------------------------------------------------------===//
1255 //===----------------------------------------------------------------------===//
1257 //===----------------------------------------------------------------------===//
1259 //===----------------------------------------------------------------------===//
1260 // Multiply and use lower result.
1262 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1263 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1264 "$dst =+ mpyi($src1, #$src2)",
1265 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1266 u8ExtPred:$src2))]>;
1269 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1270 "$dst =- mpyi($src1, #$src2)",
1271 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1272 u8ImmPred:$src2)))]>;
1275 // s9 is NOT the same as m9 - but it works.. so far.
1276 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1277 // depending on the value of m9. See Arch Spec.
1278 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1279 CextOpcode = "MPYI", InputType = "imm" in
1280 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1281 "$dst = mpyi($src1, #$src2)",
1282 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1283 s9ExtPred:$src2))]>, ImmRegRel;
1286 let CextOpcode = "MPYI", InputType = "reg" in
1287 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1288 "$dst = mpyi($src1, $src2)",
1289 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1290 (i32 IntRegs:$src2)))]>, ImmRegRel;
1293 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1294 CextOpcode = "MPYI_acc", InputType = "imm" in
1295 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1296 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1297 "$dst += mpyi($src2, #$src3)",
1298 [(set (i32 IntRegs:$dst),
1299 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1300 (i32 IntRegs:$src1)))],
1301 "$src1 = $dst">, ImmRegRel;
1304 let CextOpcode = "MPYI_acc", InputType = "reg" in
1305 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1306 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1307 "$dst += mpyi($src2, $src3)",
1308 [(set (i32 IntRegs:$dst),
1309 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1310 (i32 IntRegs:$src1)))],
1311 "$src1 = $dst">, ImmRegRel;
1314 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1315 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1316 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1317 "$dst -= mpyi($src2, #$src3)",
1318 [(set (i32 IntRegs:$dst),
1319 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1320 u8ExtPred:$src3)))],
1323 // Multiply and use upper result.
1324 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1325 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1327 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1328 "$dst = mpy($src1, $src2)",
1329 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1330 (i32 IntRegs:$src2)))]>;
1332 // Rd=mpy(Rs,Rt):rnd
1334 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1335 "$dst = mpyu($src1, $src2)",
1336 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1337 (i32 IntRegs:$src2)))]>;
1339 // Multiply and use full result.
1341 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1342 "$dst = mpyu($src1, $src2)",
1343 [(set (i64 DoubleRegs:$dst),
1344 (mul (i64 (anyext (i32 IntRegs:$src1))),
1345 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1348 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1349 "$dst = mpy($src1, $src2)",
1350 [(set (i64 DoubleRegs:$dst),
1351 (mul (i64 (sext (i32 IntRegs:$src1))),
1352 (i64 (sext (i32 IntRegs:$src2)))))]>;
1354 // Multiply and accumulate, use full result.
1355 // Rxx[+-]=mpy(Rs,Rt)
1357 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1358 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1359 "$dst += mpy($src2, $src3)",
1360 [(set (i64 DoubleRegs:$dst),
1361 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1362 (i64 (sext (i32 IntRegs:$src3)))),
1363 (i64 DoubleRegs:$src1)))],
1367 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1368 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1369 "$dst -= mpy($src2, $src3)",
1370 [(set (i64 DoubleRegs:$dst),
1371 (sub (i64 DoubleRegs:$src1),
1372 (mul (i64 (sext (i32 IntRegs:$src2))),
1373 (i64 (sext (i32 IntRegs:$src3))))))],
1376 // Rxx[+-]=mpyu(Rs,Rt)
1378 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1379 IntRegs:$src2, IntRegs:$src3),
1380 "$dst += mpyu($src2, $src3)",
1381 [(set (i64 DoubleRegs:$dst),
1382 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1383 (i64 (anyext (i32 IntRegs:$src3)))),
1384 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1387 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1388 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1389 "$dst -= mpyu($src2, $src3)",
1390 [(set (i64 DoubleRegs:$dst),
1391 (sub (i64 DoubleRegs:$src1),
1392 (mul (i64 (anyext (i32 IntRegs:$src2))),
1393 (i64 (anyext (i32 IntRegs:$src3))))))],
1397 let InputType = "reg", CextOpcode = "ADD_acc" in
1398 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1399 IntRegs:$src2, IntRegs:$src3),
1400 "$dst += add($src2, $src3)",
1401 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1402 (i32 IntRegs:$src3)),
1403 (i32 IntRegs:$src1)))],
1404 "$src1 = $dst">, ImmRegRel;
1406 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1407 InputType = "imm", CextOpcode = "ADD_acc" in
1408 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1409 IntRegs:$src2, s8Ext:$src3),
1410 "$dst += add($src2, #$src3)",
1411 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1412 s8_16ExtPred:$src3),
1413 (i32 IntRegs:$src1)))],
1414 "$src1 = $dst">, ImmRegRel;
1416 let CextOpcode = "SUB_acc", InputType = "reg" in
1417 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1418 IntRegs:$src2, IntRegs:$src3),
1419 "$dst -= add($src2, $src3)",
1420 [(set (i32 IntRegs:$dst),
1421 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1422 (i32 IntRegs:$src3))))],
1423 "$src1 = $dst">, ImmRegRel;
1425 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1426 CextOpcode = "SUB_acc", InputType = "imm" in
1427 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1428 IntRegs:$src2, s8Ext:$src3),
1429 "$dst -= add($src2, #$src3)",
1430 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1431 (add (i32 IntRegs:$src2),
1432 s8_16ExtPred:$src3)))],
1433 "$src1 = $dst">, ImmRegRel;
1435 //===----------------------------------------------------------------------===//
1437 //===----------------------------------------------------------------------===//
1439 //===----------------------------------------------------------------------===//
1441 //===----------------------------------------------------------------------===//
1442 //===----------------------------------------------------------------------===//
1444 //===----------------------------------------------------------------------===//
1446 //===----------------------------------------------------------------------===//
1448 //===----------------------------------------------------------------------===//
1449 //===----------------------------------------------------------------------===//
1451 //===----------------------------------------------------------------------===//
1453 //===----------------------------------------------------------------------===//
1455 //===----------------------------------------------------------------------===//
1456 //===----------------------------------------------------------------------===//
1458 //===----------------------------------------------------------------------===//
1460 //===----------------------------------------------------------------------===//
1462 //===----------------------------------------------------------------------===//
1464 // Store doubleword.
1466 //===----------------------------------------------------------------------===//
1467 // Post increment store
1468 //===----------------------------------------------------------------------===//
1470 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1471 bit isNot, bit isPredNew> {
1472 let isPredicatedNew = isPredNew in
1473 def NAME : STInst2PI<(outs IntRegs:$dst),
1474 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1475 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1476 ") ")#mnemonic#"($src2++#$offset) = $src3",
1481 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1482 Operand ImmOp, bit PredNot> {
1483 let isPredicatedFalse = PredNot in {
1484 defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1486 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1487 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1491 let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1492 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1495 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1496 let isPredicable = 1 in
1497 def NAME : STInst2PI<(outs IntRegs:$dst),
1498 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1499 mnemonic#"($src1++#$offset) = $src2",
1503 let isPredicated = 1 in {
1504 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1505 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1510 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1511 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1512 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1514 let isNVStorable = 0 in
1515 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1517 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1518 s4_3ImmPred:$offset),
1519 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1521 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1522 s4_3ImmPred:$offset),
1523 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1525 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1526 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1528 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1529 s4_3ImmPred:$offset),
1530 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1532 //===----------------------------------------------------------------------===//
1533 // multiclass for the store instructions with MEMri operand.
1534 //===----------------------------------------------------------------------===//
1535 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1537 let isPredicatedNew = isPredNew in
1538 def NAME : STInst2<(outs),
1539 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1540 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1541 ") ")#mnemonic#"($addr) = $src2",
1545 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1546 let isPredicatedFalse = PredNot in {
1547 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1550 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1551 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1555 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1556 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1557 bits<5> ImmBits, bits<5> PredImmBits> {
1559 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1560 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1562 def NAME : STInst2<(outs),
1563 (ins MEMri:$addr, RC:$src),
1564 mnemonic#"($addr) = $src",
1567 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1568 isPredicated = 1 in {
1569 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1570 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1575 let addrMode = BaseImmOffset, isMEMri = "true" in {
1576 let accessSize = ByteAccess in
1577 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1579 let accessSize = HalfWordAccess in
1580 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1582 let accessSize = WordAccess in
1583 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1585 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1586 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1589 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1590 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1592 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1593 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1595 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1596 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1598 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1599 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1602 //===----------------------------------------------------------------------===//
1603 // multiclass for the store instructions with base+immediate offset
1605 //===----------------------------------------------------------------------===//
1606 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1607 bit isNot, bit isPredNew> {
1608 let isPredicatedNew = isPredNew in
1609 def NAME : STInst2<(outs),
1610 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1611 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1612 ") ")#mnemonic#"($src2+#$src3) = $src4",
1616 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1618 let isPredicatedFalse = PredNot, isPredicated = 1 in {
1619 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1622 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1623 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1627 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1628 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1629 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1630 bits<5> PredImmBits> {
1632 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1633 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1635 def NAME : STInst2<(outs),
1636 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1637 mnemonic#"($src1+#$src2) = $src3",
1640 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1641 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1642 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1647 let addrMode = BaseImmOffset, InputType = "reg" in {
1648 let accessSize = ByteAccess in
1649 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1650 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1652 let accessSize = HalfWordAccess in
1653 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1654 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1656 let accessSize = WordAccess in
1657 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1658 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1660 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1661 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1662 u6_3Ext, 14, 9>, AddrModeRel;
1665 let AddedComplexity = 10 in {
1666 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1667 s11_0ExtPred:$offset)),
1668 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1669 (i32 IntRegs:$src1))>;
1671 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1672 s11_1ExtPred:$offset)),
1673 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1674 (i32 IntRegs:$src1))>;
1676 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1677 s11_2ExtPred:$offset)),
1678 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1679 (i32 IntRegs:$src1))>;
1681 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1682 s11_3ExtPred:$offset)),
1683 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1684 (i64 DoubleRegs:$src1))>;
1687 // memh(Rx++#s4:1)=Rt.H
1691 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1692 def STriw_pred : STInst2<(outs),
1693 (ins MEMri:$addr, PredRegs:$src1),
1694 "Error; should not emit",
1697 // Allocate stack frame.
1698 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1699 def ALLOCFRAME : STInst2<(outs),
1701 "allocframe(#$amt)",
1704 //===----------------------------------------------------------------------===//
1706 //===----------------------------------------------------------------------===//
1708 //===----------------------------------------------------------------------===//
1710 //===----------------------------------------------------------------------===//
1712 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1713 "$dst = not($src1)",
1714 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1717 // Sign extend word to doubleword.
1718 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1719 "$dst = sxtw($src1)",
1720 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1721 //===----------------------------------------------------------------------===//
1723 //===----------------------------------------------------------------------===//
1725 //===----------------------------------------------------------------------===//
1727 //===----------------------------------------------------------------------===//
1729 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1730 "$dst = clrbit($src1, #$src2)",
1731 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1733 (shl 1, u5ImmPred:$src2))))]>;
1735 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1736 "$dst = clrbit($src1, #$src2)",
1739 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1740 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1741 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1744 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1745 "$dst = setbit($src1, #$src2)",
1746 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1747 (shl 1, u5ImmPred:$src2)))]>;
1749 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1750 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1751 "$dst = setbit($src1, #$src2)",
1754 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1755 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1758 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1759 "$dst = setbit($src1, #$src2)",
1760 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1761 (shl 1, u5ImmPred:$src2)))]>;
1763 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1764 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1765 "$dst = togglebit($src1, #$src2)",
1768 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1769 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1771 // Predicate transfer.
1772 let neverHasSideEffects = 1 in
1773 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1774 "$dst = $src1 /* Should almost never emit this. */",
1777 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1778 "$dst = $src1 /* Should almost never emit this. */",
1779 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1780 //===----------------------------------------------------------------------===//
1782 //===----------------------------------------------------------------------===//
1784 //===----------------------------------------------------------------------===//
1786 //===----------------------------------------------------------------------===//
1787 // Shift by immediate.
1788 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1789 "$dst = asr($src1, #$src2)",
1790 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1791 u5ImmPred:$src2))]>;
1793 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1794 "$dst = asr($src1, #$src2)",
1795 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1796 u6ImmPred:$src2))]>;
1798 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1799 "$dst = asl($src1, #$src2)",
1800 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1801 u5ImmPred:$src2))]>;
1803 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1804 "$dst = asl($src1, #$src2)",
1805 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1806 u6ImmPred:$src2))]>;
1808 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1809 "$dst = lsr($src1, #$src2)",
1810 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1811 u5ImmPred:$src2))]>;
1813 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1814 "$dst = lsr($src1, #$src2)",
1815 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1816 u6ImmPred:$src2))]>;
1818 // Shift by immediate and add.
1819 let AddedComplexity = 100 in
1820 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1822 "$dst = addasl($src1, $src2, #$src3)",
1823 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1824 (shl (i32 IntRegs:$src2),
1825 u3ImmPred:$src3)))]>;
1827 // Shift by register.
1828 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1829 "$dst = asl($src1, $src2)",
1830 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1831 (i32 IntRegs:$src2)))]>;
1833 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1834 "$dst = asr($src1, $src2)",
1835 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1836 (i32 IntRegs:$src2)))]>;
1838 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1839 "$dst = lsl($src1, $src2)",
1840 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1841 (i32 IntRegs:$src2)))]>;
1843 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1844 "$dst = lsr($src1, $src2)",
1845 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1846 (i32 IntRegs:$src2)))]>;
1848 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1849 "$dst = asl($src1, $src2)",
1850 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1851 (i32 IntRegs:$src2)))]>;
1853 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1854 "$dst = lsl($src1, $src2)",
1855 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1856 (i32 IntRegs:$src2)))]>;
1858 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1860 "$dst = asr($src1, $src2)",
1861 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1862 (i32 IntRegs:$src2)))]>;
1864 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1866 "$dst = lsr($src1, $src2)",
1867 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1868 (i32 IntRegs:$src2)))]>;
1870 //===----------------------------------------------------------------------===//
1872 //===----------------------------------------------------------------------===//
1874 //===----------------------------------------------------------------------===//
1876 //===----------------------------------------------------------------------===//
1877 //===----------------------------------------------------------------------===//
1879 //===----------------------------------------------------------------------===//
1881 //===----------------------------------------------------------------------===//
1883 //===----------------------------------------------------------------------===//
1884 //===----------------------------------------------------------------------===//
1886 //===----------------------------------------------------------------------===//
1888 //===----------------------------------------------------------------------===//
1890 //===----------------------------------------------------------------------===//
1892 //===----------------------------------------------------------------------===//
1894 //===----------------------------------------------------------------------===//
1895 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1896 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1899 let hasSideEffects = 1, isSolo = 1 in
1900 def BARRIER : SYSInst<(outs), (ins),
1902 [(HexagonBARRIER)]>;
1904 //===----------------------------------------------------------------------===//
1906 //===----------------------------------------------------------------------===//
1908 // TFRI64 - assembly mapped.
1909 let isReMaterializable = 1 in
1910 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1912 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1914 // Pseudo instruction to encode a set of conditional transfers.
1915 // This instruction is used instead of a mux and trades-off codesize
1916 // for performance. We conduct this transformation optimistically in
1917 // the hope that these instructions get promoted to dot-new transfers.
1918 let AddedComplexity = 100, isPredicated = 1 in
1919 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1922 "Error; should not emit",
1923 [(set (i32 IntRegs:$dst),
1924 (i32 (select (i1 PredRegs:$src1),
1925 (i32 IntRegs:$src2),
1926 (i32 IntRegs:$src3))))]>;
1927 let AddedComplexity = 100, isPredicated = 1 in
1928 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1929 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1930 "Error; should not emit",
1931 [(set (i32 IntRegs:$dst),
1932 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1933 s12ImmPred:$src3)))]>;
1935 let AddedComplexity = 100, isPredicated = 1 in
1936 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1937 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1938 "Error; should not emit",
1939 [(set (i32 IntRegs:$dst),
1940 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1941 (i32 IntRegs:$src3))))]>;
1943 let AddedComplexity = 100, isPredicated = 1 in
1944 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1945 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1946 "Error; should not emit",
1947 [(set (i32 IntRegs:$dst),
1948 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1949 s12ImmPred:$src3)))]>;
1951 // Generate frameindex addresses.
1952 let isReMaterializable = 1 in
1953 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1954 "$dst = add($src1)",
1955 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1960 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1961 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1962 "loop0($offset, #$src2)",
1966 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1967 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1968 "loop0($offset, $src2)",
1972 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1973 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1974 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
1979 // Support for generating global address.
1980 // Taken from X86InstrInfo.td.
1981 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1985 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1986 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
1988 // HI/LO Instructions
1989 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1990 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1991 "$dst.l = #LO($global)",
1994 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1995 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1996 "$dst.h = #HI($global)",
1999 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2000 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2001 "$dst.l = #LO($imm_value)",
2005 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2006 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2007 "$dst.h = #HI($imm_value)",
2010 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2011 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2012 "$dst.l = #LO($jt)",
2015 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2016 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2017 "$dst.h = #HI($jt)",
2021 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2022 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2023 "$dst.l = #LO($label)",
2026 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2027 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2028 "$dst.h = #HI($label)",
2031 // This pattern is incorrect. When we add small data, we should change
2032 // this pattern to use memw(#foo).
2033 // This is for sdata.
2034 let isMoveImm = 1 in
2035 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2036 "$dst = CONST32(#$global)",
2037 [(set (i32 IntRegs:$dst),
2038 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2040 // This is for non-sdata.
2041 let isReMaterializable = 1, isMoveImm = 1 in
2042 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2043 "$dst = CONST32(#$global)",
2044 [(set (i32 IntRegs:$dst),
2045 (HexagonCONST32 tglobaladdr:$global))]>;
2047 let isReMaterializable = 1, isMoveImm = 1 in
2048 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2049 "$dst = CONST32(#$jt)",
2050 [(set (i32 IntRegs:$dst),
2051 (HexagonCONST32 tjumptable:$jt))]>;
2053 let isReMaterializable = 1, isMoveImm = 1 in
2054 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2055 "$dst = CONST32(#$global)",
2056 [(set (i32 IntRegs:$dst),
2057 (HexagonCONST32_GP tglobaladdr:$global))]>;
2059 let isReMaterializable = 1, isMoveImm = 1 in
2060 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2061 "$dst = CONST32(#$global)",
2062 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2064 // Map BlockAddress lowering to CONST32_Int_Real
2065 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
2066 (CONST32_Int_Real tblockaddress:$addr)>;
2068 let isReMaterializable = 1, isMoveImm = 1 in
2069 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2070 "$dst = CONST32($label)",
2071 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2073 let isReMaterializable = 1, isMoveImm = 1 in
2074 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2075 "$dst = CONST64(#$global)",
2076 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2078 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2079 "$dst = xor($dst, $dst)",
2080 [(set (i1 PredRegs:$dst), 0)]>;
2082 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2083 "$dst = mpy($src1, $src2)",
2084 [(set (i32 IntRegs:$dst),
2085 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2086 (i64 (sext (i32 IntRegs:$src2))))),
2089 // Pseudo instructions.
2090 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2092 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2093 SDTCisVT<1, i32> ]>;
2095 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2096 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2098 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2099 [SDNPHasChain, SDNPOutGlue]>;
2101 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2103 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2104 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2106 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2107 // Optional Flag and Variable Arguments.
2108 // Its 1 Operand has pointer type.
2109 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2110 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2112 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2113 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2114 "Should never be emitted",
2115 [(callseq_start timm:$amt)]>;
2118 let Defs = [R29, R30, R31], Uses = [R29] in {
2119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2120 "Should never be emitted",
2121 [(callseq_end timm:$amt1, timm:$amt2)]>;
2124 let isCall = 1, neverHasSideEffects = 1,
2125 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2126 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2127 def CALL : JInst<(outs), (ins calltarget:$dst),
2131 // Call subroutine from register.
2132 let isCall = 1, neverHasSideEffects = 1,
2133 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2134 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2135 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2141 // Indirect tail-call.
2142 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
2143 def TCRETURNR : T_JMPr;
2145 // Direct tail-calls.
2146 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
2147 isTerminator = 1, isCodeGenOnly = 1 in {
2148 def TCRETURNtg : T_JMP<(ins calltarget:$dst)>;
2149 def TCRETURNtext : T_JMP<(ins calltarget:$dst)>;
2152 // Map call instruction.
2153 def : Pat<(call (i32 IntRegs:$dst)),
2154 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2155 def : Pat<(call tglobaladdr:$dst),
2156 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2157 def : Pat<(call texternalsym:$dst),
2158 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2160 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2161 (TCRETURNtg tglobaladdr:$dst)>;
2162 def : Pat<(HexagonTCRet texternalsym:$dst),
2163 (TCRETURNtext texternalsym:$dst)>;
2164 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2165 (TCRETURNR (i32 IntRegs:$dst))>;
2167 // Atomic load and store support
2168 // 8 bit atomic load
2169 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2170 (i32 (LDriub ADDRriS11_0:$src1))>;
2172 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2173 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2175 // 16 bit atomic load
2176 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2177 (i32 (LDriuh ADDRriS11_1:$src1))>;
2179 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2180 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2182 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2183 (i32 (LDriw ADDRriS11_2:$src1))>;
2185 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2186 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2188 // 64 bit atomic load
2189 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2190 (i64 (LDrid ADDRriS11_3:$src1))>;
2192 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2193 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2196 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2197 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2199 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2200 (i32 IntRegs:$src1)),
2201 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2202 (i32 IntRegs:$src1))>;
2205 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2206 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2208 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2209 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2210 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2211 (i32 IntRegs:$src1))>;
2213 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2214 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2216 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2217 (i32 IntRegs:$src1)),
2218 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2219 (i32 IntRegs:$src1))>;
2224 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2225 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2227 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2228 (i64 DoubleRegs:$src1)),
2229 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2230 (i64 DoubleRegs:$src1))>;
2232 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2233 def : Pat <(and (i32 IntRegs:$src1), 65535),
2234 (ZXTH (i32 IntRegs:$src1))>;
2236 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2237 def : Pat <(and (i32 IntRegs:$src1), 255),
2238 (ZXTB (i32 IntRegs:$src1))>;
2240 // Map Add(p1, true) to p1 = not(p1).
2241 // Add(p1, false) should never be produced,
2242 // if it does, it got to be mapped to NOOP.
2243 def : Pat <(add (i1 PredRegs:$src1), -1),
2244 (NOT_p (i1 PredRegs:$src1))>;
2246 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2247 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2248 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2249 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2250 (i32 IntRegs:$src3),
2251 (i32 IntRegs:$src4)),
2252 (i32 (TFR_condset_rr (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)),
2253 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2254 Requires<[HasV2TOnly]>;
2256 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2257 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2258 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2261 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2262 // => r0 = TFR_condset_ri(p0, r1, #i)
2263 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2264 (i32 IntRegs:$src3)),
2265 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2266 s12ImmPred:$src2))>;
2268 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2269 // => r0 = TFR_condset_ir(p0, #i, r1)
2270 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2271 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2272 (i32 IntRegs:$src2)))>;
2274 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2275 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
2276 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2278 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2279 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
2280 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2283 let AddedComplexity = 100 in
2284 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
2285 (i64 (COMBINE_rr (TFRI 0),
2286 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
2289 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2290 let AddedComplexity = 10 in
2291 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2292 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2294 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2295 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2296 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2298 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2299 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2300 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2301 subreg_loreg))))))>;
2303 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2304 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2305 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2306 subreg_loreg))))))>;
2308 // We want to prevent emitting pnot's as much as possible.
2309 // Map brcond with an unsupported setcc to a JMP_f.
2310 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2312 (JMP_f (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2315 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2317 (JMP_f (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2319 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2320 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2322 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2323 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
2325 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
2326 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2328 (JMP_f (CMPGTri (i32 IntRegs:$src1),
2329 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
2331 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2332 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2334 (JMP_t (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
2336 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2338 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2341 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2343 (JMP_f (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2346 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2348 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2351 // Map from a 64-bit select to an emulated 64-bit mux.
2352 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2353 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2354 (i64 DoubleRegs:$src3)),
2355 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2356 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2358 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2360 (i32 (MUX_rr (i1 PredRegs:$src1),
2361 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2363 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2364 subreg_loreg))))))>;
2366 // Map from a 1-bit select to logical ops.
2367 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2368 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2369 (i1 PredRegs:$src3)),
2370 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2371 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2373 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2374 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2375 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2377 // Map for truncating from 64 immediates to 32 bit immediates.
2378 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2379 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2381 // Map for truncating from i64 immediates to i1 bit immediates.
2382 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2383 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2386 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2387 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2388 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2391 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2392 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2393 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2395 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2396 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2397 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2400 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2401 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2402 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2405 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2406 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2407 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2410 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2411 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2412 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2414 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2415 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2416 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2418 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2419 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2420 // Better way to do this?
2421 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2422 (i64 (SXTW (i32 IntRegs:$src1)))>;
2424 // Map cmple -> cmpgt.
2425 // rs <= rt -> !(rs > rt).
2426 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2427 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
2429 // rs <= rt -> !(rs > rt).
2430 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2431 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2433 // Rss <= Rtt -> !(Rss > Rtt).
2434 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2435 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2437 // Map cmpne -> cmpeq.
2438 // Hexagon_TODO: We should improve on this.
2439 // rs != rt -> !(rs == rt).
2440 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2441 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
2443 // Map cmpne(Rs) -> !cmpeqe(Rs).
2444 // rs != rt -> !(rs == rt).
2445 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2446 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2448 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2449 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2450 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2452 // Map cmpne(Rss) -> !cmpew(Rss).
2453 // rs != rt -> !(rs == rt).
2454 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2455 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2456 (i64 DoubleRegs:$src2)))))>;
2458 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2459 // rs >= rt -> !(rt > rs).
2460 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2461 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2463 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
2464 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
2465 (i1 (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
2467 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2468 // rss >= rtt -> !(rtt > rss).
2469 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2470 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2471 (i64 DoubleRegs:$src1)))))>;
2473 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2474 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2475 // rs < rt -> !(rs >= rt).
2476 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2477 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
2479 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2480 // rs < rt -> rt > rs.
2481 // We can let assembler map it, or we can do in the compiler itself.
2482 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2483 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2485 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2486 // rss < rtt -> (rtt > rss).
2487 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2488 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2490 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2491 // rs < rt -> rt > rs.
2492 // We can let assembler map it, or we can do in the compiler itself.
2493 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2494 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2496 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2497 // rs < rt -> rt > rs.
2498 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2499 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2501 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
2502 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
2503 (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
2505 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
2506 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
2507 (i1 (CMPGTUri (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
2509 // Generate cmpgtu(Rs, #u9)
2510 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
2511 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ExtPred:$src2))>;
2513 // Map from Rs >= Rt -> !(Rt > Rs).
2514 // rs >= rt -> !(rt > rs).
2515 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2516 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2518 // Map from Rs >= Rt -> !(Rt > Rs).
2519 // rs >= rt -> !(rt > rs).
2520 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2521 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2523 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
2524 // Map from (Rs <= Rt) -> !(Rs > Rt).
2525 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2526 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2528 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2529 // Map from (Rs <= Rt) -> !(Rs > Rt).
2530 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2531 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2535 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2536 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2539 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2540 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2542 // Convert sign-extended load back to load and sign extend.
2544 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2545 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2547 // Convert any-extended load back to load and sign extend.
2549 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2550 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2552 // Convert sign-extended load back to load and sign extend.
2554 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2555 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2557 // Convert sign-extended load back to load and sign extend.
2559 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2560 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2565 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2566 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2569 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2570 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2574 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2575 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2579 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2580 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2583 let AddedComplexity = 20 in
2584 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2585 s11_0ExtPred:$offset))),
2586 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2587 s11_0ExtPred:$offset)))>,
2591 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
2592 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2595 let AddedComplexity = 20 in
2596 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
2597 s11_0ExtPred:$offset))),
2598 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2599 s11_0ExtPred:$offset)))>,
2603 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2604 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2607 let AddedComplexity = 20 in
2608 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2609 s11_1ExtPred:$offset))),
2610 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2611 s11_1ExtPred:$offset)))>,
2615 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2616 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2619 let AddedComplexity = 100 in
2620 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2621 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2622 s11_2ExtPred:$offset)))>,
2625 let AddedComplexity = 10 in
2626 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2627 (i32 (LDriw ADDRriS11_0:$src1))>;
2629 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2630 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2631 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2633 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2634 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2635 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2637 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2638 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2639 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2642 let AddedComplexity = 100 in
2643 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2645 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2646 s11_2ExtPred:$offset2)))))),
2647 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2648 (LDriw_indexed IntRegs:$src2,
2649 s11_2ExtPred:$offset2)))>;
2651 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2653 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2654 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2655 (LDriw ADDRriS11_2:$srcLow)))>;
2657 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2659 (i64 (zext (i32 IntRegs:$srcLow))))),
2660 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2663 let AddedComplexity = 100 in
2664 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2666 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2667 s11_2ExtPred:$offset2)))))),
2668 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2669 (LDriw_indexed IntRegs:$src2,
2670 s11_2ExtPred:$offset2)))>;
2672 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2674 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2675 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2676 (LDriw ADDRriS11_2:$srcLow)))>;
2678 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2680 (i64 (zext (i32 IntRegs:$srcLow))))),
2681 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2684 // Any extended 64-bit load.
2685 // anyext i32 -> i64
2686 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2687 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2690 // When there is an offset we should prefer the pattern below over the pattern above.
2691 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2692 // So this complexity below is comfortably higher to allow for choosing the below.
2693 // If this is not done then we generate addresses such as
2694 // ********************************************
2695 // r1 = add (r0, #4)
2696 // r1 = memw(r1 + #0)
2698 // r1 = memw(r0 + #4)
2699 // ********************************************
2700 let AddedComplexity = 100 in
2701 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2702 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2703 s11_2ExtPred:$offset)))>,
2706 // anyext i16 -> i64.
2707 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2708 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2711 let AddedComplexity = 20 in
2712 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2713 s11_1ExtPred:$offset))),
2714 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2715 s11_1ExtPred:$offset)))>,
2718 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2719 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2720 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2723 // Multiply 64-bit unsigned and use upper result.
2724 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2739 (COMBINE_rr (TFRI 0),
2745 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2747 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2748 subreg_loreg)))), 32)),
2750 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2751 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2752 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2753 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2754 32)), subreg_loreg)))),
2755 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2756 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2758 // Multiply 64-bit signed and use upper result.
2759 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2763 (COMBINE_rr (TFRI 0),
2773 (COMBINE_rr (TFRI 0),
2779 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2781 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2782 subreg_loreg)))), 32)),
2784 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2785 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2786 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2787 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2788 32)), subreg_loreg)))),
2789 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2790 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2792 // Hexagon specific ISD nodes.
2793 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2794 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2795 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2796 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2797 SDTHexagonADJDYNALLOC>;
2798 // Needed to tag these instructions for stack layout.
2799 let usesCustomInserter = 1 in
2800 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2802 "$dst = add($src1, #$src2)",
2803 [(set (i32 IntRegs:$dst),
2804 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2805 s16ImmPred:$src2))]>;
2807 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2808 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2809 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2811 [(set (i32 IntRegs:$dst),
2812 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2814 let AddedComplexity = 100 in
2815 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2816 (COPY (i32 IntRegs:$src1))>;
2818 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2820 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2821 (i32 (CONST32_set_jt tjumptable:$dst))>;
2825 // Multi-class for logical operators :
2826 // Shift by immediate/register and accumulate/logical
2827 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2828 def _ri : SInst_acc<(outs IntRegs:$dst),
2829 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2830 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2831 [(set (i32 IntRegs:$dst),
2832 (OpNode2 (i32 IntRegs:$src1),
2833 (OpNode1 (i32 IntRegs:$src2),
2834 u5ImmPred:$src3)))],
2837 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2838 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2839 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2840 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2841 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2845 // Multi-class for logical operators :
2846 // Shift by register and accumulate/logical (32/64 bits)
2847 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2848 def _rr : SInst_acc<(outs IntRegs:$dst),
2849 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2850 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2851 [(set (i32 IntRegs:$dst),
2852 (OpNode2 (i32 IntRegs:$src1),
2853 (OpNode1 (i32 IntRegs:$src2),
2854 (i32 IntRegs:$src3))))],
2857 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
2858 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2859 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2860 [(set (i64 DoubleRegs:$dst),
2861 (OpNode2 (i64 DoubleRegs:$src1),
2862 (OpNode1 (i64 DoubleRegs:$src2),
2863 (i32 IntRegs:$src3))))],
2868 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
2869 let AddedComplexity = 100 in
2870 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
2871 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
2872 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
2873 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
2876 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
2877 let AddedComplexity = 100 in
2878 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
2879 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
2880 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
2881 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
2884 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
2885 let AddedComplexity = 100 in
2886 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
2889 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
2890 xtype_xor_imm<"asl", shl>;
2892 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
2893 xtype_xor_imm<"lsr", srl>;
2895 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
2896 defm LSL : basic_xtype_reg<"lsl", shl>;
2898 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
2899 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
2900 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2902 //===----------------------------------------------------------------------===//
2903 // V3 Instructions +
2904 //===----------------------------------------------------------------------===//
2906 include "HexagonInstrInfoV3.td"
2908 //===----------------------------------------------------------------------===//
2909 // V3 Instructions -
2910 //===----------------------------------------------------------------------===//
2912 //===----------------------------------------------------------------------===//
2913 // V4 Instructions +
2914 //===----------------------------------------------------------------------===//
2916 include "HexagonInstrInfoV4.td"
2918 //===----------------------------------------------------------------------===//
2919 // V4 Instructions -
2920 //===----------------------------------------------------------------------===//
2922 //===----------------------------------------------------------------------===//
2923 // V5 Instructions +
2924 //===----------------------------------------------------------------------===//
2926 include "HexagonInstrInfoV5.td"
2928 //===----------------------------------------------------------------------===//
2929 // V5 Instructions -
2930 //===----------------------------------------------------------------------===//