1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
66 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
69 : ALU32Inst <(outs PredRegs:$dst),
70 (ins IntRegs:$src1, ImmOp:$src2),
71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
72 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
76 let CextOpcode = mnemonic;
77 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
78 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
82 let Inst{27-24} = 0b0101;
83 let Inst{23-22} = MajOp;
84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
85 let Inst{20-16} = src1;
86 let Inst{13-5} = src2{8-0};
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
94 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
96 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
100 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
101 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
102 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
107 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
108 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
110 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
112 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
113 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
115 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
116 "$Rd = "#mnemonic#"($Rs, $Rt)",
117 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
118 let isCommutable = IsComm;
119 let BaseOpcode = mnemonic#_rr;
120 let CextOpcode = mnemonic;
128 let Inst{26-24} = MajOp;
129 let Inst{23-21} = MinOp;
130 let Inst{20-16} = !if(OpsRev,Rt,Rs);
131 let Inst{12-8} = !if(OpsRev,Rs,Rt);
135 let hasSideEffects = 0, hasNewValue = 1 in
136 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
137 bit OpsRev, bit PredNot, bit PredNew>
138 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
139 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
140 "$Rd = "#mnemonic#"($Rs, $Rt)",
141 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
142 let isPredicated = 1;
143 let isPredicatedFalse = PredNot;
144 let isPredicatedNew = PredNew;
145 let BaseOpcode = mnemonic#_rr;
146 let CextOpcode = mnemonic;
155 let Inst{26-24} = MajOp;
156 let Inst{23-21} = MinOp;
157 let Inst{20-16} = !if(OpsRev,Rt,Rs);
158 let Inst{13} = PredNew;
159 let Inst{12-8} = !if(OpsRev,Rs,Rt);
160 let Inst{7} = PredNot;
165 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
167 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
168 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
171 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
172 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
173 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
174 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
176 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
177 bits<3> MinOp, bit OpsRev, bit IsComm>
178 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
179 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
182 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
183 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
185 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in {
186 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
187 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
188 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
189 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
190 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
191 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
194 let Itinerary = ALU32_3op_tc_2_SLOT0123 in
195 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
197 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
198 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
200 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
202 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
203 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
204 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
205 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
208 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
209 bit OpsRev, bit IsComm> {
210 let isPredicable = 1 in
211 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
212 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
215 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
216 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
217 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
218 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
219 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
221 // Pats for instruction selection.
222 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
223 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
224 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
226 def: BinOp32_pat<add, A2_add, i32>;
227 def: BinOp32_pat<and, A2_and, i32>;
228 def: BinOp32_pat<or, A2_or, i32>;
229 def: BinOp32_pat<sub, A2_sub, i32>;
230 def: BinOp32_pat<xor, A2_xor, i32>;
232 // A few special cases producing register pairs:
233 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
234 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
236 let isPredicable = 1 in
237 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
239 // Conditional combinew uses "newt/f" instead of "t/fnew".
240 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
241 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
242 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
243 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
246 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
247 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
248 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
249 "$Pd = "#mnemonic#"($Rs, $Rt)",
250 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
251 let CextOpcode = mnemonic;
252 let isCommutable = IsComm;
258 let Inst{27-24} = 0b0010;
259 let Inst{22-21} = MinOp;
260 let Inst{20-16} = Rs;
263 let Inst{3-2} = 0b00;
267 let Itinerary = ALU32_3op_tc_2early_SLOT0123 in {
268 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
269 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
270 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
273 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
274 // that reverse the order of the operands.
275 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
277 // Pats for compares. They use PatFrags as operands, not SDNodes,
278 // since seteq/setgt/etc. are defined as ParFrags.
279 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
280 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
281 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
283 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
284 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
285 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
287 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
288 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
290 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in
291 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
292 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
293 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
299 let CextOpcode = "mux";
300 let InputType = "reg";
301 let hasSideEffects = 0;
304 let Inst{27-24} = 0b0100;
305 let Inst{20-16} = Rs;
311 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
312 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
314 // Combines the two immediates into a double register.
315 // Increase complexity to make it greater than any complexity of a combine
316 // that involves a register.
318 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
319 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
320 AddedComplexity = 75 in
321 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
322 "$Rdd = combine(#$s8, #$S8)",
323 [(set (i64 DoubleRegs:$Rdd),
324 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
330 let Inst{27-23} = 0b11000;
331 let Inst{22-16} = S8{7-1};
332 let Inst{13} = S8{0};
337 //===----------------------------------------------------------------------===//
338 // Template class for predicated ADD of a reg and an Immediate value.
339 //===----------------------------------------------------------------------===//
340 let hasNewValue = 1, hasSideEffects = 0 in
341 class T_Addri_Pred <bit PredNot, bit PredNew>
342 : ALU32_ri <(outs IntRegs:$Rd),
343 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
344 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
345 ") $Rd = ")#"add($Rs, #$s8)"> {
351 let isPredicatedNew = PredNew;
354 let Inst{27-24} = 0b0100;
355 let Inst{23} = PredNot;
356 let Inst{22-21} = Pu;
357 let Inst{20-16} = Rs;
358 let Inst{13} = PredNew;
363 //===----------------------------------------------------------------------===//
364 // A2_addi: Add a signed immediate to a register.
365 //===----------------------------------------------------------------------===//
366 let hasNewValue = 1, hasSideEffects = 0 in
367 class T_Addri <Operand immOp>
368 : ALU32_ri <(outs IntRegs:$Rd),
369 (ins IntRegs:$Rs, immOp:$s16),
370 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
377 let Inst{27-21} = s16{15-9};
378 let Inst{20-16} = Rs;
379 let Inst{13-5} = s16{8-0};
383 //===----------------------------------------------------------------------===//
384 // Multiclass for ADD of a register and an immediate value.
385 //===----------------------------------------------------------------------===//
386 multiclass Addri_Pred<string mnemonic, bit PredNot> {
387 let isPredicatedFalse = PredNot in {
388 def NAME : T_Addri_Pred<PredNot, 0>;
390 def NAME#new : T_Addri_Pred<PredNot, 1>;
394 let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
395 multiclass Addri_base<string mnemonic, SDNode OpNode> {
396 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
397 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
398 def A2_#NAME : T_Addri<s16Ext>;
400 let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
401 defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
402 defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
407 defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
409 def: Pat<(i32 (add I32:$Rs, s16ExtPred:$s16)),
410 (i32 (A2_addi I32:$Rs, imm:$s16))>;
412 //===----------------------------------------------------------------------===//
413 // Template class used for the following ALU32 instructions.
416 //===----------------------------------------------------------------------===//
417 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
418 InputType = "imm", hasNewValue = 1 in
419 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
420 : ALU32_ri <(outs IntRegs:$Rd),
421 (ins IntRegs:$Rs, s10Ext:$s10),
422 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
423 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
427 let CextOpcode = mnemonic;
431 let Inst{27-24} = 0b0110;
432 let Inst{23-22} = MinOp;
433 let Inst{21} = s10{9};
434 let Inst{20-16} = Rs;
435 let Inst{13-5} = s10{8-0};
439 def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
440 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
442 // Subtract register from immediate
443 // Rd32=sub(#s10,Rs32)
444 let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1,
445 opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
446 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
447 "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
454 let Inst{27-22} = 0b011001;
455 let Inst{21} = s10{9};
456 let Inst{20-16} = Rs;
457 let Inst{13-5} = s10{8-0};
462 let hasSideEffects = 0 in
463 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
465 let Inst{27-24} = 0b1111;
468 def: Pat<(sub s10ExtPred:$s10, IntRegs:$Rs),
469 (A2_subri imm:$s10, IntRegs:$Rs)>;
471 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
472 def: Pat<(not (i32 IntRegs:$src1)),
473 (A2_subri -1, IntRegs:$src1)>;
475 let hasSideEffects = 0, hasNewValue = 1 in
476 class T_tfr16<bit isHi>
477 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
478 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
479 [], "$src1 = $Rx" > {
484 let Inst{27-26} = 0b00;
485 let Inst{25-24} = !if(isHi, 0b10, 0b01);
486 let Inst{23-22} = u16{15-14};
488 let Inst{20-16} = Rx;
489 let Inst{13-0} = u16{13-0};
492 def A2_tfril: T_tfr16<0>;
493 def A2_tfrih: T_tfr16<1>;
495 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
496 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
497 class T_tfr_pred<bit isPredNot, bit isPredNew>
498 : ALU32Inst<(outs IntRegs:$dst),
499 (ins PredRegs:$src1, IntRegs:$src2),
500 "if ("#!if(isPredNot, "!", "")#
501 "$src1"#!if(isPredNew, ".new", "")#
507 let isPredicatedFalse = isPredNot;
508 let isPredicatedNew = isPredNew;
511 let Inst{27-24} = 0b0100;
512 let Inst{23} = isPredNot;
513 let Inst{13} = isPredNew;
516 let Inst{22-21} = src1;
517 let Inst{20-16} = src2;
520 let isPredicable = 1 in
521 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
528 let Inst{27-21} = 0b0000011;
529 let Inst{20-16} = src;
534 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
535 multiclass tfr_base<string CextOp> {
536 let CextOpcode = CextOp, BaseOpcode = CextOp in {
540 def t : T_tfr_pred<0, 0>;
541 def f : T_tfr_pred<1, 0>;
543 def tnew : T_tfr_pred<0, 1>;
544 def fnew : T_tfr_pred<1, 1>;
548 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
549 // Please don't add bits to this instruction as it'll be converted into
550 // 'combine' before object code emission.
551 let isPredicated = 1 in
552 class T_tfrp_pred<bit PredNot, bit PredNew>
553 : ALU32_rr <(outs DoubleRegs:$dst),
554 (ins PredRegs:$src1, DoubleRegs:$src2),
555 "if ("#!if(PredNot, "!", "")#"$src1"
556 #!if(PredNew, ".new", "")#") $dst = $src2" > {
557 let isPredicatedFalse = PredNot;
558 let isPredicatedNew = PredNew;
561 // Assembler mapped to A2_combinew.
562 // Please don't add bits to this instruction as it'll be converted into
563 // 'combine' before object code emission.
564 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
565 (ins DoubleRegs:$src),
568 let hasSideEffects = 0 in
569 multiclass TFR64_base<string BaseName> {
570 let BaseOpcode = BaseName in {
571 let isPredicable = 1 in
574 def t : T_tfrp_pred <0, 0>;
575 def f : T_tfrp_pred <1, 0>;
577 def tnew : T_tfrp_pred <0, 1>;
578 def fnew : T_tfrp_pred <1, 1>;
582 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
583 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
584 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
585 class T_TFRI_Pred<bit PredNot, bit PredNew>
586 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
587 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
588 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
589 let isPredicatedFalse = PredNot;
590 let isPredicatedNew = PredNew;
597 let Inst{27-24} = 0b1110;
598 let Inst{23} = PredNot;
599 let Inst{22-21} = Pu;
601 let Inst{19-16,12-5} = s12;
602 let Inst{13} = PredNew;
606 def C2_cmoveit : T_TFRI_Pred<0, 0>;
607 def C2_cmoveif : T_TFRI_Pred<1, 0>;
608 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
609 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
611 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
612 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
613 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
614 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
615 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
616 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
622 let Inst{27-24} = 0b1000;
623 let Inst{23-22,20-16,13-5} = s16;
627 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
628 let isAsmParserOnly = 1 in
629 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
632 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
633 isAsmParserOnly = 1 in
634 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
636 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
638 // TODO: see if this instruction can be deleted..
639 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
640 isAsmParserOnly = 1 in
641 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 //===----------------------------------------------------------------------===//
652 // Scalar mux register immediate.
653 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
654 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
655 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
656 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
663 let Inst{27-24} = 0b0011;
664 let Inst{23} = MajOp;
665 let Inst{22-21} = Pu;
666 let Inst{20-16} = Rs;
672 let opExtendable = 2 in
673 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
674 "$Rd = mux($Pu, #$s8, $Rs)">;
676 let opExtendable = 3 in
677 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
678 "$Rd = mux($Pu, $Rs, #$s8)">;
680 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
681 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
683 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
684 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
686 // C2_muxii: Scalar mux immediates.
687 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
688 opExtentBits = 8, opExtendable = 2 in
689 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
690 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
691 "$Rd = mux($Pu, #$s8, #$S8)" ,
692 [(set (i32 IntRegs:$Rd),
693 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
701 let Inst{27-25} = 0b101;
702 let Inst{24-23} = Pu;
703 let Inst{22-16} = S8{7-1};
704 let Inst{13} = S8{0};
709 //===----------------------------------------------------------------------===//
710 // template class for non-predicated alu32_2op instructions
711 // - aslh, asrh, sxtb, sxth, zxth
712 //===----------------------------------------------------------------------===//
713 let hasNewValue = 1, opNewValue = 0 in
714 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
715 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
716 "$Rd = "#mnemonic#"($Rs)", [] > {
722 let Inst{27-24} = 0b0000;
723 let Inst{23-21} = minOp;
726 let Inst{20-16} = Rs;
729 //===----------------------------------------------------------------------===//
730 // template class for predicated alu32_2op instructions
731 // - aslh, asrh, sxtb, sxth, zxtb, zxth
732 //===----------------------------------------------------------------------===//
733 let hasSideEffects = 0, validSubTargets = HasV4SubT,
734 hasNewValue = 1, opNewValue = 0 in
735 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
737 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
738 !if(isPredNot, "if (!$Pu", "if ($Pu")
739 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
746 let Inst{27-24} = 0b0000;
747 let Inst{23-21} = minOp;
749 let Inst{11} = isPredNot;
750 let Inst{10} = isPredNew;
753 let Inst{20-16} = Rs;
756 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
757 let isPredicatedFalse = PredNot in {
758 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
761 let isPredicatedNew = 1 in
762 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
766 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
767 let BaseOpcode = mnemonic in {
768 let isPredicable = 1, hasSideEffects = 0 in
769 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
771 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
772 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
773 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
778 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
779 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
780 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
781 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
782 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
784 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
785 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
786 // predicated forms while 'and' doesn't. Since integrated assembler can't
787 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
788 // immediate operand is set to '255'.
790 let hasNewValue = 1, opNewValue = 0 in
791 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
792 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
799 let Inst{27-22} = 0b011000;
801 let Inst{20-16} = Rs;
802 let Inst{21} = s10{9};
803 let Inst{13-5} = s10{8-0};
806 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
807 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
808 let BaseOpcode = mnemonic in {
809 let isPredicable = 1, hasSideEffects = 0 in
810 def A2_#NAME : T_ZXTB;
812 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
813 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
814 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
819 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
821 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
822 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
823 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
824 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
826 //===----------------------------------------------------------------------===//
827 // Template class for vector add and avg
828 //===----------------------------------------------------------------------===//
830 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
831 bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
832 : ALU64_rr < (outs DoubleRegs:$Rdd),
833 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
834 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
835 #!if(isCrnd,":crnd","")
836 #!if(isSat, ":sat", ""),
837 [], "", ALU64_tc_2_SLOT23 > {
844 let Inst{27-24} = 0b0011;
845 let Inst{23-21} = majOp;
846 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
847 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
848 let Inst{7-5} = minOp;
852 // ALU64 - Vector add
853 // Rdd=vadd[u][bhw](Rss,Rtt)
854 let Itinerary = ALU64_tc_1_SLOT23 in {
855 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
856 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
857 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
860 // Rdd=vadd[u][bhw](Rss,Rtt):sat
861 let Defs = [USR_OVF] in {
862 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
863 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
864 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
865 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
868 // ALU64 - Vector average
869 // Rdd=vavg[u][bhw](Rss,Rtt)
870 let Itinerary = ALU64_tc_1_SLOT23 in {
871 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
872 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
873 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
874 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
875 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
878 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
879 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
880 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
881 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
882 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
884 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
885 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
886 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
888 // Rdd=vnavg[bh](Rss,Rtt)
889 let Itinerary = ALU64_tc_1_SLOT23 in {
890 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
891 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
894 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
895 let Defs = [USR_OVF] in {
896 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
897 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
898 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
899 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
902 // Rdd=vsub[u][bh](Rss,Rtt)
903 let Itinerary = ALU64_tc_1_SLOT23 in {
904 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
905 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
906 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
909 // Rdd=vsub[u][bh](Rss,Rtt):sat
910 let Defs = [USR_OVF] in {
911 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
912 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
913 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
914 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
917 // Rdd=vmax[u][bhw](Rss,Rtt)
918 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
919 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
920 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
921 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
922 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
923 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
925 // Rdd=vmin[u][bhw](Rss,Rtt)
926 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
927 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
928 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
929 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
930 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
931 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
933 //===----------------------------------------------------------------------===//
934 // Template class for vector compare
935 //===----------------------------------------------------------------------===//
936 let hasSideEffects = 0 in
937 class T_vcmp <string Str, bits<4> minOp>
938 : ALU64_rr <(outs PredRegs:$Pd),
939 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
940 "$Pd = "#Str#"($Rss, $Rtt)", [],
941 "", ALU64_tc_2early_SLOT23> {
948 let Inst{27-23} = 0b00100;
949 let Inst{13} = minOp{3};
950 let Inst{7-5} = minOp{2-0};
952 let Inst{20-16} = Rss;
953 let Inst{12-8} = Rtt;
956 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
957 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
958 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
960 // Vector compare bytes
961 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
962 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
964 // Vector compare halfwords
965 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
966 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
967 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
969 // Vector compare words
970 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
971 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
972 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
974 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
975 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
976 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
977 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
978 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
979 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
980 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
981 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
983 //===----------------------------------------------------------------------===//
985 //===----------------------------------------------------------------------===//
988 //===----------------------------------------------------------------------===//
990 //===----------------------------------------------------------------------===//
992 //===----------------------------------------------------------------------===//
994 //===----------------------------------------------------------------------===//
997 //===----------------------------------------------------------------------===//
999 //===----------------------------------------------------------------------===//
1001 //===----------------------------------------------------------------------===//
1003 // Add/Subtract halfword
1004 // Rd=add(Rt.L,Rs.[HL])[:sat]
1005 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1006 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1007 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1008 //===----------------------------------------------------------------------===//
1010 let hasNewValue = 1, opNewValue = 0 in
1011 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1012 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1013 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1014 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
1015 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
1016 #!if(isSat,":sat","")
1017 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
1021 let IClass = 0b1101;
1023 let Inst{27-23} = 0b01010;
1024 let Inst{22} = hasShift;
1025 let Inst{21} = isSub;
1026 let Inst{7} = isSat;
1027 let Inst{6-5} = LHbits;
1029 let Inst{12-8} = Rt;
1030 let Inst{20-16} = Rs;
1033 //Rd=sub(Rt.L,Rs.[LH])
1034 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1035 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1037 //Rd=add(Rt.L,Rs.[LH])
1038 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1039 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1041 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1042 //Rd=sub(Rt.L,Rs.[LH]):sat
1043 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1044 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1046 //Rd=add(Rt.L,Rs.[LH]):sat
1047 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1048 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1051 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1052 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1053 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1054 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1055 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1057 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1058 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1059 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1060 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
1061 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1063 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1064 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1065 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1066 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1067 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
1068 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1070 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1071 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1072 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1073 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
1074 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
1078 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
1079 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
1081 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
1082 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1084 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1085 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1087 // Subtract halfword.
1088 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1089 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1091 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1092 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1094 let hasSideEffects = 0, hasNewValue = 1 in
1095 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1096 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1097 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1102 let IClass = 0b1101;
1103 let Inst{27-24} = 0b0000;
1104 let Inst{20-16} = Rs;
1105 let Inst{12-8} = Rt;
1109 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1110 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1111 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1112 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1113 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1118 let IClass = 0b1101;
1120 let Inst{27-23} = 0b01011;
1121 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1122 let Inst{7} = isUnsigned;
1124 let Inst{12-8} = !if(isMax, Rs, Rt);
1125 let Inst{20-16} = !if(isMax, Rt, Rs);
1128 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1129 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1130 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1131 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1133 // Here, depending on the operand being selected, we'll either generate a
1134 // min or max instruction.
1136 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1137 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1138 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1139 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1141 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1142 InstHexagon Inst, InstHexagon SwapInst> {
1143 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1144 (VT RC:$src1), (VT RC:$src2)),
1145 (Inst RC:$src1, RC:$src2)>;
1146 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1147 (VT RC:$src2), (VT RC:$src1)),
1148 (SwapInst RC:$src1, RC:$src2)>;
1152 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1153 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1155 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1156 (i32 PositiveHalfWord:$src2))),
1157 (i32 PositiveHalfWord:$src1),
1158 (i32 PositiveHalfWord:$src2))), i16),
1159 (Inst IntRegs:$src1, IntRegs:$src2)>;
1161 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1162 (i32 PositiveHalfWord:$src2))),
1163 (i32 PositiveHalfWord:$src2),
1164 (i32 PositiveHalfWord:$src1))), i16),
1165 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1168 let AddedComplexity = 200 in {
1169 defm: MinMax_pats<setge, A2_max, A2_min>;
1170 defm: MinMax_pats<setgt, A2_max, A2_min>;
1171 defm: MinMax_pats<setle, A2_min, A2_max>;
1172 defm: MinMax_pats<setlt, A2_min, A2_max>;
1173 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1174 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1175 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1176 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1179 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1180 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1181 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1183 let isCommutable = IsComm;
1184 let hasSideEffects = 0;
1190 let IClass = 0b1101;
1191 let Inst{27-21} = 0b0010100;
1192 let Inst{20-16} = Rs;
1193 let Inst{12-8} = Rt;
1194 let Inst{7-5} = MinOp;
1198 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1199 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1200 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1202 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1203 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1204 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1206 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1207 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1208 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1209 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1210 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1212 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1213 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1214 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1215 let hasSideEffects = 0;
1222 let IClass = 0b1101;
1223 let Inst{27-24} = 0b0001;
1224 let Inst{20-16} = Rs;
1225 let Inst{12-8} = Rt;
1230 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1231 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1233 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1234 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1235 "", ALU64_tc_1_SLOT23> {
1236 let hasSideEffects = 0;
1237 let isCommutable = IsComm;
1243 let IClass = 0b1101;
1244 let Inst{27-24} = RegType;
1245 let Inst{23-21} = MajOp;
1246 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1247 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1248 let Inst{7-5} = MinOp;
1252 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1253 bit OpsRev, bit IsComm>
1254 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1257 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1258 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1260 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1261 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1263 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1265 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1268 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1269 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1270 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1272 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1273 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1274 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1276 //===----------------------------------------------------------------------===//
1278 //===----------------------------------------------------------------------===//
1280 //===----------------------------------------------------------------------===//
1282 //===----------------------------------------------------------------------===//
1284 //===----------------------------------------------------------------------===//
1286 //===----------------------------------------------------------------------===//
1288 //===----------------------------------------------------------------------===//
1290 //===----------------------------------------------------------------------===//
1292 //===----------------------------------------------------------------------===//
1294 //===----------------------------------------------------------------------===//
1296 //===----------------------------------------------------------------------===//
1298 //===----------------------------------------------------------------------===//
1299 // Logical reductions on predicates.
1301 // Looping instructions.
1303 // Pipelined looping instructions.
1305 // Logical operations on predicates.
1306 let hasSideEffects = 0 in
1307 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1308 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1309 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1313 let IClass = 0b0110;
1314 let Inst{27-23} = 0b10111;
1315 let Inst{22-21} = OpBits;
1317 let Inst{17-16} = Ps;
1322 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1323 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1324 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1326 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1327 (C2_not PredRegs:$Ps)>;
1329 let hasSideEffects = 0 in
1330 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1331 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1332 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1333 [], "", CR_tc_2early_SLOT23> {
1338 let IClass = 0b0110;
1339 let Inst{27-24} = 0b1011;
1340 let Inst{23-21} = OpBits;
1342 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1343 let Inst{13} = 0b0; // instructions.
1344 let Inst{9-8} = !if(Rev,Ps,Pt);
1348 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1349 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1350 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1351 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1352 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1354 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1355 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1356 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1357 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1358 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1360 let hasSideEffects = 0, hasNewValue = 1 in
1361 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1362 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1367 let IClass = 0b1000;
1368 let Inst{27-24} = 0b1001;
1369 let Inst{22-21} = 0b00;
1370 let Inst{17-16} = Ps;
1375 let hasSideEffects = 0 in
1376 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1377 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1381 let IClass = 0b1000;
1382 let Inst{27-24} = 0b0110;
1387 // User control register transfer.
1388 //===----------------------------------------------------------------------===//
1390 //===----------------------------------------------------------------------===//
1392 //===----------------------------------------------------------------------===//
1394 //===----------------------------------------------------------------------===//
1396 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1397 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1398 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1400 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1401 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1403 class CondStr<string CReg, bit True, bit New> {
1404 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1406 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1407 string S = Mnemonic # !if(Taken, ":t", !if(New, ":nt", ""));
1410 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1412 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1413 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1414 class T_JMP<string ExtStr>
1415 : JInst<(outs), (ins brtarget:$dst),
1416 "jump " # ExtStr # "$dst",
1417 [], "", J_tc_2early_SLOT23> {
1419 let IClass = 0b0101;
1421 let Inst{27-25} = 0b100;
1422 let Inst{24-16} = dst{23-15};
1423 let Inst{13-1} = dst{14-2};
1426 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1427 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1428 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1429 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1430 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1431 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1432 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1434 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1435 let isTaken = isTak;
1436 let isPredicatedFalse = PredNot;
1437 let isPredicatedNew = isPredNew;
1441 let IClass = 0b0101;
1443 let Inst{27-24} = 0b1100;
1444 let Inst{21} = PredNot;
1445 let Inst{12} = isTak;
1446 let Inst{11} = isPredNew;
1447 let Inst{9-8} = src;
1448 let Inst{23-22} = dst{16-15};
1449 let Inst{20-16} = dst{14-10};
1450 let Inst{13} = dst{9};
1451 let Inst{7-1} = dst{8-2};
1454 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1455 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken
1457 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1458 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1461 multiclass JMP_base<string BaseOp, string ExtStr> {
1462 let BaseOpcode = BaseOp in {
1463 def NAME : T_JMP<ExtStr>;
1464 defm t : JMP_Pred<0, ExtStr>;
1465 defm f : JMP_Pred<1, ExtStr>;
1469 // Jumps to address stored in a register, JUMPR_MISC
1470 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1471 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1472 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1474 : JRInst<(outs), (ins IntRegs:$dst),
1475 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1478 let IClass = 0b0101;
1479 let Inst{27-21} = 0b0010100;
1480 let Inst{20-16} = dst;
1483 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1484 hasSideEffects = 0, InputType = "reg" in
1485 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1486 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1487 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1488 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1489 "", J_tc_2early_SLOT2> {
1491 let isTaken = isTak;
1492 let isPredicatedFalse = PredNot;
1493 let isPredicatedNew = isPredNew;
1497 let IClass = 0b0101;
1499 let Inst{27-22} = 0b001101;
1500 let Inst{21} = PredNot;
1501 let Inst{20-16} = dst;
1502 let Inst{12} = isTak;
1503 let Inst{11} = isPredNew;
1504 let Inst{9-8} = src;
1507 multiclass JMPR_Pred<bit PredNot> {
1508 def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
1510 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1511 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1514 multiclass JMPR_base<string BaseOp> {
1515 let BaseOpcode = BaseOp in {
1517 defm t : JMPR_Pred<0>;
1518 defm f : JMPR_Pred<1>;
1522 let isCall = 1, hasSideEffects = 1 in
1523 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1524 dag InputDag = (ins IntRegs:$Rs)>
1525 : JRInst<(outs), InputDag,
1526 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1527 "if ($Pu) callr $Rs"),
1529 [], "", J_tc_2early_SLOT2> {
1532 let isPredicated = isPred;
1533 let isPredicatedFalse = isPredNot;
1535 let IClass = 0b0101;
1536 let Inst{27-25} = 0b000;
1537 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1539 let Inst{21} = isPredNot;
1540 let Inst{9-8} = !if (isPred, Pu, 0b00);
1541 let Inst{20-16} = Rs;
1545 let Defs = VolatileV3.Regs in {
1546 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1547 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1550 let isTerminator = 1, hasSideEffects = 0 in {
1551 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1553 // Deal with explicit assembly
1554 // - never extened a jump #, always extend a jump ##
1555 let isAsmParserOnly = 1 in {
1556 defm J2_jump_ext : JMP_base<"JMP", "##">;
1557 defm J2_jump_noext : JMP_base<"JMP", "#">;
1560 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1562 let isReturn = 1, isCodeGenOnly = 1 in
1563 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1566 def: Pat<(br bb:$dst),
1567 (J2_jump brtarget:$dst)>;
1569 (JMPret (i32 R31))>;
1570 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1571 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1573 // A return through builtin_eh_return.
1574 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1575 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1576 def EH_RETURN_JMPR : T_JMPr;
1578 def: Pat<(eh_return),
1579 (EH_RETURN_JMPR (i32 R31))>;
1580 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1581 (J2_jumpr IntRegs:$dst)>;
1582 def: Pat<(brind (i32 IntRegs:$dst)),
1583 (J2_jumpr IntRegs:$dst)>;
1585 //===----------------------------------------------------------------------===//
1587 //===----------------------------------------------------------------------===//
1589 //===----------------------------------------------------------------------===//
1591 //===----------------------------------------------------------------------===//
1593 // Load - Base with Immediate offset addressing mode
1594 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1595 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1597 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1598 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1603 bits<11> offsetBits;
1605 string ImmOpStr = !cast<string>(ImmOp);
1606 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1607 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1608 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1609 /* s11_0Ext */ offset{10-0})));
1610 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1611 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1612 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1613 /* s11_0Ext */ 11)));
1614 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
1616 let IClass = 0b1001;
1619 let Inst{26-25} = offsetBits{10-9};
1620 let Inst{24-21} = MajOp;
1621 let Inst{20-16} = src1;
1622 let Inst{13-5} = offsetBits{8-0};
1623 let Inst{4-0} = dst;
1626 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1627 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1628 Operand ImmOp, bit isNot, bit isPredNew>
1629 : LDInst<(outs RC:$dst),
1630 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1631 "if ("#!if(isNot, "!$src1", "$src1")
1632 #!if(isPredNew, ".new", "")
1633 #") $dst = "#mnemonic#"($src2 + #$offset)",
1634 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1640 string ImmOpStr = !cast<string>(ImmOp);
1642 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1643 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1644 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1645 /* u6_0Ext */ offset{5-0})));
1646 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1647 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1648 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1650 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1651 let isPredicatedNew = isPredNew;
1652 let isPredicatedFalse = isNot;
1654 let IClass = 0b0100;
1658 let Inst{26} = isNot;
1659 let Inst{25} = isPredNew;
1660 let Inst{24-21} = MajOp;
1661 let Inst{20-16} = src2;
1663 let Inst{12-11} = src1;
1664 let Inst{10-5} = offsetBits;
1665 let Inst{4-0} = dst;
1668 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1669 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1670 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1671 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1672 let isPredicable = 1 in
1673 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1676 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1677 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1680 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1681 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1685 let accessSize = ByteAccess in {
1686 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1687 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1690 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1691 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1692 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1695 let accessSize = WordAccess, opExtentAlign = 2 in
1696 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1698 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1699 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1701 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1702 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1703 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1706 let accessSize = WordAccess, opExtentAlign = 2 in {
1707 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
1708 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
1711 // Patterns to select load-indexed (i.e. load from base+offset).
1712 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1714 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1715 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1716 (VT (MI IntRegs:$Rs, imm:$Off))>;
1717 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1720 let AddedComplexity = 20 in {
1721 defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
1722 defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
1723 defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
1724 defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
1725 defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
1726 defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
1728 defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1729 defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1730 defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1731 defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
1732 defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
1733 defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1734 defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1735 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1739 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1740 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1742 let AddedComplexity = 20 in
1743 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1744 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1746 //===----------------------------------------------------------------------===//
1747 // Post increment load
1748 //===----------------------------------------------------------------------===//
1749 //===----------------------------------------------------------------------===//
1750 // Template class for non-predicated post increment loads with immediate offset.
1751 //===----------------------------------------------------------------------===//
1752 let hasSideEffects = 0, addrMode = PostInc in
1753 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1755 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1756 (ins IntRegs:$src1, ImmOp:$offset),
1757 "$dst = "#mnemonic#"($src1++#$offset)" ,
1766 string ImmOpStr = !cast<string>(ImmOp);
1767 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1768 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1769 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1770 /* s4_0Imm */ offset{3-0})));
1771 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1773 let IClass = 0b1001;
1775 let Inst{27-25} = 0b101;
1776 let Inst{24-21} = MajOp;
1777 let Inst{20-16} = src1;
1778 let Inst{13-12} = 0b00;
1779 let Inst{8-5} = offsetBits;
1780 let Inst{4-0} = dst;
1783 //===----------------------------------------------------------------------===//
1784 // Template class for predicated post increment loads with immediate offset.
1785 //===----------------------------------------------------------------------===//
1786 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1787 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1788 bits<4> MajOp, bit isPredNot, bit isPredNew >
1789 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1790 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1791 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1792 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1802 let isPredicatedNew = isPredNew;
1803 let isPredicatedFalse = isPredNot;
1805 string ImmOpStr = !cast<string>(ImmOp);
1806 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1807 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1808 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1809 /* s4_0Imm */ offset{3-0})));
1810 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1812 let IClass = 0b1001;
1814 let Inst{27-25} = 0b101;
1815 let Inst{24-21} = MajOp;
1816 let Inst{20-16} = src2;
1818 let Inst{12} = isPredNew;
1819 let Inst{11} = isPredNot;
1820 let Inst{10-9} = src1;
1821 let Inst{8-5} = offsetBits;
1822 let Inst{4-0} = dst;
1825 //===----------------------------------------------------------------------===//
1826 // Multiclass for post increment loads with immediate offset.
1827 //===----------------------------------------------------------------------===//
1829 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1830 Operand ImmOp, bits<4> MajOp> {
1831 let BaseOpcode = "POST_"#BaseOp in {
1832 let isPredicable = 1 in
1833 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1836 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1837 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1840 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1841 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1845 // post increment byte loads with immediate offset
1846 let accessSize = ByteAccess in {
1847 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1848 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1851 // post increment halfword loads with immediate offset
1852 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1853 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1854 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1857 // post increment word loads with immediate offset
1858 let accessSize = WordAccess, opExtentAlign = 2 in
1859 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1861 // post increment doubleword loads with immediate offset
1862 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1863 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1865 // Rd=memb[u]h(Rx++#s4:1)
1866 // Rdd=memb[u]h(Rx++#s4:2)
1867 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1868 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1869 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1871 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in {
1872 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
1873 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
1876 //===----------------------------------------------------------------------===//
1877 // Template class for post increment loads with register offset.
1878 //===----------------------------------------------------------------------===//
1879 let hasSideEffects = 0, addrMode = PostInc in
1880 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1881 MemAccessSize AccessSz>
1882 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1883 (ins IntRegs:$src1, ModRegs:$src2),
1884 "$dst = "#mnemonic#"($src1++$src2)" ,
1885 [], "$src1 = $_dst_" > {
1890 let accessSize = AccessSz;
1891 let IClass = 0b1001;
1893 let Inst{27-25} = 0b110;
1894 let Inst{24-21} = MajOp;
1895 let Inst{20-16} = src1;
1896 let Inst{13} = src2;
1899 let Inst{4-0} = dst;
1902 let hasNewValue = 1 in {
1903 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1904 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1905 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1906 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1907 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
1909 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
1912 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
1913 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
1916 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1917 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
1918 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1919 (ins IntRegs:$addr, s11_2Ext:$off),
1920 ".error \"should not emit\"", []>;
1922 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
1923 def L2_deallocframe : LDInst<(outs), (ins),
1926 let IClass = 0b1001;
1928 let Inst{27-16} = 0b000000011110;
1930 let Inst{4-0} = 0b11110;
1933 // Load / Post increment circular addressing mode.
1934 let Uses = [CS], hasSideEffects = 0 in
1935 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
1936 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
1937 (ins IntRegs:$Rz, ModRegs:$Mu),
1938 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
1944 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
1945 let IClass = 0b1001;
1947 let Inst{27-25} = 0b100;
1948 let Inst{24-21} = MajOp;
1949 let Inst{20-16} = Rz;
1954 let Inst{4-0} = dst;
1957 let accessSize = ByteAccess in {
1958 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
1959 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
1962 let accessSize = HalfWordAccess in {
1963 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
1964 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
1965 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
1966 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
1969 let accessSize = WordAccess in {
1970 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
1971 let hasNewValue = 0 in {
1972 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
1973 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
1977 let accessSize = DoubleWordAccess in
1978 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
1980 //===----------------------------------------------------------------------===//
1981 // Circular loads with immediate offset.
1982 //===----------------------------------------------------------------------===//
1983 let Uses = [CS], mayLoad = 1, hasSideEffects = 0 in
1984 class T_load_pci <string mnemonic, RegisterClass RC,
1985 Operand ImmOp, bits<4> MajOp>
1986 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
1987 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
1988 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
1996 string ImmOpStr = !cast<string>(ImmOp);
1997 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
1998 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1999 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2000 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2001 /* s4_0Imm */ offset{3-0})));
2002 let IClass = 0b1001;
2003 let Inst{27-25} = 0b100;
2004 let Inst{24-21} = MajOp;
2005 let Inst{20-16} = Rz;
2009 let Inst{8-5} = offsetBits;
2010 let Inst{4-0} = dst;
2013 // Byte variants of circ load
2014 let accessSize = ByteAccess in {
2015 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2016 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2019 // Half word variants of circ load
2020 let accessSize = HalfWordAccess in {
2021 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2022 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2023 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2024 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2027 // Word variants of circ load
2028 let accessSize = WordAccess in
2029 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2031 let accessSize = WordAccess, hasNewValue = 0 in {
2032 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
2033 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
2036 let accessSize = DoubleWordAccess, hasNewValue = 0 in
2037 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2039 // L[24]_load[wd]_locked: Load word/double with lock.
2041 class T_load_locked <string mnemonic, RegisterClass RC>
2042 : LD0Inst <(outs RC:$dst),
2044 "$dst = "#mnemonic#"($src)"> {
2047 let IClass = 0b1001;
2048 let Inst{27-21} = 0b0010000;
2049 let Inst{20-16} = src;
2050 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2052 let Inst{4-0} = dst;
2054 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in
2055 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2056 let accessSize = DoubleWordAccess in
2057 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
2059 // S[24]_store[wd]_locked: Store word/double conditionally.
2060 let isSoloAX = 1, isPredicateLate = 1 in
2061 class T_store_locked <string mnemonic, RegisterClass RC>
2062 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2063 mnemonic#"($Rs, $Pd) = $Rt"> {
2068 let IClass = 0b1010;
2069 let Inst{27-23} = 0b00001;
2070 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
2072 let Inst{20-16} = Rs;
2073 let Inst{12-8} = Rt;
2077 let accessSize = WordAccess in
2078 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2080 let accessSize = DoubleWordAccess in
2081 def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
2083 //===----------------------------------------------------------------------===//
2084 // Bit-reversed loads with auto-increment register
2085 //===----------------------------------------------------------------------===//
2086 let hasSideEffects = 0 in
2087 class T_load_pbr<string mnemonic, RegisterClass RC,
2088 MemAccessSize addrSize, bits<4> majOp>
2090 <(outs RC:$dst, IntRegs:$_dst_),
2091 (ins IntRegs:$Rz, ModRegs:$Mu),
2092 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
2093 [] , "$Rz = $_dst_" > {
2095 let accessSize = addrSize;
2101 let IClass = 0b1001;
2103 let Inst{27-25} = 0b111;
2104 let Inst{24-21} = majOp;
2105 let Inst{20-16} = Rz;
2109 let Inst{4-0} = dst;
2112 let hasNewValue =1, opNewValue = 0 in {
2113 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2114 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2115 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2116 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2117 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2118 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2119 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2122 def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
2123 def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
2124 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2126 //===----------------------------------------------------------------------===//
2128 //===----------------------------------------------------------------------===//
2130 //===----------------------------------------------------------------------===//
2132 //===----------------------------------------------------------------------===//
2133 //===----------------------------------------------------------------------===//
2135 //===----------------------------------------------------------------------===//
2137 //===----------------------------------------------------------------------===//
2139 //===----------------------------------------------------------------------===//
2140 //===----------------------------------------------------------------------===//
2142 //===----------------------------------------------------------------------===//
2144 //===----------------------------------------------------------------------===//
2146 //===----------------------------------------------------------------------===//
2148 //===----------------------------------------------------------------------===//
2150 // MPYS / Multipy signed/unsigned halfwords
2151 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2152 //===----------------------------------------------------------------------===//
2154 let hasNewValue = 1, opNewValue = 0 in
2155 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
2156 bit hasShift, bit isUnsigned>
2157 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2158 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2159 #", $Rt."#!if(LHbits{0},"h)","l)")
2160 #!if(hasShift,":<<1","")
2161 #!if(isRnd,":rnd","")
2162 #!if(isSat,":sat",""),
2163 [], "", M_tc_3x_SLOT23 > {
2168 let IClass = 0b1110;
2170 let Inst{27-24} = 0b1100;
2171 let Inst{23} = hasShift;
2172 let Inst{22} = isUnsigned;
2173 let Inst{21} = isRnd;
2174 let Inst{7} = isSat;
2175 let Inst{6-5} = LHbits;
2177 let Inst{20-16} = Rs;
2178 let Inst{12-8} = Rt;
2181 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2182 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2183 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2184 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2185 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2186 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
2187 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
2188 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2189 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2191 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2192 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2193 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2194 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2195 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2196 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2197 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2198 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2199 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2201 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2202 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2203 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2204 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2205 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2206 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2207 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2208 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2209 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2211 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2212 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2213 let Defs = [USR_OVF] in {
2214 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2215 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2216 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2217 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2218 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2219 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2220 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2221 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2223 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2224 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2225 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2226 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2227 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2228 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2229 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2230 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2233 //===----------------------------------------------------------------------===//
2235 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2236 // result from the accumulator.
2237 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2238 //===----------------------------------------------------------------------===//
2240 let hasNewValue = 1, opNewValue = 0 in
2241 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2242 bit hasShift, bit isUnsigned >
2243 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2244 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2245 #"($Rs."#!if(LHbits{1},"h","l")
2246 #", $Rt."#!if(LHbits{0},"h)","l)")
2247 #!if(hasShift,":<<1","")
2248 #!if(isSat,":sat",""),
2249 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2254 let IClass = 0b1110;
2255 let Inst{27-24} = 0b1110;
2256 let Inst{23} = hasShift;
2257 let Inst{22} = isUnsigned;
2258 let Inst{21} = isNac;
2259 let Inst{7} = isSat;
2260 let Inst{6-5} = LHbits;
2262 let Inst{20-16} = Rs;
2263 let Inst{12-8} = Rt;
2266 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2267 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2268 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2269 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2270 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2271 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2272 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2273 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2274 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2276 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2277 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2278 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2279 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2280 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2281 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2282 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2283 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2284 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2286 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2287 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2288 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2289 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2290 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2291 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2292 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2293 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2294 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2296 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2297 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2298 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2299 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2300 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2301 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2302 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2303 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2304 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2306 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2307 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2308 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2309 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2310 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2311 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2312 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2313 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2314 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2316 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2317 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2318 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2319 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2320 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2321 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2322 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2323 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2324 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2326 //===----------------------------------------------------------------------===//
2328 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2329 // result from the 64-bit destination register.
2330 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2331 //===----------------------------------------------------------------------===//
2333 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2334 : MInst_acc<(outs DoubleRegs:$Rxx),
2335 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2336 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2337 #"($Rs."#!if(LHbits{1},"h","l")
2338 #", $Rt."#!if(LHbits{0},"h)","l)")
2339 #!if(hasShift,":<<1",""),
2340 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2345 let IClass = 0b1110;
2347 let Inst{27-24} = 0b0110;
2348 let Inst{23} = hasShift;
2349 let Inst{22} = isUnsigned;
2350 let Inst{21} = isNac;
2352 let Inst{6-5} = LHbits;
2353 let Inst{4-0} = Rxx;
2354 let Inst{20-16} = Rs;
2355 let Inst{12-8} = Rt;
2358 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2359 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2360 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2361 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2363 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2364 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2365 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2366 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2368 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2369 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2370 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2371 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2373 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2374 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2375 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2376 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2378 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2379 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2380 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2381 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2383 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2384 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2385 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2386 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2388 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2389 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2390 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2391 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2393 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2394 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2395 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2396 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2398 //===----------------------------------------------------------------------===//
2399 // Template Class -- Vector Multipy
2400 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2401 //===----------------------------------------------------------------------===//
2402 class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
2403 bit isRnd, bit isSat >
2404 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2405 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2406 #!if(isRnd,":rnd","")
2407 #!if(isSat,":sat",""),
2413 let IClass = 0b1110;
2415 let Inst{27-24} = 0b1000;
2416 let Inst{23-21} = MajOp;
2417 let Inst{7-5} = MinOp;
2418 let Inst{4-0} = Rdd;
2419 let Inst{20-16} = Rss;
2420 let Inst{12-8} = Rtt;
2423 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
2424 let Defs = [USR_OVF] in {
2425 def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
2426 def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
2428 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
2429 def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
2430 def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
2432 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
2433 def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>;
2434 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
2436 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2437 def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>;
2438 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
2440 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
2441 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
2442 def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>;
2443 def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>;
2444 def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>;
2446 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
2447 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
2448 def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>;
2449 def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>;
2450 def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>;
2452 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
2453 def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>;
2454 def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>;
2455 def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>;
2456 def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>;
2458 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
2459 def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>;
2460 def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>;
2461 def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>;
2462 def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>;
2465 let hasNewValue = 1, opNewValue = 0 in
2466 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2467 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2468 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2469 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2471 #"($src1, $src2"#op2Suffix#")"
2472 #!if(MajOp{2}, ":<<1", "")
2473 #!if(isRnd, ":rnd", "")
2474 #!if(isSat, ":sat", "")
2475 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2480 let IClass = 0b1110;
2482 let Inst{27-24} = RegTyBits;
2483 let Inst{23-21} = MajOp;
2484 let Inst{20-16} = src1;
2486 let Inst{12-8} = src2;
2487 let Inst{7-5} = MinOp;
2488 let Inst{4-0} = dst;
2491 class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
2492 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
2494 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2495 bit isSat = 0, bit isRnd = 0 >
2496 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2498 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2499 bit isSat = 0, bit isRnd = 0 >
2500 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2502 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2503 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2504 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2506 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
2507 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
2508 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
2510 let CextOpcode = "mpyi", InputType = "reg" in
2511 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2513 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2514 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2516 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2518 def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>;
2519 def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>;
2521 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2522 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2524 def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
2525 def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
2526 def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
2527 def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
2530 def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
2531 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2532 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2533 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2535 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2536 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2538 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2539 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2540 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2542 let hasNewValue = 1, opNewValue = 0 in
2543 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2544 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2545 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2546 pattern, "", M_tc_3x_SLOT23> {
2551 let IClass = 0b1110;
2553 let Inst{27-24} = 0b0000;
2554 let Inst{23} = isNeg;
2557 let Inst{20-16} = Rs;
2558 let Inst{12-5} = u8;
2561 let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
2562 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2563 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2565 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2566 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2569 // Assember mapped to M2_mpyi
2570 let isAsmParserOnly = 1 in
2571 def M2_mpyui : MInst<(outs IntRegs:$dst),
2572 (ins IntRegs:$src1, IntRegs:$src2),
2573 "$dst = mpyui($src1, $src2)">;
2576 // s9 is NOT the same as m9 - but it works.. so far.
2577 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2578 // depending on the value of m9. See Arch Spec.
2579 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2580 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
2581 isAsmParserOnly = 1 in
2582 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2583 "$dst = mpyi($src1, #$src2)",
2584 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2585 s9ExtPred:$src2))]>, ImmRegRel;
2587 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2588 InputType = "imm" in
2589 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2590 list<dag> pattern = []>
2591 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2592 "$dst "#mnemonic#"($src2, #$src3)",
2593 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2598 let IClass = 0b1110;
2600 let Inst{27-26} = 0b00;
2601 let Inst{25-23} = MajOp;
2602 let Inst{20-16} = src2;
2604 let Inst{12-5} = src3;
2605 let Inst{4-0} = dst;
2608 let InputType = "reg", hasNewValue = 1 in
2609 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2610 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2611 bit isSat = 0, bit isShift = 0>
2612 : MInst < (outs IntRegs:$dst),
2613 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2614 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2615 #!if(isShift, ":<<1", "")
2616 #!if(isSat, ":sat", ""),
2617 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2622 let IClass = 0b1110;
2624 let Inst{27-24} = 0b1111;
2625 let Inst{23-21} = MajOp;
2626 let Inst{20-16} = !if(isSwap, src3, src2);
2628 let Inst{12-8} = !if(isSwap, src2, src3);
2629 let Inst{7-5} = MinOp;
2630 let Inst{4-0} = dst;
2633 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
2634 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2635 [(set (i32 IntRegs:$dst),
2636 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2637 IntRegs:$src1))]>, ImmRegRel;
2639 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2640 [(set (i32 IntRegs:$dst),
2641 (add (mul IntRegs:$src2, IntRegs:$src3),
2642 IntRegs:$src1))]>, ImmRegRel;
2645 let CextOpcode = "ADD_acc" in {
2646 let isExtentSigned = 1 in
2647 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2648 [(set (i32 IntRegs:$dst),
2649 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2650 (i32 IntRegs:$src1)))]>, ImmRegRel;
2652 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2653 [(set (i32 IntRegs:$dst),
2654 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2655 (i32 IntRegs:$src1)))]>, ImmRegRel;
2658 let CextOpcode = "SUB_acc" in {
2659 let isExtentSigned = 1 in
2660 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2662 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2665 let Itinerary = M_tc_3x_SLOT23 in
2666 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2668 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2669 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2671 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2673 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2674 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2676 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2677 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2678 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2680 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2681 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2683 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2684 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2686 //===----------------------------------------------------------------------===//
2687 // Template Class -- XType Vector Instructions
2688 //===----------------------------------------------------------------------===//
2689 class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2690 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2691 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2697 let IClass = 0b1110;
2699 let Inst{27-24} = 0b1000;
2700 let Inst{23-21} = MajOp;
2701 let Inst{7-5} = MinOp;
2702 let Inst{4-0} = Rdd;
2703 let Inst{20-16} = Rss;
2704 let Inst{12-8} = Rtt;
2707 class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2708 : MInst <(outs DoubleRegs:$Rdd),
2709 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2710 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2711 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
2716 let IClass = 0b1110;
2718 let Inst{27-24} = 0b1010;
2719 let Inst{23-21} = MajOp;
2720 let Inst{7-5} = MinOp;
2721 let Inst{4-0} = Rdd;
2722 let Inst{20-16} = Rss;
2723 let Inst{12-8} = Rtt;
2726 class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
2727 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
2728 "$Rdd = "#opc#"($Rtt, $Rss)",
2729 [], "",M_tc_2_SLOT23 > {
2734 let IClass = 0b1110;
2736 let Inst{27-24} = 0b1000;
2737 let Inst{23-21} = MajOp;
2738 let Inst{7-5} = 0b000;
2739 let Inst{4-0} = Rdd;
2740 let Inst{20-16} = Rss;
2741 let Inst{12-8} = Rtt;
2744 // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
2745 def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
2746 def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
2748 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
2749 def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
2750 def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
2752 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
2753 def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
2755 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
2756 def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">;
2758 // Vector reduce complex multiply real or imaginary:
2759 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
2760 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
2761 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
2762 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
2763 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
2765 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
2766 def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
2767 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
2768 def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
2770 // Vector reduce halfwords:
2771 // Rdd[+]=vrmpyh(Rss,Rtt)
2772 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
2773 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
2775 //===----------------------------------------------------------------------===//
2776 // Template Class -- Vector Multipy with accumulation.
2777 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2778 //===----------------------------------------------------------------------===//
2779 let Defs = [USR_OVF] in
2780 class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
2781 bit hasShift, bit isRnd >
2782 : MInst <(outs DoubleRegs:$Rxx),
2783 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2784 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2785 #!if(isRnd,":rnd","")#":sat",
2786 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2791 let IClass = 0b1110;
2793 let Inst{27-24} = 0b1010;
2794 let Inst{23-21} = MajOp;
2795 let Inst{7-5} = MinOp;
2796 let Inst{4-0} = Rxx;
2797 let Inst{20-16} = Rss;
2798 let Inst{12-8} = Rtt;
2801 class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp,
2802 bit hasShift, bit isRnd >
2803 : MInst <(outs DoubleRegs:$Rxx),
2804 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2805 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2806 #!if(isRnd,":rnd",""),
2807 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2812 let IClass = 0b1110;
2814 let Inst{27-24} = 0b1010;
2815 let Inst{23-21} = MajOp;
2816 let Inst{7-5} = MinOp;
2817 let Inst{4-0} = Rxx;
2818 let Inst{20-16} = Rss;
2819 let Inst{12-8} = Rtt;
2822 // Vector multiply word by signed half with accumulation
2823 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
2824 def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>;
2825 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
2826 def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>;
2827 def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>;
2829 def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>;
2830 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
2831 def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>;
2832 def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>;
2834 // Vector multiply word by unsigned half with accumulation
2835 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
2836 def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>;
2837 def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>;
2838 def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>;
2839 def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>;
2841 def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>;
2842 def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>;
2843 def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>;
2844 def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>;
2846 // Vector multiply even halfwords with accumulation
2847 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
2848 def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>;
2849 def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>;
2850 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
2852 // Vector dual multiply with accumulation
2853 // Rxx+=vdmpy(Rss,Rtt)[:sat]
2854 def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>;
2855 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
2857 // Vector complex multiply real or imaginary with accumulation
2858 // Rxx+=vcmpy[ir](Rss,Rtt):sat
2859 def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
2860 def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
2862 //===----------------------------------------------------------------------===//
2863 // Template Class -- Multiply signed/unsigned halfwords with and without
2864 // saturation and rounding
2865 //===----------------------------------------------------------------------===//
2866 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
2867 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
2868 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2869 #", $Rt."#!if(LHbits{0},"h)","l)")
2870 #!if(hasShift,":<<1","")
2871 #!if(isRnd,":rnd",""),
2877 let IClass = 0b1110;
2879 let Inst{27-24} = 0b0100;
2880 let Inst{23} = hasShift;
2881 let Inst{22} = isUnsigned;
2882 let Inst{21} = isRnd;
2883 let Inst{6-5} = LHbits;
2884 let Inst{4-0} = Rdd;
2885 let Inst{20-16} = Rs;
2886 let Inst{12-8} = Rt;
2889 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
2890 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
2891 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
2892 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
2894 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
2895 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
2896 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
2897 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
2899 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
2900 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
2901 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
2902 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
2904 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
2905 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
2906 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
2907 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
2909 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
2910 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
2911 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
2912 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
2913 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
2915 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
2916 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
2917 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
2918 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
2920 //===----------------------------------------------------------------------===//
2921 // Template Class for xtype mpy:
2924 // multiply 32X32 and use full result
2925 //===----------------------------------------------------------------------===//
2926 let hasSideEffects = 0 in
2927 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2928 bit isSat, bit hasShift, bit isConj>
2929 : MInst <(outs DoubleRegs:$Rdd),
2930 (ins IntRegs:$Rs, IntRegs:$Rt),
2931 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
2932 #!if(hasShift,":<<1","")
2933 #!if(isSat,":sat",""),
2939 let IClass = 0b1110;
2941 let Inst{27-24} = 0b0101;
2942 let Inst{23-21} = MajOp;
2943 let Inst{20-16} = Rs;
2944 let Inst{12-8} = Rt;
2945 let Inst{7-5} = MinOp;
2946 let Inst{4-0} = Rdd;
2949 //===----------------------------------------------------------------------===//
2950 // Template Class for xtype mpy with accumulation into 64-bit:
2953 // multiply 32X32 and use full result
2954 //===----------------------------------------------------------------------===//
2955 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
2956 bit isSat, bit hasShift, bit isConj>
2957 : MInst <(outs DoubleRegs:$Rxx),
2958 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2959 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
2960 #!if(hasShift,":<<1","")
2961 #!if(isSat,":sat",""),
2963 [] , "$dst2 = $Rxx" > {
2968 let IClass = 0b1110;
2970 let Inst{27-24} = 0b0111;
2971 let Inst{23-21} = MajOp;
2972 let Inst{20-16} = Rs;
2973 let Inst{12-8} = Rt;
2974 let Inst{7-5} = MinOp;
2975 let Inst{4-0} = Rxx;
2978 // MPY - Multiply and use full result
2979 // Rdd = mpy[u](Rs,Rt)
2980 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
2981 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
2983 // Rxx[+-]= mpy[u](Rs,Rt)
2984 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
2985 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
2986 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
2987 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
2989 // Complex multiply real or imaginary
2990 // Rxx=cmpy[ir](Rs,Rt)
2991 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
2992 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
2994 // Rxx+=cmpy[ir](Rs,Rt)
2995 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
2996 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
2999 // Rdd=cmpy(Rs,Rt)[:<<]:sat
3000 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
3001 def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
3003 // Rdd=cmpy(Rs,Rt*)[:<<]:sat
3004 def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
3005 def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
3007 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
3008 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
3009 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
3010 def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
3011 def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
3013 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
3014 def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
3015 def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
3016 def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
3017 def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
3019 // Vector multiply halfwords
3020 // Rdd=vmpyh(Rs,Rt)[:<<]:sat
3021 //let Defs = [USR_OVF] in {
3022 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>;
3023 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
3026 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
3027 def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>;
3028 def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>;
3029 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
3031 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3032 (i64 (anyext (i32 IntRegs:$src2))))),
3033 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3035 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3036 (i64 (sext (i32 IntRegs:$src2))))),
3037 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3039 def: Pat<(i64 (mul (is_sext_i32:$src1),
3040 (is_sext_i32:$src2))),
3041 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3043 // Multiply and accumulate, use full result.
3044 // Rxx[+-]=mpy(Rs,Rt)
3046 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3047 (mul (i64 (sext (i32 IntRegs:$src2))),
3048 (i64 (sext (i32 IntRegs:$src3)))))),
3049 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3051 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3052 (mul (i64 (sext (i32 IntRegs:$src2))),
3053 (i64 (sext (i32 IntRegs:$src3)))))),
3054 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3056 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3057 (mul (i64 (anyext (i32 IntRegs:$src2))),
3058 (i64 (anyext (i32 IntRegs:$src3)))))),
3059 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3061 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3062 (mul (i64 (zext (i32 IntRegs:$src2))),
3063 (i64 (zext (i32 IntRegs:$src3)))))),
3064 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3066 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3067 (mul (i64 (anyext (i32 IntRegs:$src2))),
3068 (i64 (anyext (i32 IntRegs:$src3)))))),
3069 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3071 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3072 (mul (i64 (zext (i32 IntRegs:$src2))),
3073 (i64 (zext (i32 IntRegs:$src3)))))),
3074 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3076 //===----------------------------------------------------------------------===//
3078 //===----------------------------------------------------------------------===//
3080 //===----------------------------------------------------------------------===//
3082 //===----------------------------------------------------------------------===//
3083 //===----------------------------------------------------------------------===//
3085 //===----------------------------------------------------------------------===//
3087 //===----------------------------------------------------------------------===//
3089 //===----------------------------------------------------------------------===//
3090 //===----------------------------------------------------------------------===//
3092 //===----------------------------------------------------------------------===//
3094 //===----------------------------------------------------------------------===//
3096 //===----------------------------------------------------------------------===//
3097 //===----------------------------------------------------------------------===//
3099 //===----------------------------------------------------------------------===//
3101 //===----------------------------------------------------------------------===//
3103 //===----------------------------------------------------------------------===//
3105 // Store doubleword.
3106 //===----------------------------------------------------------------------===//
3107 // Template class for non-predicated post increment stores with immediate offset
3108 //===----------------------------------------------------------------------===//
3109 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
3110 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3111 bits<4> MajOp, bit isHalf >
3112 : STInst <(outs IntRegs:$_dst_),
3113 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3114 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
3115 [], "$src1 = $_dst_" >,
3122 string ImmOpStr = !cast<string>(ImmOp);
3123 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3124 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3125 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3126 /* s4_0Imm */ offset{3-0})));
3127 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3129 let IClass = 0b1010;
3131 let Inst{27-25} = 0b101;
3132 let Inst{24-21} = MajOp;
3133 let Inst{20-16} = src1;
3135 let Inst{12-8} = src2;
3137 let Inst{6-3} = offsetBits;
3141 //===----------------------------------------------------------------------===//
3142 // Template class for predicated post increment stores with immediate offset
3143 //===----------------------------------------------------------------------===//
3144 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
3145 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3146 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
3147 : STInst <(outs IntRegs:$_dst_),
3148 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3149 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3150 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
3151 [], "$src2 = $_dst_" >,
3159 string ImmOpStr = !cast<string>(ImmOp);
3160 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3161 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3162 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3163 /* s4_0Imm */ offset{3-0})));
3165 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3166 let isPredicatedNew = isPredNew;
3167 let isPredicatedFalse = isPredNot;
3169 let IClass = 0b1010;
3171 let Inst{27-25} = 0b101;
3172 let Inst{24-21} = MajOp;
3173 let Inst{20-16} = src2;
3175 let Inst{12-8} = src3;
3176 let Inst{7} = isPredNew;
3177 let Inst{6-3} = offsetBits;
3178 let Inst{2} = isPredNot;
3179 let Inst{1-0} = src1;
3182 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
3183 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
3185 let BaseOpcode = "POST_"#BaseOp in {
3186 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
3189 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
3190 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
3193 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3195 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3200 let accessSize = ByteAccess in
3201 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3203 let accessSize = HalfWordAccess in
3204 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3206 let accessSize = WordAccess in
3207 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3209 let accessSize = DoubleWordAccess in
3210 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3212 let accessSize = HalfWordAccess, isNVStorable = 0 in
3213 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3215 class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset,
3217 : Pat<(Store Value:$src1, I32:$src2, Offset:$offset),
3218 (MI I32:$src2, imm:$offset, Value:$src1)>;
3220 def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>;
3221 def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>;
3222 def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>;
3223 def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>;
3225 //===----------------------------------------------------------------------===//
3226 // Template class for post increment stores with register offset.
3227 //===----------------------------------------------------------------------===//
3228 let isNVStorable = 1 in
3229 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
3230 MemAccessSize AccessSz, bit isHalf = 0>
3231 : STInst <(outs IntRegs:$_dst_),
3232 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3233 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
3234 [], "$src1 = $_dst_" > {
3238 let accessSize = AccessSz;
3240 let IClass = 0b1010;
3242 let Inst{27-24} = 0b1101;
3243 let Inst{23-21} = MajOp;
3244 let Inst{20-16} = src1;
3245 let Inst{13} = src2;
3246 let Inst{12-8} = src3;
3250 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3251 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3252 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3253 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
3255 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3257 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
3258 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3259 bits<3>MajOp, bit isH = 0>
3261 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3262 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
3263 AddrModeRel, ImmRegRel {
3265 bits<14> src2; // Actual address offset
3267 bits<11> offsetBits; // Represents offset encoding
3269 string ImmOpStr = !cast<string>(ImmOp);
3271 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
3272 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
3273 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
3274 /* s11_0Ext */ 11)));
3275 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
3276 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
3277 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
3278 /* s11_0Ext */ src2{10-0})));
3279 let IClass = 0b1010;
3282 let Inst{26-25} = offsetBits{10-9};
3284 let Inst{23-21} = MajOp;
3285 let Inst{20-16} = src1;
3286 let Inst{13} = offsetBits{8};
3287 let Inst{12-8} = src3;
3288 let Inst{7-0} = offsetBits{7-0};
3291 let opExtendable = 2, isPredicated = 1 in
3292 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3293 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
3295 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3296 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3297 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
3298 [],"",V2LDST_tc_st_SLOT01 >,
3299 AddrModeRel, ImmRegRel {
3302 bits<9> src3; // Actual address offset
3304 bits<6> offsetBits; // Represents offset encoding
3306 let isPredicatedNew = isPredNew;
3307 let isPredicatedFalse = PredNot;
3309 string ImmOpStr = !cast<string>(ImmOp);
3310 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
3311 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
3312 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
3314 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
3315 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
3316 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
3317 /* u6_0Ext */ src3{5-0})));
3318 let IClass = 0b0100;
3321 let Inst{26} = PredNot;
3322 let Inst{25} = isPredNew;
3324 let Inst{23-21} = MajOp;
3325 let Inst{20-16} = src2;
3326 let Inst{13} = offsetBits{5};
3327 let Inst{12-8} = src4;
3328 let Inst{7-3} = offsetBits{4-0};
3329 let Inst{1-0} = src1;
3332 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
3333 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
3334 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
3335 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
3336 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
3339 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
3340 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
3343 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3345 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3350 let addrMode = BaseImmOffset, InputType = "imm" in {
3351 let accessSize = ByteAccess in
3352 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3354 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3355 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3357 let accessSize = WordAccess, opExtentAlign = 2 in
3358 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3360 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
3361 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
3364 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3365 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3369 // Patterns for generating stores, where the address takes different forms:
3372 // - simple (base address without offset).
3373 // These would usually be used together (via Storex_pat defined below), but
3374 // in some cases one may want to apply different properties (such as
3375 // AddedComplexity) to the individual patterns.
3376 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3377 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
3378 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3380 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3381 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3382 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3383 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3384 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3386 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3388 def: Storex_fi_pat <Store, Value, MI>;
3389 def: Storex_add_pat <Store, Value, ImmPred, MI>;
3392 // Regular stores in the DAG have two operands: value and address.
3393 // Atomic stores also have two, but they are reversed: address, value.
3394 // To use atomic stores with the patterns, they need to have their operands
3395 // swapped. This relies on the knowledge that the F.Fragment uses names
3397 class SwapSt<PatFrag F>
3398 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
3400 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
3401 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
3402 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
3403 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
3405 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
3406 (S2_storerb_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3408 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
3409 (S2_storerh_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3411 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
3412 (S2_storeri_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3414 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
3415 (S2_storerd_io AddrFI:$addr, 0, (i64 DoubleRegs:$src1))>;
3418 let AddedComplexity = 10 in {
3419 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
3420 s11_0ExtPred:$offset)),
3421 (S2_storerb_io IntRegs:$src2, s11_0ImmPred:$offset,
3422 (i32 IntRegs:$src1))>;
3424 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
3425 s11_1ExtPred:$offset)),
3426 (S2_storerh_io IntRegs:$src2, s11_1ImmPred:$offset,
3427 (i32 IntRegs:$src1))>;
3429 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
3430 s11_2ExtPred:$offset)),
3431 (S2_storeri_io IntRegs:$src2, s11_2ImmPred:$offset,
3432 (i32 IntRegs:$src1))>;
3434 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
3435 s11_3ExtPred:$offset)),
3436 (S2_storerd_io IntRegs:$src2, s11_3ImmPred:$offset,
3437 (i64 DoubleRegs:$src1))>;
3440 // memh(Rx++#s4:1)=Rt.H
3443 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
3444 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3445 def STriw_pred : STInst<(outs),
3446 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3447 ".error \"should not emit\"", []>;
3449 // S2_allocframe: Allocate stack frame.
3450 let Defs = [R29, R30], Uses = [R29, R31, R30],
3451 hasSideEffects = 0, accessSize = DoubleWordAccess in
3452 def S2_allocframe: ST0Inst <
3453 (outs), (ins u11_3Imm:$u11_3),
3454 "allocframe(#$u11_3)" > {
3457 let IClass = 0b1010;
3458 let Inst{27-16} = 0b000010011101;
3459 let Inst{13-11} = 0b000;
3460 let Inst{10-0} = u11_3{13-3};
3463 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3464 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3465 let Uses = [CS], isNVStorable = 1 in
3466 class T_store_pci <string mnemonic, RegisterClass RC,
3467 Operand Imm, bits<4>MajOp,
3468 MemAccessSize AlignSize, string RegSrc = "Rt">
3469 : STInst <(outs IntRegs:$_dst_),
3470 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3471 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3478 let accessSize = AlignSize;
3480 let IClass = 0b1010;
3481 let Inst{27-25} = 0b100;
3482 let Inst{24-21} = MajOp;
3483 let Inst{20-16} = Rz;
3485 let Inst{12-8} = Rt;
3488 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3489 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3490 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3491 /* ByteAccess */ offset{3-0})));
3495 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3497 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3499 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3500 HalfWordAccess, "Rt.h">;
3501 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3503 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3506 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3507 class T_storenew_pci <string mnemonic, Operand Imm,
3508 bits<2>MajOp, MemAccessSize AlignSize>
3509 : NVInst < (outs IntRegs:$_dst_),
3510 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3511 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3519 let accessSize = AlignSize;
3521 let IClass = 0b1010;
3522 let Inst{27-21} = 0b1001101;
3523 let Inst{20-16} = Rz;
3525 let Inst{12-11} = MajOp;
3526 let Inst{10-8} = Nt;
3529 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3530 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3531 /* ByteAccess */ offset{3-0}));
3535 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3536 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3537 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3539 //===----------------------------------------------------------------------===//
3540 // Circular stores with auto-increment register
3541 //===----------------------------------------------------------------------===//
3542 let Uses = [CS], isNVStorable = 1 in
3543 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3544 MemAccessSize AlignSize, string RegSrc = "Rt">
3545 : STInst <(outs IntRegs:$_dst_),
3546 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3547 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3554 let accessSize = AlignSize;
3556 let IClass = 0b1010;
3557 let Inst{27-25} = 0b100;
3558 let Inst{24-21} = MajOp;
3559 let Inst{20-16} = Rz;
3561 let Inst{12-8} = Rt;
3566 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3567 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3568 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3569 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3570 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3571 HalfWordAccess, "Rt.h">;
3573 //===----------------------------------------------------------------------===//
3574 // Circular .new stores with auto-increment register
3575 //===----------------------------------------------------------------------===//
3576 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3577 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3578 MemAccessSize AlignSize>
3579 : NVInst <(outs IntRegs:$_dst_),
3580 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3581 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3588 let accessSize = AlignSize;
3590 let IClass = 0b1010;
3591 let Inst{27-21} = 0b1001101;
3592 let Inst{20-16} = Rz;
3594 let Inst{12-11} = MajOp;
3595 let Inst{10-8} = Nt;
3600 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3601 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3602 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3604 //===----------------------------------------------------------------------===//
3605 // Bit-reversed stores with auto-increment register
3606 //===----------------------------------------------------------------------===//
3607 let hasSideEffects = 0 in
3608 class T_store_pbr<string mnemonic, RegisterClass RC,
3609 MemAccessSize addrSize, bits<3> majOp,
3612 <(outs IntRegs:$_dst_),
3613 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3614 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3615 [], "$Rz = $_dst_" > {
3617 let accessSize = addrSize;
3623 let IClass = 0b1010;
3625 let Inst{27-24} = 0b1111;
3626 let Inst{23-21} = majOp;
3628 let Inst{20-16} = Rz;
3630 let Inst{12-8} = src;
3633 let isNVStorable = 1 in {
3634 let BaseOpcode = "S2_storerb_pbr" in
3635 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3636 0b000>, NewValueRel;
3637 let BaseOpcode = "S2_storerh_pbr" in
3638 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3639 0b010>, NewValueRel;
3640 let BaseOpcode = "S2_storeri_pbr" in
3641 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3642 0b100>, NewValueRel;
3645 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3646 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3648 //===----------------------------------------------------------------------===//
3649 // Bit-reversed .new stores with auto-increment register
3650 //===----------------------------------------------------------------------===//
3651 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3652 hasSideEffects = 0 in
3653 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3654 : NVInst <(outs IntRegs:$_dst_),
3655 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3656 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3657 "$Rz = $_dst_">, NewValueRel {
3658 let accessSize = addrSize;
3663 let IClass = 0b1010;
3665 let Inst{27-21} = 0b1111101;
3666 let Inst{12-11} = majOp;
3668 let Inst{20-16} = Rz;
3670 let Inst{10-8} = Nt;
3673 let BaseOpcode = "S2_storerb_pbr" in
3674 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3676 let BaseOpcode = "S2_storerh_pbr" in
3677 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3679 let BaseOpcode = "S2_storeri_pbr" in
3680 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3682 //===----------------------------------------------------------------------===//
3684 //===----------------------------------------------------------------------===//
3686 //===----------------------------------------------------------------------===//
3687 // Template class for S_2op instructions.
3688 //===----------------------------------------------------------------------===//
3689 let hasSideEffects = 0 in
3690 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3691 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3692 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3693 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3694 [], "", S_2op_tc_1_SLOT23 > {
3698 let IClass = 0b1000;
3700 let Inst{27-24} = RegTyBits;
3701 let Inst{23-22} = MajOp;
3703 let Inst{20-16} = src;
3704 let Inst{7-5} = MinOp;
3705 let Inst{4-0} = dst;
3708 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3709 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3711 let hasNewValue = 1 in
3712 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3713 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3715 let hasNewValue = 1 in
3716 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3717 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3719 // Vector sign/zero extend
3720 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3721 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3722 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3723 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3724 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3727 // Vector splat bytes/halfwords
3728 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3729 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
3730 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
3733 // Sign extend word to doubleword
3734 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3736 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3738 // Vector saturate and pack
3739 let Defs = [USR_OVF] in {
3740 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
3741 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
3742 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3743 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3744 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3745 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
3749 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
3750 def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
3752 // Swizzle the bytes of a word
3753 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3756 let Defs = [USR_OVF] in {
3757 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
3758 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
3759 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
3760 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
3761 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
3762 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
3765 let Itinerary = S_2op_tc_2_SLOT23 in {
3766 // Vector round and pack
3767 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
3769 let Defs = [USR_OVF] in
3770 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
3773 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
3775 // Absolute value word
3776 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
3778 let Defs = [USR_OVF] in
3779 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
3781 // Negate with saturation
3782 let Defs = [USR_OVF] in
3783 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
3786 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
3787 (i32 (sub 0, (i32 IntRegs:$src))),
3788 (i32 IntRegs:$src))),
3789 (A2_abs IntRegs:$src)>;
3791 let AddedComplexity = 50 in
3792 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
3793 (i32 IntRegs:$src)),
3794 (sra (i32 IntRegs:$src), (i32 31)))),
3795 (A2_abs IntRegs:$src)>;
3797 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3798 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
3799 bit isSat, bit isRnd, list<dag> pattern = []>
3800 : SInst <(outs RCOut:$dst),
3801 (ins RCIn:$src, u5Imm:$u5),
3802 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
3803 #!if(isRnd, ":rnd", ""),
3804 pattern, "", S_2op_tc_2_SLOT23> {
3809 let IClass = 0b1000;
3811 let Inst{27-24} = RegTyBits;
3812 let Inst{23-21} = MajOp;
3813 let Inst{20-16} = src;
3815 let Inst{12-8} = u5;
3816 let Inst{7-5} = MinOp;
3817 let Inst{4-0} = dst;
3820 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3821 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
3823 let hasNewValue = 1 in
3824 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3825 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
3827 let hasNewValue = 1 in
3828 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3829 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
3830 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
3831 isSat, isRnd, pattern>;
3833 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
3834 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
3835 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
3836 (u5ImmPred:$u5)))]>;
3838 // Vector arithmetic shift right by immediate with truncate and pack
3839 def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>;
3841 // Arithmetic/logical shift right/left by immediate
3842 let Itinerary = S_2op_tc_1_SLOT23 in {
3843 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
3844 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
3845 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
3848 // Shift left by immediate with saturation
3849 let Defs = [USR_OVF] in
3850 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
3852 // Shift right with round
3853 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
3855 let isAsmParserOnly = 1 in
3856 def S2_asr_i_r_rnd_goodsyntax
3857 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
3858 "$dst = asrrnd($src, #$u5)",
3859 [], "", S_2op_tc_1_SLOT23>;
3861 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
3864 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
3866 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
3867 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
3868 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
3871 let IClass = 0b1000;
3872 let Inst{27-24} = 0;
3873 let Inst{23-22} = MajOp;
3874 let Inst{20-16} = Rss;
3875 let Inst{7-5} = minOp;
3876 let Inst{4-0} = Rdd;
3879 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
3880 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
3881 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
3883 // Innterleave/deinterleave
3884 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
3885 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
3887 // Vector Complex conjugate
3888 def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
3890 // Vector saturate without pack
3891 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
3892 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
3893 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
3894 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
3896 // Vector absolute value halfwords with and without saturation
3897 // Rdd64=vabsh(Rss64)[:sat]
3898 def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
3899 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
3901 // Vector absolute value words with and without saturation
3902 def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
3903 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
3905 //===----------------------------------------------------------------------===//
3907 //===----------------------------------------------------------------------===//
3910 let hasSideEffects = 0, hasNewValue = 1 in
3911 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
3913 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
3916 let IClass = 0b1000;
3918 let Inst{26} = Is32;
3919 let Inst{25-24} = 0b00;
3920 let Inst{23-21} = MajOp;
3921 let Inst{20-16} = Rs;
3922 let Inst{7-5} = MinOp;
3926 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
3927 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
3928 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
3930 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
3931 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
3932 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
3934 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
3935 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
3936 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
3937 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
3938 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
3939 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
3940 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
3941 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
3942 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
3944 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
3945 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
3946 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
3947 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
3948 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
3949 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
3951 // Bit set/clear/toggle
3953 let hasSideEffects = 0, hasNewValue = 1 in
3954 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
3955 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
3956 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
3960 let IClass = 0b1000;
3961 let Inst{27-21} = 0b1100110;
3962 let Inst{20-16} = Rs;
3964 let Inst{12-8} = u5;
3965 let Inst{7-5} = MinOp;
3969 let hasSideEffects = 0, hasNewValue = 1 in
3970 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
3971 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
3972 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
3976 let IClass = 0b1100;
3977 let Inst{27-22} = 0b011010;
3978 let Inst{20-16} = Rs;
3979 let Inst{12-8} = Rt;
3980 let Inst{7-6} = MinOp;
3984 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
3985 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
3986 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
3987 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
3988 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
3989 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
3991 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
3992 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3993 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3994 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3995 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3996 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3997 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
3998 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3999 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4000 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4001 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4002 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4006 let hasSideEffects = 0 in
4007 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
4008 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4009 "$Pd = "#MnOp#"($Rs, #$u5)",
4010 [], "", S_2op_tc_2early_SLOT23> {
4014 let IClass = 0b1000;
4015 let Inst{27-24} = 0b0101;
4016 let Inst{23-21} = MajOp;
4017 let Inst{20-16} = Rs;
4019 let Inst{12-8} = u5;
4023 let hasSideEffects = 0 in
4024 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
4025 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4026 "$Pd = "#MnOp#"($Rs, $Rt)",
4027 [], "", S_3op_tc_2early_SLOT23> {
4031 let IClass = 0b1100;
4032 let Inst{27-22} = 0b011100;
4033 let Inst{21} = IsNeg;
4034 let Inst{20-16} = Rs;
4035 let Inst{12-8} = Rt;
4039 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
4040 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
4042 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
4043 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4044 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4045 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4046 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4047 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4048 (S2_tstbit_i IntRegs:$Rs, 0)>;
4049 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
4050 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4053 let hasSideEffects = 0 in
4054 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
4055 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4056 "$Pd = "#MnOp#"($Rs, #$u6)",
4057 [], "", S_2op_tc_2early_SLOT23> {
4061 let IClass = 0b1000;
4062 let Inst{27-24} = 0b0101;
4063 let Inst{23-22} = MajOp;
4064 let Inst{21} = IsNeg;
4065 let Inst{20-16} = Rs;
4066 let Inst{13-8} = u6;
4070 let hasSideEffects = 0 in
4071 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
4072 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4073 "$Pd = "#MnOp#"($Rs, $Rt)",
4074 [], "", S_3op_tc_2early_SLOT23> {
4078 let IClass = 0b1100;
4079 let Inst{27-24} = 0b0111;
4080 let Inst{23-22} = MajOp;
4081 let Inst{21} = IsNeg;
4082 let Inst{20-16} = Rs;
4083 let Inst{12-8} = Rt;
4087 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
4088 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
4089 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
4091 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
4092 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4093 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4094 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4095 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4098 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
4099 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4100 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4102 //===----------------------------------------------------------------------===//
4104 //===----------------------------------------------------------------------===//
4106 //===----------------------------------------------------------------------===//
4108 //===----------------------------------------------------------------------===//
4109 //===----------------------------------------------------------------------===//
4111 //===----------------------------------------------------------------------===//
4113 //===----------------------------------------------------------------------===//
4115 //===----------------------------------------------------------------------===//
4117 //===----------------------------------------------------------------------===//
4119 //===----------------------------------------------------------------------===//
4121 //===----------------------------------------------------------------------===//
4123 //===----------------------------------------------------------------------===//
4125 // Predicate transfer.
4126 let hasSideEffects = 0, hasNewValue = 1 in
4127 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4128 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
4132 let IClass = 0b1000;
4133 let Inst{27-24} = 0b1001;
4135 let Inst{17-16} = Ps;
4139 // Transfer general register to predicate.
4140 let hasSideEffects = 0 in
4141 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4142 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
4146 let IClass = 0b1000;
4147 let Inst{27-21} = 0b0101010;
4148 let Inst{20-16} = Rs;
4153 //===----------------------------------------------------------------------===//
4155 //===----------------------------------------------------------------------===//
4157 //===----------------------------------------------------------------------===//
4159 //===----------------------------------------------------------------------===//
4160 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
4161 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
4162 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
4163 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
4167 let IClass = 0b1000;
4168 let Inst{27-24} = 0;
4169 let Inst{23-21} = MajOp;
4170 let Inst{20-16} = src1;
4171 let Inst{7-5} = MinOp;
4172 let Inst{4-0} = dst;
4175 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
4176 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
4177 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
4178 u6ImmPred:$src2))]> {
4180 let Inst{13-8} = src2;
4183 // Shift by immediate.
4184 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
4185 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
4186 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
4188 // Shift left by small amount and add.
4189 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in
4190 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4191 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4192 "$Rd = addasl($Rt, $Rs, #$u3)" ,
4193 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4194 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4195 "", S_3op_tc_2_SLOT23> {
4201 let IClass = 0b1100;
4203 let Inst{27-21} = 0b0100000;
4204 let Inst{20-16} = Rs;
4206 let Inst{12-8} = Rt;
4211 //===----------------------------------------------------------------------===//
4213 //===----------------------------------------------------------------------===//
4215 //===----------------------------------------------------------------------===//
4217 //===----------------------------------------------------------------------===//
4218 //===----------------------------------------------------------------------===//
4220 //===----------------------------------------------------------------------===//
4222 //===----------------------------------------------------------------------===//
4224 //===----------------------------------------------------------------------===//
4225 //===----------------------------------------------------------------------===//
4227 //===----------------------------------------------------------------------===//
4229 //===----------------------------------------------------------------------===//
4231 //===----------------------------------------------------------------------===//
4233 //===----------------------------------------------------------------------===//
4235 //===----------------------------------------------------------------------===//
4236 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
4238 let hasSideEffects = 1, isSoloAX = 1 in
4239 def Y2_barrier : SYSInst<(outs), (ins),
4241 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
4242 let Inst{31-28} = 0b1010;
4243 let Inst{27-21} = 0b1000000;
4246 //===----------------------------------------------------------------------===//
4248 //===----------------------------------------------------------------------===//
4249 //===----------------------------------------------------------------------===//
4251 //===----------------------------------------------------------------------===//
4253 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4254 opExtendable = 0, hasSideEffects = 0 in
4255 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4256 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
4257 #mnemonic#"($offset, #$src2)",
4258 [], "" , CR_tc_3x_SLOT3> {
4262 let IClass = 0b0110;
4264 let Inst{27-22} = 0b100100;
4265 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4266 let Inst{20-16} = src2{9-5};
4267 let Inst{12-8} = offset{8-4};
4268 let Inst{7-5} = src2{4-2};
4269 let Inst{4-3} = offset{3-2};
4270 let Inst{1-0} = src2{1-0};
4273 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4274 opExtendable = 0, hasSideEffects = 0 in
4275 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4276 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4277 #mnemonic#"($offset, $src2)",
4278 [], "" ,CR_tc_3x_SLOT3> {
4282 let IClass = 0b0110;
4284 let Inst{27-22} = 0b000000;
4285 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4286 let Inst{20-16} = src2;
4287 let Inst{12-8} = offset{8-4};
4288 let Inst{4-3} = offset{3-2};
4291 multiclass LOOP_ri<string mnemonic> {
4292 def i : LOOP_iBase<mnemonic, brtarget>;
4293 def r : LOOP_rBase<mnemonic, brtarget>;
4297 let Defs = [SA0, LC0, USR] in
4298 defm J2_loop0 : LOOP_ri<"loop0">;
4300 // Interestingly only loop0's appear to set usr.lpcfg
4301 let Defs = [SA1, LC1] in
4302 defm J2_loop1 : LOOP_ri<"loop1">;
4304 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4305 Defs = [PC, LC0], Uses = [SA0, LC0] in {
4306 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4311 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4312 Defs = [PC, LC1], Uses = [SA1, LC1] in {
4313 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4318 // Pipelined loop instructions, sp[123]loop0
4319 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4320 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4321 opExtendable = 0, isPredicateLate = 1 in
4322 class SPLOOP_iBase<string SP, bits<2> op>
4323 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4324 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
4328 let IClass = 0b0110;
4330 let Inst{22-21} = op;
4331 let Inst{27-23} = 0b10011;
4332 let Inst{20-16} = U10{9-5};
4333 let Inst{12-8} = r7_2{8-4};
4334 let Inst{7-5} = U10{4-2};
4335 let Inst{4-3} = r7_2{3-2};
4336 let Inst{1-0} = U10{1-0};
4339 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4340 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4341 opExtendable = 0, isPredicateLate = 1 in
4342 class SPLOOP_rBase<string SP, bits<2> op>
4343 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4344 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
4348 let IClass = 0b0110;
4350 let Inst{22-21} = op;
4351 let Inst{27-23} = 0b00001;
4352 let Inst{20-16} = Rs;
4353 let Inst{12-8} = r7_2{8-4};
4354 let Inst{4-3} = r7_2{3-2};
4357 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
4358 def i : SPLOOP_iBase<mnemonic, op>;
4359 def r : SPLOOP_rBase<mnemonic, op>;
4362 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4363 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
4364 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
4366 // if (Rs[!>=<]=#0) jump:[t/nt]
4367 let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0,
4368 hasSideEffects = 0 in
4369 class J2_jump_0_Base<string compare, bit isTak, bits<2> op>
4370 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4371 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > {
4375 let IClass = 0b0110;
4377 let Inst{27-24} = 0b0001;
4378 let Inst{23-22} = op;
4379 let Inst{12} = isTak;
4380 let Inst{21} = r13_2{14};
4381 let Inst{20-16} = Rs;
4382 let Inst{11-1} = r13_2{12-2};
4383 let Inst{13} = r13_2{13};
4386 multiclass J2_jump_compare_0<string compare, bits<2> op> {
4387 def NAME : J2_jump_0_Base<compare, 0, op>;
4388 def NAME#pt : J2_jump_0_Base<compare, 1, op>;
4391 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
4392 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
4393 defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>;
4394 defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>;
4396 // Transfer to/from Control/GPR Guest/GPR
4397 let hasSideEffects = 0 in
4398 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
4399 : CRInst <(outs CTRC:$dst), (ins RC:$src),
4400 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4404 let IClass = 0b0110;
4406 let Inst{27-25} = 0b001;
4407 let Inst{24} = isDouble;
4408 let Inst{23-21} = 0b001;
4409 let Inst{20-16} = src;
4410 let Inst{4-0} = dst;
4413 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4414 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4415 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4417 let hasSideEffects = 0 in
4418 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
4419 : CRInst <(outs RC:$dst), (ins CTRC:$src),
4420 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4424 let IClass = 0b0110;
4426 let Inst{27-26} = 0b10;
4427 let Inst{25} = isSingle;
4428 let Inst{24-21} = 0b0000;
4429 let Inst{20-16} = src;
4430 let Inst{4-0} = dst;
4433 let hasNewValue = 1, opNewValue = 0 in
4434 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4435 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4436 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4438 // Y4_trace: Send value to etm trace.
4439 let isSoloAX = 1, hasSideEffects = 0 in
4440 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4444 let IClass = 0b0110;
4445 let Inst{27-21} = 0b0010010;
4446 let Inst{20-16} = Rs;
4449 let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
4450 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
4451 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
4452 "Error; should not emit",
4453 [(set (i32 IntRegs:$dst),
4454 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
4455 s12ImmPred:$src3)))]>;
4457 let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
4458 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
4459 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
4460 "Error; should not emit",
4461 [(set (i32 IntRegs:$dst),
4462 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4463 (i32 IntRegs:$src3))))]>;
4465 let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
4466 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
4467 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
4468 "Error; should not emit",
4469 [(set (i32 IntRegs:$dst),
4470 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4471 s12ImmPred:$src3)))]>;
4473 // Generate frameindex addresses.
4474 let isReMaterializable = 1, isCodeGenOnly = 1 in
4475 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
4476 "$dst = add($src1)",
4477 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
4479 // Support for generating global address.
4480 // Taken from X86InstrInfo.td.
4481 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
4484 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
4485 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
4487 // HI/LO Instructions
4488 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4489 hasNewValue = 1, opNewValue = 0 in
4490 class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp>
4491 : ALU32_ri<(outs IntRegs:$dst),
4492 (ins i32imm:$imm_value),
4493 "$dst"#RegHalf#" = #"#Op#"($imm_value)", []> {
4496 let IClass = 0b0111;
4499 let Inst{26-24} = MajOp;
4500 let Inst{21} = MinOp;
4501 let Inst{20-16} = dst;
4502 let Inst{23-22} = !if (!eq(Op, "LO"), imm_value{15-14}, imm_value{31-30});
4503 let Inst{13-0} = !if (!eq(Op, "LO"), imm_value{13-0}, imm_value{29-16});
4506 let isAsmParserOnly = 1 in {
4507 def LO : REG_IMMED<".l", "LO", 0b0, 0b001, 0b1>;
4508 def LO_H : REG_IMMED<".l", "HI", 0b0, 0b001, 0b1>;
4509 def HI : REG_IMMED<".h", "HI", 0b0, 0b010, 0b1>;
4510 def HI_L : REG_IMMED<".h", "LO", 0b0, 0b010, 0b1>;
4513 let isMoveImm = 1, isCodeGenOnly = 1 in
4514 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4515 "$dst.l = #LO($label@GOTREL)",
4518 let isMoveImm = 1, isCodeGenOnly = 1 in
4519 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4520 "$dst.h = #HI($label@GOTREL)",
4523 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4524 isAsmParserOnly = 1 in
4525 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4526 "$dst.l = #LO($imm_value)",
4530 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4531 isAsmParserOnly = 1 in
4532 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4533 "$dst.h = #HI($imm_value)",
4536 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4537 isAsmParserOnly = 1 in
4538 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4539 "$dst.l = #LO($jt)",
4542 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4543 isAsmParserOnly = 1 in
4544 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4545 "$dst.h = #HI($jt)",
4548 // This pattern is incorrect. When we add small data, we should change
4549 // this pattern to use memw(#foo).
4550 // This is for sdata.
4551 let isMoveImm = 1, isAsmParserOnly = 1 in
4552 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4553 "$dst = CONST32(#$global)",
4554 [(set (i32 IntRegs:$dst),
4555 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4557 let isReMaterializable = 1, isMoveImm = 1 in
4558 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4559 "$dst = CONST32(#$global)",
4560 [(set (i32 IntRegs:$dst),
4561 (HexagonCONST32 tglobaladdr:$global))]>;
4563 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4564 def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4565 "$dst = CONST32(#$jt)",
4566 [(set (i32 IntRegs:$dst),
4567 (HexagonCONST32 tjumptable:$jt))]>;
4569 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4570 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4571 "$dst = CONST32(#$global)",
4572 [(set (i32 IntRegs:$dst),
4573 (HexagonCONST32_GP tglobaladdr:$global))]>;
4575 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4576 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
4577 "$dst = CONST32(#$global)",
4578 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4580 // Map BlockAddress lowering to CONST32_Int_Real
4581 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
4582 (CONST32_Int_Real tblockaddress:$addr)>;
4584 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4585 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4586 "$dst = CONST32($label)",
4587 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4589 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4590 def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
4591 "$dst = CONST64(#$global)",
4592 [(set (i64 DoubleRegs:$dst), imm:$global)]>;
4594 let isCodeGenOnly = 1 in
4595 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
4596 "$dst = xor($dst, $dst)",
4597 [(set (i1 PredRegs:$dst), 0)]>;
4599 // Pseudo instructions.
4600 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4601 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4602 SDTCisVT<1, i32> ]>;
4604 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4605 [SDNPHasChain, SDNPOutGlue]>;
4606 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4607 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4609 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4611 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4612 // Optional Flag and Variable Arguments.
4613 // Its 1 Operand has pointer type.
4614 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4615 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4617 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
4618 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4619 ".error \"should not emit\" ",
4620 [(callseq_start timm:$amt)]>;
4622 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
4623 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4624 ".error \"should not emit\" ",
4625 [(callseq_end timm:$amt1, timm:$amt2)]>;
4627 // Call subroutine indirectly.
4628 let Defs = VolatileV3.Regs in
4629 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4631 // Indirect tail-call.
4632 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4633 isTerminator = 1, isCodeGenOnly = 1 in
4634 def TCRETURNr : T_JMPr;
4636 // Direct tail-calls.
4637 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4638 isTerminator = 1, isCodeGenOnly = 1 in {
4639 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4640 [], "", J_tc_2early_SLOT23>;
4641 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4642 [], "", J_tc_2early_SLOT23>;
4646 def: Pat<(HexagonTCRet tglobaladdr:$dst),
4647 (TCRETURNtg tglobaladdr:$dst)>;
4648 def: Pat<(HexagonTCRet texternalsym:$dst),
4649 (TCRETURNtext texternalsym:$dst)>;
4650 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4651 (TCRETURNr (i32 IntRegs:$dst))>;
4653 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4654 def: Pat<(and (i32 IntRegs:$src1), 65535),
4655 (A2_zxth IntRegs:$src1)>;
4657 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4658 def: Pat<(and (i32 IntRegs:$src1), 255),
4659 (A2_zxtb IntRegs:$src1)>;
4661 // Map Add(p1, true) to p1 = not(p1).
4662 // Add(p1, false) should never be produced,
4663 // if it does, it got to be mapped to NOOP.
4664 def: Pat<(add (i1 PredRegs:$src1), -1),
4665 (C2_not PredRegs:$src1)>;
4667 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4668 def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ExtPred:$src3),
4669 (C2_muxii PredRegs:$src1, s8ExtPred:$src3, s8ImmPred:$src2)>;
4671 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4672 // => r0 = C2_muxir(p0, r1, #i)
4673 def: Pat<(select (not (i1 PredRegs:$src1)), s8ExtPred:$src2,
4674 (i32 IntRegs:$src3)),
4675 (C2_muxir PredRegs:$src1, IntRegs:$src3, s8ExtPred:$src2)>;
4677 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4678 // => r0 = C2_muxri (p0, #i, r1)
4679 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s8ExtPred:$src3),
4680 (C2_muxri PredRegs:$src1, s8ExtPred:$src3, IntRegs:$src2)>;
4682 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4683 def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4684 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4686 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4687 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4688 (A2_sxtw (LoReg DoubleRegs:$src1))>;
4690 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)).
4691 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4692 (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>;
4694 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)).
4695 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4696 (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>;
4698 // We want to prevent emitting pnot's as much as possible.
4699 // Map brcond with an unsupported setcc to a J2_jumpf.
4700 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4702 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4705 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4707 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4709 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4710 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4712 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4713 (J2_jumpt PredRegs:$src1, bb:$offset)>;
4715 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4716 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
4717 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
4720 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
4721 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4723 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
4725 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4727 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
4730 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4732 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4735 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4737 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4740 // Map from a 64-bit select to an emulated 64-bit mux.
4741 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4742 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4743 (i64 DoubleRegs:$src3)),
4744 (i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
4745 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4747 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4749 (i32 (C2_mux (i1 PredRegs:$src1),
4750 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4752 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4753 subreg_loreg))))))>;
4755 // Map from a 1-bit select to logical ops.
4756 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4757 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
4758 (i1 PredRegs:$src3)),
4759 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
4760 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
4762 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
4763 def : Pat<(i1 (load ADDRriS11_2:$addr)),
4764 (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
4766 // Map for truncating from 64 immediates to 32 bit immediates.
4767 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
4768 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
4770 // Map for truncating from i64 immediates to i1 bit immediates.
4771 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
4772 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4775 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
4776 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4777 (S2_storerb_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4780 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
4781 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4782 (S2_storerh_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4784 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
4785 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4786 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4789 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
4790 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4791 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4794 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
4795 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4796 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4799 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
4800 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4801 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4803 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
4804 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
4805 (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
4807 // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
4808 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
4809 // Better way to do this?
4810 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
4811 (i64 (A2_sxtw (i32 IntRegs:$src1)))>;
4813 // Map cmple -> cmpgt.
4814 // rs <= rt -> !(rs > rt).
4815 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
4816 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
4818 // rs <= rt -> !(rs > rt).
4819 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4820 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4822 // Rss <= Rtt -> !(Rss > Rtt).
4823 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4824 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4826 // Map cmpne -> cmpeq.
4827 // Hexagon_TODO: We should improve on this.
4828 // rs != rt -> !(rs == rt).
4829 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
4830 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
4832 // Map cmpne(Rs) -> !cmpeqe(Rs).
4833 // rs != rt -> !(rs == rt).
4834 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4835 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
4837 // Convert setne back to xor for hexagon since we compute w/ pred registers.
4838 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
4839 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4841 // Map cmpne(Rss) -> !cmpew(Rss).
4842 // rs != rt -> !(rs == rt).
4843 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4844 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
4845 (i64 DoubleRegs:$src2)))))>;
4847 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
4848 // rs >= rt -> !(rt > rs).
4849 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4850 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
4852 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
4853 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
4854 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
4856 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
4857 // rss >= rtt -> !(rtt > rss).
4858 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4859 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
4860 (i64 DoubleRegs:$src1)))))>;
4862 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
4863 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
4864 // rs < rt -> !(rs >= rt).
4865 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
4866 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
4868 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
4869 // rs < rt -> rt > rs.
4870 // We can let assembler map it, or we can do in the compiler itself.
4871 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4872 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4874 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
4875 // rss < rtt -> (rtt > rss).
4876 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4877 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4879 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
4880 // rs < rt -> rt > rs.
4881 // We can let assembler map it, or we can do in the compiler itself.
4882 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4883 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4885 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
4886 // rs < rt -> rt > rs.
4887 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4888 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4890 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
4891 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
4892 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
4894 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
4895 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
4896 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
4898 // Generate cmpgtu(Rs, #u9)
4899 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
4900 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
4902 // Map from Rs >= Rt -> !(Rt > Rs).
4903 // rs >= rt -> !(rt > rs).
4904 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4905 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
4907 // Map from Rs >= Rt -> !(Rt > Rs).
4908 // rs >= rt -> !(rt > rs).
4909 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4910 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
4912 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
4913 // Map from (Rs <= Rt) -> !(Rs > Rt).
4914 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4915 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4917 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
4918 // Map from (Rs <= Rt) -> !(Rs > Rt).
4919 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4920 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4924 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
4925 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
4928 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
4929 (i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
4931 // Convert sign-extended load back to load and sign extend.
4933 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
4934 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4936 // Convert any-extended load back to load and sign extend.
4938 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
4939 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4941 // Convert sign-extended load back to load and sign extend.
4943 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
4944 (i64 (A2_sxtw (L2_loadrh_io AddrFI:$src1, 0)))>;
4946 // Convert sign-extended load back to load and sign extend.
4948 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
4949 (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
4954 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4955 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4958 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
4959 (i64 (A2_combinew (A2_tfrsi 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
4963 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
4964 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4968 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
4969 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4972 let AddedComplexity = 20 in
4973 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
4974 s11_0ExtPred:$offset))),
4975 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4976 s11_0ExtPred:$offset)))>,
4980 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
4981 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4984 let AddedComplexity = 20 in
4985 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
4986 s11_0ExtPred:$offset))),
4987 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4988 s11_0ExtPred:$offset)))>,
4992 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
4993 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
4996 let AddedComplexity = 20 in
4997 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
4998 s11_1ExtPred:$offset))),
4999 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
5000 s11_1ExtPred:$offset)))>,
5004 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
5005 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
5008 let AddedComplexity = 100 in
5009 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
5010 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
5011 s11_2ExtPred:$offset)))>,
5014 let AddedComplexity = 10 in
5015 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
5016 (i32 (L2_loadri_io AddrFI:$src1, 0))>;
5018 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5019 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
5020 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
5022 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5023 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
5024 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
5026 // Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
5027 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
5028 (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
5031 let AddedComplexity = 100 in
5032 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5034 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
5035 s11_2ExtPred:$offset2)))))),
5036 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5037 (L2_loadri_io IntRegs:$src2,
5038 s11_2ExtPred:$offset2)))>;
5040 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5042 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
5043 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5044 (L2_loadri_io AddrFI:$srcLow, 0)))>;
5046 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5048 (i64 (zext (i32 IntRegs:$srcLow))))),
5049 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5052 let AddedComplexity = 100 in
5053 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5055 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
5056 s11_2ExtPred:$offset2)))))),
5057 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5058 (L2_loadri_io IntRegs:$src2,
5059 s11_2ExtPred:$offset2)))>;
5061 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5063 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
5064 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5065 (L2_loadri_io AddrFI:$srcLow, 0)))>;
5067 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5069 (i64 (zext (i32 IntRegs:$srcLow))))),
5070 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5073 // Any extended 64-bit load.
5074 // anyext i32 -> i64
5075 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
5076 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
5079 // When there is an offset we should prefer the pattern below over the pattern above.
5080 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
5081 // So this complexity below is comfortably higher to allow for choosing the below.
5082 // If this is not done then we generate addresses such as
5083 // ********************************************
5084 // r1 = add (r0, #4)
5085 // r1 = memw(r1 + #0)
5087 // r1 = memw(r0 + #4)
5088 // ********************************************
5089 let AddedComplexity = 100 in
5090 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
5091 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
5092 s11_2ExtPred:$offset)))>,
5095 // anyext i16 -> i64.
5096 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
5097 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io AddrFI:$src1, 0)))>,
5100 let AddedComplexity = 20 in
5101 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
5102 s11_1ExtPred:$offset))),
5103 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io IntRegs:$src1,
5104 s11_1ExtPred:$offset)))>,
5107 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
5108 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
5109 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
5112 // Multiply 64-bit unsigned and use upper result.
5113 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5128 (A2_combinew (A2_tfrsi 0),
5135 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
5137 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
5138 subreg_loreg)))), 32)),
5140 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5141 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
5142 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
5143 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
5144 32)), subreg_loreg)))),
5145 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5146 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
5148 // Multiply 64-bit signed and use upper result.
5149 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5153 (A2_combinew (A2_tfrsi 0),
5163 (A2_combinew (A2_tfrsi 0),
5170 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
5172 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
5173 subreg_loreg)))), 32)),
5175 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5176 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
5177 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
5178 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
5179 32)), subreg_loreg)))),
5180 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5181 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
5183 // Hexagon specific ISD nodes.
5184 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
5185 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
5186 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
5187 SDTHexagonADJDYNALLOC>;
5188 // Needed to tag these instructions for stack layout.
5189 let usesCustomInserter = 1, isAsmParserOnly = 1 in
5190 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
5192 "$dst = add($src1, #$src2)",
5193 [(set (i32 IntRegs:$dst),
5194 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
5195 s16ImmPred:$src2))]>;
5197 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
5198 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
5199 let isCodeGenOnly = 1 in
5200 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5202 [(set (i32 IntRegs:$dst),
5203 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5205 let AddedComplexity = 100 in
5206 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5207 (COPY (i32 IntRegs:$src1))>;
5209 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
5211 def : Pat<(HexagonWrapperJT tjumptable:$dst),
5212 (i32 (CONST32_set_jt tjumptable:$dst))>;
5216 //===----------------------------------------------------------------------===//
5218 // Shift by immediate/register and accumulate/logical
5219 //===----------------------------------------------------------------------===//
5221 // Rx[+-&|]=asr(Rs,#u5)
5222 // Rx[+-&|^]=lsr(Rs,#u5)
5223 // Rx[+-&|^]=asl(Rs,#u5)
5225 let hasNewValue = 1, opNewValue = 0 in
5226 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5227 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5228 : SInst_acc<(outs IntRegs:$Rx),
5229 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5230 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5231 [(set (i32 IntRegs:$Rx),
5232 (OpNode2 (i32 IntRegs:$src1),
5233 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5234 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
5239 let IClass = 0b1000;
5241 let Inst{27-24} = 0b1110;
5242 let Inst{23-22} = majOp{2-1};
5244 let Inst{7} = majOp{0};
5245 let Inst{6-5} = minOp;
5247 let Inst{20-16} = Rs;
5248 let Inst{12-8} = u5;
5251 // Rx[+-&|]=asr(Rs,Rt)
5252 // Rx[+-&|^]=lsr(Rs,Rt)
5253 // Rx[+-&|^]=asl(Rs,Rt)
5255 let hasNewValue = 1, opNewValue = 0 in
5256 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5257 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
5258 : SInst_acc<(outs IntRegs:$Rx),
5259 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5260 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5261 [(set (i32 IntRegs:$Rx),
5262 (OpNode2 (i32 IntRegs:$src1),
5263 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5264 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
5269 let IClass = 0b1100;
5271 let Inst{27-24} = 0b1100;
5272 let Inst{23-22} = majOp;
5273 let Inst{7-6} = minOp;
5275 let Inst{20-16} = Rs;
5276 let Inst{12-8} = Rt;
5279 // Rxx[+-&|]=asr(Rss,#u6)
5280 // Rxx[+-&|^]=lsr(Rss,#u6)
5281 // Rxx[+-&|^]=asl(Rss,#u6)
5283 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5284 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5285 : SInst_acc<(outs DoubleRegs:$Rxx),
5286 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
5287 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5288 [(set (i64 DoubleRegs:$Rxx),
5289 (OpNode2 (i64 DoubleRegs:$src1),
5290 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
5291 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
5296 let IClass = 0b1000;
5298 let Inst{27-24} = 0b0010;
5299 let Inst{23-22} = majOp{2-1};
5300 let Inst{7} = majOp{0};
5301 let Inst{6-5} = minOp;
5302 let Inst{4-0} = Rxx;
5303 let Inst{20-16} = Rss;
5304 let Inst{13-8} = u6;
5308 // Rxx[+-&|]=asr(Rss,Rt)
5309 // Rxx[+-&|^]=lsr(Rss,Rt)
5310 // Rxx[+-&|^]=asl(Rss,Rt)
5311 // Rxx[+-&|^]=lsl(Rss,Rt)
5313 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5314 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5315 : SInst_acc<(outs DoubleRegs:$Rxx),
5316 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5317 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5318 [(set (i64 DoubleRegs:$Rxx),
5319 (OpNode2 (i64 DoubleRegs:$src1),
5320 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5321 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
5326 let IClass = 0b1100;
5328 let Inst{27-24} = 0b1011;
5329 let Inst{23-21} = majOp;
5330 let Inst{20-16} = Rss;
5331 let Inst{12-8} = Rt;
5332 let Inst{7-6} = minOp;
5333 let Inst{4-0} = Rxx;
5336 //===----------------------------------------------------------------------===//
5337 // Multi-class for the shift instructions with logical/arithmetic operators.
5338 //===----------------------------------------------------------------------===//
5340 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
5341 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
5342 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
5343 OpNode2, majOp, minOp >;
5344 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
5345 OpNode2, majOp, minOp >;
5348 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5349 let AddedComplexity = 100 in
5350 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5352 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5353 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5354 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
5357 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5358 let AddedComplexity = 100 in
5359 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
5362 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5364 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5365 xtype_xor_imm_acc<"lsr", srl, 0b01>;
5367 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5368 xtype_xor_imm_acc<"asl", shl, 0b10>;
5370 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
5371 let AddedComplexity = 100 in
5372 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
5374 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
5375 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5376 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5379 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
5380 let AddedComplexity = 100 in
5381 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
5383 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
5384 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
5385 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5386 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
5389 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5390 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5391 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
5394 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
5395 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5396 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5397 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
5399 //===----------------------------------------------------------------------===//
5400 let hasSideEffects = 0 in
5401 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
5402 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
5403 : SInst <(outs RC:$dst),
5404 (ins DoubleRegs:$src1, DoubleRegs:$src2),
5405 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
5406 #!if(hasShift,":>>1","")
5407 #!if(isSat, ":sat", ""),
5408 [], "", S_3op_tc_2_SLOT23 > {
5413 let IClass = 0b1100;
5415 let Inst{27-24} = 0b0001;
5416 let Inst{23-22} = MajOp;
5417 let Inst{20-16} = !if (SwapOps, src2, src1);
5418 let Inst{12-8} = !if (SwapOps, src1, src2);
5419 let Inst{7-5} = MinOp;
5420 let Inst{4-0} = dst;
5423 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
5424 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
5425 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
5426 isSat, isRnd, hasShift>;
5428 let Itinerary = S_3op_tc_1_SLOT23 in {
5429 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5430 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5431 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5432 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
5434 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
5435 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
5438 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
5440 let hasSideEffects = 0 in
5441 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
5442 : SInst < (outs DoubleRegs:$Rdd),
5443 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5444 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5445 [], "", S_3op_tc_1_SLOT23 > {
5451 let IClass = 0b1100;
5453 let Inst{27-24} = 0b0010;
5454 let Inst{23-21} = MajOp;
5455 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5456 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5458 let Inst{4-0} = Rdd;
5461 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5462 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
5464 //===----------------------------------------------------------------------===//
5465 // Template class used by vector shift, vector rotate, vector neg,
5466 // 32-bit shift, 64-bit shifts, etc.
5467 //===----------------------------------------------------------------------===//
5469 let hasSideEffects = 0 in
5470 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
5471 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
5472 : SInst <(outs RC:$dst),
5473 (ins RC:$src1, IntRegs:$src2),
5474 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
5475 pattern, "", S_3op_tc_1_SLOT23> {
5480 let IClass = 0b1100;
5482 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5483 let Inst{23-22} = MajOp;
5484 let Inst{20-16} = src1;
5485 let Inst{12-8} = src2;
5486 let Inst{7-6} = MinOp;
5487 let Inst{4-0} = dst;
5490 let hasNewValue = 1 in
5491 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5492 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5493 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5494 (i32 IntRegs:$src2)))]>;
5496 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
5497 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
5498 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5501 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5502 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5503 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5504 (i32 IntRegs:$src2)))]>;
5507 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5508 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5511 // Shift by register
5512 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5514 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5515 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5516 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5517 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5519 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5521 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5522 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5523 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5524 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5526 // Shift by register with saturation
5527 // Rd=asr(Rs,Rt):sat
5528 // Rd=asl(Rs,Rt):sat
5530 let Defs = [USR_OVF] in {
5531 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5532 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5535 let hasNewValue = 1, hasSideEffects = 0 in
5536 class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
5537 : SInst < (outs IntRegs:$Rd),
5538 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5539 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5540 #!if(hasShift, ":<<1", "")
5541 #!if(isRnd, ":rnd", "")
5542 #!if(isSat, ":sat", ""),
5543 [], "", S_3op_tc_1_SLOT23 > {
5548 let IClass = 0b1100;
5550 let Inst{27-24} = 0b0101;
5551 let Inst{20-16} = Rss;
5552 let Inst{12-8} = Rt;
5553 let Inst{7-5} = MinOp;
5557 def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>;
5559 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
5560 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5562 let hasSideEffects = 0 in
5563 class T_S3op_7 <string mnemonic, bit MajOp >
5564 : SInst <(outs DoubleRegs:$Rdd),
5565 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
5566 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
5567 [], "", S_3op_tc_1_SLOT23 > {
5573 let IClass = 0b1100;
5575 let Inst{27-24} = 0b0000;
5576 let Inst{23} = MajOp;
5577 let Inst{20-16} = !if(MajOp, Rss, Rtt);
5578 let Inst{12-8} = !if(MajOp, Rtt, Rss);
5580 let Inst{4-0} = Rdd;
5583 def S2_valignib : T_S3op_7 < "valignb", 0>;
5584 def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
5586 //===----------------------------------------------------------------------===//
5587 // Template class for 'insert bitfield' instructions
5588 //===----------------------------------------------------------------------===//
5589 let hasSideEffects = 0 in
5590 class T_S3op_insert <string mnemonic, RegisterClass RC>
5591 : SInst <(outs RC:$dst),
5592 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5593 "$dst = "#mnemonic#"($src2, $src3)" ,
5594 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5599 let IClass = 0b1100;
5601 let Inst{27-26} = 0b10;
5602 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5604 let Inst{20-16} = src2;
5605 let Inst{12-8} = src3;
5606 let Inst{4-0} = dst;
5609 let hasSideEffects = 0 in
5610 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5611 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5612 "$dst = insert($src1, #$src2, #$src3)",
5613 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5620 string ImmOpStr = !cast<string>(ImmOp);
5622 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5623 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5625 let IClass = 0b1000;
5627 let Inst{27-24} = RegTyBits;
5628 let Inst{23} = bit23;
5629 let Inst{22-21} = src3{4-3};
5630 let Inst{20-16} = src1;
5631 let Inst{13} = bit13;
5632 let Inst{12-8} = src2{4-0};
5633 let Inst{7-5} = src3{2-0};
5634 let Inst{4-0} = dst;
5637 // Rx=insert(Rs,Rtt)
5638 // Rx=insert(Rs,#u5,#U5)
5639 let hasNewValue = 1 in {
5640 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5641 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5644 // Rxx=insert(Rss,Rtt)
5645 // Rxx=insert(Rss,#u6,#U6)
5646 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5647 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5649 //===----------------------------------------------------------------------===//
5650 // Template class for 'extract bitfield' instructions
5651 //===----------------------------------------------------------------------===//
5652 let hasNewValue = 1, hasSideEffects = 0 in
5653 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5654 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5655 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5656 [], "", S_3op_tc_2_SLOT23 > {
5661 let IClass = 0b1100;
5663 let Inst{27-22} = 0b100100;
5664 let Inst{20-16} = Rs;
5665 let Inst{12-8} = Rtt;
5666 let Inst{7-6} = MinOp;
5670 let hasSideEffects = 0 in
5671 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5672 RegisterClass RC, Operand ImmOp>
5673 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5674 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5675 [], "", S_2op_tc_2_SLOT23> {
5682 string ImmOpStr = !cast<string>(ImmOp);
5684 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5685 !if (!eq(mnemonic, "extractu"), 0, 1));
5687 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5689 let IClass = 0b1000;
5691 let Inst{27-24} = RegTyBits;
5692 let Inst{23} = bit23;
5693 let Inst{22-21} = src3{4-3};
5694 let Inst{20-16} = src1;
5695 let Inst{13} = bit13;
5696 let Inst{12-8} = src2{4-0};
5697 let Inst{7-5} = src3{2-0};
5698 let Inst{4-0} = dst;
5703 // Rdd=extractu(Rss,Rtt)
5704 // Rdd=extractu(Rss,#u6,#U6)
5705 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5706 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5708 // Rd=extractu(Rs,Rtt)
5709 // Rd=extractu(Rs,#u5,#U5)
5710 let hasNewValue = 1 in {
5711 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5712 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5715 //===----------------------------------------------------------------------===//
5716 // :raw for of tableindx[bdhw] insns
5717 //===----------------------------------------------------------------------===//
5719 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5720 class tableidxRaw<string OpStr, bits<2>MinOp>
5721 : SInst <(outs IntRegs:$Rx),
5722 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5723 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5724 [], "$Rx = $_dst_" > {
5730 let IClass = 0b1000;
5732 let Inst{27-24} = 0b0111;
5733 let Inst{23-22} = MinOp;
5734 let Inst{21} = u4{3};
5735 let Inst{20-16} = Rs;
5736 let Inst{13-8} = S6;
5737 let Inst{7-5} = u4{2-0};
5741 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5742 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5743 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5744 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5746 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5747 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5748 (i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
5750 //===----------------------------------------------------------------------===//
5751 // V3 Instructions +
5752 //===----------------------------------------------------------------------===//
5754 include "HexagonInstrInfoV3.td"
5756 //===----------------------------------------------------------------------===//
5757 // V3 Instructions -
5758 //===----------------------------------------------------------------------===//
5760 //===----------------------------------------------------------------------===//
5761 // V4 Instructions +
5762 //===----------------------------------------------------------------------===//
5764 include "HexagonInstrInfoV4.td"
5766 //===----------------------------------------------------------------------===//
5767 // V4 Instructions -
5768 //===----------------------------------------------------------------------===//
5770 //===----------------------------------------------------------------------===//
5771 // V5 Instructions +
5772 //===----------------------------------------------------------------------===//
5774 include "HexagonInstrInfoV5.td"
5776 //===----------------------------------------------------------------------===//
5777 // V5 Instructions -
5778 //===----------------------------------------------------------------------===//
5780 //===----------------------------------------------------------------------===//
5781 // ALU32/64/Vector +
5782 //===----------------------------------------------------------------------===///
5784 include "HexagonInstrInfoVector.td"