1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 //===----------------------------------------------------------------------===//
30 // Multi-class for logical operators.
31 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
32 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
33 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
34 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
36 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
37 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
38 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
42 // Multi-class for compare ops.
43 let isCompare = 1 in {
44 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
45 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
46 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
47 [(set (i1 PredRegs:$dst),
48 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
51 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
52 let CextOpcode = CextOp in {
53 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
54 opExtentBits = 10, InputType = "imm" in
55 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
56 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
57 [(set (i1 PredRegs:$dst),
58 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
62 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
63 let CextOpcode = CextOp in {
64 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
65 opExtentBits = 9, InputType = "imm" in
66 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
67 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
68 [(set (i1 PredRegs:$dst),
69 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
73 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
74 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
75 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
76 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
77 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
82 //===----------------------------------------------------------------------===//
83 // ALU32/ALU (Instructions with register-register form)
84 //===----------------------------------------------------------------------===//
85 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
86 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
88 def HexagonWrapperCombineII :
89 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
91 def HexagonWrapperCombineRR :
92 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
94 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
95 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
97 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
98 "$Rd = "#mnemonic#"($Rs, $Rt)",
99 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
100 let isCommutable = IsComm;
101 let BaseOpcode = mnemonic#_rr;
102 let CextOpcode = mnemonic;
110 let Inst{26-24} = MajOp;
111 let Inst{23-21} = MinOp;
112 let Inst{20-16} = !if(OpsRev,Rt,Rs);
113 let Inst{12-8} = !if(OpsRev,Rs,Rt);
117 let hasSideEffects = 0, hasNewValue = 1 in
118 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
119 bit OpsRev, bit PredNot, bit PredNew>
120 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
121 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
123 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
124 let isPredicated = 1;
125 let isPredicatedFalse = PredNot;
126 let isPredicatedNew = PredNew;
127 let BaseOpcode = mnemonic#_rr;
128 let CextOpcode = mnemonic;
137 let Inst{26-24} = MajOp;
138 let Inst{23-21} = MinOp;
139 let Inst{20-16} = !if(OpsRev,Rt,Rs);
140 let Inst{13} = PredNew;
141 let Inst{12-8} = !if(OpsRev,Rs,Rt);
142 let Inst{7} = PredNot;
147 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
149 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
150 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
151 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
152 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
155 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
156 bit OpsRev, bit IsComm> {
157 let isPredicable = 1 in
158 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
159 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
162 let isCodeGenOnly = 0 in
163 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
164 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
165 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
166 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
167 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
169 // Pats for instruction selection.
170 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
171 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
172 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
174 def: BinOp32_pat<add, A2_add, i32>;
175 def: BinOp32_pat<and, A2_and, i32>;
176 def: BinOp32_pat<or, A2_or, i32>;
177 def: BinOp32_pat<sub, A2_sub, i32>;
178 def: BinOp32_pat<xor, A2_xor, i32>;
180 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
182 let isPredicatedNew = isPredNew in
183 def NAME : ALU32_rr<(outs RC:$dst),
184 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
185 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
186 ") $dst = ")#mnemonic#"($src2, $src3)",
190 multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
191 let isPredicatedFalse = PredNot in {
192 defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
194 defm _cdn#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 1>;
198 //===----------------------------------------------------------------------===//
199 // template class for non-predicated alu32_2op instructions
200 // - aslh, asrh, sxtb, sxth, zxth
201 //===----------------------------------------------------------------------===//
202 let hasNewValue = 1, opNewValue = 0 in
203 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
204 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
205 "$Rd = "#mnemonic#"($Rs)", [] > {
211 let Inst{27-24} = 0b0000;
212 let Inst{23-21} = minOp;
215 let Inst{20-16} = Rs;
218 //===----------------------------------------------------------------------===//
219 // template class for predicated alu32_2op instructions
220 // - aslh, asrh, sxtb, sxth, zxtb, zxth
221 //===----------------------------------------------------------------------===//
222 let hasSideEffects = 0, validSubTargets = HasV4SubT,
223 hasNewValue = 1, opNewValue = 0 in
224 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
226 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
227 !if(isPredNot, "if (!$Pu", "if ($Pu")
228 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
235 let Inst{27-24} = 0b0000;
236 let Inst{23-21} = minOp;
238 let Inst{11} = isPredNot;
239 let Inst{10} = isPredNew;
242 let Inst{20-16} = Rs;
245 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
246 let isPredicatedFalse = PredNot in {
247 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
250 let isPredicatedNew = 1 in
251 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
255 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
256 let BaseOpcode = mnemonic in {
257 let isPredicable = 1, hasSideEffects = 0 in
258 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
260 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
261 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
262 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
267 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
268 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
269 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
270 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
271 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
273 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
274 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
275 // predicated forms while 'and' doesn't. Since integrated assembler can't
276 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
277 // immediate operand is set to '255'.
279 let hasNewValue = 1, opNewValue = 0 in
280 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
281 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
288 let Inst{27-22} = 0b011000;
290 let Inst{20-16} = Rs;
291 let Inst{21} = s10{9};
292 let Inst{13-5} = s10{8-0};
295 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
296 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
297 let BaseOpcode = mnemonic in {
298 let isPredicable = 1, hasSideEffects = 0 in
299 def A2_#NAME : T_ZXTB;
301 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
302 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
303 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
308 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
310 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in
311 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
312 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
313 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
319 let CextOpcode = "mux";
320 let InputType = "reg";
321 let hasSideEffects = 0;
324 let Inst{27-24} = 0b0100;
325 let Inst{20-16} = Rs;
331 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
332 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
334 // Combines the two integer registers SRC1 and SRC2 into a double register.
335 let isPredicable = 1 in
336 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
337 (ins IntRegs:$src1, IntRegs:$src2),
338 "$dst = combine($src1, $src2)",
339 [(set (i64 DoubleRegs:$dst),
340 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
341 (i32 IntRegs:$src2))))]>;
343 multiclass Combine_base {
344 let BaseOpcode = "combine" in {
345 def NAME : T_Combine;
346 let hasSideEffects = 0, isPredicated = 1 in {
347 defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
348 defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
353 defm COMBINE_rr : Combine_base, PredNewRel;
355 // Combines the two immediates SRC1 and SRC2 into a double register.
356 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
357 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
358 "$dst = combine(#$src1, #$src2)",
359 [(set (i64 DoubleRegs:$dst),
360 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
362 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
363 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
365 //===----------------------------------------------------------------------===//
366 // ALU32/ALU (ADD with register-immediate form)
367 //===----------------------------------------------------------------------===//
368 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
369 let isPredicatedNew = isPredNew in
370 def NAME : ALU32_ri<(outs IntRegs:$dst),
371 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
372 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
373 ") $dst = ")#mnemonic#"($src2, #$src3)",
377 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
378 let isPredicatedFalse = PredNot in {
379 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
381 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
385 let isExtendable = 1, InputType = "imm" in
386 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
387 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
388 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
390 def NAME : ALU32_ri<(outs IntRegs:$dst),
391 (ins IntRegs:$src1, s16Ext:$src2),
392 "$dst = "#mnemonic#"($src1, #$src2)",
393 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
394 (s16ExtPred:$src2)))]>;
396 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
397 hasSideEffects = 0, isPredicated = 1 in {
398 defm Pt : ALU32ri_Pred<mnemonic, 0>;
399 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
404 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
406 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
407 CextOpcode = "OR", InputType = "imm" in
408 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
409 (ins IntRegs:$src1, s10Ext:$src2),
410 "$dst = or($src1, #$src2)",
411 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
412 s10ExtPred:$src2))]>, ImmRegRel;
414 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
415 InputType = "imm", CextOpcode = "AND" in
416 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
417 (ins IntRegs:$src1, s10Ext:$src2),
418 "$dst = and($src1, #$src2)",
419 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
420 s10ExtPred:$src2))]>, ImmRegRel;
423 let hasSideEffects = 0 in
424 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
426 let Inst{27-24} = 0b1111;
429 // Rd32=sub(#s10,Rs32)
430 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
431 CextOpcode = "SUB", InputType = "imm" in
432 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
433 (ins s10Ext:$src1, IntRegs:$src2),
434 "$dst = sub(#$src1, $src2)",
435 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
438 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
439 def : Pat<(not (i32 IntRegs:$src1)),
440 (SUB_ri -1, (i32 IntRegs:$src1))>;
442 // Rd = neg(Rs) gets mapped to Rd=sub(#0, Rs).
443 // Pattern definition for 'neg' was not necessary.
445 multiclass TFR_Pred<bit PredNot> {
446 let isPredicatedFalse = PredNot in {
447 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
448 (ins PredRegs:$src1, IntRegs:$src2),
449 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
452 let isPredicatedNew = 1 in
453 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
454 (ins PredRegs:$src1, IntRegs:$src2),
455 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
460 let InputType = "reg", hasSideEffects = 0 in
461 multiclass TFR_base<string CextOp> {
462 let CextOpcode = CextOp, BaseOpcode = CextOp in {
463 let isPredicable = 1 in
464 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
468 let isPredicated = 1 in {
469 defm Pt : TFR_Pred<0>;
470 defm NotPt : TFR_Pred<1>;
475 class T_TFR64_Pred<bit PredNot, bit isPredNew>
476 : ALU32_rr<(outs DoubleRegs:$dst),
477 (ins PredRegs:$src1, DoubleRegs:$src2),
478 !if(PredNot, "if (!$src1", "if ($src1")#
479 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
486 let Inst{27-24} = 0b1101;
487 let Inst{13} = isPredNew;
488 let Inst{7} = PredNot;
490 let Inst{6-5} = src1;
491 let Inst{20-17} = src2{4-1};
493 let Inst{12-9} = src2{4-1};
497 multiclass TFR64_Pred<bit PredNot> {
498 let isPredicatedFalse = PredNot in {
499 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
501 let isPredicatedNew = 1 in
502 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
506 let hasSideEffects = 0 in
507 multiclass TFR64_base<string BaseName> {
508 let BaseOpcode = BaseName in {
509 let isPredicable = 1 in
510 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
511 (ins DoubleRegs:$src1),
517 let Inst{27-23} = 0b01010;
519 let Inst{20-17} = src1{4-1};
521 let Inst{12-9} = src1{4-1};
525 let isPredicated = 1 in {
526 defm Pt : TFR64_Pred<0>;
527 defm NotPt : TFR64_Pred<1>;
532 multiclass TFRI_Pred<bit PredNot> {
533 let isMoveImm = 1, isPredicatedFalse = PredNot in {
534 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
535 (ins PredRegs:$src1, s12Ext:$src2),
536 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
540 let isPredicatedNew = 1 in
541 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
542 (ins PredRegs:$src1, s12Ext:$src2),
543 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
548 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
549 multiclass TFRI_base<string CextOp> {
550 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
551 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
552 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
553 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
555 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
557 let opExtendable = 2, opExtentBits = 12, hasSideEffects = 0,
558 isPredicated = 1 in {
559 defm Pt : TFRI_Pred<0>;
560 defm NotPt : TFRI_Pred<1>;
565 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
566 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
567 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
569 // Transfer control register.
570 let hasSideEffects = 0 in
571 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
574 //===----------------------------------------------------------------------===//
576 //===----------------------------------------------------------------------===//
579 //===----------------------------------------------------------------------===//
581 //===----------------------------------------------------------------------===//
583 let hasSideEffects = 0 in
584 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
585 (ins s8Imm:$src1, s8Imm:$src2),
586 "$dst = combine(#$src1, #$src2)",
590 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
593 "$dst = vmux($src1, $src2, $src3)",
596 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
597 CextOpcode = "MUX", InputType = "imm" in
598 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
600 "$dst = mux($src1, #$src2, $src3)",
601 [(set (i32 IntRegs:$dst),
602 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
603 (i32 IntRegs:$src3))))]>, ImmRegRel;
605 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
606 CextOpcode = "MUX", InputType = "imm" in
607 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
609 "$dst = mux($src1, $src2, #$src3)",
610 [(set (i32 IntRegs:$dst),
611 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
612 s8ExtPred:$src3)))]>, ImmRegRel;
614 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
615 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
617 "$dst = mux($src1, #$src2, #$src3)",
618 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
620 s8ImmPred:$src3)))]>;
622 def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
623 (A2_aslh IntRegs:$src1)>;
625 def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
626 (A2_asrh IntRegs:$src1)>;
628 def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
629 (A2_sxtb IntRegs:$src1)>;
631 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
632 (A2_sxth IntRegs:$src1)>;
634 //===----------------------------------------------------------------------===//
636 //===----------------------------------------------------------------------===//
639 //===----------------------------------------------------------------------===//
641 //===----------------------------------------------------------------------===//
644 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
645 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
646 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
647 "$Pd = "#mnemonic#"($Rs, $Rt)",
648 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
649 let CextOpcode = mnemonic;
650 let isCommutable = IsComm;
656 let Inst{27-24} = 0b0010;
657 let Inst{22-21} = MinOp;
658 let Inst{20-16} = Rs;
661 let Inst{3-2} = 0b00;
665 let Itinerary = ALU32_3op_tc_2early_SLOT0123 in {
666 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
667 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
668 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
671 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
672 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
674 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
675 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
676 "", ALU64_tc_1_SLOT23> {
677 let hasSideEffects = 0;
678 let isCommutable = IsComm;
685 let Inst{27-24} = RegType;
686 let Inst{23-21} = MajOp;
687 let Inst{20-16} = !if (OpsRev,Rt,Rs);
688 let Inst{12-8} = !if (OpsRev,Rs,Rt);
689 let Inst{7-5} = MinOp;
693 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
694 bit OpsRev, bit IsComm>
695 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
698 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
699 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
701 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
702 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
704 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
705 // that reverse the order of the operands.
706 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
708 // Pats for compares. They use PatFrags as operands, not SDNodes,
709 // since seteq/setgt/etc. are defined as ParFrags.
710 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
711 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
712 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
714 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
715 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
716 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
718 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
719 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
722 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
723 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
724 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
726 // SDNode for converting immediate C to C-1.
727 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
728 // Return the byte immediate const-1 as an SDNode.
729 int32_t imm = N->getSExtValue();
730 return XformSToSM1Imm(imm);
733 // SDNode for converting immediate C to C-1.
734 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
735 // Return the byte immediate const-1 as an SDNode.
736 uint32_t imm = N->getZExtValue();
737 return XformUToUM1Imm(imm);
740 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
742 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
744 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
746 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
748 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
750 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
752 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
754 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
756 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
757 "$dst = tstbit($src1, $src2)",
758 [(set (i1 PredRegs:$dst),
759 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
761 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
762 "$dst = tstbit($src1, $src2)",
763 [(set (i1 PredRegs:$dst),
764 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
766 //===----------------------------------------------------------------------===//
768 //===----------------------------------------------------------------------===//
771 //===----------------------------------------------------------------------===//
773 //===----------------------------------------------------------------------===//
775 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
777 "$dst = add($src1, $src2)",
778 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
779 (i64 DoubleRegs:$src2)))]>;
784 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
785 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
786 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
788 // Logical operations.
789 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
791 "$dst = and($src1, $src2)",
792 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
793 (i64 DoubleRegs:$src2)))]>;
795 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
797 "$dst = or($src1, $src2)",
798 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
799 (i64 DoubleRegs:$src2)))]>;
801 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
803 "$dst = xor($src1, $src2)",
804 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
805 (i64 DoubleRegs:$src2)))]>;
808 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
809 "$dst = max($src2, $src1)",
810 [(set (i32 IntRegs:$dst),
811 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
812 (i32 IntRegs:$src1))),
813 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
815 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
816 "$dst = maxu($src2, $src1)",
817 [(set (i32 IntRegs:$dst),
818 (i32 (select (i1 (setult (i32 IntRegs:$src2),
819 (i32 IntRegs:$src1))),
820 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
822 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
824 "$dst = max($src2, $src1)",
825 [(set (i64 DoubleRegs:$dst),
826 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
827 (i64 DoubleRegs:$src1))),
828 (i64 DoubleRegs:$src1),
829 (i64 DoubleRegs:$src2))))]>;
831 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
833 "$dst = maxu($src2, $src1)",
834 [(set (i64 DoubleRegs:$dst),
835 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
836 (i64 DoubleRegs:$src1))),
837 (i64 DoubleRegs:$src1),
838 (i64 DoubleRegs:$src2))))]>;
841 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
842 "$dst = min($src2, $src1)",
843 [(set (i32 IntRegs:$dst),
844 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
845 (i32 IntRegs:$src1))),
846 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
848 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
849 "$dst = minu($src2, $src1)",
850 [(set (i32 IntRegs:$dst),
851 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
852 (i32 IntRegs:$src1))),
853 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
855 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
857 "$dst = min($src2, $src1)",
858 [(set (i64 DoubleRegs:$dst),
859 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
860 (i64 DoubleRegs:$src1))),
861 (i64 DoubleRegs:$src1),
862 (i64 DoubleRegs:$src2))))]>;
864 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
866 "$dst = minu($src2, $src1)",
867 [(set (i64 DoubleRegs:$dst),
868 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
869 (i64 DoubleRegs:$src1))),
870 (i64 DoubleRegs:$src1),
871 (i64 DoubleRegs:$src2))))]>;
874 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
876 "$dst = sub($src1, $src2)",
877 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
878 (i64 DoubleRegs:$src2)))]>;
880 // Subtract halfword.
882 //===----------------------------------------------------------------------===//
884 //===----------------------------------------------------------------------===//
886 //===----------------------------------------------------------------------===//
888 //===----------------------------------------------------------------------===//
890 //===----------------------------------------------------------------------===//
892 //===----------------------------------------------------------------------===//
894 //===----------------------------------------------------------------------===//
896 //===----------------------------------------------------------------------===//
898 //===----------------------------------------------------------------------===//
900 //===----------------------------------------------------------------------===//
902 //===----------------------------------------------------------------------===//
904 //===----------------------------------------------------------------------===//
905 // Logical reductions on predicates.
907 // Looping instructions.
909 // Pipelined looping instructions.
911 // Logical operations on predicates.
912 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
913 "$dst = and($src1, $src2)",
914 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
915 (i1 PredRegs:$src2)))]>;
917 let hasSideEffects = 0 in
918 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
920 "$dst = and($src1, !$src2)",
923 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
924 "$dst = any8($src1)",
927 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
928 "$dst = all8($src1)",
931 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
933 "$dst = vitpack($src1, $src2)",
936 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
939 "$dst = valignb($src1, $src2, $src3)",
942 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
945 "$dst = vspliceb($src1, $src2, $src3)",
948 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
949 "$dst = mask($src1)",
952 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
954 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
956 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
957 "$dst = or($src1, $src2)",
958 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
959 (i1 PredRegs:$src2)))]>;
961 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
962 "$dst = xor($src1, $src2)",
963 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
964 (i1 PredRegs:$src2)))]>;
967 // User control register transfer.
968 //===----------------------------------------------------------------------===//
970 //===----------------------------------------------------------------------===//
972 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
973 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
974 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone,
977 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
978 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
980 let InputType = "imm", isBarrier = 1, isPredicable = 1,
981 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
982 opExtentBits = 24, isCodeGenOnly = 0 in
983 class T_JMP <dag InsDag, list<dag> JumpList = []>
984 : JInst<(outs), InsDag,
985 "jump $dst" , JumpList> {
990 let Inst{27-25} = 0b100;
991 let Inst{24-16} = dst{23-15};
992 let Inst{13-1} = dst{14-2};
995 let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
996 Defs = [PC], isPredicated = 1, opExtentBits = 17 in
997 class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
998 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
999 !if(PredNot, "if (!$src", "if ($src")#
1000 !if(isPredNew, ".new) ", ") ")#"jump"#
1001 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
1003 let isTaken = isTak;
1004 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
1005 let isPredicatedFalse = PredNot;
1006 let isPredicatedNew = isPredNew;
1010 let IClass = 0b0101;
1012 let Inst{27-24} = 0b1100;
1013 let Inst{21} = PredNot;
1014 let Inst{12} = !if(isPredNew, isTak, zero);
1015 let Inst{11} = isPredNew;
1016 let Inst{9-8} = src;
1017 let Inst{23-22} = dst{16-15};
1018 let Inst{20-16} = dst{14-10};
1019 let Inst{13} = dst{9};
1020 let Inst{7-1} = dst{8-2};
1023 let isBarrier = 1, Defs = [PC], isPredicable = 1, InputType = "reg" in
1024 class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
1025 : JRInst<(outs ), InsDag,
1030 let IClass = 0b0101;
1031 let Inst{27-21} = 0b0010100;
1032 let Inst{20-16} = dst;
1035 let Defs = [PC], isPredicated = 1, InputType = "reg" in
1036 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
1037 JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
1038 !if(PredNot, "if (!$src", "if ($src")#
1039 !if(isPredNew, ".new) ", ") ")#"jumpr"#
1040 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
1042 let isTaken = isTak;
1043 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
1044 let isPredicatedFalse = PredNot;
1045 let isPredicatedNew = isPredNew;
1049 let IClass = 0b0101;
1051 let Inst{27-22} = 0b001101;
1052 let Inst{21} = PredNot;
1053 let Inst{20-16} = dst;
1054 let Inst{12} = !if(isPredNew, isTak, zero);
1055 let Inst{11} = isPredNew;
1056 let Inst{9-8} = src;
1057 let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
1058 let validSubTargets = !if(isPredNew, HasV3SubT, HasV2SubT);
1061 multiclass JMP_Pred<bit PredNot> {
1062 def _#NAME : T_JMP_c<PredNot, 0, 0>;
1064 def _#NAME#new_t : T_JMP_c<PredNot, 1, 1>; // taken
1065 def _#NAME#new_nt : T_JMP_c<PredNot, 1, 0>; // not taken
1068 multiclass JMP_base<string BaseOp> {
1069 let BaseOpcode = BaseOp in {
1070 def NAME : T_JMP<(ins brtarget:$dst), [(br bb:$dst)]>;
1071 defm t : JMP_Pred<0>;
1072 defm f : JMP_Pred<1>;
1076 multiclass JMPR_Pred<bit PredNot> {
1077 def NAME: T_JMPr_c<PredNot, 0, 0>;
1079 def NAME#new_tV3 : T_JMPr_c<PredNot, 1, 1>; // taken
1080 def NAME#new_ntV3 : T_JMPr_c<PredNot, 1, 0>; // not taken
1083 multiclass JMPR_base<string BaseOp> {
1084 let BaseOpcode = BaseOp in {
1086 defm _t : JMPR_Pred<0>;
1087 defm _f : JMPR_Pred<1>;
1091 let isTerminator = 1, hasSideEffects = 0 in {
1093 defm JMP : JMP_base<"JMP">, PredNewRel;
1095 let isBranch = 1, isIndirectBranch = 1 in
1096 defm JMPR : JMPR_base<"JMPr">, PredNewRel;
1098 let isReturn = 1, isCodeGenOnly = 1 in
1099 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1102 def : Pat<(retflag),
1103 (JMPret (i32 R31))>;
1105 def : Pat <(brcond (i1 PredRegs:$src1), bb:$offset),
1106 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
1108 // A return through builtin_eh_return.
1109 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1110 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1111 def EH_RETURN_JMPR : T_JMPr;
1113 def : Pat<(eh_return),
1114 (EH_RETURN_JMPR (i32 R31))>;
1116 def : Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1117 (JMPR (i32 IntRegs:$dst))>;
1119 def : Pat<(brind (i32 IntRegs:$dst)),
1120 (JMPR (i32 IntRegs:$dst))>;
1122 //===----------------------------------------------------------------------===//
1124 //===----------------------------------------------------------------------===//
1126 //===----------------------------------------------------------------------===//
1128 //===----------------------------------------------------------------------===//
1130 // Load -- MEMri operand
1131 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
1132 bit isNot, bit isPredNew> {
1133 let isPredicatedNew = isPredNew in
1134 def NAME : LDInst2<(outs RC:$dst),
1135 (ins PredRegs:$src1, MEMri:$addr),
1136 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1137 ") ")#"$dst = "#mnemonic#"($addr)",
1141 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1142 let isPredicatedFalse = PredNot in {
1143 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1145 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1149 let isExtendable = 1, hasSideEffects = 0 in
1150 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1151 bits<5> ImmBits, bits<5> PredImmBits> {
1153 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1154 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1156 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
1157 "$dst = "#mnemonic#"($addr)",
1160 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1161 isPredicated = 1 in {
1162 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
1163 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
1168 let addrMode = BaseImmOffset, isMEMri = "true" in {
1169 let accessSize = ByteAccess in {
1170 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
1171 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
1174 let accessSize = HalfWordAccess in {
1175 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
1176 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
1179 let accessSize = WordAccess in
1180 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
1182 let accessSize = DoubleWordAccess in
1183 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
1186 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
1187 (LDrib ADDRriS11_0:$addr) >;
1189 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
1190 (LDriub ADDRriS11_0:$addr) >;
1192 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
1193 (LDrih ADDRriS11_1:$addr) >;
1195 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
1196 (LDriuh ADDRriS11_1:$addr) >;
1198 def : Pat < (i32 (load ADDRriS11_2:$addr)),
1199 (LDriw ADDRriS11_2:$addr) >;
1201 def : Pat < (i64 (load ADDRriS11_3:$addr)),
1202 (LDrid ADDRriS11_3:$addr) >;
1205 // Load - Base with Immediate offset addressing mode
1206 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1207 bit isNot, bit isPredNew> {
1208 let isPredicatedNew = isPredNew in
1209 def NAME : LDInst2<(outs RC:$dst),
1210 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
1211 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1212 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
1216 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1218 let isPredicatedFalse = PredNot in {
1219 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1221 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1225 let isExtendable = 1, hasSideEffects = 0 in
1226 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1227 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1228 bits<5> PredImmBits> {
1230 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1231 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1232 isPredicable = 1, AddedComplexity = 20 in
1233 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1234 "$dst = "#mnemonic#"($src1+#$offset)",
1237 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1238 isPredicated = 1 in {
1239 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
1240 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
1245 let addrMode = BaseImmOffset in {
1246 let accessSize = ByteAccess in {
1247 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1248 11, 6>, AddrModeRel;
1249 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1250 11, 6>, AddrModeRel;
1252 let accessSize = HalfWordAccess in {
1253 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1254 12, 7>, AddrModeRel;
1255 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1256 12, 7>, AddrModeRel;
1258 let accessSize = WordAccess in
1259 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1260 13, 8>, AddrModeRel;
1262 let accessSize = DoubleWordAccess in
1263 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1264 14, 9>, AddrModeRel;
1267 let AddedComplexity = 20 in {
1268 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1269 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1271 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1272 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1274 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1275 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1277 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1278 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1280 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1281 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1283 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1284 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1287 //===----------------------------------------------------------------------===//
1288 // Post increment load
1289 //===----------------------------------------------------------------------===//
1291 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1292 bit isNot, bit isPredNew> {
1293 let isPredicatedNew = isPredNew in
1294 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1295 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1296 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1297 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1302 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1303 Operand ImmOp, bit PredNot> {
1304 let isPredicatedFalse = PredNot in {
1305 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1307 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1308 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1312 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1315 let BaseOpcode = "POST_"#BaseOp in {
1316 let isPredicable = 1 in
1317 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1318 (ins IntRegs:$src1, ImmOp:$offset),
1319 "$dst = "#mnemonic#"($src1++#$offset)",
1323 let isPredicated = 1 in {
1324 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1325 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1330 let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
1331 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1333 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1335 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1337 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1339 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1341 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1345 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1346 (i32 (LDrib ADDRriS11_0:$addr)) >;
1348 // Load byte any-extend.
1349 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1350 (i32 (LDrib ADDRriS11_0:$addr)) >;
1352 // Indexed load byte any-extend.
1353 let AddedComplexity = 20 in
1354 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1355 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1357 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1358 (i32 (LDrih ADDRriS11_1:$addr))>;
1360 let AddedComplexity = 20 in
1361 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1362 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1364 let AddedComplexity = 10 in
1365 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1366 (i32 (LDriub ADDRriS11_0:$addr))>;
1368 let AddedComplexity = 20 in
1369 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1370 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1373 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1374 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1375 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1377 "Error; should not emit",
1380 // Deallocate stack frame.
1381 let Defs = [R29, R30, R31], Uses = [R29], hasSideEffects = 0 in {
1382 def DEALLOCFRAME : LDInst2<(outs), (ins),
1387 // Load and unpack bytes to halfwords.
1388 //===----------------------------------------------------------------------===//
1390 //===----------------------------------------------------------------------===//
1392 //===----------------------------------------------------------------------===//
1394 //===----------------------------------------------------------------------===//
1395 //===----------------------------------------------------------------------===//
1397 //===----------------------------------------------------------------------===//
1399 //===----------------------------------------------------------------------===//
1401 //===----------------------------------------------------------------------===//
1402 //===----------------------------------------------------------------------===//
1404 //===----------------------------------------------------------------------===//
1406 //===----------------------------------------------------------------------===//
1408 //===----------------------------------------------------------------------===//
1409 // Multiply and use lower result.
1411 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1412 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1413 "$dst =+ mpyi($src1, #$src2)",
1414 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1415 u8ExtPred:$src2))]>;
1418 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1419 "$dst =- mpyi($src1, #$src2)",
1420 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1421 u8ImmPred:$src2)))]>;
1424 // s9 is NOT the same as m9 - but it works.. so far.
1425 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1426 // depending on the value of m9. See Arch Spec.
1427 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1428 CextOpcode = "MPYI", InputType = "imm" in
1429 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1430 "$dst = mpyi($src1, #$src2)",
1431 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1432 s9ExtPred:$src2))]>, ImmRegRel;
1435 let CextOpcode = "MPYI", InputType = "reg" in
1436 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1437 "$dst = mpyi($src1, $src2)",
1438 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1439 (i32 IntRegs:$src2)))]>, ImmRegRel;
1442 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1443 CextOpcode = "MPYI_acc", InputType = "imm" in
1444 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1445 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1446 "$dst += mpyi($src2, #$src3)",
1447 [(set (i32 IntRegs:$dst),
1448 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1449 (i32 IntRegs:$src1)))],
1450 "$src1 = $dst">, ImmRegRel;
1453 let CextOpcode = "MPYI_acc", InputType = "reg" in
1454 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1455 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1456 "$dst += mpyi($src2, $src3)",
1457 [(set (i32 IntRegs:$dst),
1458 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1459 (i32 IntRegs:$src1)))],
1460 "$src1 = $dst">, ImmRegRel;
1463 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1464 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1465 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1466 "$dst -= mpyi($src2, #$src3)",
1467 [(set (i32 IntRegs:$dst),
1468 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1469 u8ExtPred:$src3)))],
1472 // Multiply and use upper result.
1473 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1474 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1476 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1477 "$dst = mpy($src1, $src2)",
1478 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1479 (i32 IntRegs:$src2)))]>;
1481 // Rd=mpy(Rs,Rt):rnd
1483 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1484 "$dst = mpyu($src1, $src2)",
1485 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1486 (i32 IntRegs:$src2)))]>;
1488 // Multiply and use full result.
1490 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1491 "$dst = mpyu($src1, $src2)",
1492 [(set (i64 DoubleRegs:$dst),
1493 (mul (i64 (anyext (i32 IntRegs:$src1))),
1494 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1497 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1498 "$dst = mpy($src1, $src2)",
1499 [(set (i64 DoubleRegs:$dst),
1500 (mul (i64 (sext (i32 IntRegs:$src1))),
1501 (i64 (sext (i32 IntRegs:$src2)))))]>;
1503 // Multiply and accumulate, use full result.
1504 // Rxx[+-]=mpy(Rs,Rt)
1506 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1507 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1508 "$dst += mpy($src2, $src3)",
1509 [(set (i64 DoubleRegs:$dst),
1510 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1511 (i64 (sext (i32 IntRegs:$src3)))),
1512 (i64 DoubleRegs:$src1)))],
1516 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1517 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1518 "$dst -= mpy($src2, $src3)",
1519 [(set (i64 DoubleRegs:$dst),
1520 (sub (i64 DoubleRegs:$src1),
1521 (mul (i64 (sext (i32 IntRegs:$src2))),
1522 (i64 (sext (i32 IntRegs:$src3))))))],
1525 // Rxx[+-]=mpyu(Rs,Rt)
1527 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1528 IntRegs:$src2, IntRegs:$src3),
1529 "$dst += mpyu($src2, $src3)",
1530 [(set (i64 DoubleRegs:$dst),
1531 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1532 (i64 (anyext (i32 IntRegs:$src3)))),
1533 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1536 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1537 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1538 "$dst -= mpyu($src2, $src3)",
1539 [(set (i64 DoubleRegs:$dst),
1540 (sub (i64 DoubleRegs:$src1),
1541 (mul (i64 (anyext (i32 IntRegs:$src2))),
1542 (i64 (anyext (i32 IntRegs:$src3))))))],
1546 let InputType = "reg", CextOpcode = "ADD_acc" in
1547 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1548 IntRegs:$src2, IntRegs:$src3),
1549 "$dst += add($src2, $src3)",
1550 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1551 (i32 IntRegs:$src3)),
1552 (i32 IntRegs:$src1)))],
1553 "$src1 = $dst">, ImmRegRel;
1555 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1556 InputType = "imm", CextOpcode = "ADD_acc" in
1557 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1558 IntRegs:$src2, s8Ext:$src3),
1559 "$dst += add($src2, #$src3)",
1560 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1561 s8_16ExtPred:$src3),
1562 (i32 IntRegs:$src1)))],
1563 "$src1 = $dst">, ImmRegRel;
1565 let CextOpcode = "SUB_acc", InputType = "reg" in
1566 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1567 IntRegs:$src2, IntRegs:$src3),
1568 "$dst -= add($src2, $src3)",
1569 [(set (i32 IntRegs:$dst),
1570 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1571 (i32 IntRegs:$src3))))],
1572 "$src1 = $dst">, ImmRegRel;
1574 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1575 CextOpcode = "SUB_acc", InputType = "imm" in
1576 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1577 IntRegs:$src2, s8Ext:$src3),
1578 "$dst -= add($src2, #$src3)",
1579 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1580 (add (i32 IntRegs:$src2),
1581 s8_16ExtPred:$src3)))],
1582 "$src1 = $dst">, ImmRegRel;
1584 //===----------------------------------------------------------------------===//
1586 //===----------------------------------------------------------------------===//
1588 //===----------------------------------------------------------------------===//
1590 //===----------------------------------------------------------------------===//
1591 //===----------------------------------------------------------------------===//
1593 //===----------------------------------------------------------------------===//
1595 //===----------------------------------------------------------------------===//
1597 //===----------------------------------------------------------------------===//
1598 //===----------------------------------------------------------------------===//
1600 //===----------------------------------------------------------------------===//
1602 //===----------------------------------------------------------------------===//
1604 //===----------------------------------------------------------------------===//
1605 //===----------------------------------------------------------------------===//
1607 //===----------------------------------------------------------------------===//
1609 //===----------------------------------------------------------------------===//
1611 //===----------------------------------------------------------------------===//
1613 // Store doubleword.
1615 //===----------------------------------------------------------------------===//
1616 // Post increment store
1617 //===----------------------------------------------------------------------===//
1619 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1620 bit isNot, bit isPredNew> {
1621 let isPredicatedNew = isPredNew in
1622 def NAME : STInst2PI<(outs IntRegs:$dst),
1623 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1624 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1625 ") ")#mnemonic#"($src2++#$offset) = $src3",
1630 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1631 Operand ImmOp, bit PredNot> {
1632 let isPredicatedFalse = PredNot in {
1633 defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1635 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1636 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1640 let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in
1641 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1644 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1645 let isPredicable = 1 in
1646 def NAME : STInst2PI<(outs IntRegs:$dst),
1647 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1648 mnemonic#"($src1++#$offset) = $src2",
1652 let isPredicated = 1 in {
1653 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1654 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1659 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1660 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1661 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1663 let isNVStorable = 0 in
1664 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1666 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1667 s4_3ImmPred:$offset),
1668 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1670 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1671 s4_3ImmPred:$offset),
1672 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1674 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1675 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1677 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1678 s4_3ImmPred:$offset),
1679 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1681 //===----------------------------------------------------------------------===//
1682 // multiclass for the store instructions with MEMri operand.
1683 //===----------------------------------------------------------------------===//
1684 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1686 let isPredicatedNew = isPredNew in
1687 def NAME : STInst2<(outs),
1688 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1689 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1690 ") ")#mnemonic#"($addr) = $src2",
1694 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1695 let isPredicatedFalse = PredNot in {
1696 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1699 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1700 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1704 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
1705 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1706 bits<5> ImmBits, bits<5> PredImmBits> {
1708 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1709 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1711 def NAME : STInst2<(outs),
1712 (ins MEMri:$addr, RC:$src),
1713 mnemonic#"($addr) = $src",
1716 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1717 isPredicated = 1 in {
1718 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1719 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1724 let addrMode = BaseImmOffset, isMEMri = "true" in {
1725 let accessSize = ByteAccess in
1726 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1728 let accessSize = HalfWordAccess in
1729 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1731 let accessSize = WordAccess in
1732 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1734 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1735 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1738 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1739 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1741 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1742 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1744 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1745 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1747 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1748 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1751 //===----------------------------------------------------------------------===//
1752 // multiclass for the store instructions with base+immediate offset
1754 //===----------------------------------------------------------------------===//
1755 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1756 bit isNot, bit isPredNew> {
1757 let isPredicatedNew = isPredNew in
1758 def NAME : STInst2<(outs),
1759 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1760 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1761 ") ")#mnemonic#"($src2+#$src3) = $src4",
1765 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1767 let isPredicatedFalse = PredNot, isPredicated = 1 in {
1768 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1771 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1772 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1776 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
1777 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1778 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1779 bits<5> PredImmBits> {
1781 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1782 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1784 def NAME : STInst2<(outs),
1785 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1786 mnemonic#"($src1+#$src2) = $src3",
1789 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1790 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1791 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1796 let addrMode = BaseImmOffset, InputType = "reg" in {
1797 let accessSize = ByteAccess in
1798 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1799 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1801 let accessSize = HalfWordAccess in
1802 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1803 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1805 let accessSize = WordAccess in
1806 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1807 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1809 let accessSize = DoubleWordAccess, isNVStorable = 0 in
1810 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1811 u6_3Ext, 14, 9>, AddrModeRel;
1814 let AddedComplexity = 10 in {
1815 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1816 s11_0ExtPred:$offset)),
1817 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1818 (i32 IntRegs:$src1))>;
1820 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1821 s11_1ExtPred:$offset)),
1822 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1823 (i32 IntRegs:$src1))>;
1825 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1826 s11_2ExtPred:$offset)),
1827 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1828 (i32 IntRegs:$src1))>;
1830 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1831 s11_3ExtPred:$offset)),
1832 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1833 (i64 DoubleRegs:$src1))>;
1836 // memh(Rx++#s4:1)=Rt.H
1840 let Defs = [R10,R11,D5], hasSideEffects = 0 in
1841 def STriw_pred : STInst2<(outs),
1842 (ins MEMri:$addr, PredRegs:$src1),
1843 "Error; should not emit",
1846 // Allocate stack frame.
1847 let Defs = [R29, R30], Uses = [R31, R30], hasSideEffects = 0 in {
1848 def ALLOCFRAME : STInst2<(outs),
1850 "allocframe(#$amt)",
1853 //===----------------------------------------------------------------------===//
1855 //===----------------------------------------------------------------------===//
1857 //===----------------------------------------------------------------------===//
1859 //===----------------------------------------------------------------------===//
1861 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1862 "$dst = not($src1)",
1863 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1866 // Sign extend word to doubleword.
1867 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1868 "$dst = sxtw($src1)",
1869 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1870 //===----------------------------------------------------------------------===//
1872 //===----------------------------------------------------------------------===//
1874 //===----------------------------------------------------------------------===//
1876 //===----------------------------------------------------------------------===//
1878 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1879 "$dst = clrbit($src1, #$src2)",
1880 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1882 (shl 1, u5ImmPred:$src2))))]>;
1884 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1885 "$dst = clrbit($src1, #$src2)",
1888 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1889 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1890 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1893 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1894 "$dst = setbit($src1, #$src2)",
1895 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1896 (shl 1, u5ImmPred:$src2)))]>;
1898 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1899 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1900 "$dst = setbit($src1, #$src2)",
1903 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1904 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1907 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1908 "$dst = setbit($src1, #$src2)",
1909 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1910 (shl 1, u5ImmPred:$src2)))]>;
1912 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1913 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1914 "$dst = togglebit($src1, #$src2)",
1917 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1918 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1920 // Predicate transfer.
1921 let hasSideEffects = 0 in
1922 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1923 "$dst = $src1 /* Should almost never emit this. */",
1926 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1927 "$dst = $src1 /* Should almost never emit this. */",
1928 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1929 //===----------------------------------------------------------------------===//
1931 //===----------------------------------------------------------------------===//
1933 //===----------------------------------------------------------------------===//
1935 //===----------------------------------------------------------------------===//
1936 // Shift by immediate.
1937 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1938 "$dst = asr($src1, #$src2)",
1939 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1940 u5ImmPred:$src2))]>;
1942 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1943 "$dst = asr($src1, #$src2)",
1944 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1945 u6ImmPred:$src2))]>;
1947 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1948 "$dst = asl($src1, #$src2)",
1949 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1950 u5ImmPred:$src2))]>;
1952 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1953 "$dst = asl($src1, #$src2)",
1954 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1955 u6ImmPred:$src2))]>;
1957 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1958 "$dst = lsr($src1, #$src2)",
1959 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1960 u5ImmPred:$src2))]>;
1962 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1963 "$dst = lsr($src1, #$src2)",
1964 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1965 u6ImmPred:$src2))]>;
1967 // Shift by immediate and add.
1968 let AddedComplexity = 100 in
1969 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1971 "$dst = addasl($src1, $src2, #$src3)",
1972 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1973 (shl (i32 IntRegs:$src2),
1974 u3ImmPred:$src3)))]>;
1976 // Shift by register.
1977 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1978 "$dst = asl($src1, $src2)",
1979 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1980 (i32 IntRegs:$src2)))]>;
1982 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1983 "$dst = asr($src1, $src2)",
1984 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1985 (i32 IntRegs:$src2)))]>;
1987 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1988 "$dst = lsl($src1, $src2)",
1989 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1990 (i32 IntRegs:$src2)))]>;
1992 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1993 "$dst = lsr($src1, $src2)",
1994 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1995 (i32 IntRegs:$src2)))]>;
1997 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1998 "$dst = asl($src1, $src2)",
1999 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2000 (i32 IntRegs:$src2)))]>;
2002 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2003 "$dst = lsl($src1, $src2)",
2004 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2005 (i32 IntRegs:$src2)))]>;
2007 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2009 "$dst = asr($src1, $src2)",
2010 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2011 (i32 IntRegs:$src2)))]>;
2013 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2015 "$dst = lsr($src1, $src2)",
2016 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2017 (i32 IntRegs:$src2)))]>;
2019 //===----------------------------------------------------------------------===//
2021 //===----------------------------------------------------------------------===//
2023 //===----------------------------------------------------------------------===//
2025 //===----------------------------------------------------------------------===//
2026 //===----------------------------------------------------------------------===//
2028 //===----------------------------------------------------------------------===//
2030 //===----------------------------------------------------------------------===//
2032 //===----------------------------------------------------------------------===//
2033 //===----------------------------------------------------------------------===//
2035 //===----------------------------------------------------------------------===//
2037 //===----------------------------------------------------------------------===//
2039 //===----------------------------------------------------------------------===//
2041 //===----------------------------------------------------------------------===//
2043 //===----------------------------------------------------------------------===//
2044 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2045 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2048 let hasSideEffects = 1, isSolo = 1 in
2049 def BARRIER : SYSInst<(outs), (ins),
2051 [(HexagonBARRIER)]>;
2053 //===----------------------------------------------------------------------===//
2055 //===----------------------------------------------------------------------===//
2057 // TFRI64 - assembly mapped.
2058 let isReMaterializable = 1 in
2059 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2061 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2063 let AddedComplexity = 100, isPredicated = 1 in
2064 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2065 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2066 "Error; should not emit",
2067 [(set (i32 IntRegs:$dst),
2068 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2069 s12ImmPred:$src3)))]>;
2071 let AddedComplexity = 100, isPredicated = 1 in
2072 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2073 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2074 "Error; should not emit",
2075 [(set (i32 IntRegs:$dst),
2076 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2077 (i32 IntRegs:$src3))))]>;
2079 let AddedComplexity = 100, isPredicated = 1 in
2080 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2081 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2082 "Error; should not emit",
2083 [(set (i32 IntRegs:$dst),
2084 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2085 s12ImmPred:$src3)))]>;
2087 // Generate frameindex addresses.
2088 let isReMaterializable = 1 in
2089 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2090 "$dst = add($src1)",
2091 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2096 let hasSideEffects = 0, Defs = [SA0, LC0] in {
2097 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2098 "loop0($offset, #$src2)",
2102 let hasSideEffects = 0, Defs = [SA0, LC0] in {
2103 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2104 "loop0($offset, $src2)",
2108 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
2109 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2110 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
2115 // Support for generating global address.
2116 // Taken from X86InstrInfo.td.
2117 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2121 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2122 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2124 // HI/LO Instructions
2125 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2126 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2127 "$dst.l = #LO($global)",
2130 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2131 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2132 "$dst.h = #HI($global)",
2135 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2136 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2137 "$dst.l = #LO($imm_value)",
2141 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2142 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2143 "$dst.h = #HI($imm_value)",
2146 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2147 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2148 "$dst.l = #LO($jt)",
2151 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2152 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2153 "$dst.h = #HI($jt)",
2157 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2158 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2159 "$dst.l = #LO($label)",
2162 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
2163 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2164 "$dst.h = #HI($label)",
2167 // This pattern is incorrect. When we add small data, we should change
2168 // this pattern to use memw(#foo).
2169 // This is for sdata.
2170 let isMoveImm = 1 in
2171 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2172 "$dst = CONST32(#$global)",
2173 [(set (i32 IntRegs:$dst),
2174 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2176 // This is for non-sdata.
2177 let isReMaterializable = 1, isMoveImm = 1 in
2178 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2179 "$dst = CONST32(#$global)",
2180 [(set (i32 IntRegs:$dst),
2181 (HexagonCONST32 tglobaladdr:$global))]>;
2183 let isReMaterializable = 1, isMoveImm = 1 in
2184 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2185 "$dst = CONST32(#$jt)",
2186 [(set (i32 IntRegs:$dst),
2187 (HexagonCONST32 tjumptable:$jt))]>;
2189 let isReMaterializable = 1, isMoveImm = 1 in
2190 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2191 "$dst = CONST32(#$global)",
2192 [(set (i32 IntRegs:$dst),
2193 (HexagonCONST32_GP tglobaladdr:$global))]>;
2195 let isReMaterializable = 1, isMoveImm = 1 in
2196 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2197 "$dst = CONST32(#$global)",
2198 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2200 // Map BlockAddress lowering to CONST32_Int_Real
2201 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
2202 (CONST32_Int_Real tblockaddress:$addr)>;
2204 let isReMaterializable = 1, isMoveImm = 1 in
2205 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2206 "$dst = CONST32($label)",
2207 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2209 let isReMaterializable = 1, isMoveImm = 1 in
2210 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2211 "$dst = CONST64(#$global)",
2212 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2214 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2215 "$dst = xor($dst, $dst)",
2216 [(set (i1 PredRegs:$dst), 0)]>;
2218 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2219 "$dst = mpy($src1, $src2)",
2220 [(set (i32 IntRegs:$dst),
2221 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2222 (i64 (sext (i32 IntRegs:$src2))))),
2225 // Pseudo instructions.
2226 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2228 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2229 SDTCisVT<1, i32> ]>;
2231 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2232 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2234 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2235 [SDNPHasChain, SDNPOutGlue]>;
2237 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2239 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2240 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2242 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2243 // Optional Flag and Variable Arguments.
2244 // Its 1 Operand has pointer type.
2245 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2246 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2248 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2249 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2250 "Should never be emitted",
2251 [(callseq_start timm:$amt)]>;
2254 let Defs = [R29, R30, R31], Uses = [R29] in {
2255 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2256 "Should never be emitted",
2257 [(callseq_end timm:$amt1, timm:$amt2)]>;
2260 let isCall = 1, hasSideEffects = 0,
2261 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2262 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2263 def CALL : JInst<(outs), (ins calltarget:$dst),
2267 // Call subroutine from register.
2268 let isCall = 1, hasSideEffects = 0,
2269 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2270 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2271 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2277 // Indirect tail-call.
2278 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
2279 def TCRETURNR : T_JMPr;
2281 // Direct tail-calls.
2282 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
2283 isTerminator = 1, isCodeGenOnly = 1 in {
2284 def TCRETURNtg : T_JMP<(ins calltarget:$dst)>;
2285 def TCRETURNtext : T_JMP<(ins calltarget:$dst)>;
2288 // Map call instruction.
2289 def : Pat<(call (i32 IntRegs:$dst)),
2290 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2291 def : Pat<(call tglobaladdr:$dst),
2292 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2293 def : Pat<(call texternalsym:$dst),
2294 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2296 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2297 (TCRETURNtg tglobaladdr:$dst)>;
2298 def : Pat<(HexagonTCRet texternalsym:$dst),
2299 (TCRETURNtext texternalsym:$dst)>;
2300 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2301 (TCRETURNR (i32 IntRegs:$dst))>;
2303 // Atomic load and store support
2304 // 8 bit atomic load
2305 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2306 (i32 (LDriub ADDRriS11_0:$src1))>;
2308 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2309 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2311 // 16 bit atomic load
2312 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2313 (i32 (LDriuh ADDRriS11_1:$src1))>;
2315 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2316 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2318 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2319 (i32 (LDriw ADDRriS11_2:$src1))>;
2321 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2322 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2324 // 64 bit atomic load
2325 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2326 (i64 (LDrid ADDRriS11_3:$src1))>;
2328 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2329 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2332 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2333 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2335 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2336 (i32 IntRegs:$src1)),
2337 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2338 (i32 IntRegs:$src1))>;
2341 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2342 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2344 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2345 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2346 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2347 (i32 IntRegs:$src1))>;
2349 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2350 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2352 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2353 (i32 IntRegs:$src1)),
2354 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2355 (i32 IntRegs:$src1))>;
2360 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2361 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2363 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2364 (i64 DoubleRegs:$src1)),
2365 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2366 (i64 DoubleRegs:$src1))>;
2368 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2369 def : Pat <(and (i32 IntRegs:$src1), 65535),
2370 (A2_zxth (i32 IntRegs:$src1))>;
2372 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2373 def : Pat <(and (i32 IntRegs:$src1), 255),
2374 (A2_zxtb (i32 IntRegs:$src1))>;
2376 // Map Add(p1, true) to p1 = not(p1).
2377 // Add(p1, false) should never be produced,
2378 // if it does, it got to be mapped to NOOP.
2379 def : Pat <(add (i1 PredRegs:$src1), -1),
2380 (NOT_p (i1 PredRegs:$src1))>;
2382 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2383 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2384 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2387 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2388 // => r0 = TFR_condset_ri(p0, r1, #i)
2389 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2390 (i32 IntRegs:$src3)),
2391 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2392 s12ImmPred:$src2))>;
2394 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2395 // => r0 = TFR_condset_ir(p0, #i, r1)
2396 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2397 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2398 (i32 IntRegs:$src2)))>;
2400 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2401 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
2402 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2404 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2405 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
2406 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2409 let AddedComplexity = 100 in
2410 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
2411 (i64 (COMBINE_rr (TFRI 0),
2412 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
2415 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2416 let AddedComplexity = 10 in
2417 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2418 (i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2420 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2421 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2422 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2424 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2425 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2426 (i64 (SXTW (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2427 subreg_loreg))))))>;
2429 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2430 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2431 (i64 (SXTW (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2432 subreg_loreg))))))>;
2434 // We want to prevent emitting pnot's as much as possible.
2435 // Map brcond with an unsupported setcc to a JMP_f.
2436 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2438 (JMP_f (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2441 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2443 (JMP_f (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2445 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2446 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2448 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2449 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
2451 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
2452 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2454 (JMP_f (CMPGTri (i32 IntRegs:$src1),
2455 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
2457 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2458 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2460 (JMP_t (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
2462 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2464 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2467 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2469 (JMP_f (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2472 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2474 (JMP_f (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2477 // Map from a 64-bit select to an emulated 64-bit mux.
2478 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2479 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2480 (i64 DoubleRegs:$src3)),
2481 (i64 (COMBINE_rr (i32 (C2_mux (i1 PredRegs:$src1),
2482 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2484 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2486 (i32 (C2_mux (i1 PredRegs:$src1),
2487 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2489 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2490 subreg_loreg))))))>;
2492 // Map from a 1-bit select to logical ops.
2493 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2494 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2495 (i1 PredRegs:$src3)),
2496 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2497 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2499 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2500 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2501 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2503 // Map for truncating from 64 immediates to 32 bit immediates.
2504 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2505 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2507 // Map for truncating from i64 immediates to i1 bit immediates.
2508 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2509 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2512 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2513 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2514 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2517 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2518 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2519 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2521 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2522 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2523 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2526 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2527 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2528 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2531 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2532 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2533 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2536 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2537 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2538 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2540 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2541 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2542 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2544 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2545 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2546 // Better way to do this?
2547 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2548 (i64 (SXTW (i32 IntRegs:$src1)))>;
2550 // Map cmple -> cmpgt.
2551 // rs <= rt -> !(rs > rt).
2552 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2553 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
2555 // rs <= rt -> !(rs > rt).
2556 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2557 (i1 (NOT_p (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2559 // Rss <= Rtt -> !(Rss > Rtt).
2560 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2561 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2563 // Map cmpne -> cmpeq.
2564 // Hexagon_TODO: We should improve on this.
2565 // rs != rt -> !(rs == rt).
2566 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2567 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
2569 // Map cmpne(Rs) -> !cmpeqe(Rs).
2570 // rs != rt -> !(rs == rt).
2571 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2572 (i1 (NOT_p (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2574 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2575 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2576 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2578 // Map cmpne(Rss) -> !cmpew(Rss).
2579 // rs != rt -> !(rs == rt).
2580 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2581 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2582 (i64 DoubleRegs:$src2)))))>;
2584 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2585 // rs >= rt -> !(rt > rs).
2586 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2587 (i1 (NOT_p (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2589 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
2590 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
2591 (i1 (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
2593 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2594 // rss >= rtt -> !(rtt > rss).
2595 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2596 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2597 (i64 DoubleRegs:$src1)))))>;
2599 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2600 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2601 // rs < rt -> !(rs >= rt).
2602 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2603 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
2605 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2606 // rs < rt -> rt > rs.
2607 // We can let assembler map it, or we can do in the compiler itself.
2608 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2609 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2611 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2612 // rss < rtt -> (rtt > rss).
2613 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2614 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2616 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2617 // rs < rt -> rt > rs.
2618 // We can let assembler map it, or we can do in the compiler itself.
2619 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2620 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2622 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2623 // rs < rt -> rt > rs.
2624 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2625 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2627 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
2628 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
2629 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
2631 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
2632 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
2633 (i1 (CMPGTUri (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
2635 // Generate cmpgtu(Rs, #u9)
2636 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
2637 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ExtPred:$src2))>;
2639 // Map from Rs >= Rt -> !(Rt > Rs).
2640 // rs >= rt -> !(rt > rs).
2641 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2642 (i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2644 // Map from Rs >= Rt -> !(Rt > Rs).
2645 // rs >= rt -> !(rt > rs).
2646 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2647 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2649 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
2650 // Map from (Rs <= Rt) -> !(Rs > Rt).
2651 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2652 (i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2654 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2655 // Map from (Rs <= Rt) -> !(Rs > Rt).
2656 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2657 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2661 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2662 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2665 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2666 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2668 // Convert sign-extended load back to load and sign extend.
2670 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2671 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2673 // Convert any-extended load back to load and sign extend.
2675 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2676 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2678 // Convert sign-extended load back to load and sign extend.
2680 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2681 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2683 // Convert sign-extended load back to load and sign extend.
2685 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2686 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2691 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2692 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2695 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2696 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2700 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2701 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2705 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2706 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2709 let AddedComplexity = 20 in
2710 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2711 s11_0ExtPred:$offset))),
2712 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2713 s11_0ExtPred:$offset)))>,
2717 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
2718 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2721 let AddedComplexity = 20 in
2722 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
2723 s11_0ExtPred:$offset))),
2724 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2725 s11_0ExtPred:$offset)))>,
2729 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2730 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2733 let AddedComplexity = 20 in
2734 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2735 s11_1ExtPred:$offset))),
2736 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2737 s11_1ExtPred:$offset)))>,
2741 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2742 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2745 let AddedComplexity = 100 in
2746 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2747 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2748 s11_2ExtPred:$offset)))>,
2751 let AddedComplexity = 10 in
2752 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2753 (i32 (LDriw ADDRriS11_0:$src1))>;
2755 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2756 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2757 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2759 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2760 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2761 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2763 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2764 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2765 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2768 let AddedComplexity = 100 in
2769 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2771 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2772 s11_2ExtPred:$offset2)))))),
2773 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2774 (LDriw_indexed IntRegs:$src2,
2775 s11_2ExtPred:$offset2)))>;
2777 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2779 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2780 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2781 (LDriw ADDRriS11_2:$srcLow)))>;
2783 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2785 (i64 (zext (i32 IntRegs:$srcLow))))),
2786 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2789 let AddedComplexity = 100 in
2790 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2792 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2793 s11_2ExtPred:$offset2)))))),
2794 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2795 (LDriw_indexed IntRegs:$src2,
2796 s11_2ExtPred:$offset2)))>;
2798 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2800 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2801 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2802 (LDriw ADDRriS11_2:$srcLow)))>;
2804 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2806 (i64 (zext (i32 IntRegs:$srcLow))))),
2807 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2810 // Any extended 64-bit load.
2811 // anyext i32 -> i64
2812 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2813 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2816 // When there is an offset we should prefer the pattern below over the pattern above.
2817 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2818 // So this complexity below is comfortably higher to allow for choosing the below.
2819 // If this is not done then we generate addresses such as
2820 // ********************************************
2821 // r1 = add (r0, #4)
2822 // r1 = memw(r1 + #0)
2824 // r1 = memw(r0 + #4)
2825 // ********************************************
2826 let AddedComplexity = 100 in
2827 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2828 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2829 s11_2ExtPred:$offset)))>,
2832 // anyext i16 -> i64.
2833 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2834 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2837 let AddedComplexity = 20 in
2838 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2839 s11_1ExtPred:$offset))),
2840 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2841 s11_1ExtPred:$offset)))>,
2844 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2845 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2846 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2849 // Multiply 64-bit unsigned and use upper result.
2850 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2865 (COMBINE_rr (TFRI 0),
2871 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2873 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2874 subreg_loreg)))), 32)),
2876 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2877 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2878 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2879 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2880 32)), subreg_loreg)))),
2881 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2882 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2884 // Multiply 64-bit signed and use upper result.
2885 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2889 (COMBINE_rr (TFRI 0),
2899 (COMBINE_rr (TFRI 0),
2905 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2907 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2908 subreg_loreg)))), 32)),
2910 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2911 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2912 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2913 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2914 32)), subreg_loreg)))),
2915 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2916 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2918 // Hexagon specific ISD nodes.
2919 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2920 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2921 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2922 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2923 SDTHexagonADJDYNALLOC>;
2924 // Needed to tag these instructions for stack layout.
2925 let usesCustomInserter = 1 in
2926 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2928 "$dst = add($src1, #$src2)",
2929 [(set (i32 IntRegs:$dst),
2930 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2931 s16ImmPred:$src2))]>;
2933 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2934 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2935 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2937 [(set (i32 IntRegs:$dst),
2938 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2940 let AddedComplexity = 100 in
2941 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2942 (COPY (i32 IntRegs:$src1))>;
2944 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2946 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2947 (i32 (CONST32_set_jt tjumptable:$dst))>;
2951 // Multi-class for logical operators :
2952 // Shift by immediate/register and accumulate/logical
2953 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2954 def _ri : SInst_acc<(outs IntRegs:$dst),
2955 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2956 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2957 [(set (i32 IntRegs:$dst),
2958 (OpNode2 (i32 IntRegs:$src1),
2959 (OpNode1 (i32 IntRegs:$src2),
2960 u5ImmPred:$src3)))],
2963 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2964 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2965 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2966 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2967 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2971 // Multi-class for logical operators :
2972 // Shift by register and accumulate/logical (32/64 bits)
2973 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2974 def _rr : SInst_acc<(outs IntRegs:$dst),
2975 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2976 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2977 [(set (i32 IntRegs:$dst),
2978 (OpNode2 (i32 IntRegs:$src1),
2979 (OpNode1 (i32 IntRegs:$src2),
2980 (i32 IntRegs:$src3))))],
2983 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
2984 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2985 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2986 [(set (i64 DoubleRegs:$dst),
2987 (OpNode2 (i64 DoubleRegs:$src1),
2988 (OpNode1 (i64 DoubleRegs:$src2),
2989 (i32 IntRegs:$src3))))],
2994 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
2995 let AddedComplexity = 100 in
2996 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
2997 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
2998 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
2999 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3002 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3003 let AddedComplexity = 100 in
3004 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3005 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3006 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3007 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3010 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3011 let AddedComplexity = 100 in
3012 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3015 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3016 xtype_xor_imm<"asl", shl>;
3018 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3019 xtype_xor_imm<"lsr", srl>;
3021 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3022 defm LSL : basic_xtype_reg<"lsl", shl>;
3024 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3025 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3026 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3028 //===----------------------------------------------------------------------===//
3029 // V3 Instructions +
3030 //===----------------------------------------------------------------------===//
3032 include "HexagonInstrInfoV3.td"
3034 //===----------------------------------------------------------------------===//
3035 // V3 Instructions -
3036 //===----------------------------------------------------------------------===//
3038 //===----------------------------------------------------------------------===//
3039 // V4 Instructions +
3040 //===----------------------------------------------------------------------===//
3042 include "HexagonInstrInfoV4.td"
3044 //===----------------------------------------------------------------------===//
3045 // V4 Instructions -
3046 //===----------------------------------------------------------------------===//
3048 //===----------------------------------------------------------------------===//
3049 // V5 Instructions +
3050 //===----------------------------------------------------------------------===//
3052 include "HexagonInstrInfoV5.td"
3054 //===----------------------------------------------------------------------===//
3055 // V5 Instructions -
3056 //===----------------------------------------------------------------------===//