1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Multi-class for logical operators.
18 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
19 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
20 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
21 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
23 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
24 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
25 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
29 // Multi-class for compare ops.
30 let isCompare = 1 in {
31 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
32 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
33 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
34 [(set (i1 PredRegs:$dst),
35 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
37 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
38 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
39 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
40 [(set (i1 PredRegs:$dst),
41 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
44 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
45 let CextOpcode = CextOp in {
46 let InputType = "reg" in
47 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
48 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
49 [(set (i1 PredRegs:$dst),
50 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
52 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
53 opExtentBits = 10, InputType = "imm" in
54 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
55 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
56 [(set (i1 PredRegs:$dst),
57 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
61 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
62 let CextOpcode = CextOp in {
63 let InputType = "reg" in
64 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
65 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
66 [(set (i1 PredRegs:$dst),
67 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
69 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
70 opExtentBits = 9, InputType = "imm" in
71 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
72 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
73 [(set (i1 PredRegs:$dst),
74 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
78 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
79 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
80 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
81 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
82 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
86 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
87 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
88 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
90 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
95 //===----------------------------------------------------------------------===//
96 // ALU32/ALU (Instructions with register-register form)
97 //===----------------------------------------------------------------------===//
98 multiclass ALU32_Pbase<string mnemonic, bit isNot,
101 let PNewValue = !if(isPredNew, "new", "") in
102 def NAME : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
104 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
105 ") $dst = ")#mnemonic#"($src2, $src3)",
109 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
110 let isPredicatedFalse = PredNot in {
111 defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
113 defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
117 let InputType = "reg" in
118 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
119 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
120 let isPredicable = 1 in
121 def NAME : ALU32_rr<(outs IntRegs:$dst),
122 (ins IntRegs:$src1, IntRegs:$src2),
123 "$dst = "#mnemonic#"($src1, $src2)",
124 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
125 (i32 IntRegs:$src2)))]>;
127 let neverHasSideEffects = 1, isPredicated = 1 in {
128 defm Pt : ALU32_Pred<mnemonic, 0>;
129 defm NotPt : ALU32_Pred<mnemonic, 1>;
134 let isCommutable = 1 in {
135 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
136 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
137 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
138 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
141 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
143 //===----------------------------------------------------------------------===//
144 // ALU32/ALU (ADD with register-immediate form)
145 //===----------------------------------------------------------------------===//
146 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
147 let PNewValue = !if(isPredNew, "new", "") in
148 def NAME : ALU32_ri<(outs IntRegs:$dst),
149 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
150 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
151 ") $dst = ")#mnemonic#"($src2, #$src3)",
155 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
156 let isPredicatedFalse = PredNot in {
157 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
159 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
163 let isExtendable = 1, InputType = "imm" in
164 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
165 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
166 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
168 def NAME : ALU32_ri<(outs IntRegs:$dst),
169 (ins IntRegs:$src1, s16Ext:$src2),
170 "$dst = "#mnemonic#"($src1, #$src2)",
171 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
172 (s16ExtPred:$src2)))]>;
174 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
175 neverHasSideEffects = 1, isPredicated = 1 in {
176 defm Pt : ALU32ri_Pred<mnemonic, 0>;
177 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
182 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
184 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
185 CextOpcode = "OR", InputType = "imm" in
186 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
187 (ins IntRegs:$src1, s10Ext:$src2),
188 "$dst = or($src1, #$src2)",
189 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
190 s10ExtPred:$src2))]>, ImmRegRel;
192 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
195 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
198 InputType = "imm", CextOpcode = "AND" in
199 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
200 (ins IntRegs:$src1, s10Ext:$src2),
201 "$dst = and($src1, #$src2)",
202 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
203 s10ExtPred:$src2))]>, ImmRegRel;
205 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
207 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
209 let neverHasSideEffects = 1 in
210 def NOP : ALU32_rr<(outs), (ins),
214 // Rd32=sub(#s10,Rs32)
215 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
216 CextOpcode = "SUB", InputType = "imm" in
217 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
218 (ins s10Ext:$src1, IntRegs:$src2),
219 "$dst = sub(#$src1, $src2)",
220 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
224 multiclass TFR_Pred<bit PredNot> {
225 let isPredicatedFalse = PredNot in {
226 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
227 (ins PredRegs:$src1, IntRegs:$src2),
228 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
231 let PNewValue = "new" in
232 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
233 (ins PredRegs:$src1, IntRegs:$src2),
234 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
239 let InputType = "reg", neverHasSideEffects = 1 in
240 multiclass TFR_base<string CextOp> {
241 let CextOpcode = CextOp, BaseOpcode = CextOp in {
242 let isPredicable = 1 in
243 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
247 let isPredicated = 1 in {
248 defm Pt : TFR_Pred<0>;
249 defm NotPt : TFR_Pred<1>;
254 class T_TFR64_Pred<bit PredNot, bit isPredNew>
255 : ALU32_rr<(outs DoubleRegs:$dst),
256 (ins PredRegs:$src1, DoubleRegs:$src2),
257 !if(PredNot, "if (!$src1", "if ($src1")#
258 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
265 let Inst{27-24} = 0b1101;
266 let Inst{13} = isPredNew;
267 let Inst{7} = PredNot;
269 let Inst{6-5} = src1;
270 let Inst{20-17} = src2{4-1};
272 let Inst{12-9} = src2{4-1};
276 multiclass TFR64_Pred<bit PredNot> {
277 let isPredicatedFalse = PredNot in {
278 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
280 let PNewValue = "new" in
281 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
285 let neverHasSideEffects = 1 in
286 multiclass TFR64_base<string BaseName> {
287 let BaseOpcode = BaseName in {
288 let isPredicable = 1 in
289 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
290 (ins DoubleRegs:$src1),
296 let Inst{27-23} = 0b01010;
298 let Inst{20-17} = src1{4-1};
300 let Inst{12-9} = src1{4-1};
304 let isPredicated = 1 in {
305 defm Pt : TFR64_Pred<0>;
306 defm NotPt : TFR64_Pred<1>;
311 multiclass TFRI_Pred<bit PredNot> {
312 let isMoveImm = 1, isPredicatedFalse = PredNot in {
313 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
314 (ins PredRegs:$src1, s12Ext:$src2),
315 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
319 let PNewValue = "new" in
320 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
321 (ins PredRegs:$src1, s12Ext:$src2),
322 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
327 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
328 multiclass TFRI_base<string CextOp> {
329 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
330 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
331 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
332 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
334 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
336 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
337 isPredicated = 1 in {
338 defm Pt : TFRI_Pred<0>;
339 defm NotPt : TFRI_Pred<1>;
344 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
345 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
346 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
348 // Transfer control register.
349 let neverHasSideEffects = 1 in
350 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 //===----------------------------------------------------------------------===//
364 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
365 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
367 def HexagonWrapperCombineII :
368 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
369 def HexagonWrapperCombineRR :
370 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
372 // Combines the two integer registers SRC1 and SRC2 into a double register.
373 let isPredicable = 1 in
374 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1,
376 "$dst = combine($src1, $src2)",
377 [(set (i64 DoubleRegs:$dst),
378 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
379 (i32 IntRegs:$src2))))]>;
381 // Rd=combine(Rt.[HL], Rs.[HL])
382 class COMBINE_halves<string A, string B>: ALU32_rr<(outs IntRegs:$dst),
385 "$dst = combine($src1."# A #", $src2."# B #")", []>;
387 let isPredicable = 1 in {
388 def COMBINE_hh : COMBINE_halves<"H", "H">;
389 def COMBINE_hl : COMBINE_halves<"H", "L">;
390 def COMBINE_lh : COMBINE_halves<"L", "H">;
391 def COMBINE_ll : COMBINE_halves<"L", "L">;
394 def : Pat<(i32 (trunc (i64 (srl (i64 DoubleRegs:$a), (i32 16))))),
395 (COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
396 (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;
398 // Combines the two immediates SRC1 and SRC2 into a double register.
399 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
400 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
401 "$dst = combine(#$src1, #$src2)",
402 [(set (i64 DoubleRegs:$dst),
403 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
405 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
406 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
409 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
412 "$dst = vmux($src1, $src2, $src3)",
415 let CextOpcode = "MUX", InputType = "reg" in
416 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
417 IntRegs:$src2, IntRegs:$src3),
418 "$dst = mux($src1, $src2, $src3)",
419 [(set (i32 IntRegs:$dst),
420 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
421 (i32 IntRegs:$src3))))]>, ImmRegRel;
423 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
424 CextOpcode = "MUX", InputType = "imm" in
425 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
427 "$dst = mux($src1, #$src2, $src3)",
428 [(set (i32 IntRegs:$dst),
429 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
430 (i32 IntRegs:$src3))))]>, ImmRegRel;
432 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
433 CextOpcode = "MUX", InputType = "imm" in
434 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
436 "$dst = mux($src1, $src2, #$src3)",
437 [(set (i32 IntRegs:$dst),
438 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
439 s8ExtPred:$src3)))]>, ImmRegRel;
441 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
442 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
444 "$dst = mux($src1, #$src2, #$src3)",
445 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
447 s8ImmPred:$src3)))]>;
449 // ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
450 multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
451 let isPredicatedNew = isPredNew in
452 def NAME : ALU32Inst<(outs IntRegs:$dst),
453 (ins PredRegs:$src1, IntRegs:$src2),
454 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
455 ") $dst = ")#mnemonic#"($src2)">,
459 multiclass ALU32_2op_Pred<string mnemonic, bit PredNot> {
460 let isPredicatedFalse = PredNot in {
461 defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
463 defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
467 multiclass ALU32_2op_base<string mnemonic> {
468 let BaseOpcode = mnemonic in {
469 let isPredicable = 1, neverHasSideEffects = 1 in
470 def NAME : ALU32Inst<(outs IntRegs:$dst),
472 "$dst = "#mnemonic#"($src1)">;
474 let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
475 neverHasSideEffects = 1 in {
476 defm Pt_V4 : ALU32_2op_Pred<mnemonic, 0>;
477 defm NotPt_V4 : ALU32_2op_Pred<mnemonic, 1>;
482 defm ASLH : ALU32_2op_base<"aslh">, PredNewRel;
483 defm ASRH : ALU32_2op_base<"asrh">, PredNewRel;
484 defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
485 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
486 defm ZXTB : ALU32_2op_base<"zxtb">, PredNewRel;
487 defm ZXTH : ALU32_2op_base<"zxth">, PredNewRel;
489 def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
490 (ASLH IntRegs:$src1)>;
492 def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
493 (ASRH IntRegs:$src1)>;
495 def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
496 (SXTB IntRegs:$src1)>;
498 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
499 (SXTH IntRegs:$src1)>;
501 //===----------------------------------------------------------------------===//
503 //===----------------------------------------------------------------------===//
506 //===----------------------------------------------------------------------===//
508 //===----------------------------------------------------------------------===//
510 // Conditional combine.
511 let neverHasSideEffects = 1, isPredicated = 1 in {
512 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
513 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
514 "if ($src1) $dst = combine($src2, $src3)",
517 let isPredicatedFalse = 1 in
518 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
519 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
520 "if (!$src1) $dst = combine($src2, $src3)",
523 let isPredicatedNew = 1 in
524 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
525 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
526 "if ($src1.new) $dst = combine($src2, $src3)",
529 let isPredicatedNew = 1, isPredicatedFalse = 1 in
530 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
531 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
532 "if (!$src1.new) $dst = combine($src2, $src3)",
537 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
538 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
539 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
540 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
541 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
542 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
543 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
545 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
547 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
549 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
551 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
553 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
555 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
557 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
559 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
561 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
562 "$dst = tstbit($src1, $src2)",
563 [(set (i1 PredRegs:$dst),
564 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
566 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
567 "$dst = tstbit($src1, $src2)",
568 [(set (i1 PredRegs:$dst),
569 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
571 //===----------------------------------------------------------------------===//
573 //===----------------------------------------------------------------------===//
576 //===----------------------------------------------------------------------===//
578 //===----------------------------------------------------------------------===//
580 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
582 "$dst = add($src1, $src2)",
583 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
584 (i64 DoubleRegs:$src2)))]>;
589 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
590 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
591 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
593 // Logical operations.
594 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
596 "$dst = and($src1, $src2)",
597 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
598 (i64 DoubleRegs:$src2)))]>;
600 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
602 "$dst = or($src1, $src2)",
603 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
604 (i64 DoubleRegs:$src2)))]>;
606 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
608 "$dst = xor($src1, $src2)",
609 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
610 (i64 DoubleRegs:$src2)))]>;
613 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
614 "$dst = max($src2, $src1)",
615 [(set (i32 IntRegs:$dst),
616 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
617 (i32 IntRegs:$src1))),
618 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
620 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
621 "$dst = maxu($src2, $src1)",
622 [(set (i32 IntRegs:$dst),
623 (i32 (select (i1 (setult (i32 IntRegs:$src2),
624 (i32 IntRegs:$src1))),
625 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
627 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
629 "$dst = max($src2, $src1)",
630 [(set (i64 DoubleRegs:$dst),
631 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
632 (i64 DoubleRegs:$src1))),
633 (i64 DoubleRegs:$src1),
634 (i64 DoubleRegs:$src2))))]>;
636 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
638 "$dst = maxu($src2, $src1)",
639 [(set (i64 DoubleRegs:$dst),
640 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
641 (i64 DoubleRegs:$src1))),
642 (i64 DoubleRegs:$src1),
643 (i64 DoubleRegs:$src2))))]>;
646 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
647 "$dst = min($src2, $src1)",
648 [(set (i32 IntRegs:$dst),
649 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
650 (i32 IntRegs:$src1))),
651 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
653 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
654 "$dst = minu($src2, $src1)",
655 [(set (i32 IntRegs:$dst),
656 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
657 (i32 IntRegs:$src1))),
658 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
660 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
662 "$dst = min($src2, $src1)",
663 [(set (i64 DoubleRegs:$dst),
664 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
665 (i64 DoubleRegs:$src1))),
666 (i64 DoubleRegs:$src1),
667 (i64 DoubleRegs:$src2))))]>;
669 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
671 "$dst = minu($src2, $src1)",
672 [(set (i64 DoubleRegs:$dst),
673 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
674 (i64 DoubleRegs:$src1))),
675 (i64 DoubleRegs:$src1),
676 (i64 DoubleRegs:$src2))))]>;
679 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
681 "$dst = sub($src1, $src2)",
682 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
683 (i64 DoubleRegs:$src2)))]>;
685 // Subtract halfword.
687 //===----------------------------------------------------------------------===//
689 //===----------------------------------------------------------------------===//
691 //===----------------------------------------------------------------------===//
693 //===----------------------------------------------------------------------===//
695 //===----------------------------------------------------------------------===//
697 //===----------------------------------------------------------------------===//
699 //===----------------------------------------------------------------------===//
701 //===----------------------------------------------------------------------===//
703 //===----------------------------------------------------------------------===//
705 //===----------------------------------------------------------------------===//
707 //===----------------------------------------------------------------------===//
709 //===----------------------------------------------------------------------===//
710 // Logical reductions on predicates.
712 // Looping instructions.
714 // Pipelined looping instructions.
716 // Logical operations on predicates.
717 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
718 "$dst = and($src1, $src2)",
719 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
720 (i1 PredRegs:$src2)))]>;
722 let neverHasSideEffects = 1 in
723 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
725 "$dst = and($src1, !$src2)",
728 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
729 "$dst = any8($src1)",
732 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
733 "$dst = all8($src1)",
736 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
738 "$dst = vitpack($src1, $src2)",
741 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
744 "$dst = valignb($src1, $src2, $src3)",
747 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
750 "$dst = vspliceb($src1, $src2, $src3)",
753 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
754 "$dst = mask($src1)",
757 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
759 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
761 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
762 "$dst = or($src1, $src2)",
763 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
764 (i1 PredRegs:$src2)))]>;
766 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
767 "$dst = xor($src1, $src2)",
768 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
769 (i1 PredRegs:$src2)))]>;
772 // User control register transfer.
773 //===----------------------------------------------------------------------===//
775 //===----------------------------------------------------------------------===//
778 //===----------------------------------------------------------------------===//
780 //===----------------------------------------------------------------------===//
782 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
783 def JMP : JInst< (outs),
784 (ins brtarget:$offset),
790 let isBranch = 1, isTerminator=1, Defs = [PC],
791 isPredicated = 1 in {
792 def JMP_c : JInst< (outs),
793 (ins PredRegs:$src, brtarget:$offset),
794 "if ($src) jump $offset",
795 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
799 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
800 isPredicated = 1 in {
801 def JMP_cNot : JInst< (outs),
802 (ins PredRegs:$src, brtarget:$offset),
803 "if (!$src) jump $offset",
807 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
808 isPredicated = 1 in {
809 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
810 "if ($pred) jump $dst",
814 // Jump to address conditioned on new predicate.
816 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
817 isPredicated = 1 in {
818 def JMP_cdnPt : JInst< (outs),
819 (ins PredRegs:$src, brtarget:$offset),
820 "if ($src.new) jump:t $offset",
825 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
826 isPredicated = 1 in {
827 def JMP_cdnNotPt : JInst< (outs),
828 (ins PredRegs:$src, brtarget:$offset),
829 "if (!$src.new) jump:t $offset",
834 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
835 isPredicated = 1 in {
836 def JMP_cdnPnt : JInst< (outs),
837 (ins PredRegs:$src, brtarget:$offset),
838 "if ($src.new) jump:nt $offset",
843 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
844 isPredicated = 1 in {
845 def JMP_cdnNotPnt : JInst< (outs),
846 (ins PredRegs:$src, brtarget:$offset),
847 "if (!$src.new) jump:nt $offset",
850 //===----------------------------------------------------------------------===//
852 //===----------------------------------------------------------------------===//
854 //===----------------------------------------------------------------------===//
856 //===----------------------------------------------------------------------===//
857 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
858 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
860 // Jump to address from register.
861 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
862 Defs = [PC], Uses = [R31] in {
863 def JMPR: JRInst<(outs), (ins),
868 // Jump to address from register.
869 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
870 Defs = [PC], Uses = [R31] in {
871 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
872 "if ($src1) jumpr r31",
876 // Jump to address from register.
877 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
878 Defs = [PC], Uses = [R31] in {
879 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
880 "if (!$src1) jumpr r31",
884 //===----------------------------------------------------------------------===//
886 //===----------------------------------------------------------------------===//
888 //===----------------------------------------------------------------------===//
890 //===----------------------------------------------------------------------===//
892 // Load -- MEMri operand
893 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
894 bit isNot, bit isPredNew> {
895 let PNewValue = !if(isPredNew, "new", "") in
896 def NAME : LDInst2<(outs RC:$dst),
897 (ins PredRegs:$src1, MEMri:$addr),
898 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
899 ") ")#"$dst = "#mnemonic#"($addr)",
903 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
904 let isPredicatedFalse = PredNot in {
905 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
907 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
911 let isExtendable = 1, neverHasSideEffects = 1 in
912 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
913 bits<5> ImmBits, bits<5> PredImmBits> {
915 let CextOpcode = CextOp, BaseOpcode = CextOp in {
916 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
918 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
919 "$dst = "#mnemonic#"($addr)",
922 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
923 isPredicated = 1 in {
924 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
925 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
930 let addrMode = BaseImmOffset, isMEMri = "true" in {
931 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
932 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
933 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
934 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
935 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
936 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
939 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
940 (LDrib ADDRriS11_0:$addr) >;
942 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
943 (LDriub ADDRriS11_0:$addr) >;
945 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
946 (LDrih ADDRriS11_1:$addr) >;
948 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
949 (LDriuh ADDRriS11_1:$addr) >;
951 def : Pat < (i32 (load ADDRriS11_2:$addr)),
952 (LDriw ADDRriS11_2:$addr) >;
954 def : Pat < (i64 (load ADDRriS11_3:$addr)),
955 (LDrid ADDRriS11_3:$addr) >;
958 // Load - Base with Immediate offset addressing mode
959 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
960 bit isNot, bit isPredNew> {
961 let PNewValue = !if(isPredNew, "new", "") in
962 def NAME : LDInst2<(outs RC:$dst),
963 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
964 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
965 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
969 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
971 let isPredicatedFalse = PredNot in {
972 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
974 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
978 let isExtendable = 1, neverHasSideEffects = 1 in
979 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
980 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
981 bits<5> PredImmBits> {
983 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
984 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
985 isPredicable = 1, AddedComplexity = 20 in
986 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
987 "$dst = "#mnemonic#"($src1+#$offset)",
990 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
991 isPredicated = 1 in {
992 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
993 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
998 let addrMode = BaseImmOffset in {
999 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1000 11, 6>, AddrModeRel;
1001 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1002 11, 6>, AddrModeRel;
1003 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1004 12, 7>, AddrModeRel;
1005 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1006 12, 7>, AddrModeRel;
1007 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1008 13, 8>, AddrModeRel;
1009 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1010 14, 9>, AddrModeRel;
1013 let AddedComplexity = 20 in {
1014 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1015 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1017 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1018 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1020 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1021 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1023 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1024 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1026 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1027 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1029 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1030 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1033 //===----------------------------------------------------------------------===//
1034 // Post increment load
1035 // Make sure that in post increment load, the first operand is always the post
1036 // increment operand.
1037 //===----------------------------------------------------------------------===//
1039 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1040 bit isNot, bit isPredNew> {
1041 let PNewValue = !if(isPredNew, "new", "") in
1042 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1043 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1044 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1045 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1050 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1051 Operand ImmOp, bit PredNot> {
1052 let isPredicatedFalse = PredNot in {
1053 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1055 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1056 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1060 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1063 let BaseOpcode = "POST_"#BaseOp in {
1064 let isPredicable = 1 in
1065 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1066 (ins IntRegs:$src1, ImmOp:$offset),
1067 "$dst = "#mnemonic#"($src1++#$offset)",
1071 let isPredicated = 1 in {
1072 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1073 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1078 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1079 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1081 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1083 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1085 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1087 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1089 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1093 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1094 (i32 (LDrib ADDRriS11_0:$addr)) >;
1096 // Load byte any-extend.
1097 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1098 (i32 (LDrib ADDRriS11_0:$addr)) >;
1100 // Indexed load byte any-extend.
1101 let AddedComplexity = 20 in
1102 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1103 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1105 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1106 (i32 (LDrih ADDRriS11_1:$addr))>;
1108 let AddedComplexity = 20 in
1109 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1110 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1112 let AddedComplexity = 10 in
1113 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1114 (i32 (LDriub ADDRriS11_0:$addr))>;
1116 let AddedComplexity = 20 in
1117 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1118 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1121 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1122 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1123 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1125 "Error; should not emit",
1128 // Deallocate stack frame.
1129 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1130 def DEALLOCFRAME : LDInst2<(outs), (ins),
1135 // Load and unpack bytes to halfwords.
1136 //===----------------------------------------------------------------------===//
1138 //===----------------------------------------------------------------------===//
1140 //===----------------------------------------------------------------------===//
1142 //===----------------------------------------------------------------------===//
1143 //===----------------------------------------------------------------------===//
1145 //===----------------------------------------------------------------------===//
1147 //===----------------------------------------------------------------------===//
1149 //===----------------------------------------------------------------------===//
1150 //===----------------------------------------------------------------------===//
1152 //===----------------------------------------------------------------------===//
1154 //===----------------------------------------------------------------------===//
1156 //===----------------------------------------------------------------------===//
1157 // Multiply and use lower result.
1159 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1160 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1161 "$dst =+ mpyi($src1, #$src2)",
1162 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1163 u8ExtPred:$src2))]>;
1166 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1167 "$dst =- mpyi($src1, #$src2)",
1168 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1169 u8ImmPred:$src2)))]>;
1172 // s9 is NOT the same as m9 - but it works.. so far.
1173 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1174 // depending on the value of m9. See Arch Spec.
1175 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1176 CextOpcode = "MPYI", InputType = "imm" in
1177 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1178 "$dst = mpyi($src1, #$src2)",
1179 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1180 s9ExtPred:$src2))]>, ImmRegRel;
1183 let CextOpcode = "MPYI", InputType = "reg" in
1184 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1185 "$dst = mpyi($src1, $src2)",
1186 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1187 (i32 IntRegs:$src2)))]>, ImmRegRel;
1190 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1191 CextOpcode = "MPYI_acc", InputType = "imm" in
1192 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1193 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1194 "$dst += mpyi($src2, #$src3)",
1195 [(set (i32 IntRegs:$dst),
1196 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1197 (i32 IntRegs:$src1)))],
1198 "$src1 = $dst">, ImmRegRel;
1201 let CextOpcode = "MPYI_acc", InputType = "reg" in
1202 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1203 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1204 "$dst += mpyi($src2, $src3)",
1205 [(set (i32 IntRegs:$dst),
1206 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1207 (i32 IntRegs:$src1)))],
1208 "$src1 = $dst">, ImmRegRel;
1211 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1212 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1213 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1214 "$dst -= mpyi($src2, #$src3)",
1215 [(set (i32 IntRegs:$dst),
1216 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1217 u8ExtPred:$src3)))],
1220 // Multiply and use upper result.
1221 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1222 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1224 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1225 "$dst = mpy($src1, $src2)",
1226 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1227 (i32 IntRegs:$src2)))]>;
1229 // Rd=mpy(Rs,Rt):rnd
1231 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1232 "$dst = mpyu($src1, $src2)",
1233 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1234 (i32 IntRegs:$src2)))]>;
1236 // Multiply and use full result.
1238 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1239 "$dst = mpyu($src1, $src2)",
1240 [(set (i64 DoubleRegs:$dst),
1241 (mul (i64 (anyext (i32 IntRegs:$src1))),
1242 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1245 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1246 "$dst = mpy($src1, $src2)",
1247 [(set (i64 DoubleRegs:$dst),
1248 (mul (i64 (sext (i32 IntRegs:$src1))),
1249 (i64 (sext (i32 IntRegs:$src2)))))]>;
1251 // Multiply and accumulate, use full result.
1252 // Rxx[+-]=mpy(Rs,Rt)
1254 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1255 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1256 "$dst += mpy($src2, $src3)",
1257 [(set (i64 DoubleRegs:$dst),
1258 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1259 (i64 (sext (i32 IntRegs:$src3)))),
1260 (i64 DoubleRegs:$src1)))],
1264 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1265 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1266 "$dst -= mpy($src2, $src3)",
1267 [(set (i64 DoubleRegs:$dst),
1268 (sub (i64 DoubleRegs:$src1),
1269 (mul (i64 (sext (i32 IntRegs:$src2))),
1270 (i64 (sext (i32 IntRegs:$src3))))))],
1273 // Rxx[+-]=mpyu(Rs,Rt)
1275 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1276 IntRegs:$src2, IntRegs:$src3),
1277 "$dst += mpyu($src2, $src3)",
1278 [(set (i64 DoubleRegs:$dst),
1279 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1280 (i64 (anyext (i32 IntRegs:$src3)))),
1281 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1284 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1285 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1286 "$dst -= mpyu($src2, $src3)",
1287 [(set (i64 DoubleRegs:$dst),
1288 (sub (i64 DoubleRegs:$src1),
1289 (mul (i64 (anyext (i32 IntRegs:$src2))),
1290 (i64 (anyext (i32 IntRegs:$src3))))))],
1294 let InputType = "reg", CextOpcode = "ADD_acc" in
1295 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1296 IntRegs:$src2, IntRegs:$src3),
1297 "$dst += add($src2, $src3)",
1298 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1299 (i32 IntRegs:$src3)),
1300 (i32 IntRegs:$src1)))],
1301 "$src1 = $dst">, ImmRegRel;
1303 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1304 InputType = "imm", CextOpcode = "ADD_acc" in
1305 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1306 IntRegs:$src2, s8Ext:$src3),
1307 "$dst += add($src2, #$src3)",
1308 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1309 s8_16ExtPred:$src3),
1310 (i32 IntRegs:$src1)))],
1311 "$src1 = $dst">, ImmRegRel;
1313 let CextOpcode = "SUB_acc", InputType = "reg" in
1314 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1315 IntRegs:$src2, IntRegs:$src3),
1316 "$dst -= add($src2, $src3)",
1317 [(set (i32 IntRegs:$dst),
1318 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1319 (i32 IntRegs:$src3))))],
1320 "$src1 = $dst">, ImmRegRel;
1322 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1323 CextOpcode = "SUB_acc", InputType = "imm" in
1324 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1325 IntRegs:$src2, s8Ext:$src3),
1326 "$dst -= add($src2, #$src3)",
1327 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1328 (add (i32 IntRegs:$src2),
1329 s8_16ExtPred:$src3)))],
1330 "$src1 = $dst">, ImmRegRel;
1332 //===----------------------------------------------------------------------===//
1334 //===----------------------------------------------------------------------===//
1336 //===----------------------------------------------------------------------===//
1338 //===----------------------------------------------------------------------===//
1339 //===----------------------------------------------------------------------===//
1341 //===----------------------------------------------------------------------===//
1343 //===----------------------------------------------------------------------===//
1345 //===----------------------------------------------------------------------===//
1346 //===----------------------------------------------------------------------===//
1348 //===----------------------------------------------------------------------===//
1350 //===----------------------------------------------------------------------===//
1352 //===----------------------------------------------------------------------===//
1353 //===----------------------------------------------------------------------===//
1355 //===----------------------------------------------------------------------===//
1357 //===----------------------------------------------------------------------===//
1359 //===----------------------------------------------------------------------===//
1361 // Store doubleword.
1363 //===----------------------------------------------------------------------===//
1364 // Post increment store
1365 //===----------------------------------------------------------------------===//
1367 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1368 bit isNot, bit isPredNew> {
1369 let PNewValue = !if(isPredNew, "new", "") in
1370 def NAME : STInst2PI<(outs IntRegs:$dst),
1371 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1372 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1373 ") ")#mnemonic#"($src2++#$offset) = $src3",
1378 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1379 Operand ImmOp, bit PredNot> {
1380 let isPredicatedFalse = PredNot in {
1381 defm _c#NAME# : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1383 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1384 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1388 let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1389 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1392 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1393 let isPredicable = 1 in
1394 def NAME : STInst2PI<(outs IntRegs:$dst),
1395 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1396 #mnemonic#"($src1++#$offset) = $src2",
1400 let isPredicated = 1 in {
1401 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1402 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1407 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1408 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1409 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1411 let isNVStorable = 0 in
1412 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1414 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1415 s4_3ImmPred:$offset),
1416 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1418 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1419 s4_3ImmPred:$offset),
1420 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1422 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1423 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1425 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1426 s4_3ImmPred:$offset),
1427 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1429 //===----------------------------------------------------------------------===//
1430 // multiclass for the store instructions with MEMri operand.
1431 //===----------------------------------------------------------------------===//
1432 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1434 let PNewValue = !if(isPredNew, "new", "") in
1435 def NAME : STInst2<(outs),
1436 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1437 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1438 ") ")#mnemonic#"($addr) = $src2",
1442 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1443 let isPredicatedFalse = PredNot in {
1444 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1447 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1448 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1452 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1453 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1454 bits<5> ImmBits, bits<5> PredImmBits> {
1456 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1457 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1459 def NAME : STInst2<(outs),
1460 (ins MEMri:$addr, RC:$src),
1461 mnemonic#"($addr) = $src",
1464 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1465 isPredicated = 1 in {
1466 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1467 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1472 let addrMode = BaseImmOffset, isMEMri = "true" in {
1473 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1474 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1475 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1477 let isNVStorable = 0 in
1478 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1481 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1482 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1484 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1485 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1487 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1488 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1490 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1491 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1494 //===----------------------------------------------------------------------===//
1495 // multiclass for the store instructions with base+immediate offset
1497 //===----------------------------------------------------------------------===//
1498 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1499 bit isNot, bit isPredNew> {
1500 let PNewValue = !if(isPredNew, "new", "") in
1501 def NAME : STInst2<(outs),
1502 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1503 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1504 ") ")#mnemonic#"($src2+#$src3) = $src4",
1508 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1510 let isPredicatedFalse = PredNot, isPredicated = 1 in {
1511 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1514 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1515 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1519 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1520 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1521 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1522 bits<5> PredImmBits> {
1524 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1525 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1527 def NAME : STInst2<(outs),
1528 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1529 mnemonic#"($src1+#$src2) = $src3",
1532 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1533 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1534 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1539 let addrMode = BaseImmOffset, InputType = "reg" in {
1540 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1541 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1542 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1543 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1544 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1545 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1546 let isNVStorable = 0 in
1547 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1548 u6_3Ext, 14, 9>, AddrModeRel;
1551 let AddedComplexity = 10 in {
1552 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1553 s11_0ExtPred:$offset)),
1554 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1555 (i32 IntRegs:$src1))>;
1557 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1558 s11_1ExtPred:$offset)),
1559 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1560 (i32 IntRegs:$src1))>;
1562 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1563 s11_2ExtPred:$offset)),
1564 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1565 (i32 IntRegs:$src1))>;
1567 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1568 s11_3ExtPred:$offset)),
1569 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1570 (i64 DoubleRegs:$src1))>;
1573 // memh(Rx++#s4:1)=Rt.H
1577 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1578 def STriw_pred : STInst2<(outs),
1579 (ins MEMri:$addr, PredRegs:$src1),
1580 "Error; should not emit",
1583 // Allocate stack frame.
1584 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1585 def ALLOCFRAME : STInst2<(outs),
1587 "allocframe(#$amt)",
1590 //===----------------------------------------------------------------------===//
1592 //===----------------------------------------------------------------------===//
1594 //===----------------------------------------------------------------------===//
1596 //===----------------------------------------------------------------------===//
1598 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1599 "$dst = not($src1)",
1600 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1603 // Sign extend word to doubleword.
1604 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1605 "$dst = sxtw($src1)",
1606 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1607 //===----------------------------------------------------------------------===//
1609 //===----------------------------------------------------------------------===//
1611 //===----------------------------------------------------------------------===//
1613 //===----------------------------------------------------------------------===//
1615 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1616 "$dst = clrbit($src1, #$src2)",
1617 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1619 (shl 1, u5ImmPred:$src2))))]>;
1621 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1622 "$dst = clrbit($src1, #$src2)",
1625 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1626 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1627 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1630 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1631 "$dst = setbit($src1, #$src2)",
1632 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1633 (shl 1, u5ImmPred:$src2)))]>;
1635 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1636 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1637 "$dst = setbit($src1, #$src2)",
1640 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1641 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1644 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1645 "$dst = setbit($src1, #$src2)",
1646 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1647 (shl 1, u5ImmPred:$src2)))]>;
1649 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1650 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1651 "$dst = togglebit($src1, #$src2)",
1654 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1655 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1657 // Predicate transfer.
1658 let neverHasSideEffects = 1 in
1659 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1660 "$dst = $src1 /* Should almost never emit this. */",
1663 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1664 "$dst = $src1 /* Should almost never emit this. */",
1665 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1666 //===----------------------------------------------------------------------===//
1668 //===----------------------------------------------------------------------===//
1670 //===----------------------------------------------------------------------===//
1672 //===----------------------------------------------------------------------===//
1673 // Shift by immediate.
1674 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1675 "$dst = asr($src1, #$src2)",
1676 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1677 u5ImmPred:$src2))]>;
1679 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1680 "$dst = asr($src1, #$src2)",
1681 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1682 u6ImmPred:$src2))]>;
1684 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1685 "$dst = asl($src1, #$src2)",
1686 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1687 u5ImmPred:$src2))]>;
1689 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1690 "$dst = asl($src1, #$src2)",
1691 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1692 u6ImmPred:$src2))]>;
1694 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1695 "$dst = lsr($src1, #$src2)",
1696 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1697 u5ImmPred:$src2))]>;
1699 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1700 "$dst = lsr($src1, #$src2)",
1701 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1702 u6ImmPred:$src2))]>;
1704 // Shift by immediate and add.
1705 let AddedComplexity = 100 in
1706 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1708 "$dst = addasl($src1, $src2, #$src3)",
1709 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1710 (shl (i32 IntRegs:$src2),
1711 u3ImmPred:$src3)))]>;
1713 // Shift by register.
1714 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1715 "$dst = asl($src1, $src2)",
1716 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1717 (i32 IntRegs:$src2)))]>;
1719 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1720 "$dst = asr($src1, $src2)",
1721 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1722 (i32 IntRegs:$src2)))]>;
1724 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1725 "$dst = lsl($src1, $src2)",
1726 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1727 (i32 IntRegs:$src2)))]>;
1729 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1730 "$dst = lsr($src1, $src2)",
1731 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1732 (i32 IntRegs:$src2)))]>;
1734 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1735 "$dst = asl($src1, $src2)",
1736 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1737 (i32 IntRegs:$src2)))]>;
1739 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1740 "$dst = lsl($src1, $src2)",
1741 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1742 (i32 IntRegs:$src2)))]>;
1744 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1746 "$dst = asr($src1, $src2)",
1747 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1748 (i32 IntRegs:$src2)))]>;
1750 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1752 "$dst = lsr($src1, $src2)",
1753 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1754 (i32 IntRegs:$src2)))]>;
1756 //===----------------------------------------------------------------------===//
1758 //===----------------------------------------------------------------------===//
1760 //===----------------------------------------------------------------------===//
1762 //===----------------------------------------------------------------------===//
1763 //===----------------------------------------------------------------------===//
1765 //===----------------------------------------------------------------------===//
1767 //===----------------------------------------------------------------------===//
1769 //===----------------------------------------------------------------------===//
1770 //===----------------------------------------------------------------------===//
1772 //===----------------------------------------------------------------------===//
1774 //===----------------------------------------------------------------------===//
1776 //===----------------------------------------------------------------------===//
1778 //===----------------------------------------------------------------------===//
1780 //===----------------------------------------------------------------------===//
1781 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1782 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1785 let hasSideEffects = 1, isSolo = 1 in
1786 def BARRIER : SYSInst<(outs), (ins),
1788 [(HexagonBARRIER)]>;
1790 //===----------------------------------------------------------------------===//
1792 //===----------------------------------------------------------------------===//
1794 // TFRI64 - assembly mapped.
1795 let isReMaterializable = 1 in
1796 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1798 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1800 // Pseudo instruction to encode a set of conditional transfers.
1801 // This instruction is used instead of a mux and trades-off codesize
1802 // for performance. We conduct this transformation optimistically in
1803 // the hope that these instructions get promoted to dot-new transfers.
1804 let AddedComplexity = 100, isPredicated = 1 in
1805 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1808 "Error; should not emit",
1809 [(set (i32 IntRegs:$dst),
1810 (i32 (select (i1 PredRegs:$src1),
1811 (i32 IntRegs:$src2),
1812 (i32 IntRegs:$src3))))]>;
1813 let AddedComplexity = 100, isPredicated = 1 in
1814 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1815 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1816 "Error; should not emit",
1817 [(set (i32 IntRegs:$dst),
1818 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1819 s12ImmPred:$src3)))]>;
1821 let AddedComplexity = 100, isPredicated = 1 in
1822 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1823 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1824 "Error; should not emit",
1825 [(set (i32 IntRegs:$dst),
1826 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1827 (i32 IntRegs:$src3))))]>;
1829 let AddedComplexity = 100, isPredicated = 1 in
1830 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1831 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1832 "Error; should not emit",
1833 [(set (i32 IntRegs:$dst),
1834 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1835 s12ImmPred:$src3)))]>;
1837 // Generate frameindex addresses.
1838 let isReMaterializable = 1 in
1839 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1840 "$dst = add($src1)",
1841 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1846 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1847 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1848 "loop0($offset, #$src2)",
1852 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1853 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1854 "loop0($offset, $src2)",
1858 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1859 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1860 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
1865 // Support for generating global address.
1866 // Taken from X86InstrInfo.td.
1867 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1871 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1872 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
1874 // HI/LO Instructions
1875 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1876 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1877 "$dst.l = #LO($global)",
1880 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1881 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1882 "$dst.h = #HI($global)",
1885 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1886 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1887 "$dst.l = #LO($imm_value)",
1891 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1892 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1893 "$dst.h = #HI($imm_value)",
1896 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1897 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1898 "$dst.l = #LO($jt)",
1901 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1902 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1903 "$dst.h = #HI($jt)",
1907 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1908 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1909 "$dst.l = #LO($label)",
1912 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
1913 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1914 "$dst.h = #HI($label)",
1917 // This pattern is incorrect. When we add small data, we should change
1918 // this pattern to use memw(#foo).
1919 // This is for sdata.
1920 let isMoveImm = 1 in
1921 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
1922 "$dst = CONST32(#$global)",
1923 [(set (i32 IntRegs:$dst),
1924 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
1926 // This is for non-sdata.
1927 let isReMaterializable = 1, isMoveImm = 1 in
1928 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1929 "$dst = CONST32(#$global)",
1930 [(set (i32 IntRegs:$dst),
1931 (HexagonCONST32 tglobaladdr:$global))]>;
1933 let isReMaterializable = 1, isMoveImm = 1 in
1934 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1935 "$dst = CONST32(#$jt)",
1936 [(set (i32 IntRegs:$dst),
1937 (HexagonCONST32 tjumptable:$jt))]>;
1939 let isReMaterializable = 1, isMoveImm = 1 in
1940 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1941 "$dst = CONST32(#$global)",
1942 [(set (i32 IntRegs:$dst),
1943 (HexagonCONST32_GP tglobaladdr:$global))]>;
1945 let isReMaterializable = 1, isMoveImm = 1 in
1946 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
1947 "$dst = CONST32(#$global)",
1948 [(set (i32 IntRegs:$dst), imm:$global) ]>;
1950 // Map BlockAddress lowering to CONST32_Int_Real
1951 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
1952 (CONST32_Int_Real tblockaddress:$addr)>;
1954 let isReMaterializable = 1, isMoveImm = 1 in
1955 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
1956 "$dst = CONST32($label)",
1957 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
1959 let isReMaterializable = 1, isMoveImm = 1 in
1960 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
1961 "$dst = CONST64(#$global)",
1962 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
1964 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
1965 "$dst = xor($dst, $dst)",
1966 [(set (i1 PredRegs:$dst), 0)]>;
1968 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1969 "$dst = mpy($src1, $src2)",
1970 [(set (i32 IntRegs:$dst),
1971 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
1972 (i64 (sext (i32 IntRegs:$src2))))),
1975 // Pseudo instructions.
1976 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
1978 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
1979 SDTCisVT<1, i32> ]>;
1981 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
1982 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
1984 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
1985 [SDNPHasChain, SDNPOutGlue]>;
1987 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1989 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
1990 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
1992 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
1993 // Optional Flag and Variable Arguments.
1994 // Its 1 Operand has pointer type.
1995 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
1996 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1998 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
1999 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2000 "Should never be emitted",
2001 [(callseq_start timm:$amt)]>;
2004 let Defs = [R29, R30, R31], Uses = [R29] in {
2005 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2006 "Should never be emitted",
2007 [(callseq_end timm:$amt1, timm:$amt2)]>;
2010 let isCall = 1, neverHasSideEffects = 1,
2011 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2012 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2013 def CALL : JInst<(outs), (ins calltarget:$dst),
2017 // Call subroutine from register.
2018 let isCall = 1, neverHasSideEffects = 1,
2019 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2020 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2021 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2027 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2028 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2029 "jump $dst // TAILCALL", []>;
2031 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2032 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2033 "jump $dst // TAILCALL", []>;
2036 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2037 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2038 "jumpr $dst // TAILCALL", []>;
2040 // Map call instruction.
2041 def : Pat<(call (i32 IntRegs:$dst)),
2042 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2043 def : Pat<(call tglobaladdr:$dst),
2044 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2045 def : Pat<(call texternalsym:$dst),
2046 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2048 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2049 (TCRETURNtg tglobaladdr:$dst)>;
2050 def : Pat<(HexagonTCRet texternalsym:$dst),
2051 (TCRETURNtext texternalsym:$dst)>;
2052 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2053 (TCRETURNR (i32 IntRegs:$dst))>;
2055 // Atomic load and store support
2056 // 8 bit atomic load
2057 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2058 (i32 (LDriub ADDRriS11_0:$src1))>;
2060 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2061 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2063 // 16 bit atomic load
2064 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2065 (i32 (LDriuh ADDRriS11_1:$src1))>;
2067 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2068 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2070 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2071 (i32 (LDriw ADDRriS11_2:$src1))>;
2073 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2074 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2076 // 64 bit atomic load
2077 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2078 (i64 (LDrid ADDRriS11_3:$src1))>;
2080 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2081 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2084 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2085 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2087 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2088 (i32 IntRegs:$src1)),
2089 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2090 (i32 IntRegs:$src1))>;
2093 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2094 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2096 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2097 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2098 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2099 (i32 IntRegs:$src1))>;
2101 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2102 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2104 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2105 (i32 IntRegs:$src1)),
2106 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2107 (i32 IntRegs:$src1))>;
2112 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2113 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2115 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2116 (i64 DoubleRegs:$src1)),
2117 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2118 (i64 DoubleRegs:$src1))>;
2120 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2121 def : Pat <(and (i32 IntRegs:$src1), 65535),
2122 (ZXTH (i32 IntRegs:$src1))>;
2124 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2125 def : Pat <(and (i32 IntRegs:$src1), 255),
2126 (ZXTB (i32 IntRegs:$src1))>;
2128 // Map Add(p1, true) to p1 = not(p1).
2129 // Add(p1, false) should never be produced,
2130 // if it does, it got to be mapped to NOOP.
2131 def : Pat <(add (i1 PredRegs:$src1), -1),
2132 (NOT_p (i1 PredRegs:$src1))>;
2134 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2135 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2136 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2137 (i32 IntRegs:$src3),
2138 (i32 IntRegs:$src4)),
2139 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2140 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2141 Requires<[HasV2TOnly]>;
2143 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2144 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2145 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2148 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2149 // => r0 = TFR_condset_ri(p0, r1, #i)
2150 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2151 (i32 IntRegs:$src3)),
2152 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2153 s12ImmPred:$src2))>;
2155 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2156 // => r0 = TFR_condset_ir(p0, #i, r1)
2157 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2158 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2159 (i32 IntRegs:$src2)))>;
2161 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2162 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2163 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2165 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2166 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2167 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2169 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2170 let AddedComplexity = 10 in
2171 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2172 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2174 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2175 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2176 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2178 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2179 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2180 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2181 subreg_loreg))))))>;
2183 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2184 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2185 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2186 subreg_loreg))))))>;
2188 // We want to prevent emitting pnot's as much as possible.
2189 // Map brcond with an unsupported setcc to a JMP_cNot.
2190 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2192 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2195 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2197 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2199 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2200 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2202 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2203 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2205 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2207 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2209 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2211 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2213 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2215 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2218 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2220 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2223 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2225 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2228 // Map from a 64-bit select to an emulated 64-bit mux.
2229 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2230 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2231 (i64 DoubleRegs:$src3)),
2232 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2233 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2235 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2237 (i32 (MUX_rr (i1 PredRegs:$src1),
2238 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2240 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2241 subreg_loreg))))))>;
2243 // Map from a 1-bit select to logical ops.
2244 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2245 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2246 (i1 PredRegs:$src3)),
2247 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2248 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2250 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2251 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2252 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2254 // Map for truncating from 64 immediates to 32 bit immediates.
2255 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2256 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2258 // Map for truncating from i64 immediates to i1 bit immediates.
2259 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2260 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2263 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2264 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2265 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2268 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2269 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2270 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2272 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2273 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2274 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2277 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2278 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2279 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2282 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2283 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2284 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2287 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2288 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2289 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2291 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2292 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2293 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2295 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2296 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2297 // Better way to do this?
2298 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2299 (i64 (SXTW (i32 IntRegs:$src1)))>;
2301 // Map cmple -> cmpgt.
2302 // rs <= rt -> !(rs > rt).
2303 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2304 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2306 // rs <= rt -> !(rs > rt).
2307 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2308 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2310 // Rss <= Rtt -> !(Rss > Rtt).
2311 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2312 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2314 // Map cmpne -> cmpeq.
2315 // Hexagon_TODO: We should improve on this.
2316 // rs != rt -> !(rs == rt).
2317 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2318 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
2320 // Map cmpne(Rs) -> !cmpeqe(Rs).
2321 // rs != rt -> !(rs == rt).
2322 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2323 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2325 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2326 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2327 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2329 // Map cmpne(Rss) -> !cmpew(Rss).
2330 // rs != rt -> !(rs == rt).
2331 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2332 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2333 (i64 DoubleRegs:$src2)))))>;
2335 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2336 // rs >= rt -> !(rt > rs).
2337 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2338 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2340 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
2341 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
2343 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2344 // rss >= rtt -> !(rtt > rss).
2345 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2346 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2347 (i64 DoubleRegs:$src1)))))>;
2349 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2350 // rs < rt -> !(rs >= rt).
2351 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2352 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
2354 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2355 // rs < rt -> rt > rs.
2356 // We can let assembler map it, or we can do in the compiler itself.
2357 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2358 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2360 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2361 // rss < rtt -> (rtt > rss).
2362 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2363 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2365 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2366 // rs < rt -> rt > rs.
2367 // We can let assembler map it, or we can do in the compiler itself.
2368 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2369 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2371 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2372 // rs < rt -> rt > rs.
2373 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2374 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2376 // Generate cmpgeu(Rs, #u8)
2377 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
2378 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2380 // Generate cmpgtu(Rs, #u9)
2381 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
2382 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
2384 // Map from Rs >= Rt -> !(Rt > Rs).
2385 // rs >= rt -> !(rt > rs).
2386 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2387 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2389 // Map from Rs >= Rt -> !(Rt > Rs).
2390 // rs >= rt -> !(rt > rs).
2391 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2392 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2394 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2395 // Map from (Rs <= Rt) -> !(Rs > Rt).
2396 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2397 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2399 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2400 // Map from (Rs <= Rt) -> !(Rs > Rt).
2401 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2402 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2406 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2407 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2410 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2411 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2413 // Convert sign-extended load back to load and sign extend.
2415 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2416 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2418 // Convert any-extended load back to load and sign extend.
2420 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2421 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2423 // Convert sign-extended load back to load and sign extend.
2425 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2426 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2428 // Convert sign-extended load back to load and sign extend.
2430 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2431 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2436 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2437 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2440 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2441 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2445 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2446 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2450 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2451 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2454 let AddedComplexity = 20 in
2455 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2456 s11_0ExtPred:$offset))),
2457 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2458 s11_0ExtPred:$offset)))>,
2462 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
2463 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2466 let AddedComplexity = 20 in
2467 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
2468 s11_0ExtPred:$offset))),
2469 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2470 s11_0ExtPred:$offset)))>,
2474 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2475 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2478 let AddedComplexity = 20 in
2479 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2480 s11_1ExtPred:$offset))),
2481 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2482 s11_1ExtPred:$offset)))>,
2486 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2487 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2490 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2491 (i32 (LDriw ADDRriS11_0:$src1))>;
2493 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2494 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2495 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2497 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2498 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2499 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2501 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2502 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2503 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2506 // Any extended 64-bit load.
2507 // anyext i32 -> i64
2508 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2509 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2512 // When there is an offset we should prefer the pattern below over the pattern above.
2513 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2514 // So this complexity below is comfortably higher to allow for choosing the below.
2515 // If this is not done then we generate addresses such as
2516 // ********************************************
2517 // r1 = add (r0, #4)
2518 // r1 = memw(r1 + #0)
2520 // r1 = memw(r0 + #4)
2521 // ********************************************
2522 let AddedComplexity = 100 in
2523 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2524 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2525 s11_2ExtPred:$offset)))>,
2528 // anyext i16 -> i64.
2529 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2530 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2533 let AddedComplexity = 20 in
2534 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2535 s11_1ExtPred:$offset))),
2536 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2537 s11_1ExtPred:$offset)))>,
2540 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2541 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2542 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2545 // Multiply 64-bit unsigned and use upper result.
2546 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2561 (COMBINE_rr (TFRI 0),
2567 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2569 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2570 subreg_loreg)))), 32)),
2572 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2573 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2574 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2575 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2576 32)), subreg_loreg)))),
2577 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2578 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2580 // Multiply 64-bit signed and use upper result.
2581 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2585 (COMBINE_rr (TFRI 0),
2595 (COMBINE_rr (TFRI 0),
2601 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2603 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2604 subreg_loreg)))), 32)),
2606 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2607 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2608 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2609 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2610 32)), subreg_loreg)))),
2611 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2612 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2614 // Hexagon specific ISD nodes.
2615 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2616 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2617 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2618 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2619 SDTHexagonADJDYNALLOC>;
2620 // Needed to tag these instructions for stack layout.
2621 let usesCustomInserter = 1 in
2622 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2624 "$dst = add($src1, #$src2)",
2625 [(set (i32 IntRegs:$dst),
2626 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2627 s16ImmPred:$src2))]>;
2629 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2630 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2631 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2633 [(set (i32 IntRegs:$dst),
2634 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2636 let AddedComplexity = 100 in
2637 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2638 (COPY (i32 IntRegs:$src1))>;
2640 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2641 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
2643 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
2644 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
2646 [(HexagonBR_JT (i32 IntRegs:$src))]>;
2648 let isBranch=1, isIndirectBranch=1, isTerminator=1 in
2649 def BRIND : JRInst<(outs), (ins IntRegs:$src),
2651 [(brind (i32 IntRegs:$src))]>;
2653 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2655 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2656 (i32 (CONST32_set_jt tjumptable:$dst))>;
2660 // Multi-class for logical operators :
2661 // Shift by immediate/register and accumulate/logical
2662 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2663 def _ri : SInst_acc<(outs IntRegs:$dst),
2664 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2665 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2666 [(set (i32 IntRegs:$dst),
2667 (OpNode2 (i32 IntRegs:$src1),
2668 (OpNode1 (i32 IntRegs:$src2),
2669 u5ImmPred:$src3)))],
2672 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2673 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2674 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2675 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2676 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2680 // Multi-class for logical operators :
2681 // Shift by register and accumulate/logical (32/64 bits)
2682 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2683 def _rr : SInst_acc<(outs IntRegs:$dst),
2684 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2685 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2686 [(set (i32 IntRegs:$dst),
2687 (OpNode2 (i32 IntRegs:$src1),
2688 (OpNode1 (i32 IntRegs:$src2),
2689 (i32 IntRegs:$src3))))],
2692 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
2693 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2694 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2695 [(set (i64 DoubleRegs:$dst),
2696 (OpNode2 (i64 DoubleRegs:$src1),
2697 (OpNode1 (i64 DoubleRegs:$src2),
2698 (i32 IntRegs:$src3))))],
2703 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
2704 let AddedComplexity = 100 in
2705 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
2706 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
2707 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
2708 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
2711 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
2712 let AddedComplexity = 100 in
2713 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
2714 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
2715 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
2716 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
2719 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
2720 let AddedComplexity = 100 in
2721 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
2724 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
2725 xtype_xor_imm<"asl", shl>;
2727 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
2728 xtype_xor_imm<"lsr", srl>;
2730 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
2731 defm LSL : basic_xtype_reg<"lsl", shl>;
2733 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
2734 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
2735 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2737 //===----------------------------------------------------------------------===//
2738 // V3 Instructions +
2739 //===----------------------------------------------------------------------===//
2741 include "HexagonInstrInfoV3.td"
2743 //===----------------------------------------------------------------------===//
2744 // V3 Instructions -
2745 //===----------------------------------------------------------------------===//
2747 //===----------------------------------------------------------------------===//
2748 // V4 Instructions +
2749 //===----------------------------------------------------------------------===//
2751 include "HexagonInstrInfoV4.td"
2753 //===----------------------------------------------------------------------===//
2754 // V4 Instructions -
2755 //===----------------------------------------------------------------------===//
2757 //===----------------------------------------------------------------------===//
2758 // V5 Instructions +
2759 //===----------------------------------------------------------------------===//
2761 include "HexagonInstrInfoV5.td"
2763 //===----------------------------------------------------------------------===//
2764 // V5 Instructions -
2765 //===----------------------------------------------------------------------===//