1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonImmediates.td"
17 //===----------------------------------------------------------------------===//
18 // Classes used for relation maps.
19 //===----------------------------------------------------------------------===//
20 // PredRel - Filter class used to relate non-predicated instructions with their
23 // PredNewRel - Filter class used to relate predicated instructions with their
24 // predicate-new forms.
25 class PredNewRel: PredRel;
26 // ImmRegRel - Filter class used to relate instructions having reg-reg form
27 // with their reg-imm counterparts.
29 // NewValueRel - Filter class used to relate regular store instructions with
30 // their new-value store form.
31 class NewValueRel: PredNewRel;
32 // NewValueRel - Filter class used to relate load/store instructions having
33 // different addressing modes with each other.
34 class AddrModeRel: NewValueRel;
36 //===----------------------------------------------------------------------===//
37 // Hexagon Instruction Predicate Definitions.
38 //===----------------------------------------------------------------------===//
39 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
40 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
41 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
42 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
43 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
44 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
45 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
46 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
47 def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
48 def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
49 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
50 def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
53 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
54 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
55 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
56 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
57 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
58 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
59 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
60 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
61 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
64 def MEMrr : Operand<i32> {
65 let PrintMethod = "printMEMrrOperand";
66 let MIOperandInfo = (ops IntRegs, IntRegs);
70 def MEMri : Operand<i32> {
71 let PrintMethod = "printMEMriOperand";
72 let MIOperandInfo = (ops IntRegs, IntRegs);
75 def MEMri_s11_2 : Operand<i32>,
76 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
77 let PrintMethod = "printMEMriOperand";
78 let MIOperandInfo = (ops IntRegs, s11Imm);
81 def FrameIndex : Operand<i32> {
82 let PrintMethod = "printFrameIndexOperand";
83 let MIOperandInfo = (ops IntRegs, s11Imm);
86 let PrintMethod = "printGlobalOperand" in
87 def globaladdress : Operand<i32>;
89 let PrintMethod = "printJumpTable" in
90 def jumptablebase : Operand<i32>;
92 def brtarget : Operand<OtherVT>;
93 def calltarget : Operand<i32>;
95 def bblabel : Operand<i32>;
96 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
98 def symbolHi32 : Operand<i32> {
99 let PrintMethod = "printSymbolHi";
101 def symbolLo32 : Operand<i32> {
102 let PrintMethod = "printSymbolLo";
105 // Multi-class for logical operators.
106 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
107 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
108 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
109 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
110 (i32 IntRegs:$c)))]>;
111 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
112 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
113 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
114 (i32 IntRegs:$c)))]>;
117 // Multi-class for compare ops.
118 let isCompare = 1 in {
119 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
120 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
121 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
122 [(set (i1 PredRegs:$dst),
123 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
125 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
126 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
127 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
128 [(set (i1 PredRegs:$dst),
129 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
132 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
133 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
134 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
135 [(set (i1 PredRegs:$dst),
136 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
137 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
138 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
139 [(set (i1 PredRegs:$dst),
140 (OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
143 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
144 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
145 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
146 [(set (i1 PredRegs:$dst),
147 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
148 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
149 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
150 [(set (i1 PredRegs:$dst),
151 (OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
154 multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
155 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
156 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
157 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
161 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
162 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
163 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
164 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
169 //===----------------------------------------------------------------------===//
170 // ALU32/ALU (Instructions with register-register form)
171 //===----------------------------------------------------------------------===//
172 multiclass ALU32_Pbase<string mnemonic, bit isNot,
175 let PNewValue = #!if(isPredNew, "new", "") in
176 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
177 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
178 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
179 ") $dst = ")#mnemonic#"($src2, $src3)",
183 multiclass ALU32_Pred<string mnemonic, bit PredNot> {
184 let PredSense = #!if(PredNot, "false", "true") in {
185 defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
187 defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
191 let InputType = "reg" in
192 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
193 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
194 let isPredicable = 1 in
195 def #NAME# : ALU32_rr<(outs IntRegs:$dst),
196 (ins IntRegs:$src1, IntRegs:$src2),
197 "$dst = "#mnemonic#"($src1, $src2)",
198 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
199 (i32 IntRegs:$src2)))]>;
201 let neverHasSideEffects = 1, isPredicated = 1 in {
202 defm Pt : ALU32_Pred<mnemonic, 0>;
203 defm NotPt : ALU32_Pred<mnemonic, 1>;
208 let isCommutable = 1 in {
209 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
210 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
211 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
212 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
215 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
217 //===----------------------------------------------------------------------===//
218 // ALU32/ALU (ADD with register-immediate form)
219 //===----------------------------------------------------------------------===//
220 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
221 let PNewValue = #!if(isPredNew, "new", "") in
222 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
223 (ins PredRegs:$src1, IntRegs:$src2, s8Imm: $src3),
224 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
225 ") $dst = ")#mnemonic#"($src2, #$src3)",
229 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
230 let PredSense = #!if(PredNot, "false", "true") in {
231 defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
233 defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
237 let InputType = "imm" in
238 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
239 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
240 let isPredicable = 1 in
241 def #NAME# : ALU32_ri<(outs IntRegs:$dst),
242 (ins IntRegs:$src1, s16Imm:$src2),
243 "$dst = "#mnemonic#"($src1, #$src2)",
244 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
245 (s16ImmPred:$src2)))]>;
247 let neverHasSideEffects = 1, isPredicated = 1 in {
248 defm Pt : ALU32ri_Pred<mnemonic, 0>;
249 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
254 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
256 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
257 (ins IntRegs:$src1, s10Imm:$src2),
258 "$dst = or($src1, #$src2)",
259 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
260 s10ImmPred:$src2))]>;
262 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
265 [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
267 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
268 (ins IntRegs:$src1, s10Imm:$src2),
269 "$dst = and($src1, #$src2)",
270 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
271 s10ImmPred:$src2))]>;
274 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
276 [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
278 let neverHasSideEffects = 1 in
279 def NOP : ALU32_rr<(outs), (ins),
283 // Rd32=sub(#s10,Rs32)
284 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
285 (ins s10Imm:$src1, IntRegs:$src2),
286 "$dst = sub(#$src1, $src2)",
287 [(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
289 // Transfer immediate.
290 let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in
291 def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
293 [(set (i32 IntRegs:$dst), s16ImmPred:$src1)]>;
295 // Transfer register.
296 let neverHasSideEffects = 1, isPredicable = 1 in
297 def TFR : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1),
301 let neverHasSideEffects = 1, isPredicable = 1 in
302 def TFR64 : ALU32_ri<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
306 // Transfer control register.
307 let neverHasSideEffects = 1 in
308 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
311 //===----------------------------------------------------------------------===//
313 //===----------------------------------------------------------------------===//
316 //===----------------------------------------------------------------------===//
318 //===----------------------------------------------------------------------===//
321 let isPredicable = 1, neverHasSideEffects = 1 in
322 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
323 (ins IntRegs:$src1, IntRegs:$src2),
324 "$dst = combine($src1, $src2)",
327 let neverHasSideEffects = 1 in
328 def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
329 (ins s8Imm:$src1, s8Imm:$src2),
330 "$dst = combine(#$src1, #$src2)",
334 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
337 "$dst = vmux($src1, $src2, $src3)",
340 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
341 IntRegs:$src2, IntRegs:$src3),
342 "$dst = mux($src1, $src2, $src3)",
343 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
345 (i32 IntRegs:$src3))))]>;
347 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
349 "$dst = mux($src1, #$src2, $src3)",
350 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
352 (i32 IntRegs:$src3))))]>;
354 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
356 "$dst = mux($src1, $src2, #$src3)",
357 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
359 s8ImmPred:$src3)))]>;
361 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
363 "$dst = mux($src1, #$src2, #$src3)",
364 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
366 s8ImmPred:$src3)))]>;
369 let isPredicable = 1 in
370 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
371 "$dst = aslh($src1)",
372 [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
374 let isPredicable = 1 in
375 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
376 "$dst = asrh($src1)",
377 [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
380 let isPredicable = 1 in
381 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
382 "$dst = sxtb($src1)",
383 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
385 let isPredicable = 1 in
386 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
387 "$dst = sxth($src1)",
388 [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
391 let isPredicable = 1, neverHasSideEffects = 1 in
392 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
393 "$dst = zxtb($src1)",
396 let isPredicable = 1, neverHasSideEffects = 1 in
397 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
398 "$dst = zxth($src1)",
400 //===----------------------------------------------------------------------===//
402 //===----------------------------------------------------------------------===//
405 //===----------------------------------------------------------------------===//
407 //===----------------------------------------------------------------------===//
409 // Conditional combine.
411 let neverHasSideEffects = 1, isPredicated = 1 in
412 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
413 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
414 "if ($src1) $dst = combine($src2, $src3)",
417 let neverHasSideEffects = 1, isPredicated = 1 in
418 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
419 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
420 "if (!$src1) $dst = combine($src2, $src3)",
423 let neverHasSideEffects = 1, isPredicated = 1 in
424 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
425 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
426 "if ($src1.new) $dst = combine($src2, $src3)",
429 let neverHasSideEffects = 1, isPredicated = 1 in
430 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
431 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
432 "if (!$src1.new) $dst = combine($src2, $src3)",
435 // Conditional transfer.
436 let neverHasSideEffects = 1, isPredicated = 1 in
437 def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
438 "if ($src1) $dst = $src2",
441 let neverHasSideEffects = 1, isPredicated = 1 in
442 def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
444 "if (!$src1) $dst = $src2",
447 let neverHasSideEffects = 1, isPredicated = 1 in
448 def TFR64_cPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
450 "if ($src1) $dst = $src2",
453 let neverHasSideEffects = 1, isPredicated = 1 in
454 def TFR64_cNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
456 "if (!$src1) $dst = $src2",
459 let neverHasSideEffects = 1, isPredicated = 1 in
460 def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
461 "if ($src1) $dst = #$src2",
464 let neverHasSideEffects = 1, isPredicated = 1 in
465 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
467 "if (!$src1) $dst = #$src2",
470 let neverHasSideEffects = 1, isPredicated = 1 in
471 def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
473 "if ($src1.new) $dst = $src2",
476 let neverHasSideEffects = 1, isPredicated = 1 in
477 def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
479 "if (!$src1.new) $dst = $src2",
482 let neverHasSideEffects = 1, isPredicated = 1 in
483 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
485 "if ($src1.new) $dst = #$src2",
488 let neverHasSideEffects = 1, isPredicated = 1 in
489 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
491 "if (!$src1.new) $dst = #$src2",
495 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
496 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
497 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
498 defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
499 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
500 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
501 defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
502 //===----------------------------------------------------------------------===//
504 //===----------------------------------------------------------------------===//
507 //===----------------------------------------------------------------------===//
509 //===----------------------------------------------------------------------===//
511 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
513 "$dst = add($src1, $src2)",
514 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
515 (i64 DoubleRegs:$src2)))]>;
520 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
521 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
522 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
524 // Logical operations.
525 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
527 "$dst = and($src1, $src2)",
528 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
529 (i64 DoubleRegs:$src2)))]>;
531 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
533 "$dst = or($src1, $src2)",
534 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
535 (i64 DoubleRegs:$src2)))]>;
537 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
539 "$dst = xor($src1, $src2)",
540 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
541 (i64 DoubleRegs:$src2)))]>;
544 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
545 "$dst = max($src2, $src1)",
546 [(set (i32 IntRegs:$dst),
547 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
548 (i32 IntRegs:$src1))),
549 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
551 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
552 "$dst = maxu($src2, $src1)",
553 [(set (i32 IntRegs:$dst),
554 (i32 (select (i1 (setult (i32 IntRegs:$src2),
555 (i32 IntRegs:$src1))),
556 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
558 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
560 "$dst = max($src2, $src1)",
561 [(set (i64 DoubleRegs:$dst),
562 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
563 (i64 DoubleRegs:$src1))),
564 (i64 DoubleRegs:$src1),
565 (i64 DoubleRegs:$src2))))]>;
567 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
569 "$dst = maxu($src2, $src1)",
570 [(set (i64 DoubleRegs:$dst),
571 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
572 (i64 DoubleRegs:$src1))),
573 (i64 DoubleRegs:$src1),
574 (i64 DoubleRegs:$src2))))]>;
577 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
578 "$dst = min($src2, $src1)",
579 [(set (i32 IntRegs:$dst),
580 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
581 (i32 IntRegs:$src1))),
582 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
584 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
585 "$dst = minu($src2, $src1)",
586 [(set (i32 IntRegs:$dst),
587 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
588 (i32 IntRegs:$src1))),
589 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
591 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
593 "$dst = min($src2, $src1)",
594 [(set (i64 DoubleRegs:$dst),
595 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
596 (i64 DoubleRegs:$src1))),
597 (i64 DoubleRegs:$src1),
598 (i64 DoubleRegs:$src2))))]>;
600 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
602 "$dst = minu($src2, $src1)",
603 [(set (i64 DoubleRegs:$dst),
604 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
605 (i64 DoubleRegs:$src1))),
606 (i64 DoubleRegs:$src1),
607 (i64 DoubleRegs:$src2))))]>;
610 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
612 "$dst = sub($src1, $src2)",
613 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
614 (i64 DoubleRegs:$src2)))]>;
616 // Subtract halfword.
618 // Transfer register.
619 let neverHasSideEffects = 1 in
620 def TFR_64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
623 //===----------------------------------------------------------------------===//
625 //===----------------------------------------------------------------------===//
627 //===----------------------------------------------------------------------===//
629 //===----------------------------------------------------------------------===//
631 //===----------------------------------------------------------------------===//
633 //===----------------------------------------------------------------------===//
635 //===----------------------------------------------------------------------===//
637 //===----------------------------------------------------------------------===//
639 //===----------------------------------------------------------------------===//
641 //===----------------------------------------------------------------------===//
643 //===----------------------------------------------------------------------===//
645 //===----------------------------------------------------------------------===//
646 // Logical reductions on predicates.
648 // Looping instructions.
650 // Pipelined looping instructions.
652 // Logical operations on predicates.
653 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
654 "$dst = and($src1, $src2)",
655 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
656 (i1 PredRegs:$src2)))]>;
658 let neverHasSideEffects = 1 in
659 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
661 "$dst = and($src1, !$src2)",
664 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
665 "$dst = any8($src1)",
668 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
669 "$dst = all8($src1)",
672 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
674 "$dst = vitpack($src1, $src2)",
677 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
680 "$dst = valignb($src1, $src2, $src3)",
683 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
686 "$dst = vspliceb($src1, $src2, $src3)",
689 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
690 "$dst = mask($src1)",
693 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
695 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
697 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
698 "$dst = or($src1, $src2)",
699 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
700 (i1 PredRegs:$src2)))]>;
702 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
703 "$dst = xor($src1, $src2)",
704 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
705 (i1 PredRegs:$src2)))]>;
708 // User control register transfer.
709 //===----------------------------------------------------------------------===//
711 //===----------------------------------------------------------------------===//
714 //===----------------------------------------------------------------------===//
716 //===----------------------------------------------------------------------===//
718 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
719 def JMP : JInst< (outs),
720 (ins brtarget:$offset),
726 let isBranch = 1, isTerminator=1, Defs = [PC],
727 isPredicated = 1 in {
728 def JMP_c : JInst< (outs),
729 (ins PredRegs:$src, brtarget:$offset),
730 "if ($src) jump $offset",
731 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
735 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
736 isPredicated = 1 in {
737 def JMP_cNot : JInst< (outs),
738 (ins PredRegs:$src, brtarget:$offset),
739 "if (!$src) jump $offset",
743 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
744 isPredicated = 1 in {
745 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
746 "if ($pred) jump $dst",
750 // Jump to address conditioned on new predicate.
752 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
753 isPredicated = 1 in {
754 def JMP_cdnPt : JInst< (outs),
755 (ins PredRegs:$src, brtarget:$offset),
756 "if ($src.new) jump:t $offset",
761 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
762 isPredicated = 1 in {
763 def JMP_cdnNotPt : JInst< (outs),
764 (ins PredRegs:$src, brtarget:$offset),
765 "if (!$src.new) jump:t $offset",
770 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
771 isPredicated = 1 in {
772 def JMP_cdnPnt : JInst< (outs),
773 (ins PredRegs:$src, brtarget:$offset),
774 "if ($src.new) jump:nt $offset",
779 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
780 isPredicated = 1 in {
781 def JMP_cdnNotPnt : JInst< (outs),
782 (ins PredRegs:$src, brtarget:$offset),
783 "if (!$src.new) jump:nt $offset",
786 //===----------------------------------------------------------------------===//
788 //===----------------------------------------------------------------------===//
790 //===----------------------------------------------------------------------===//
792 //===----------------------------------------------------------------------===//
793 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
794 [SDNPHasChain, SDNPOptInGlue]>;
796 // Jump to address from register.
797 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
798 Defs = [PC], Uses = [R31] in {
799 def JMPR: JRInst<(outs), (ins),
804 // Jump to address from register.
805 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
806 Defs = [PC], Uses = [R31] in {
807 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
808 "if ($src1) jumpr r31",
812 // Jump to address from register.
813 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
814 Defs = [PC], Uses = [R31] in {
815 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
816 "if (!$src1) jumpr r31",
820 //===----------------------------------------------------------------------===//
822 //===----------------------------------------------------------------------===//
824 //===----------------------------------------------------------------------===//
826 //===----------------------------------------------------------------------===//
830 let isPredicable = 1 in
831 def LDrid : LDInst<(outs DoubleRegs:$dst),
833 "$dst = memd($addr)",
834 [(set (i64 DoubleRegs:$dst), (i64 (load ADDRriS11_3:$addr)))]>;
836 let isPredicable = 1, AddedComplexity = 20 in
837 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
838 (ins IntRegs:$src1, s11_3Imm:$offset),
839 "$dst = memd($src1+#$offset)",
840 [(set (i64 DoubleRegs:$dst),
841 (i64 (load (add (i32 IntRegs:$src1),
842 s11_3ImmPred:$offset))))]>;
844 let neverHasSideEffects = 1 in
845 def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
846 (ins globaladdress:$global, u16Imm:$offset),
847 "$dst = memd(#$global+$offset)",
851 let neverHasSideEffects = 1 in
852 def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
853 (ins globaladdress:$global),
854 "$dst = memd(#$global)",
858 //===----------------------------------------------------------------------===//
859 // Post increment load
860 // Make sure that in post increment load, the first operand is always the post
861 // increment operand.
862 //===----------------------------------------------------------------------===//
864 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
865 bit isNot, bit isPredNew> {
866 let PNewValue = #!if(isPredNew, "new", "") in
867 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
868 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
869 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
870 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
875 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
876 Operand ImmOp, bit PredNot> {
877 let PredSense = #!if(PredNot, "false", "true") in {
878 defm _c#NAME# : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
880 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
881 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
885 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
888 let BaseOpcode = "POST_"#BaseOp in {
889 let isPredicable = 1 in
890 def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
891 (ins IntRegs:$src1, ImmOp:$offset),
892 "$dst = "#mnemonic#"($src1++#$offset)",
896 let isPredicated = 1 in {
897 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
898 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
903 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
904 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
906 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
908 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
910 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
912 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
914 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
918 // Load doubleword conditionally.
919 let neverHasSideEffects = 1, isPredicated = 1 in
920 def LDrid_cPt : LDInst2<(outs DoubleRegs:$dst),
921 (ins PredRegs:$src1, MEMri:$addr),
922 "if ($src1) $dst = memd($addr)",
926 let neverHasSideEffects = 1, isPredicated = 1 in
927 def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$dst),
928 (ins PredRegs:$src1, MEMri:$addr),
929 "if (!$src1) $dst = memd($addr)",
932 let neverHasSideEffects = 1, isPredicated = 1 in
933 def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
934 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
935 "if ($src1) $dst = memd($src2+#$src3)",
938 let neverHasSideEffects = 1, isPredicated = 1 in
939 def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
940 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
941 "if (!$src1) $dst = memd($src2+#$src3)",
944 let neverHasSideEffects = 1, isPredicated = 1 in
945 def LDrid_cdnPt : LDInst2<(outs DoubleRegs:$dst),
946 (ins PredRegs:$src1, MEMri:$addr),
947 "if ($src1.new) $dst = memd($addr)",
950 let neverHasSideEffects = 1, isPredicated = 1 in
951 def LDrid_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
952 (ins PredRegs:$src1, MEMri:$addr),
953 "if (!$src1.new) $dst = memd($addr)",
956 let neverHasSideEffects = 1, isPredicated = 1 in
957 def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
958 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
959 "if ($src1.new) $dst = memd($src2+#$src3)",
962 let neverHasSideEffects = 1, isPredicated = 1 in
963 def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
964 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
965 "if (!$src1.new) $dst = memd($src2+#$src3)",
970 let isPredicable = 1 in
971 def LDrib : LDInst<(outs IntRegs:$dst),
973 "$dst = memb($addr)",
974 [(set (i32 IntRegs:$dst), (i32 (sextloadi8 ADDRriS11_0:$addr)))]>;
976 // Load byte any-extend.
977 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
978 (i32 (LDrib ADDRriS11_0:$addr)) >;
980 // Indexed load byte.
981 let isPredicable = 1, AddedComplexity = 20 in
982 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
983 (ins IntRegs:$src1, s11_0Imm:$offset),
984 "$dst = memb($src1+#$offset)",
985 [(set (i32 IntRegs:$dst),
986 (i32 (sextloadi8 (add (i32 IntRegs:$src1),
987 s11_0ImmPred:$offset))))]>;
989 // Indexed load byte any-extend.
990 let AddedComplexity = 20 in
991 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
992 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
994 let neverHasSideEffects = 1 in
995 def LDrib_GP : LDInst2<(outs IntRegs:$dst),
996 (ins globaladdress:$global, u16Imm:$offset),
997 "$dst = memb(#$global+$offset)",
1001 let neverHasSideEffects = 1 in
1002 def LDb_GP : LDInst2<(outs IntRegs:$dst),
1003 (ins globaladdress:$global),
1004 "$dst = memb(#$global)",
1008 let neverHasSideEffects = 1 in
1009 def LDub_GP : LDInst2<(outs IntRegs:$dst),
1010 (ins globaladdress:$global),
1011 "$dst = memub(#$global)",
1015 // Load byte conditionally.
1016 let neverHasSideEffects = 1, isPredicated = 1 in
1017 def LDrib_cPt : LDInst2<(outs IntRegs:$dst),
1018 (ins PredRegs:$src1, MEMri:$addr),
1019 "if ($src1) $dst = memb($addr)",
1022 let neverHasSideEffects = 1, isPredicated = 1 in
1023 def LDrib_cNotPt : LDInst2<(outs IntRegs:$dst),
1024 (ins PredRegs:$src1, MEMri:$addr),
1025 "if (!$src1) $dst = memb($addr)",
1028 let neverHasSideEffects = 1, isPredicated = 1 in
1029 def LDrib_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1030 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1031 "if ($src1) $dst = memb($src2+#$src3)",
1034 let neverHasSideEffects = 1, isPredicated = 1 in
1035 def LDrib_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1036 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1037 "if (!$src1) $dst = memb($src2+#$src3)",
1040 let neverHasSideEffects = 1, isPredicated = 1 in
1041 def LDrib_cdnPt : LDInst2<(outs IntRegs:$dst),
1042 (ins PredRegs:$src1, MEMri:$addr),
1043 "if ($src1.new) $dst = memb($addr)",
1046 let neverHasSideEffects = 1, isPredicated = 1 in
1047 def LDrib_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1048 (ins PredRegs:$src1, MEMri:$addr),
1049 "if (!$src1.new) $dst = memb($addr)",
1052 let neverHasSideEffects = 1, isPredicated = 1 in
1053 def LDrib_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1054 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1055 "if ($src1.new) $dst = memb($src2+#$src3)",
1058 let neverHasSideEffects = 1, isPredicated = 1 in
1059 def LDrib_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1060 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1061 "if (!$src1.new) $dst = memb($src2+#$src3)",
1066 let isPredicable = 1 in
1067 def LDrih : LDInst<(outs IntRegs:$dst),
1069 "$dst = memh($addr)",
1070 [(set (i32 IntRegs:$dst), (i32 (sextloadi16 ADDRriS11_1:$addr)))]>;
1072 let isPredicable = 1, AddedComplexity = 20 in
1073 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
1074 (ins IntRegs:$src1, s11_1Imm:$offset),
1075 "$dst = memh($src1+#$offset)",
1076 [(set (i32 IntRegs:$dst),
1077 (i32 (sextloadi16 (add (i32 IntRegs:$src1),
1078 s11_1ImmPred:$offset))))]>;
1080 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1081 (i32 (LDrih ADDRriS11_1:$addr))>;
1083 let AddedComplexity = 20 in
1084 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1085 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1087 let neverHasSideEffects = 1 in
1088 def LDrih_GP : LDInst2<(outs IntRegs:$dst),
1089 (ins globaladdress:$global, u16Imm:$offset),
1090 "$dst = memh(#$global+$offset)",
1094 let neverHasSideEffects = 1 in
1095 def LDh_GP : LDInst2<(outs IntRegs:$dst),
1096 (ins globaladdress:$global),
1097 "$dst = memh(#$global)",
1101 let neverHasSideEffects = 1 in
1102 def LDuh_GP : LDInst2<(outs IntRegs:$dst),
1103 (ins globaladdress:$global),
1104 "$dst = memuh(#$global)",
1108 // Load halfword conditionally.
1109 let neverHasSideEffects = 1, isPredicated = 1 in
1110 def LDrih_cPt : LDInst2<(outs IntRegs:$dst),
1111 (ins PredRegs:$src1, MEMri:$addr),
1112 "if ($src1) $dst = memh($addr)",
1115 let neverHasSideEffects = 1, isPredicated = 1 in
1116 def LDrih_cNotPt : LDInst2<(outs IntRegs:$dst),
1117 (ins PredRegs:$src1, MEMri:$addr),
1118 "if (!$src1) $dst = memh($addr)",
1121 let neverHasSideEffects = 1, isPredicated = 1 in
1122 def LDrih_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1123 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1124 "if ($src1) $dst = memh($src2+#$src3)",
1127 let neverHasSideEffects = 1, isPredicated = 1 in
1128 def LDrih_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1129 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1130 "if (!$src1) $dst = memh($src2+#$src3)",
1133 let neverHasSideEffects = 1, isPredicated = 1 in
1134 def LDrih_cdnPt : LDInst2<(outs IntRegs:$dst),
1135 (ins PredRegs:$src1, MEMri:$addr),
1136 "if ($src1.new) $dst = memh($addr)",
1139 let neverHasSideEffects = 1, isPredicated = 1 in
1140 def LDrih_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1141 (ins PredRegs:$src1, MEMri:$addr),
1142 "if (!$src1.new) $dst = memh($addr)",
1145 let neverHasSideEffects = 1, isPredicated = 1 in
1146 def LDrih_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1147 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1148 "if ($src1.new) $dst = memh($src2+#$src3)",
1151 let neverHasSideEffects = 1, isPredicated = 1 in
1152 def LDrih_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1153 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1154 "if (!$src1.new) $dst = memh($src2+#$src3)",
1157 // Load unsigned byte.
1158 let isPredicable = 1 in
1159 def LDriub : LDInst<(outs IntRegs:$dst),
1161 "$dst = memub($addr)",
1162 [(set (i32 IntRegs:$dst), (i32 (zextloadi8 ADDRriS11_0:$addr)))]>;
1164 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1165 (i32 (LDriub ADDRriS11_0:$addr))>;
1167 let isPredicable = 1, AddedComplexity = 20 in
1168 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
1169 (ins IntRegs:$src1, s11_0Imm:$offset),
1170 "$dst = memub($src1+#$offset)",
1171 [(set (i32 IntRegs:$dst),
1172 (i32 (zextloadi8 (add (i32 IntRegs:$src1),
1173 s11_0ImmPred:$offset))))]>;
1175 let AddedComplexity = 20 in
1176 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1177 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1179 let neverHasSideEffects = 1 in
1180 def LDriub_GP : LDInst2<(outs IntRegs:$dst),
1181 (ins globaladdress:$global, u16Imm:$offset),
1182 "$dst = memub(#$global+$offset)",
1186 // Load unsigned byte conditionally.
1187 let neverHasSideEffects = 1, isPredicated = 1 in
1188 def LDriub_cPt : LDInst2<(outs IntRegs:$dst),
1189 (ins PredRegs:$src1, MEMri:$addr),
1190 "if ($src1) $dst = memub($addr)",
1193 let neverHasSideEffects = 1, isPredicated = 1 in
1194 def LDriub_cNotPt : LDInst2<(outs IntRegs:$dst),
1195 (ins PredRegs:$src1, MEMri:$addr),
1196 "if (!$src1) $dst = memub($addr)",
1199 let neverHasSideEffects = 1, isPredicated = 1 in
1200 def LDriub_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1201 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1202 "if ($src1) $dst = memub($src2+#$src3)",
1205 let neverHasSideEffects = 1, isPredicated = 1 in
1206 def LDriub_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1207 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1208 "if (!$src1) $dst = memub($src2+#$src3)",
1211 let neverHasSideEffects = 1, isPredicated = 1 in
1212 def LDriub_cdnPt : LDInst2<(outs IntRegs:$dst),
1213 (ins PredRegs:$src1, MEMri:$addr),
1214 "if ($src1.new) $dst = memub($addr)",
1217 let neverHasSideEffects = 1, isPredicated = 1 in
1218 def LDriub_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1219 (ins PredRegs:$src1, MEMri:$addr),
1220 "if (!$src1.new) $dst = memub($addr)",
1223 let neverHasSideEffects = 1, isPredicated = 1 in
1224 def LDriub_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1225 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1226 "if ($src1.new) $dst = memub($src2+#$src3)",
1229 let neverHasSideEffects = 1, isPredicated = 1 in
1230 def LDriub_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1231 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1232 "if (!$src1.new) $dst = memub($src2+#$src3)",
1235 // Load unsigned halfword.
1236 let isPredicable = 1 in
1237 def LDriuh : LDInst<(outs IntRegs:$dst),
1239 "$dst = memuh($addr)",
1240 [(set (i32 IntRegs:$dst), (i32 (zextloadi16 ADDRriS11_1:$addr)))]>;
1242 // Indexed load unsigned halfword.
1243 let isPredicable = 1, AddedComplexity = 20 in
1244 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
1245 (ins IntRegs:$src1, s11_1Imm:$offset),
1246 "$dst = memuh($src1+#$offset)",
1247 [(set (i32 IntRegs:$dst),
1248 (i32 (zextloadi16 (add (i32 IntRegs:$src1),
1249 s11_1ImmPred:$offset))))]>;
1251 let neverHasSideEffects = 1 in
1252 def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
1253 (ins globaladdress:$global, u16Imm:$offset),
1254 "$dst = memuh(#$global+$offset)",
1258 // Load unsigned halfword conditionally.
1259 let neverHasSideEffects = 1, isPredicated = 1 in
1260 def LDriuh_cPt : LDInst2<(outs IntRegs:$dst),
1261 (ins PredRegs:$src1, MEMri:$addr),
1262 "if ($src1) $dst = memuh($addr)",
1265 let neverHasSideEffects = 1, isPredicated = 1 in
1266 def LDriuh_cNotPt : LDInst2<(outs IntRegs:$dst),
1267 (ins PredRegs:$src1, MEMri:$addr),
1268 "if (!$src1) $dst = memuh($addr)",
1271 let neverHasSideEffects = 1, isPredicated = 1 in
1272 def LDriuh_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1273 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1274 "if ($src1) $dst = memuh($src2+#$src3)",
1277 let neverHasSideEffects = 1, isPredicated = 1 in
1278 def LDriuh_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1279 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1280 "if (!$src1) $dst = memuh($src2+#$src3)",
1283 let neverHasSideEffects = 1, isPredicated = 1 in
1284 def LDriuh_cdnPt : LDInst2<(outs IntRegs:$dst),
1285 (ins PredRegs:$src1, MEMri:$addr),
1286 "if ($src1.new) $dst = memuh($addr)",
1289 let neverHasSideEffects = 1, isPredicated = 1 in
1290 def LDriuh_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1291 (ins PredRegs:$src1, MEMri:$addr),
1292 "if (!$src1.new) $dst = memuh($addr)",
1295 let neverHasSideEffects = 1, isPredicated = 1 in
1296 def LDriuh_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1297 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1298 "if ($src1.new) $dst = memuh($src2+#$src3)",
1301 let neverHasSideEffects = 1, isPredicated = 1 in
1302 def LDriuh_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1303 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1304 "if (!$src1.new) $dst = memuh($src2+#$src3)",
1309 let isPredicable = 1 in
1310 def LDriw : LDInst<(outs IntRegs:$dst),
1311 (ins MEMri:$addr), "$dst = memw($addr)",
1312 [(set IntRegs:$dst, (i32 (load ADDRriS11_2:$addr)))]>;
1315 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1316 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1318 "Error; should not emit",
1322 let isPredicable = 1, AddedComplexity = 20 in
1323 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
1324 (ins IntRegs:$src1, s11_2Imm:$offset),
1325 "$dst = memw($src1+#$offset)",
1326 [(set IntRegs:$dst, (i32 (load (add IntRegs:$src1,
1327 s11_2ImmPred:$offset))))]>;
1329 let neverHasSideEffects = 1 in
1330 def LDriw_GP : LDInst2<(outs IntRegs:$dst),
1331 (ins globaladdress:$global, u16Imm:$offset),
1332 "$dst = memw(#$global+$offset)",
1336 let neverHasSideEffects = 1 in
1337 def LDw_GP : LDInst2<(outs IntRegs:$dst),
1338 (ins globaladdress:$global),
1339 "$dst = memw(#$global)",
1343 // Load word conditionally.
1345 let neverHasSideEffects = 1, isPredicated = 1 in
1346 def LDriw_cPt : LDInst2<(outs IntRegs:$dst),
1347 (ins PredRegs:$src1, MEMri:$addr),
1348 "if ($src1) $dst = memw($addr)",
1351 let neverHasSideEffects = 1, isPredicated = 1 in
1352 def LDriw_cNotPt : LDInst2<(outs IntRegs:$dst),
1353 (ins PredRegs:$src1, MEMri:$addr),
1354 "if (!$src1) $dst = memw($addr)",
1357 let neverHasSideEffects = 1, isPredicated = 1 in
1358 def LDriw_indexed_cPt : LDInst2<(outs IntRegs:$dst),
1359 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1360 "if ($src1) $dst = memw($src2+#$src3)",
1363 let neverHasSideEffects = 1, isPredicated = 1 in
1364 def LDriw_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
1365 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1366 "if (!$src1) $dst = memw($src2+#$src3)",
1369 let neverHasSideEffects = 1, isPredicated = 1 in
1370 def LDriw_cdnPt : LDInst2<(outs IntRegs:$dst),
1371 (ins PredRegs:$src1, MEMri:$addr),
1372 "if ($src1.new) $dst = memw($addr)",
1375 let neverHasSideEffects = 1, isPredicated = 1 in
1376 def LDriw_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1377 (ins PredRegs:$src1, MEMri:$addr),
1378 "if (!$src1.new) $dst = memw($addr)",
1381 let neverHasSideEffects = 1, isPredicated = 1 in
1382 def LDriw_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
1383 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1384 "if ($src1.new) $dst = memw($src2+#$src3)",
1387 let neverHasSideEffects = 1, isPredicated = 1 in
1388 def LDriw_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
1389 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1390 "if (!$src1.new) $dst = memw($src2+#$src3)",
1393 // Deallocate stack frame.
1394 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1395 def DEALLOCFRAME : LDInst2<(outs), (ins i32imm:$amt1),
1400 // Load and unpack bytes to halfwords.
1401 //===----------------------------------------------------------------------===//
1403 //===----------------------------------------------------------------------===//
1405 //===----------------------------------------------------------------------===//
1407 //===----------------------------------------------------------------------===//
1408 //===----------------------------------------------------------------------===//
1410 //===----------------------------------------------------------------------===//
1412 //===----------------------------------------------------------------------===//
1414 //===----------------------------------------------------------------------===//
1415 //===----------------------------------------------------------------------===//
1417 //===----------------------------------------------------------------------===//
1419 //===----------------------------------------------------------------------===//
1421 //===----------------------------------------------------------------------===//
1422 // Multiply and use lower result.
1424 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1425 "$dst =+ mpyi($src1, #$src2)",
1426 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1427 u8ImmPred:$src2))]>;
1430 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1431 "$dst =- mpyi($src1, #$src2)",
1432 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1433 n8ImmPred:$src2))]>;
1436 // s9 is NOT the same as m9 - but it works.. so far.
1437 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1438 // depending on the value of m9. See Arch Spec.
1439 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1440 "$dst = mpyi($src1, #$src2)",
1441 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1442 s9ImmPred:$src2))]>;
1445 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1446 "$dst = mpyi($src1, $src2)",
1447 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1448 (i32 IntRegs:$src2)))]>;
1451 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1452 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1453 "$dst += mpyi($src2, #$src3)",
1454 [(set (i32 IntRegs:$dst),
1455 (add (mul (i32 IntRegs:$src2), u8ImmPred:$src3),
1456 (i32 IntRegs:$src1)))],
1460 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1461 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1462 "$dst += mpyi($src2, $src3)",
1463 [(set (i32 IntRegs:$dst),
1464 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1465 (i32 IntRegs:$src1)))],
1469 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1470 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1471 "$dst -= mpyi($src2, #$src3)",
1472 [(set (i32 IntRegs:$dst),
1473 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1474 u8ImmPred:$src3)))],
1477 // Multiply and use upper result.
1478 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1479 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1481 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1482 "$dst = mpy($src1, $src2)",
1483 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1484 (i32 IntRegs:$src2)))]>;
1486 // Rd=mpy(Rs,Rt):rnd
1488 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1489 "$dst = mpyu($src1, $src2)",
1490 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1491 (i32 IntRegs:$src2)))]>;
1493 // Multiply and use full result.
1495 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1496 "$dst = mpyu($src1, $src2)",
1497 [(set (i64 DoubleRegs:$dst),
1498 (mul (i64 (anyext (i32 IntRegs:$src1))),
1499 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1502 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1503 "$dst = mpy($src1, $src2)",
1504 [(set (i64 DoubleRegs:$dst),
1505 (mul (i64 (sext (i32 IntRegs:$src1))),
1506 (i64 (sext (i32 IntRegs:$src2)))))]>;
1508 // Multiply and accumulate, use full result.
1509 // Rxx[+-]=mpy(Rs,Rt)
1511 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1512 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1513 "$dst += mpy($src2, $src3)",
1514 [(set (i64 DoubleRegs:$dst),
1515 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1516 (i64 (sext (i32 IntRegs:$src3)))),
1517 (i64 DoubleRegs:$src1)))],
1521 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1522 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1523 "$dst -= mpy($src2, $src3)",
1524 [(set (i64 DoubleRegs:$dst),
1525 (sub (i64 DoubleRegs:$src1),
1526 (mul (i64 (sext (i32 IntRegs:$src2))),
1527 (i64 (sext (i32 IntRegs:$src3))))))],
1530 // Rxx[+-]=mpyu(Rs,Rt)
1532 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1533 IntRegs:$src2, IntRegs:$src3),
1534 "$dst += mpyu($src2, $src3)",
1535 [(set (i64 DoubleRegs:$dst),
1536 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1537 (i64 (anyext (i32 IntRegs:$src3)))),
1538 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1541 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1542 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1543 "$dst += mpyu($src2, $src3)",
1544 [(set (i64 DoubleRegs:$dst),
1545 (sub (i64 DoubleRegs:$src1),
1546 (mul (i64 (anyext (i32 IntRegs:$src2))),
1547 (i64 (anyext (i32 IntRegs:$src3))))))],
1551 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1552 IntRegs:$src2, IntRegs:$src3),
1553 "$dst += add($src2, $src3)",
1554 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1555 (i32 IntRegs:$src3)),
1556 (i32 IntRegs:$src1)))],
1559 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1560 IntRegs:$src2, s8Imm:$src3),
1561 "$dst += add($src2, #$src3)",
1562 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1564 (i32 IntRegs:$src1)))],
1567 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1568 IntRegs:$src2, IntRegs:$src3),
1569 "$dst -= add($src2, $src3)",
1570 [(set (i32 IntRegs:$dst),
1571 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1572 (i32 IntRegs:$src3))))],
1575 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1576 IntRegs:$src2, s8Imm:$src3),
1577 "$dst -= add($src2, #$src3)",
1578 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1579 (add (i32 IntRegs:$src2),
1580 s8ImmPred:$src3)))],
1583 //===----------------------------------------------------------------------===//
1585 //===----------------------------------------------------------------------===//
1587 //===----------------------------------------------------------------------===//
1589 //===----------------------------------------------------------------------===//
1590 //===----------------------------------------------------------------------===//
1592 //===----------------------------------------------------------------------===//
1594 //===----------------------------------------------------------------------===//
1596 //===----------------------------------------------------------------------===//
1597 //===----------------------------------------------------------------------===//
1599 //===----------------------------------------------------------------------===//
1601 //===----------------------------------------------------------------------===//
1603 //===----------------------------------------------------------------------===//
1604 //===----------------------------------------------------------------------===//
1606 //===----------------------------------------------------------------------===//
1608 //===----------------------------------------------------------------------===//
1610 //===----------------------------------------------------------------------===//
1612 /// Assumptions::: ****** DO NOT IGNORE ********
1613 /// 1. Make sure that in post increment store, the zero'th operand is always the
1614 /// post increment operand.
1615 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1618 // Store doubleword.
1619 let isPredicable = 1 in
1620 def STrid : STInst<(outs),
1621 (ins MEMri:$addr, DoubleRegs:$src1),
1622 "memd($addr) = $src1",
1623 [(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr)]>;
1625 // Indexed store double word.
1626 let AddedComplexity = 10, isPredicable = 1 in
1627 def STrid_indexed : STInst<(outs),
1628 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
1629 "memd($src1+#$src2) = $src3",
1630 [(store (i64 DoubleRegs:$src3),
1631 (add (i32 IntRegs:$src1), s11_3ImmPred:$src2))]>;
1633 let neverHasSideEffects = 1 in
1634 def STrid_GP : STInst2<(outs),
1635 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1636 "memd(#$global+$offset) = $src",
1640 let neverHasSideEffects = 1 in
1641 def STd_GP : STInst2<(outs),
1642 (ins globaladdress:$global, DoubleRegs:$src),
1643 "memd(#$global) = $src",
1647 let hasCtrlDep = 1, isPredicable = 1 in
1648 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1649 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1650 "memd($src2++#$offset) = $src1",
1652 (post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
1653 s4_3ImmPred:$offset))],
1656 // Store doubleword conditionally.
1657 // if ([!]Pv) memd(Rs+#u6:3)=Rtt
1658 // if (Pv) memd(Rs+#u6:3)=Rtt
1659 let AddedComplexity = 10, neverHasSideEffects = 1,
1661 def STrid_cPt : STInst2<(outs),
1662 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1663 "if ($src1) memd($addr) = $src2",
1666 // if (!Pv) memd(Rs+#u6:3)=Rtt
1667 let AddedComplexity = 10, neverHasSideEffects = 1,
1669 def STrid_cNotPt : STInst2<(outs),
1670 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1671 "if (!$src1) memd($addr) = $src2",
1674 // if (Pv) memd(Rs+#u6:3)=Rtt
1675 let AddedComplexity = 10, neverHasSideEffects = 1,
1677 def STrid_indexed_cPt : STInst2<(outs),
1678 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1680 "if ($src1) memd($src2+#$src3) = $src4",
1683 // if (!Pv) memd(Rs+#u6:3)=Rtt
1684 let AddedComplexity = 10, neverHasSideEffects = 1,
1686 def STrid_indexed_cNotPt : STInst2<(outs),
1687 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1689 "if (!$src1) memd($src2+#$src3) = $src4",
1692 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1693 // if (Pv) memd(Rx++#s4:3)=Rtt
1694 let AddedComplexity = 10, neverHasSideEffects = 1,
1696 def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
1697 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1699 "if ($src1) memd($src3++#$offset) = $src2",
1703 // if (!Pv) memd(Rx++#s4:3)=Rtt
1704 let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
1706 def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1707 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1709 "if (!$src1) memd($src3++#$offset) = $src2",
1715 // memb(Rs+#s11:0)=Rt
1716 let isPredicable = 1 in
1717 def STrib : STInst<(outs),
1718 (ins MEMri:$addr, IntRegs:$src1),
1719 "memb($addr) = $src1",
1720 [(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr)]>;
1722 let AddedComplexity = 10, isPredicable = 1 in
1723 def STrib_indexed : STInst<(outs),
1724 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1725 "memb($src1+#$src2) = $src3",
1726 [(truncstorei8 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1727 s11_0ImmPred:$src2))]>;
1729 // memb(gp+#u16:0)=Rt
1730 let neverHasSideEffects = 1 in
1731 def STrib_GP : STInst2<(outs),
1732 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1733 "memb(#$global+$offset) = $src",
1738 let neverHasSideEffects = 1 in
1739 def STb_GP : STInst2<(outs),
1740 (ins globaladdress:$global, IntRegs:$src),
1741 "memb(#$global) = $src",
1745 // memb(Rx++#s4:0)=Rt
1746 let hasCtrlDep = 1, isPredicable = 1 in
1747 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1750 "memb($src2++#$offset) = $src1",
1752 (post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1753 s4_0ImmPred:$offset))],
1756 // Store byte conditionally.
1757 // if ([!]Pv) memb(Rs+#u6:0)=Rt
1758 // if (Pv) memb(Rs+#u6:0)=Rt
1759 let neverHasSideEffects = 1, isPredicated = 1 in
1760 def STrib_cPt : STInst2<(outs),
1761 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1762 "if ($src1) memb($addr) = $src2",
1765 // if (!Pv) memb(Rs+#u6:0)=Rt
1766 let neverHasSideEffects = 1, isPredicated = 1 in
1767 def STrib_cNotPt : STInst2<(outs),
1768 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1769 "if (!$src1) memb($addr) = $src2",
1772 // if (Pv) memb(Rs+#u6:0)=Rt
1773 let neverHasSideEffects = 1, isPredicated = 1 in
1774 def STrib_indexed_cPt : STInst2<(outs),
1775 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1776 "if ($src1) memb($src2+#$src3) = $src4",
1779 // if (!Pv) memb(Rs+#u6:0)=Rt
1780 let neverHasSideEffects = 1, isPredicated = 1 in
1781 def STrib_indexed_cNotPt : STInst2<(outs),
1782 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1783 "if (!$src1) memb($src2+#$src3) = $src4",
1786 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1787 // if (Pv) memb(Rx++#s4:0)=Rt
1788 let hasCtrlDep = 1, isPredicated = 1 in
1789 def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
1790 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1791 "if ($src1) memb($src3++#$offset) = $src2",
1794 // if (!Pv) memb(Rx++#s4:0)=Rt
1795 let hasCtrlDep = 1, isPredicated = 1 in
1796 def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1797 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1798 "if (!$src1) memb($src3++#$offset) = $src2",
1803 // memh(Rs+#s11:1)=Rt
1804 let isPredicable = 1 in
1805 def STrih : STInst<(outs),
1806 (ins MEMri:$addr, IntRegs:$src1),
1807 "memh($addr) = $src1",
1808 [(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr)]>;
1811 let AddedComplexity = 10, isPredicable = 1 in
1812 def STrih_indexed : STInst<(outs),
1813 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1814 "memh($src1+#$src2) = $src3",
1815 [(truncstorei16 (i32 IntRegs:$src3), (add (i32 IntRegs:$src1),
1816 s11_1ImmPred:$src2))]>;
1818 let neverHasSideEffects = 1 in
1819 def STrih_GP : STInst2<(outs),
1820 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1821 "memh(#$global+$offset) = $src",
1825 let neverHasSideEffects = 1 in
1826 def STh_GP : STInst2<(outs),
1827 (ins globaladdress:$global, IntRegs:$src),
1828 "memh(#$global) = $src",
1832 // memh(Rx++#s4:1)=Rt.H
1833 // memh(Rx++#s4:1)=Rt
1834 let hasCtrlDep = 1, isPredicable = 1 in
1835 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1836 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1837 "memh($src2++#$offset) = $src1",
1839 (post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1840 s4_1ImmPred:$offset))],
1843 // Store halfword conditionally.
1844 // if ([!]Pv) memh(Rs+#u6:1)=Rt
1845 // if (Pv) memh(Rs+#u6:1)=Rt
1846 let neverHasSideEffects = 1, isPredicated = 1 in
1847 def STrih_cPt : STInst2<(outs),
1848 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1849 "if ($src1) memh($addr) = $src2",
1852 // if (!Pv) memh(Rs+#u6:1)=Rt
1853 let neverHasSideEffects = 1, isPredicated = 1 in
1854 def STrih_cNotPt : STInst2<(outs),
1855 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1856 "if (!$src1) memh($addr) = $src2",
1859 // if (Pv) memh(Rs+#u6:1)=Rt
1860 let neverHasSideEffects = 1, isPredicated = 1 in
1861 def STrih_indexed_cPt : STInst2<(outs),
1862 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1863 "if ($src1) memh($src2+#$src3) = $src4",
1866 // if (!Pv) memh(Rs+#u6:1)=Rt
1867 let neverHasSideEffects = 1, isPredicated = 1 in
1868 def STrih_indexed_cNotPt : STInst2<(outs),
1869 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1870 "if (!$src1) memh($src2+#$src3) = $src4",
1873 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1874 // if (Pv) memh(Rx++#s4:1)=Rt
1875 let hasCtrlDep = 1, isPredicated = 1 in
1876 def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
1877 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1878 "if ($src1) memh($src3++#$offset) = $src2",
1881 // if (!Pv) memh(Rx++#s4:1)=Rt
1882 let hasCtrlDep = 1, isPredicated = 1 in
1883 def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1884 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1885 "if (!$src1) memh($src3++#$offset) = $src2",
1891 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1892 def STriw_pred : STInst2<(outs),
1893 (ins MEMri:$addr, PredRegs:$src1),
1894 "Error; should not emit",
1897 // memw(Rs+#s11:2)=Rt
1898 let isPredicable = 1 in
1899 def STriw : STInst<(outs),
1900 (ins MEMri:$addr, IntRegs:$src1),
1901 "memw($addr) = $src1",
1902 [(store (i32 IntRegs:$src1), ADDRriS11_2:$addr)]>;
1904 let AddedComplexity = 10, isPredicable = 1 in
1905 def STriw_indexed : STInst<(outs),
1906 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
1907 "memw($src1+#$src2) = $src3",
1908 [(store (i32 IntRegs:$src3),
1909 (add (i32 IntRegs:$src1), s11_2ImmPred:$src2))]>;
1911 let neverHasSideEffects = 1 in
1912 def STriw_GP : STInst2<(outs),
1913 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1914 "memw(#$global+$offset) = $src",
1918 let neverHasSideEffects = 1 in
1919 def STw_GP : STInst2<(outs),
1920 (ins globaladdress:$global, IntRegs:$src),
1921 "memw(#$global) = $src",
1925 let hasCtrlDep = 1, isPredicable = 1 in
1926 def POST_STwri : STInstPI<(outs IntRegs:$dst),
1927 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1928 "memw($src2++#$offset) = $src1",
1930 (post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
1931 s4_2ImmPred:$offset))],
1934 // Store word conditionally.
1935 // if ([!]Pv) memw(Rs+#u6:2)=Rt
1936 // if (Pv) memw(Rs+#u6:2)=Rt
1937 let neverHasSideEffects = 1, isPredicated = 1 in
1938 def STriw_cPt : STInst2<(outs),
1939 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1940 "if ($src1) memw($addr) = $src2",
1943 // if (!Pv) memw(Rs+#u6:2)=Rt
1944 let neverHasSideEffects = 1, isPredicated = 1 in
1945 def STriw_cNotPt : STInst2<(outs),
1946 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1947 "if (!$src1) memw($addr) = $src2",
1950 // if (Pv) memw(Rs+#u6:2)=Rt
1951 let neverHasSideEffects = 1, isPredicated = 1 in
1952 def STriw_indexed_cPt : STInst2<(outs),
1953 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
1954 "if ($src1) memw($src2+#$src3) = $src4",
1957 // if (!Pv) memw(Rs+#u6:2)=Rt
1958 let neverHasSideEffects = 1, isPredicated = 1 in
1959 def STriw_indexed_cNotPt : STInst2<(outs),
1960 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
1961 "if (!$src1) memw($src2+#$src3) = $src4",
1964 // if ([!]Pv) memw(Rx++#s4:2)=Rt
1965 // if (Pv) memw(Rx++#s4:2)=Rt
1966 let hasCtrlDep = 1, isPredicated = 1 in
1967 def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
1968 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1969 "if ($src1) memw($src3++#$offset) = $src2",
1972 // if (!Pv) memw(Rx++#s4:2)=Rt
1973 let hasCtrlDep = 1, isPredicated = 1 in
1974 def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
1975 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1976 "if (!$src1) memw($src3++#$offset) = $src2",
1981 // Allocate stack frame.
1982 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1983 def ALLOCFRAME : STInst2<(outs),
1985 "allocframe(#$amt)",
1988 //===----------------------------------------------------------------------===//
1990 //===----------------------------------------------------------------------===//
1992 //===----------------------------------------------------------------------===//
1994 //===----------------------------------------------------------------------===//
1996 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1997 "$dst = not($src1)",
1998 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
2001 // Sign extend word to doubleword.
2002 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2003 "$dst = sxtw($src1)",
2004 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
2005 //===----------------------------------------------------------------------===//
2007 //===----------------------------------------------------------------------===//
2009 //===----------------------------------------------------------------------===//
2011 //===----------------------------------------------------------------------===//
2013 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2014 "$dst = clrbit($src1, #$src2)",
2015 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
2017 (shl 1, u5ImmPred:$src2))))]>;
2019 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2020 "$dst = clrbit($src1, #$src2)",
2023 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
2024 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
2025 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
2028 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2029 "$dst = setbit($src1, #$src2)",
2030 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
2031 (shl 1, u5ImmPred:$src2)))]>;
2033 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
2034 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2035 "$dst = setbit($src1, #$src2)",
2038 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
2039 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
2042 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2043 "$dst = setbit($src1, #$src2)",
2044 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
2045 (shl 1, u5ImmPred:$src2)))]>;
2047 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
2048 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2049 "$dst = togglebit($src1, #$src2)",
2052 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
2053 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
2055 // Predicate transfer.
2056 let neverHasSideEffects = 1 in
2057 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2058 "$dst = $src1 /* Should almost never emit this. */",
2061 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2062 "$dst = $src1 /* Should almost never emit this. */",
2063 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
2064 //===----------------------------------------------------------------------===//
2066 //===----------------------------------------------------------------------===//
2068 //===----------------------------------------------------------------------===//
2070 //===----------------------------------------------------------------------===//
2071 // Shift by immediate.
2072 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2073 "$dst = asr($src1, #$src2)",
2074 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2075 u5ImmPred:$src2))]>;
2077 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2078 "$dst = asr($src1, #$src2)",
2079 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2080 u6ImmPred:$src2))]>;
2082 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2083 "$dst = asl($src1, #$src2)",
2084 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2085 u5ImmPred:$src2))]>;
2087 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2088 "$dst = asl($src1, #$src2)",
2089 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2090 u6ImmPred:$src2))]>;
2092 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2093 "$dst = lsr($src1, #$src2)",
2094 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2095 u5ImmPred:$src2))]>;
2097 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2098 "$dst = lsr($src1, #$src2)",
2099 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2100 u6ImmPred:$src2))]>;
2102 // Shift by immediate and add.
2103 let AddedComplexity = 100 in
2104 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2106 "$dst = addasl($src1, $src2, #$src3)",
2107 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
2108 (shl (i32 IntRegs:$src2),
2109 u3ImmPred:$src3)))]>;
2111 // Shift by register.
2112 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2113 "$dst = asl($src1, $src2)",
2114 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2115 (i32 IntRegs:$src2)))]>;
2117 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2118 "$dst = asr($src1, $src2)",
2119 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2120 (i32 IntRegs:$src2)))]>;
2122 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2123 "$dst = lsl($src1, $src2)",
2124 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2125 (i32 IntRegs:$src2)))]>;
2127 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2128 "$dst = lsr($src1, $src2)",
2129 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2130 (i32 IntRegs:$src2)))]>;
2132 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2133 "$dst = asl($src1, $src2)",
2134 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2135 (i32 IntRegs:$src2)))]>;
2137 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2138 "$dst = lsl($src1, $src2)",
2139 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2140 (i32 IntRegs:$src2)))]>;
2142 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2144 "$dst = asr($src1, $src2)",
2145 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2146 (i32 IntRegs:$src2)))]>;
2148 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2150 "$dst = lsr($src1, $src2)",
2151 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2152 (i32 IntRegs:$src2)))]>;
2154 //===----------------------------------------------------------------------===//
2156 //===----------------------------------------------------------------------===//
2158 //===----------------------------------------------------------------------===//
2160 //===----------------------------------------------------------------------===//
2161 //===----------------------------------------------------------------------===//
2163 //===----------------------------------------------------------------------===//
2165 //===----------------------------------------------------------------------===//
2167 //===----------------------------------------------------------------------===//
2168 //===----------------------------------------------------------------------===//
2170 //===----------------------------------------------------------------------===//
2172 //===----------------------------------------------------------------------===//
2174 //===----------------------------------------------------------------------===//
2176 //===----------------------------------------------------------------------===//
2178 //===----------------------------------------------------------------------===//
2179 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2180 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2183 let hasSideEffects = 1, isHexagonSolo = 1 in
2184 def BARRIER : SYSInst<(outs), (ins),
2186 [(HexagonBARRIER)]>;
2188 //===----------------------------------------------------------------------===//
2190 //===----------------------------------------------------------------------===//
2192 // TFRI64 - assembly mapped.
2193 let isReMaterializable = 1 in
2194 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2196 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2198 // Pseudo instruction to encode a set of conditional transfers.
2199 // This instruction is used instead of a mux and trades-off codesize
2200 // for performance. We conduct this transformation optimistically in
2201 // the hope that these instructions get promoted to dot-new transfers.
2202 let AddedComplexity = 100, isPredicated = 1 in
2203 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2206 "Error; should not emit",
2207 [(set (i32 IntRegs:$dst),
2208 (i32 (select (i1 PredRegs:$src1),
2209 (i32 IntRegs:$src2),
2210 (i32 IntRegs:$src3))))]>;
2211 let AddedComplexity = 100, isPredicated = 1 in
2212 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2213 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2214 "Error; should not emit",
2215 [(set (i32 IntRegs:$dst),
2216 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2217 s12ImmPred:$src3)))]>;
2219 let AddedComplexity = 100, isPredicated = 1 in
2220 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2221 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2222 "Error; should not emit",
2223 [(set (i32 IntRegs:$dst),
2224 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2225 (i32 IntRegs:$src3))))]>;
2227 let AddedComplexity = 100, isPredicated = 1 in
2228 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2229 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2230 "Error; should not emit",
2231 [(set (i32 IntRegs:$dst),
2232 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2233 s12ImmPred:$src3)))]>;
2235 // Generate frameindex addresses.
2236 let isReMaterializable = 1 in
2237 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2238 "$dst = add($src1)",
2239 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2244 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2245 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2246 "loop0($offset, #$src2)",
2250 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2251 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2252 "loop0($offset, $src2)",
2256 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2257 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2258 def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
2263 // Support for generating global address.
2264 // Taken from X86InstrInfo.td.
2265 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2269 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2270 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2272 // HI/LO Instructions
2273 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2274 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2275 "$dst.l = #LO($global)",
2278 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2279 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2280 "$dst.h = #HI($global)",
2283 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2284 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2285 "$dst.l = #LO($imm_value)",
2289 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2290 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2291 "$dst.h = #HI($imm_value)",
2294 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2295 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2296 "$dst.l = #LO($jt)",
2299 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2300 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2301 "$dst.h = #HI($jt)",
2305 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
2306 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2307 "$dst.l = #LO($label)",
2310 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
2311 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2312 "$dst.h = #HI($label)",
2315 // This pattern is incorrect. When we add small data, we should change
2316 // this pattern to use memw(#foo).
2317 // This is for sdata.
2318 let isMoveImm = 1 in
2319 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2320 "$dst = CONST32(#$global)",
2321 [(set (i32 IntRegs:$dst),
2322 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2324 // This is for non-sdata.
2325 let isReMaterializable = 1, isMoveImm = 1 in
2326 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2327 "$dst = CONST32(#$global)",
2328 [(set (i32 IntRegs:$dst),
2329 (HexagonCONST32 tglobaladdr:$global))]>;
2331 let isReMaterializable = 1, isMoveImm = 1 in
2332 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2333 "$dst = CONST32(#$jt)",
2334 [(set (i32 IntRegs:$dst),
2335 (HexagonCONST32 tjumptable:$jt))]>;
2337 let isReMaterializable = 1, isMoveImm = 1 in
2338 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2339 "$dst = CONST32(#$global)",
2340 [(set (i32 IntRegs:$dst),
2341 (HexagonCONST32_GP tglobaladdr:$global))]>;
2343 let isReMaterializable = 1, isMoveImm = 1 in
2344 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2345 "$dst = CONST32(#$global)",
2346 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2348 let isReMaterializable = 1, isMoveImm = 1 in
2349 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2350 "$dst = CONST32($label)",
2351 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2353 let isReMaterializable = 1, isMoveImm = 1 in
2354 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2355 "$dst = CONST64(#$global)",
2356 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2358 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2359 "$dst = xor($dst, $dst)",
2360 [(set (i1 PredRegs:$dst), 0)]>;
2362 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2363 "$dst = mpy($src1, $src2)",
2364 [(set (i32 IntRegs:$dst),
2365 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2366 (i64 (sext (i32 IntRegs:$src2))))),
2369 // Pseudo instructions.
2370 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2372 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2373 SDTCisVT<1, i32> ]>;
2375 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2376 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2378 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2379 [SDNPHasChain, SDNPOutGlue]>;
2381 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2383 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2384 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2386 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2387 // Optional Flag and Variable Arguments.
2388 // Its 1 Operand has pointer type.
2389 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2390 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2392 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2393 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2394 "Should never be emitted",
2395 [(callseq_start timm:$amt)]>;
2398 let Defs = [R29, R30, R31], Uses = [R29] in {
2399 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2400 "Should never be emitted",
2401 [(callseq_end timm:$amt1, timm:$amt2)]>;
2404 let isCall = 1, neverHasSideEffects = 1,
2405 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2406 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2407 def CALL : JInst<(outs), (ins calltarget:$dst),
2411 // Call subroutine from register.
2412 let isCall = 1, neverHasSideEffects = 1,
2413 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2414 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2415 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2421 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2422 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
2423 "jump $dst // TAILCALL", []>;
2425 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2426 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
2427 "jump $dst // TAILCALL", []>;
2430 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2431 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2432 "jumpr $dst // TAILCALL", []>;
2434 // Map call instruction.
2435 def : Pat<(call (i32 IntRegs:$dst)),
2436 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2437 def : Pat<(call tglobaladdr:$dst),
2438 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2439 def : Pat<(call texternalsym:$dst),
2440 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2442 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2443 (TCRETURNtg tglobaladdr:$dst)>;
2444 def : Pat<(HexagonTCRet texternalsym:$dst),
2445 (TCRETURNtext texternalsym:$dst)>;
2446 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2447 (TCRETURNR (i32 IntRegs:$dst))>;
2449 // Atomic load and store support
2450 // 8 bit atomic load
2451 def : Pat<(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
2452 (i32 (LDub_GP tglobaladdr:$global))>,
2455 def : Pat<(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2456 u16ImmPred:$offset)),
2457 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2460 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2461 (i32 (LDriub ADDRriS11_0:$src1))>;
2463 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2464 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2468 // 16 bit atomic load
2469 def : Pat<(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
2470 (i32 (LDuh_GP tglobaladdr:$global))>,
2473 def : Pat<(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2474 u16ImmPred:$offset)),
2475 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2478 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2479 (i32 (LDriuh ADDRriS11_1:$src1))>;
2481 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2482 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2486 // 32 bit atomic load
2487 def : Pat<(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
2488 (i32 (LDw_GP tglobaladdr:$global))>,
2491 def : Pat<(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2492 u16ImmPred:$offset)),
2493 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2496 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2497 (i32 (LDriw ADDRriS11_2:$src1))>;
2499 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2500 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2503 // 64 bit atomic load
2504 def : Pat<(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
2505 (i64 (LDd_GP tglobaladdr:$global))>,
2508 def : Pat<(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2509 u16ImmPred:$offset)),
2510 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2513 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2514 (i64 (LDrid ADDRriS11_3:$src1))>;
2516 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2517 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2520 // 64 bit atomic store
2521 def : Pat<(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2522 (i64 DoubleRegs:$src1)),
2523 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2526 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2527 u16ImmPred:$offset),
2528 (i64 DoubleRegs:$src1)),
2529 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2530 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2532 // 8 bit atomic store
2533 def : Pat<(atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2534 (i32 IntRegs:$src1)),
2535 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2538 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2539 u16ImmPred:$offset),
2540 (i32 IntRegs:$src1)),
2541 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset,
2542 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2544 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2545 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2547 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2548 (i32 IntRegs:$src1)),
2549 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2550 (i32 IntRegs:$src1))>;
2553 // 16 bit atomic store
2554 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2555 (i32 IntRegs:$src1)),
2556 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2559 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2560 u16ImmPred:$offset),
2561 (i32 IntRegs:$src1)),
2562 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset,
2563 (i32 IntRegs:$src1))>, Requires<[NoV4T]>;
2565 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2566 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2568 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2569 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2570 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2571 (i32 IntRegs:$src1))>;
2574 // 32 bit atomic store
2575 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2576 (i32 IntRegs:$src1)),
2577 (STw_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2580 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2581 u16ImmPred:$offset),
2582 (i32 IntRegs:$src1)),
2583 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
2584 (i32 IntRegs:$src1))>,
2587 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2588 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2590 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2591 (i32 IntRegs:$src1)),
2592 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2593 (i32 IntRegs:$src1))>;
2598 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2599 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2601 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2602 (i64 DoubleRegs:$src1)),
2603 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2604 (i64 DoubleRegs:$src1))>;
2606 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2607 def : Pat <(and (i32 IntRegs:$src1), 65535),
2608 (ZXTH (i32 IntRegs:$src1))>;
2610 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2611 def : Pat <(and (i32 IntRegs:$src1), 255),
2612 (ZXTB (i32 IntRegs:$src1))>;
2614 // Map Add(p1, true) to p1 = not(p1).
2615 // Add(p1, false) should never be produced,
2616 // if it does, it got to be mapped to NOOP.
2617 def : Pat <(add (i1 PredRegs:$src1), -1),
2618 (NOT_p (i1 PredRegs:$src1))>;
2620 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2621 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2622 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2623 (i32 IntRegs:$src3),
2624 (i32 IntRegs:$src4)),
2625 (i32 (TFR_condset_rr (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2626 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2627 Requires<[HasV2TOnly]>;
2629 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2630 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2631 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2634 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2635 // => r0 = TFR_condset_ri(p0, r1, #i)
2636 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2637 (i32 IntRegs:$src3)),
2638 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2639 s12ImmPred:$src2))>;
2641 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2642 // => r0 = TFR_condset_ir(p0, #i, r1)
2643 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, s12ImmPred:$src3),
2644 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2645 (i32 IntRegs:$src2)))>;
2647 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2648 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2649 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2651 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2652 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2653 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2655 // Map from store(globaladdress + x) -> memd(#foo + x).
2656 let AddedComplexity = 100 in
2657 def : Pat <(store (i64 DoubleRegs:$src1),
2658 (add (HexagonCONST32_GP tglobaladdr:$global),
2659 u16ImmPred:$offset)),
2660 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset,
2661 (i64 DoubleRegs:$src1))>, Requires<[NoV4T]>;
2663 // Map from store(globaladdress) -> memd(#foo).
2664 let AddedComplexity = 100 in
2665 def : Pat <(store (i64 DoubleRegs:$src1),
2666 (HexagonCONST32_GP tglobaladdr:$global)),
2667 (STd_GP tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2670 // Map from store(globaladdress + x) -> memw(#foo + x).
2671 let AddedComplexity = 100 in
2672 def : Pat <(store (i32 IntRegs:$src1),
2673 (add (HexagonCONST32_GP tglobaladdr:$global),
2674 u16ImmPred:$offset)),
2675 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2678 // Map from store(globaladdress) -> memw(#foo + 0).
2679 let AddedComplexity = 100 in
2680 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2681 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>;
2683 // Map from store(globaladdress) -> memw(#foo).
2684 let AddedComplexity = 100 in
2685 def : Pat <(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2686 (STriw_GP tglobaladdr:$global, 0, (i32 IntRegs:$src1))>,
2689 // Map from store(globaladdress + x) -> memh(#foo + x).
2690 let AddedComplexity = 100 in
2691 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2692 (add (HexagonCONST32_GP tglobaladdr:$global),
2693 u16ImmPred:$offset)),
2694 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2697 // Map from store(globaladdress) -> memh(#foo).
2698 let AddedComplexity = 100 in
2699 def : Pat <(truncstorei16 (i32 IntRegs:$src1),
2700 (HexagonCONST32_GP tglobaladdr:$global)),
2701 (STh_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2704 // Map from store(globaladdress + x) -> memb(#foo + x).
2705 let AddedComplexity = 100 in
2706 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2707 (add (HexagonCONST32_GP tglobaladdr:$global),
2708 u16ImmPred:$offset)),
2709 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
2712 // Map from store(globaladdress) -> memb(#foo).
2713 let AddedComplexity = 100 in
2714 def : Pat <(truncstorei8 (i32 IntRegs:$src1),
2715 (HexagonCONST32_GP tglobaladdr:$global)),
2716 (STb_GP tglobaladdr:$global, (i32 IntRegs:$src1))>,
2719 // Map from load(globaladdress + x) -> memw(#foo + x).
2720 let AddedComplexity = 100 in
2721 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2722 u16ImmPred:$offset))),
2723 (i32 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2726 // Map from load(globaladdress) -> memw(#foo).
2727 let AddedComplexity = 100 in
2728 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
2729 (i32 (LDw_GP tglobaladdr:$global))>,
2732 // Map from load(globaladdress + x) -> memd(#foo + x).
2733 let AddedComplexity = 100 in
2734 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2735 u16ImmPred:$offset))),
2736 (i64 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2739 // Map from load(globaladdress) -> memw(#foo + 0).
2740 let AddedComplexity = 100 in
2741 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2742 (i64 (LDd_GP tglobaladdr:$global))>,
2745 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd.
2746 let AddedComplexity = 100 in
2747 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2748 (i1 (TFR_PdRs (i32 (LDb_GP tglobaladdr:$global))))>,
2751 // Map from load(globaladdress + x) -> memh(#foo + x).
2752 let AddedComplexity = 100 in
2753 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2754 u16ImmPred:$offset))),
2755 (i32 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2758 // Map from load(globaladdress + x) -> memh(#foo + x).
2759 let AddedComplexity = 100 in
2760 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2761 (i32 (LDrih_GP tglobaladdr:$global, 0))>,
2764 // Map from load(globaladdress + x) -> memuh(#foo + x).
2765 let AddedComplexity = 100 in
2766 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2767 u16ImmPred:$offset))),
2768 (i32 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2771 // Map from load(globaladdress) -> memuh(#foo).
2772 let AddedComplexity = 100 in
2773 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2774 (i32 (LDriuh_GP tglobaladdr:$global, 0))>,
2777 // Map from load(globaladdress) -> memh(#foo).
2778 let AddedComplexity = 100 in
2779 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2780 (i32 (LDh_GP tglobaladdr:$global))>,
2783 // Map from load(globaladdress) -> memuh(#foo).
2784 let AddedComplexity = 100 in
2785 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
2786 (i32 (LDuh_GP tglobaladdr:$global))>,
2789 // Map from load(globaladdress + x) -> memb(#foo + x).
2790 let AddedComplexity = 100 in
2791 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2792 u16ImmPred:$offset))),
2793 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2796 // Map from load(globaladdress + x) -> memb(#foo + x).
2797 let AddedComplexity = 100 in
2798 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2799 u16ImmPred:$offset))),
2800 (i32 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2803 // Map from load(globaladdress + x) -> memub(#foo + x).
2804 let AddedComplexity = 100 in
2805 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2806 u16ImmPred:$offset))),
2807 (i32 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset))>,
2810 // Map from load(globaladdress) -> memb(#foo).
2811 let AddedComplexity = 100 in
2812 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2813 (i32 (LDb_GP tglobaladdr:$global))>,
2816 // Map from load(globaladdress) -> memb(#foo).
2817 let AddedComplexity = 100 in
2818 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2819 (i32 (LDb_GP tglobaladdr:$global))>,
2822 // Map from load(globaladdress) -> memub(#foo).
2823 let AddedComplexity = 100 in
2824 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
2825 (i32 (LDub_GP tglobaladdr:$global))>,
2828 // When the Interprocedural Global Variable optimizer realizes that a
2829 // certain global variable takes only two constant values, it shrinks the
2830 // global to a boolean. Catch those loads here in the following 3 patterns.
2831 let AddedComplexity = 100 in
2832 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2833 (i32 (LDb_GP tglobaladdr:$global))>,
2836 let AddedComplexity = 100 in
2837 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2838 (i32 (LDb_GP tglobaladdr:$global))>,
2841 let AddedComplexity = 100 in
2842 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
2843 (i32 (LDub_GP tglobaladdr:$global))>,
2846 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2847 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2848 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2850 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2851 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2852 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2854 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2855 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2856 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2857 subreg_loreg))))))>;
2859 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2860 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2861 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2862 subreg_loreg))))))>;
2864 // We want to prevent emitting pnot's as much as possible.
2865 // Map brcond with an unsupported setcc to a JMP_cNot.
2866 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2868 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2871 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2873 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2875 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2876 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2878 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2879 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2881 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2883 (JMP_cNot (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2), bb:$offset)>;
2885 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2887 (JMP_c (CMPLTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>;
2889 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2891 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2894 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2896 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2899 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2901 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2904 // Map from a 64-bit select to an emulated 64-bit mux.
2905 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2906 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2907 (i64 DoubleRegs:$src3)),
2908 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2909 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2911 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2913 (i32 (MUX_rr (i1 PredRegs:$src1),
2914 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2916 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2917 subreg_loreg))))))>;
2919 // Map from a 1-bit select to logical ops.
2920 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2921 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2922 (i1 PredRegs:$src3)),
2923 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2924 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2926 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2927 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2928 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2930 // Map for truncating from 64 immediates to 32 bit immediates.
2931 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2932 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2934 // Map for truncating from i64 immediates to i1 bit immediates.
2935 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2936 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2939 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2940 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2941 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2944 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2945 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2946 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2948 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2949 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2950 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2953 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2954 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2955 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2958 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2959 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2960 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2962 let AddedComplexity = 100 in
2963 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2965 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2966 (STb_GP tglobaladdr:$global, (TFRI 1))>,
2969 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2970 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2971 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2973 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2974 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2975 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2977 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2978 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2979 // Better way to do this?
2980 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2981 (i64 (SXTW (i32 IntRegs:$src1)))>;
2983 // Map cmple -> cmpgt.
2984 // rs <= rt -> !(rs > rt).
2985 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ImmPred:$src2)),
2986 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ImmPred:$src2)))>;
2988 // rs <= rt -> !(rs > rt).
2989 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2990 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2992 // Rss <= Rtt -> !(Rss > Rtt).
2993 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2994 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2996 // Map cmpne -> cmpeq.
2997 // Hexagon_TODO: We should improve on this.
2998 // rs != rt -> !(rs == rt).
2999 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3000 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2))))>;
3002 // Map cmpne(Rs) -> !cmpeqe(Rs).
3003 // rs != rt -> !(rs == rt).
3004 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3005 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
3007 // Convert setne back to xor for hexagon since we compute w/ pred registers.
3008 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
3009 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
3011 // Map cmpne(Rss) -> !cmpew(Rss).
3012 // rs != rt -> !(rs == rt).
3013 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3014 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
3015 (i64 DoubleRegs:$src2)))))>;
3017 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
3018 // rs >= rt -> !(rt > rs).
3019 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3020 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
3022 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ImmPred:$src2)),
3023 (i1 (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2))>;
3025 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
3026 // rss >= rtt -> !(rtt > rss).
3027 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3028 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
3029 (i64 DoubleRegs:$src1)))))>;
3031 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
3032 // rs < rt -> !(rs >= rt).
3033 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3034 (i1 (NOT_p (CMPGEri (i32 IntRegs:$src1), s8ImmPred:$src2)))>;
3036 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
3037 // rs < rt -> rt > rs.
3038 // We can let assembler map it, or we can do in the compiler itself.
3039 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3040 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3042 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
3043 // rss < rtt -> (rtt > rss).
3044 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3045 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3047 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
3048 // rs < rt -> rt > rs.
3049 // We can let assembler map it, or we can do in the compiler itself.
3050 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3051 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3053 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
3054 // rs < rt -> rt > rs.
3055 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3056 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3058 // Generate cmpgeu(Rs, #u8)
3059 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ImmPred:$src2)),
3060 (i1 (CMPGEUri (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3062 // Generate cmpgtu(Rs, #u9)
3063 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)),
3064 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ImmPred:$src2))>;
3066 // Map from Rs >= Rt -> !(Rt > Rs).
3067 // rs >= rt -> !(rt > rs).
3068 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3069 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
3071 // Map from Rs >= Rt -> !(Rt > Rs).
3072 // rs >= rt -> !(rt > rs).
3073 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3074 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
3076 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
3077 // Map from (Rs <= Rt) -> !(Rs > Rt).
3078 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3079 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3081 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
3082 // Map from (Rs <= Rt) -> !(Rs > Rt).
3083 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3084 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3088 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
3089 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
3092 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
3093 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
3095 // Convert sign-extended load back to load and sign extend.
3097 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
3098 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3100 // Convert any-extended load back to load and sign extend.
3102 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
3103 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3105 // Convert sign-extended load back to load and sign extend.
3107 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
3108 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
3110 // Convert sign-extended load back to load and sign extend.
3112 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
3113 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
3118 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3119 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3122 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
3123 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>;
3126 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
3127 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3130 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
3131 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
3134 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
3135 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
3138 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
3139 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3141 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
3142 (i32 (LDriw ADDRriS11_0:$src1))>;
3144 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3145 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3146 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3148 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3149 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
3150 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
3152 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
3153 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
3154 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
3157 // Any extended 64-bit load.
3158 // anyext i32 -> i64
3159 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
3160 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
3162 // anyext i16 -> i64.
3163 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
3164 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
3166 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
3167 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
3168 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>;
3170 // Multiply 64-bit unsigned and use upper result.
3171 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3186 (COMBINE_rr (TFRI 0),
3192 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3194 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3195 subreg_loreg)))), 32)),
3197 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3198 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3199 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3200 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3201 32)), subreg_loreg)))),
3202 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3203 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3205 // Multiply 64-bit signed and use upper result.
3206 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3210 (COMBINE_rr (TFRI 0),
3220 (COMBINE_rr (TFRI 0),
3226 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3228 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3229 subreg_loreg)))), 32)),
3231 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3232 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3233 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3234 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3235 32)), subreg_loreg)))),
3236 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3237 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3239 // Hexagon specific ISD nodes.
3240 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3241 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
3242 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
3243 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3244 SDTHexagonADJDYNALLOC>;
3245 // Needed to tag these instructions for stack layout.
3246 let usesCustomInserter = 1 in
3247 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3249 "$dst = add($src1, #$src2)",
3250 [(set (i32 IntRegs:$dst),
3251 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3252 s16ImmPred:$src2))]>;
3254 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3255 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3256 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3258 [(set (i32 IntRegs:$dst),
3259 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3261 let AddedComplexity = 100 in
3262 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3263 (COPY (i32 IntRegs:$src1))>;
3265 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3266 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3268 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3269 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3271 [(HexagonBR_JT (i32 IntRegs:$src))]>;
3273 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3275 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3276 (i32 (CONST32_set_jt tjumptable:$dst))>;
3280 // Multi-class for logical operators :
3281 // Shift by immediate/register and accumulate/logical
3282 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3283 def _ri : SInst_acc<(outs IntRegs:$dst),
3284 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3285 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3286 [(set (i32 IntRegs:$dst),
3287 (OpNode2 (i32 IntRegs:$src1),
3288 (OpNode1 (i32 IntRegs:$src2),
3289 u5ImmPred:$src3)))],
3292 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3293 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3294 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3295 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3296 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3300 // Multi-class for logical operators :
3301 // Shift by register and accumulate/logical (32/64 bits)
3302 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3303 def _rr : SInst_acc<(outs IntRegs:$dst),
3304 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3305 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3306 [(set (i32 IntRegs:$dst),
3307 (OpNode2 (i32 IntRegs:$src1),
3308 (OpNode1 (i32 IntRegs:$src2),
3309 (i32 IntRegs:$src3))))],
3312 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3313 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3314 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3315 [(set (i64 DoubleRegs:$dst),
3316 (OpNode2 (i64 DoubleRegs:$src1),
3317 (OpNode1 (i64 DoubleRegs:$src2),
3318 (i32 IntRegs:$src3))))],
3323 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3324 let AddedComplexity = 100 in
3325 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3326 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3327 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3328 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3331 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3332 let AddedComplexity = 100 in
3333 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3334 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3335 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3336 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3339 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3340 let AddedComplexity = 100 in
3341 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3344 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3345 xtype_xor_imm<"asl", shl>;
3347 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3348 xtype_xor_imm<"lsr", srl>;
3350 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3351 defm LSL : basic_xtype_reg<"lsl", shl>;
3353 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3354 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3355 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3357 //===----------------------------------------------------------------------===//
3358 // V3 Instructions +
3359 //===----------------------------------------------------------------------===//
3361 include "HexagonInstrInfoV3.td"
3363 //===----------------------------------------------------------------------===//
3364 // V3 Instructions -
3365 //===----------------------------------------------------------------------===//
3367 //===----------------------------------------------------------------------===//
3368 // V4 Instructions +
3369 //===----------------------------------------------------------------------===//
3371 include "HexagonInstrInfoV4.td"
3373 //===----------------------------------------------------------------------===//
3374 // V4 Instructions -
3375 //===----------------------------------------------------------------------===//
3377 //===----------------------------------------------------------------------===//
3378 // V5 Instructions +
3379 //===----------------------------------------------------------------------===//
3381 include "HexagonInstrInfoV5.td"
3383 //===----------------------------------------------------------------------===//
3384 // V5 Instructions -
3385 //===----------------------------------------------------------------------===//
3387 //===----------------------------------------------------------------------===//
3388 // Generate mapping table to relate non-predicate instructions with their
3389 // predicated formats - true and false.
3392 def getPredOpcode : InstrMapping {
3393 let FilterClass = "PredRel";
3394 // Instructions with the same BaseOpcode and isNVStore values form a row.
3395 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
3396 // Instructions with the same predicate sense form a column.
3397 let ColFields = ["PredSense"];
3398 // The key column is the unpredicated instructions.
3400 // Value columns are PredSense=true and PredSense=false
3401 let ValueCols = [["true"], ["false"]];
3404 //===----------------------------------------------------------------------===//
3405 // Generate mapping table to relate predicated instructions with their .new
3408 def getPredNewOpcode : InstrMapping {
3409 let FilterClass = "PredNewRel";
3410 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
3411 let ColFields = ["PNewValue"];
3413 let ValueCols = [["new"]];