1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonImmediates.td"
17 //===----------------------------------------------------------------------===//
18 // Hexagon Instruction Predicate Definitions.
19 //===----------------------------------------------------------------------===//
20 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
21 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
22 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
23 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
24 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
25 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
26 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
27 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
28 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
31 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
32 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
33 def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
34 def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
35 def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
36 def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
37 def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
38 def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
39 def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
42 def MEMrr : Operand<i32> {
43 let PrintMethod = "printMEMrrOperand";
44 let MIOperandInfo = (ops IntRegs, IntRegs);
48 def MEMri : Operand<i32> {
49 let PrintMethod = "printMEMriOperand";
50 let MIOperandInfo = (ops IntRegs, IntRegs);
53 def MEMri_s11_2 : Operand<i32>,
54 ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
55 let PrintMethod = "printMEMriOperand";
56 let MIOperandInfo = (ops IntRegs, s11Imm);
59 def FrameIndex : Operand<i32> {
60 let PrintMethod = "printFrameIndexOperand";
61 let MIOperandInfo = (ops IntRegs, s11Imm);
64 let PrintMethod = "printGlobalOperand" in
65 def globaladdress : Operand<i32>;
67 let PrintMethod = "printJumpTable" in
68 def jumptablebase : Operand<i32>;
70 def brtarget : Operand<OtherVT>;
71 def calltarget : Operand<i32>;
73 def bblabel : Operand<i32>;
74 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
76 def symbolHi32 : Operand<i32> {
77 let PrintMethod = "printSymbolHi";
79 def symbolLo32 : Operand<i32> {
80 let PrintMethod = "printSymbolLo";
83 // Multi-class for logical operators.
84 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
85 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
86 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
87 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
88 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
89 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
90 [(set IntRegs:$dst, (OpNode s10Imm:$b, IntRegs:$c))]>;
93 // Multi-class for compare ops.
94 let isCompare = 1 in {
95 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
96 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
97 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
98 [(set PredRegs:$dst, (OpNode DoubleRegs:$b, DoubleRegs:$c))]>;
100 multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
101 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
102 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
103 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
106 multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
107 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
108 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
109 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
110 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
111 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
112 [(set PredRegs:$dst, (OpNode IntRegs:$b, s10ImmPred:$c))]>;
115 multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
116 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
117 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
118 [(set PredRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
119 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
120 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
121 [(set PredRegs:$dst, (OpNode IntRegs:$b, u9ImmPred:$c))]>;
124 multiclass CMP32_ri_u9<string OpcStr, PatFrag OpNode> {
125 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
126 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
127 [(set PredRegs:$dst, (OpNode IntRegs:$b, u9ImmPred:$c))]>;
130 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
131 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
132 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
133 [(set PredRegs:$dst, (OpNode IntRegs:$b, s8ImmPred:$c))]>;
137 //===----------------------------------------------------------------------===//
139 //===----------------------------------------------------------------------===//
141 //===----------------------------------------------------------------------===//
142 // http://qualnet.qualcomm.com/~erich/v1/htmldocs/index.html
143 // http://qualnet.qualcomm.com/~erich/v2/htmldocs/index.html
144 // http://qualnet.qualcomm.com/~erich/v3/htmldocs/index.html
145 // http://qualnet.qualcomm.com/~erich/v4/htmldocs/index.html
146 // http://qualnet.qualcomm.com/~erich/v5/htmldocs/index.html
147 //===----------------------------------------------------------------------===//
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 let isPredicable = 1 in
154 def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
155 (ins IntRegs:$src1, IntRegs:$src2),
156 "$dst = add($src1, $src2)",
157 [(set IntRegs:$dst, (add IntRegs:$src1, IntRegs:$src2))]>;
159 let isPredicable = 1 in
160 def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
161 (ins IntRegs:$src1, s16Imm:$src2),
162 "$dst = add($src1, #$src2)",
163 [(set IntRegs:$dst, (add IntRegs:$src1, s16ImmPred:$src2))]>;
165 // Logical operations.
166 let isPredicable = 1 in
167 def XOR_rr : ALU32_rr<(outs IntRegs:$dst),
168 (ins IntRegs:$src1, IntRegs:$src2),
169 "$dst = xor($src1, $src2)",
170 [(set IntRegs:$dst, (xor IntRegs:$src1, IntRegs:$src2))]>;
172 let isPredicable = 1 in
173 def AND_rr : ALU32_rr<(outs IntRegs:$dst),
174 (ins IntRegs:$src1, IntRegs:$src2),
175 "$dst = and($src1, $src2)",
176 [(set IntRegs:$dst, (and IntRegs:$src1, IntRegs:$src2))]>;
178 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
179 (ins IntRegs:$src1, s8Imm:$src2),
180 "$dst = or($src1, #$src2)",
181 [(set IntRegs:$dst, (or IntRegs:$src1, s8ImmPred:$src2))]>;
183 def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
186 [(set IntRegs:$dst, (not IntRegs:$src1))]>;
188 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
189 (ins IntRegs:$src1, s10Imm:$src2),
190 "$dst = and($src1, #$src2)",
191 [(set IntRegs:$dst, (and IntRegs:$src1, s10ImmPred:$src2))]>;
193 let isPredicable = 1 in
194 def OR_rr : ALU32_rr<(outs IntRegs:$dst),
195 (ins IntRegs:$src1, IntRegs:$src2),
196 "$dst = or($src1, $src2)",
197 [(set IntRegs:$dst, (or IntRegs:$src1, IntRegs:$src2))]>;
200 def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
202 [(set IntRegs:$dst, (ineg IntRegs:$src1))]>;
204 let neverHasSideEffects = 1 in
205 def NOP : ALU32_rr<(outs), (ins),
210 let isPredicable = 1 in
211 def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
212 (ins IntRegs:$src1, IntRegs:$src2),
213 "$dst = sub($src1, $src2)",
214 [(set IntRegs:$dst, (sub IntRegs:$src1, IntRegs:$src2))]>;
216 // Transfer immediate.
217 let isReMaterializable = 1, isPredicable = 1 in
218 def TFRI : ALU32_ri<(outs IntRegs:$dst), (ins s16Imm:$src1),
220 [(set IntRegs:$dst, s16ImmPred:$src1)]>;
222 // Transfer register.
223 let neverHasSideEffects = 1, isPredicable = 1 in
224 def TFR : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1),
228 // Transfer control register.
229 let neverHasSideEffects = 1 in
230 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
243 let isPredicable = 1, neverHasSideEffects = 1 in
244 def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
245 (ins IntRegs:$src1, IntRegs:$src2),
246 "$dst = combine($src1, $src2)",
250 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
253 "$dst = vmux($src1, $src2, $src3)",
256 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
257 IntRegs:$src2, IntRegs:$src3),
258 "$dst = mux($src1, $src2, $src3)",
259 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
262 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
264 "$dst = mux($src1, #$src2, $src3)",
265 [(set IntRegs:$dst, (select PredRegs:$src1,
266 s8ImmPred:$src2, IntRegs:$src3))]>;
268 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
270 "$dst = mux($src1, $src2, #$src3)",
271 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
274 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
276 "$dst = mux($src1, #$src2, #$src3)",
277 [(set IntRegs:$dst, (select PredRegs:$src1, s8ImmPred:$src2,
281 let isPredicable = 1 in
282 def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
283 "$dst = aslh($src1)",
284 [(set IntRegs:$dst, (shl 16, IntRegs:$src1))]>;
286 let isPredicable = 1 in
287 def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
288 "$dst = asrh($src1)",
289 [(set IntRegs:$dst, (sra 16, IntRegs:$src1))]>;
292 let isPredicable = 1 in
293 def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
294 "$dst = sxtb($src1)",
295 [(set IntRegs:$dst, (sext_inreg IntRegs:$src1, i8))]>;
297 let isPredicable = 1 in
298 def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
299 "$dst = sxth($src1)",
300 [(set IntRegs:$dst, (sext_inreg IntRegs:$src1, i16))]>;
303 let isPredicable = 1, neverHasSideEffects = 1 in
304 def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
305 "$dst = zxtb($src1)",
308 let isPredicable = 1, neverHasSideEffects = 1 in
309 def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
310 "$dst = zxth($src1)",
312 //===----------------------------------------------------------------------===//
314 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
319 //===----------------------------------------------------------------------===//
322 let neverHasSideEffects = 1, isPredicated = 1 in
323 def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
324 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
325 "if ($src1) $dst = add($src2, #$src3)",
328 let neverHasSideEffects = 1, isPredicated = 1 in
329 def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
330 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
331 "if (!$src1) $dst = add($src2, #$src3)",
334 let neverHasSideEffects = 1, isPredicated = 1 in
335 def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
336 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
337 "if ($src1.new) $dst = add($src2, #$src3)",
340 let neverHasSideEffects = 1, isPredicated = 1 in
341 def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
342 (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
343 "if (!$src1.new) $dst = add($src2, #$src3)",
346 let neverHasSideEffects = 1, isPredicated = 1 in
347 def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
348 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
349 "if ($src1) $dst = add($src2, $src3)",
352 let neverHasSideEffects = 1, isPredicated = 1 in
353 def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
354 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
355 "if (!$src1) $dst = add($src2, $src3)",
358 let neverHasSideEffects = 1, isPredicated = 1 in
359 def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
360 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
361 "if ($src1.new) $dst = add($src2, $src3)",
364 let neverHasSideEffects = 1, isPredicated = 1 in
365 def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
366 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
367 "if (!$src1.new) $dst = add($src2, $src3)",
371 // Conditional combine.
373 let neverHasSideEffects = 1, isPredicated = 1 in
374 def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
375 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
376 "if ($src1) $dst = combine($src2, $src3)",
379 let neverHasSideEffects = 1, isPredicated = 1 in
380 def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
381 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
382 "if (!$src1) $dst = combine($src2, $src3)",
385 let neverHasSideEffects = 1, isPredicated = 1 in
386 def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
387 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
388 "if ($src1.new) $dst = combine($src2, $src3)",
391 let neverHasSideEffects = 1, isPredicated = 1 in
392 def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
393 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
394 "if (!$src1.new) $dst = combine($src2, $src3)",
397 // Conditional logical operations.
399 let isPredicated = 1 in
400 def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
401 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
402 "if ($src1) $dst = xor($src2, $src3)",
405 let isPredicated = 1 in
406 def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
407 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
408 "if (!$src1) $dst = xor($src2, $src3)",
411 let isPredicated = 1 in
412 def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
413 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
414 "if ($src1.new) $dst = xor($src2, $src3)",
417 let isPredicated = 1 in
418 def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
419 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
420 "if (!$src1.new) $dst = xor($src2, $src3)",
423 let isPredicated = 1 in
424 def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
425 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
426 "if ($src1) $dst = and($src2, $src3)",
429 let isPredicated = 1 in
430 def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
431 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
432 "if (!$src1) $dst = and($src2, $src3)",
435 let isPredicated = 1 in
436 def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
437 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
438 "if ($src1.new) $dst = and($src2, $src3)",
441 let isPredicated = 1 in
442 def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
443 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
444 "if (!$src1.new) $dst = and($src2, $src3)",
447 let isPredicated = 1 in
448 def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
449 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
450 "if ($src1) $dst = or($src2, $src3)",
453 let isPredicated = 1 in
454 def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
455 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
456 "if (!$src1) $dst = or($src2, $src3)",
459 let isPredicated = 1 in
460 def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
461 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
462 "if ($src1.new) $dst = or($src2, $src3)",
465 let isPredicated = 1 in
466 def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
468 "if (!$src1.new) $dst = or($src2, $src3)",
472 // Conditional subtract.
474 let isPredicated = 1 in
475 def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
476 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
477 "if ($src1) $dst = sub($src2, $src3)",
480 let isPredicated = 1 in
481 def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
482 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
483 "if (!$src1) $dst = sub($src2, $src3)",
486 let isPredicated = 1 in
487 def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
488 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
489 "if ($src1.new) $dst = sub($src2, $src3)",
492 let isPredicated = 1 in
493 def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
494 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
495 "if (!$src1.new) $dst = sub($src2, $src3)",
499 // Conditional transfer.
501 let neverHasSideEffects = 1, isPredicated = 1 in
502 def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
503 "if ($src1) $dst = $src2",
506 let neverHasSideEffects = 1, isPredicated = 1 in
507 def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
509 "if (!$src1) $dst = $src2",
512 let neverHasSideEffects = 1, isPredicated = 1 in
513 def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
514 "if ($src1) $dst = #$src2",
517 let neverHasSideEffects = 1, isPredicated = 1 in
518 def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
520 "if (!$src1) $dst = #$src2",
523 let neverHasSideEffects = 1, isPredicated = 1 in
524 def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
526 "if ($src1.new) $dst = $src2",
529 let neverHasSideEffects = 1, isPredicated = 1 in
530 def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
532 "if (!$src1.new) $dst = $src2",
535 let neverHasSideEffects = 1, isPredicated = 1 in
536 def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
538 "if ($src1.new) $dst = #$src2",
541 let neverHasSideEffects = 1, isPredicated = 1 in
542 def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
544 "if (!$src1.new) $dst = #$src2",
548 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
549 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
550 defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
551 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
552 defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
553 defm CMPGEU : CMP32_ri_u9<"cmp.geu", setuge>;
554 //===----------------------------------------------------------------------===//
556 //===----------------------------------------------------------------------===//
558 //===----------------------------------------------------------------------===//
560 //===----------------------------------------------------------------------===//
561 // Vector add halfwords
563 // Vector averagehalfwords
565 // Vector subtract halfwords
566 //===----------------------------------------------------------------------===//
568 //===----------------------------------------------------------------------===//
571 //===----------------------------------------------------------------------===//
573 //===----------------------------------------------------------------------===//
575 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
577 "$dst = add($src1, $src2)",
578 [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
579 DoubleRegs:$src2))]>;
584 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
585 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
586 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
588 // Logical operations.
589 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
591 "$dst = and($src1, $src2)",
592 [(set DoubleRegs:$dst, (and DoubleRegs:$src1,
593 DoubleRegs:$src2))]>;
595 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
597 "$dst = or($src1, $src2)",
598 [(set DoubleRegs:$dst, (or DoubleRegs:$src1, DoubleRegs:$src2))]>;
600 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
602 "$dst = xor($src1, $src2)",
603 [(set DoubleRegs:$dst, (xor DoubleRegs:$src1,
604 DoubleRegs:$src2))]>;
607 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
608 "$dst = max($src2, $src1)",
609 [(set IntRegs:$dst, (select (i1 (setlt IntRegs:$src2,
611 IntRegs:$src1, IntRegs:$src2))]>;
614 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
615 "$dst = min($src2, $src1)",
616 [(set IntRegs:$dst, (select (i1 (setgt IntRegs:$src2,
618 IntRegs:$src1, IntRegs:$src2))]>;
621 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
623 "$dst = sub($src1, $src2)",
624 [(set DoubleRegs:$dst, (sub DoubleRegs:$src1,
625 DoubleRegs:$src2))]>;
627 // Subtract halfword.
629 // Transfer register.
630 let neverHasSideEffects = 1 in
631 def TFR_64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
634 //===----------------------------------------------------------------------===//
636 //===----------------------------------------------------------------------===//
638 //===----------------------------------------------------------------------===//
640 //===----------------------------------------------------------------------===//
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
648 //===----------------------------------------------------------------------===//
650 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
666 //===----------------------------------------------------------------------===//
668 //===----------------------------------------------------------------------===//
670 //===----------------------------------------------------------------------===//
672 //===----------------------------------------------------------------------===//
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
678 //===----------------------------------------------------------------------===//
680 //===----------------------------------------------------------------------===//
681 // Logical reductions on predicates.
683 // Looping instructions.
685 // Pipelined looping instructions.
687 // Logical operations on predicates.
688 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
689 "$dst = and($src1, $src2)",
690 [(set PredRegs:$dst, (and PredRegs:$src1, PredRegs:$src2))]>;
692 let neverHasSideEffects = 1 in
693 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
695 "$dst = and($src1, !$src2)",
698 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
699 "$dst = any8($src1)",
702 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
703 "$dst = all8($src1)",
706 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
708 "$dst = vitpack($src1, $src2)",
711 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
714 "$dst = valignb($src1, $src2, $src3)",
717 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
720 "$dst = vspliceb($src1, $src2, $src3)",
723 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
724 "$dst = mask($src1)",
727 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
729 [(set PredRegs:$dst, (not PredRegs:$src1))]>;
731 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
732 "$dst = or($src1, $src2)",
733 [(set PredRegs:$dst, (or PredRegs:$src1, PredRegs:$src2))]>;
735 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
736 "$dst = xor($src1, $src2)",
737 [(set PredRegs:$dst, (xor PredRegs:$src1, PredRegs:$src2))]>;
740 // User control register transfer.
741 //===----------------------------------------------------------------------===//
743 //===----------------------------------------------------------------------===//
746 //===----------------------------------------------------------------------===//
748 //===----------------------------------------------------------------------===//
750 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
751 def JMP : JInst< (outs),
752 (ins brtarget:$offset),
758 let isBranch = 1, isTerminator=1, Defs = [PC],
759 isPredicated = 1 in {
760 def JMP_c : JInst< (outs),
761 (ins PredRegs:$src, brtarget:$offset),
762 "if ($src) jump $offset",
763 [(brcond PredRegs:$src, bb:$offset)]>;
767 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
768 isPredicated = 1 in {
769 def JMP_cNot : JInst< (outs),
770 (ins PredRegs:$src, brtarget:$offset),
771 "if (!$src) jump $offset",
775 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
776 isPredicated = 1 in {
777 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
778 "if ($pred) jump $dst",
782 // Jump to address conditioned on new predicate.
784 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
785 isPredicated = 1 in {
786 def JMP_cdnPt : JInst< (outs),
787 (ins PredRegs:$src, brtarget:$offset),
788 "if ($src.new) jump:t $offset",
793 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
794 isPredicated = 1 in {
795 def JMP_cdnNotPt : JInst< (outs),
796 (ins PredRegs:$src, brtarget:$offset),
797 "if (!$src.new) jump:t $offset",
802 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
803 isPredicated = 1 in {
804 def JMP_cdnPnt : JInst< (outs),
805 (ins PredRegs:$src, brtarget:$offset),
806 "if ($src.new) jump:nt $offset",
811 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
812 isPredicated = 1 in {
813 def JMP_cdnNotPnt : JInst< (outs),
814 (ins PredRegs:$src, brtarget:$offset),
815 "if (!$src.new) jump:nt $offset",
818 //===----------------------------------------------------------------------===//
820 //===----------------------------------------------------------------------===//
822 //===----------------------------------------------------------------------===//
824 //===----------------------------------------------------------------------===//
825 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
826 [SDNPHasChain, SDNPOptInGlue]>;
828 // Jump to address from register.
829 let isReturn = 1, isTerminator = 1, isBarrier = 1,
830 Defs = [PC], Uses = [R31] in {
831 def JMPR: JRInst<(outs), (ins),
836 // Jump to address from register.
837 let isReturn = 1, isTerminator = 1, isBarrier = 1,
838 Defs = [PC], Uses = [R31] in {
839 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
840 "if ($src1) jumpr r31",
844 // Jump to address from register.
845 let isReturn = 1, isTerminator = 1, isBarrier = 1,
846 Defs = [PC], Uses = [R31] in {
847 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
848 "if (!$src1) jumpr r31",
852 //===----------------------------------------------------------------------===//
854 //===----------------------------------------------------------------------===//
856 //===----------------------------------------------------------------------===//
858 //===----------------------------------------------------------------------===//
860 /// Make sure that in post increment load, the first operand is always the post
861 /// increment operand.
864 let isPredicable = 1 in
865 def LDrid : LDInst<(outs DoubleRegs:$dst),
867 "$dst = memd($addr)",
868 [(set DoubleRegs:$dst, (load ADDRriS11_3:$addr))]>;
870 let isPredicable = 1, AddedComplexity = 20 in
871 def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
872 (ins IntRegs:$src1, s11_3Imm:$offset),
873 "$dst=memd($src1+#$offset)",
874 [(set DoubleRegs:$dst, (load (add IntRegs:$src1,
875 s11_3ImmPred:$offset)))]>;
877 let mayLoad = 1, neverHasSideEffects = 1 in
878 def LDrid_GP : LDInst<(outs DoubleRegs:$dst),
879 (ins globaladdress:$global, u16Imm:$offset),
880 "$dst=memd(#$global+$offset)",
883 let mayLoad = 1, neverHasSideEffects = 1 in
884 def LDd_GP : LDInst<(outs DoubleRegs:$dst),
885 (ins globaladdress:$global),
886 "$dst=memd(#$global)",
889 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
890 def POST_LDrid : LDInstPI<(outs DoubleRegs:$dst, IntRegs:$dst2),
891 (ins IntRegs:$src1, s4Imm:$offset),
892 "$dst = memd($src1++#$offset)",
896 // Load doubleword conditionally.
897 let mayLoad = 1, neverHasSideEffects = 1 in
898 def LDrid_cPt : LDInst<(outs DoubleRegs:$dst),
899 (ins PredRegs:$src1, MEMri:$addr),
900 "if ($src1) $dst = memd($addr)",
904 let mayLoad = 1, neverHasSideEffects = 1 in
905 def LDrid_cNotPt : LDInst<(outs DoubleRegs:$dst),
906 (ins PredRegs:$src1, MEMri:$addr),
907 "if (!$src1) $dst = memd($addr)",
910 let mayLoad = 1, neverHasSideEffects = 1 in
911 def LDrid_indexed_cPt : LDInst<(outs DoubleRegs:$dst),
912 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
913 "if ($src1) $dst=memd($src2+#$src3)",
916 let mayLoad = 1, neverHasSideEffects = 1 in
917 def LDrid_indexed_cNotPt : LDInst<(outs DoubleRegs:$dst),
918 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
919 "if (!$src1) $dst=memd($src2+#$src3)",
922 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
923 def POST_LDrid_cPt : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
924 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
925 "if ($src1) $dst1 = memd($src2++#$src3)",
929 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
930 def POST_LDrid_cNotPt : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
931 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
932 "if (!$src1) $dst1 = memd($src2++#$src3)",
936 let mayLoad = 1, neverHasSideEffects = 1 in
937 def LDrid_cdnPt : LDInst<(outs DoubleRegs:$dst),
938 (ins PredRegs:$src1, MEMri:$addr),
939 "if ($src1.new) $dst = memd($addr)",
942 let mayLoad = 1, neverHasSideEffects = 1 in
943 def LDrid_cdnNotPt : LDInst<(outs DoubleRegs:$dst),
944 (ins PredRegs:$src1, MEMri:$addr),
945 "if (!$src1.new) $dst = memd($addr)",
948 let mayLoad = 1, neverHasSideEffects = 1 in
949 def LDrid_indexed_cdnPt : LDInst<(outs DoubleRegs:$dst),
950 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
951 "if ($src1.new) $dst=memd($src2+#$src3)",
954 let mayLoad = 1, neverHasSideEffects = 1 in
955 def LDrid_indexed_cdnNotPt : LDInst<(outs DoubleRegs:$dst),
956 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
957 "if (!$src1.new) $dst=memd($src2+#$src3)",
962 let isPredicable = 1 in
963 def LDrib : LDInst<(outs IntRegs:$dst),
965 "$dst = memb($addr)",
966 [(set IntRegs:$dst, (sextloadi8 ADDRriS11_0:$addr))]>;
968 def LDrib_ae : LDInst<(outs IntRegs:$dst),
970 "$dst = memb($addr)",
971 [(set IntRegs:$dst, (extloadi8 ADDRriS11_0:$addr))]>;
973 // Indexed load byte.
974 let isPredicable = 1, AddedComplexity = 20 in
975 def LDrib_indexed : LDInst<(outs IntRegs:$dst),
976 (ins IntRegs:$src1, s11_0Imm:$offset),
977 "$dst=memb($src1+#$offset)",
978 [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,
979 s11_0ImmPred:$offset)))]>;
982 // Indexed load byte any-extend.
983 let AddedComplexity = 20 in
984 def LDrib_ae_indexed : LDInst<(outs IntRegs:$dst),
985 (ins IntRegs:$src1, s11_0Imm:$offset),
986 "$dst=memb($src1+#$offset)",
987 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
988 s11_0ImmPred:$offset)))]>;
990 let mayLoad = 1, neverHasSideEffects = 1 in
991 def LDrib_GP : LDInst<(outs IntRegs:$dst),
992 (ins globaladdress:$global, u16Imm:$offset),
993 "$dst=memb(#$global+$offset)",
996 let mayLoad = 1, neverHasSideEffects = 1 in
997 def LDb_GP : LDInst<(outs IntRegs:$dst),
998 (ins globaladdress:$global),
999 "$dst=memb(#$global)",
1002 let mayLoad = 1, neverHasSideEffects = 1 in
1003 def LDub_GP : LDInst<(outs IntRegs:$dst),
1004 (ins globaladdress:$global),
1005 "$dst=memub(#$global)",
1008 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1009 def POST_LDrib : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1010 (ins IntRegs:$src1, s4Imm:$offset),
1011 "$dst = memb($src1++#$offset)",
1015 // Load byte conditionally.
1016 let mayLoad = 1, neverHasSideEffects = 1 in
1017 def LDrib_cPt : LDInst<(outs IntRegs:$dst),
1018 (ins PredRegs:$src1, MEMri:$addr),
1019 "if ($src1) $dst = memb($addr)",
1022 let mayLoad = 1, neverHasSideEffects = 1 in
1023 def LDrib_cNotPt : LDInst<(outs IntRegs:$dst),
1024 (ins PredRegs:$src1, MEMri:$addr),
1025 "if (!$src1) $dst = memb($addr)",
1028 let mayLoad = 1, neverHasSideEffects = 1 in
1029 def LDrib_indexed_cPt : LDInst<(outs IntRegs:$dst),
1030 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1031 "if ($src1) $dst = memb($src2+#$src3)",
1034 let mayLoad = 1, neverHasSideEffects = 1 in
1035 def LDrib_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1036 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1037 "if (!$src1) $dst = memb($src2+#$src3)",
1040 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1041 def POST_LDrib_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1042 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1043 "if ($src1) $dst1 = memb($src2++#$src3)",
1047 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1048 def POST_LDrib_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1049 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1050 "if (!$src1) $dst1 = memb($src2++#$src3)",
1054 let mayLoad = 1, neverHasSideEffects = 1 in
1055 def LDrib_cdnPt : LDInst<(outs IntRegs:$dst),
1056 (ins PredRegs:$src1, MEMri:$addr),
1057 "if ($src1.new) $dst = memb($addr)",
1060 let mayLoad = 1, neverHasSideEffects = 1 in
1061 def LDrib_cdnNotPt : LDInst<(outs IntRegs:$dst),
1062 (ins PredRegs:$src1, MEMri:$addr),
1063 "if (!$src1.new) $dst = memb($addr)",
1066 let mayLoad = 1, neverHasSideEffects = 1 in
1067 def LDrib_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1068 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1069 "if ($src1.new) $dst = memb($src2+#$src3)",
1072 let mayLoad = 1, neverHasSideEffects = 1 in
1073 def LDrib_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1074 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1075 "if (!$src1.new) $dst = memb($src2+#$src3)",
1080 let isPredicable = 1 in
1081 def LDrih : LDInst<(outs IntRegs:$dst),
1083 "$dst = memh($addr)",
1084 [(set IntRegs:$dst, (sextloadi16 ADDRriS11_1:$addr))]>;
1086 let isPredicable = 1, AddedComplexity = 20 in
1087 def LDrih_indexed : LDInst<(outs IntRegs:$dst),
1088 (ins IntRegs:$src1, s11_1Imm:$offset),
1089 "$dst=memh($src1+#$offset)",
1090 [(set IntRegs:$dst, (sextloadi16 (add IntRegs:$src1,
1091 s11_1ImmPred:$offset)))] >;
1093 def LDrih_ae : LDInst<(outs IntRegs:$dst),
1095 "$dst = memh($addr)",
1096 [(set IntRegs:$dst, (extloadi16 ADDRriS11_1:$addr))]>;
1098 let AddedComplexity = 20 in
1099 def LDrih_ae_indexed : LDInst<(outs IntRegs:$dst),
1100 (ins IntRegs:$src1, s11_1Imm:$offset),
1101 "$dst=memh($src1+#$offset)",
1102 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
1103 s11_1ImmPred:$offset)))] >;
1105 let mayLoad = 1, neverHasSideEffects = 1 in
1106 def LDrih_GP : LDInst<(outs IntRegs:$dst),
1107 (ins globaladdress:$global, u16Imm:$offset),
1108 "$dst=memh(#$global+$offset)",
1111 let mayLoad = 1, neverHasSideEffects = 1 in
1112 def LDh_GP : LDInst<(outs IntRegs:$dst),
1113 (ins globaladdress:$global),
1114 "$dst=memh(#$global)",
1117 let mayLoad = 1, neverHasSideEffects = 1 in
1118 def LDuh_GP : LDInst<(outs IntRegs:$dst),
1119 (ins globaladdress:$global),
1120 "$dst=memuh(#$global)",
1124 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1125 def POST_LDrih : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1126 (ins IntRegs:$src1, s4Imm:$offset),
1127 "$dst = memh($src1++#$offset)",
1131 // Load halfword conditionally.
1132 let mayLoad = 1, neverHasSideEffects = 1 in
1133 def LDrih_cPt : LDInst<(outs IntRegs:$dst),
1134 (ins PredRegs:$src1, MEMri:$addr),
1135 "if ($src1) $dst = memh($addr)",
1138 let mayLoad = 1, neverHasSideEffects = 1 in
1139 def LDrih_cNotPt : LDInst<(outs IntRegs:$dst),
1140 (ins PredRegs:$src1, MEMri:$addr),
1141 "if (!$src1) $dst = memh($addr)",
1144 let mayLoad = 1, neverHasSideEffects = 1 in
1145 def LDrih_indexed_cPt : LDInst<(outs IntRegs:$dst),
1146 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1147 "if ($src1) $dst = memh($src2+#$src3)",
1150 let mayLoad = 1, neverHasSideEffects = 1 in
1151 def LDrih_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1152 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1153 "if (!$src1) $dst = memh($src2+#$src3)",
1156 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1157 def POST_LDrih_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1158 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1159 "if ($src1) $dst1 = memh($src2++#$src3)",
1163 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1164 def POST_LDrih_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1165 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1166 "if (!$src1) $dst1 = memh($src2++#$src3)",
1170 let mayLoad = 1, neverHasSideEffects = 1 in
1171 def LDrih_cdnPt : LDInst<(outs IntRegs:$dst),
1172 (ins PredRegs:$src1, MEMri:$addr),
1173 "if ($src1.new) $dst = memh($addr)",
1176 let mayLoad = 1, neverHasSideEffects = 1 in
1177 def LDrih_cdnNotPt : LDInst<(outs IntRegs:$dst),
1178 (ins PredRegs:$src1, MEMri:$addr),
1179 "if (!$src1.new) $dst = memh($addr)",
1182 let mayLoad = 1, neverHasSideEffects = 1 in
1183 def LDrih_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1184 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1185 "if ($src1.new) $dst = memh($src2+#$src3)",
1188 let mayLoad = 1, neverHasSideEffects = 1 in
1189 def LDrih_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1190 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1191 "if (!$src1.new) $dst = memh($src2+#$src3)",
1194 // Load unsigned byte.
1195 let isPredicable = 1 in
1196 def LDriub : LDInst<(outs IntRegs:$dst),
1198 "$dst = memub($addr)",
1199 [(set IntRegs:$dst, (zextloadi8 ADDRriS11_0:$addr))]>;
1201 let isPredicable = 1 in
1202 def LDriubit : LDInst<(outs IntRegs:$dst),
1204 "$dst = memub($addr)",
1205 [(set IntRegs:$dst, (zextloadi1 ADDRriS11_0:$addr))]>;
1207 let isPredicable = 1, AddedComplexity = 20 in
1208 def LDriub_indexed : LDInst<(outs IntRegs:$dst),
1209 (ins IntRegs:$src1, s11_0Imm:$offset),
1210 "$dst=memub($src1+#$offset)",
1211 [(set IntRegs:$dst, (zextloadi8 (add IntRegs:$src1,
1212 s11_0ImmPred:$offset)))]>;
1214 let AddedComplexity = 20 in
1215 def LDriubit_indexed : LDInst<(outs IntRegs:$dst),
1216 (ins IntRegs:$src1, s11_0Imm:$offset),
1217 "$dst=memub($src1+#$offset)",
1218 [(set IntRegs:$dst, (zextloadi1 (add IntRegs:$src1,
1219 s11_0ImmPred:$offset)))]>;
1221 def LDriub_ae : LDInst<(outs IntRegs:$dst),
1223 "$dst = memub($addr)",
1224 [(set IntRegs:$dst, (extloadi8 ADDRriS11_0:$addr))]>;
1227 let AddedComplexity = 20 in
1228 def LDriub_ae_indexed : LDInst<(outs IntRegs:$dst),
1229 (ins IntRegs:$src1, s11_0Imm:$offset),
1230 "$dst=memub($src1+#$offset)",
1231 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
1232 s11_0ImmPred:$offset)))]>;
1234 let mayLoad = 1, neverHasSideEffects = 1 in
1235 def LDriub_GP : LDInst<(outs IntRegs:$dst),
1236 (ins globaladdress:$global, u16Imm:$offset),
1237 "$dst=memub(#$global+$offset)",
1240 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1241 def POST_LDriub : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1242 (ins IntRegs:$src1, s4Imm:$offset),
1243 "$dst = memub($src1++#$offset)",
1247 // Load unsigned byte conditionally.
1248 let mayLoad = 1, neverHasSideEffects = 1 in
1249 def LDriub_cPt : LDInst<(outs IntRegs:$dst),
1250 (ins PredRegs:$src1, MEMri:$addr),
1251 "if ($src1) $dst = memub($addr)",
1254 let mayLoad = 1, neverHasSideEffects = 1 in
1255 def LDriub_cNotPt : LDInst<(outs IntRegs:$dst),
1256 (ins PredRegs:$src1, MEMri:$addr),
1257 "if (!$src1) $dst = memub($addr)",
1260 let mayLoad = 1, neverHasSideEffects = 1 in
1261 def LDriub_indexed_cPt : LDInst<(outs IntRegs:$dst),
1262 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1263 "if ($src1) $dst = memub($src2+#$src3)",
1266 let mayLoad = 1, neverHasSideEffects = 1 in
1267 def LDriub_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1268 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1269 "if (!$src1) $dst = memub($src2+#$src3)",
1272 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1273 def POST_LDriub_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1274 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1275 "if ($src1) $dst1 = memub($src2++#$src3)",
1279 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1280 def POST_LDriub_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1281 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
1282 "if (!$src1) $dst1 = memub($src2++#$src3)",
1286 let mayLoad = 1, neverHasSideEffects = 1 in
1287 def LDriub_cdnPt : LDInst<(outs IntRegs:$dst),
1288 (ins PredRegs:$src1, MEMri:$addr),
1289 "if ($src1.new) $dst = memub($addr)",
1292 let mayLoad = 1, neverHasSideEffects = 1 in
1293 def LDriub_cdnNotPt : LDInst<(outs IntRegs:$dst),
1294 (ins PredRegs:$src1, MEMri:$addr),
1295 "if (!$src1.new) $dst = memub($addr)",
1298 let mayLoad = 1, neverHasSideEffects = 1 in
1299 def LDriub_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1300 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1301 "if ($src1.new) $dst = memub($src2+#$src3)",
1304 let mayLoad = 1, neverHasSideEffects = 1 in
1305 def LDriub_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1306 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
1307 "if (!$src1.new) $dst = memub($src2+#$src3)",
1310 // Load unsigned halfword.
1311 let isPredicable = 1 in
1312 def LDriuh : LDInst<(outs IntRegs:$dst),
1314 "$dst = memuh($addr)",
1315 [(set IntRegs:$dst, (zextloadi16 ADDRriS11_1:$addr))]>;
1317 // Indexed load unsigned halfword.
1318 let isPredicable = 1, AddedComplexity = 20 in
1319 def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
1320 (ins IntRegs:$src1, s11_1Imm:$offset),
1321 "$dst=memuh($src1+#$offset)",
1322 [(set IntRegs:$dst, (zextloadi16 (add IntRegs:$src1,
1323 s11_1ImmPred:$offset)))]>;
1325 def LDriuh_ae : LDInst<(outs IntRegs:$dst),
1327 "$dst = memuh($addr)",
1328 [(set IntRegs:$dst, (extloadi16 ADDRriS11_1:$addr))]>;
1331 // Indexed load unsigned halfword any-extend.
1332 let AddedComplexity = 20 in
1333 def LDriuh_ae_indexed : LDInst<(outs IntRegs:$dst),
1334 (ins IntRegs:$src1, s11_1Imm:$offset),
1335 "$dst=memuh($src1+#$offset)",
1336 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
1337 s11_1ImmPred:$offset)))] >;
1339 let mayLoad = 1, neverHasSideEffects = 1 in
1340 def LDriuh_GP : LDInst<(outs IntRegs:$dst),
1341 (ins globaladdress:$global, u16Imm:$offset),
1342 "$dst=memuh(#$global+$offset)",
1345 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1346 def POST_LDriuh : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1347 (ins IntRegs:$src1, s4Imm:$offset),
1348 "$dst = memuh($src1++#$offset)",
1352 // Load unsigned halfword conditionally.
1353 let mayLoad = 1, neverHasSideEffects = 1 in
1354 def LDriuh_cPt : LDInst<(outs IntRegs:$dst),
1355 (ins PredRegs:$src1, MEMri:$addr),
1356 "if ($src1) $dst = memuh($addr)",
1359 let mayLoad = 1, neverHasSideEffects = 1 in
1360 def LDriuh_cNotPt : LDInst<(outs IntRegs:$dst),
1361 (ins PredRegs:$src1, MEMri:$addr),
1362 "if (!$src1) $dst = memuh($addr)",
1365 let mayLoad = 1, neverHasSideEffects = 1 in
1366 def LDriuh_indexed_cPt : LDInst<(outs IntRegs:$dst),
1367 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1368 "if ($src1) $dst = memuh($src2+#$src3)",
1371 let mayLoad = 1, neverHasSideEffects = 1 in
1372 def LDriuh_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1373 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1374 "if (!$src1) $dst = memuh($src2+#$src3)",
1377 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1378 def POST_LDriuh_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1379 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1380 "if ($src1) $dst1 = memuh($src2++#$src3)",
1384 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1385 def POST_LDriuh_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1386 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
1387 "if (!$src1) $dst1 = memuh($src2++#$src3)",
1391 let mayLoad = 1, neverHasSideEffects = 1 in
1392 def LDriuh_cdnPt : LDInst<(outs IntRegs:$dst),
1393 (ins PredRegs:$src1, MEMri:$addr),
1394 "if ($src1.new) $dst = memuh($addr)",
1397 let mayLoad = 1, neverHasSideEffects = 1 in
1398 def LDriuh_cdnNotPt : LDInst<(outs IntRegs:$dst),
1399 (ins PredRegs:$src1, MEMri:$addr),
1400 "if (!$src1.new) $dst = memuh($addr)",
1403 let mayLoad = 1, neverHasSideEffects = 1 in
1404 def LDriuh_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1405 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1406 "if ($src1.new) $dst = memuh($src2+#$src3)",
1409 let mayLoad = 1, neverHasSideEffects = 1 in
1410 def LDriuh_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1411 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
1412 "if (!$src1.new) $dst = memuh($src2+#$src3)",
1417 let isPredicable = 1 in
1418 def LDriw : LDInst<(outs IntRegs:$dst),
1419 (ins MEMri:$addr), "$dst = memw($addr)",
1420 [(set IntRegs:$dst, (load ADDRriS11_2:$addr))]>;
1423 let mayLoad = 1, Defs = [R10,R11] in
1424 def LDriw_pred : LDInst<(outs PredRegs:$dst),
1426 "Error; should not emit",
1430 let isPredicable = 1, AddedComplexity = 20 in
1431 def LDriw_indexed : LDInst<(outs IntRegs:$dst),
1432 (ins IntRegs:$src1, s11_2Imm:$offset),
1433 "$dst=memw($src1+#$offset)",
1434 [(set IntRegs:$dst, (load (add IntRegs:$src1,
1435 s11_2ImmPred:$offset)))]>;
1437 let mayLoad = 1, neverHasSideEffects = 1 in
1438 def LDriw_GP : LDInst<(outs IntRegs:$dst),
1439 (ins globaladdress:$global, u16Imm:$offset),
1440 "$dst=memw(#$global+$offset)",
1443 let mayLoad = 1, neverHasSideEffects = 1 in
1444 def LDw_GP : LDInst<(outs IntRegs:$dst),
1445 (ins globaladdress:$global),
1446 "$dst=memw(#$global)",
1449 let isPredicable = 1, mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1450 def POST_LDriw : LDInstPI<(outs IntRegs:$dst, IntRegs:$dst2),
1451 (ins IntRegs:$src1, s4Imm:$offset),
1452 "$dst = memw($src1++#$offset)",
1456 // Load word conditionally.
1458 let mayLoad = 1, neverHasSideEffects = 1 in
1459 def LDriw_cPt : LDInst<(outs IntRegs:$dst),
1460 (ins PredRegs:$src1, MEMri:$addr),
1461 "if ($src1) $dst = memw($addr)",
1464 let mayLoad = 1, neverHasSideEffects = 1 in
1465 def LDriw_cNotPt : LDInst<(outs IntRegs:$dst),
1466 (ins PredRegs:$src1, MEMri:$addr),
1467 "if (!$src1) $dst = memw($addr)",
1470 let mayLoad = 1, neverHasSideEffects = 1 in
1471 def LDriw_indexed_cPt : LDInst<(outs IntRegs:$dst),
1472 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1473 "if ($src1) $dst=memw($src2+#$src3)",
1476 let mayLoad = 1, neverHasSideEffects = 1 in
1477 def LDriw_indexed_cNotPt : LDInst<(outs IntRegs:$dst),
1478 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1479 "if (!$src1) $dst=memw($src2+#$src3)",
1482 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1483 def POST_LDriw_cPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1484 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1485 "if ($src1) $dst1 = memw($src2++#$src3)",
1489 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
1490 def POST_LDriw_cNotPt : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
1491 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
1492 "if (!$src1) $dst1 = memw($src2++#$src3)",
1496 let mayLoad = 1, neverHasSideEffects = 1 in
1497 def LDriw_cdnPt : LDInst<(outs IntRegs:$dst),
1498 (ins PredRegs:$src1, MEMri:$addr),
1499 "if ($src1.new) $dst = memw($addr)",
1502 let mayLoad = 1, neverHasSideEffects = 1 in
1503 def LDriw_cdnNotPt : LDInst<(outs IntRegs:$dst),
1504 (ins PredRegs:$src1, MEMri:$addr),
1505 "if (!$src1.new) $dst = memw($addr)",
1508 let mayLoad = 1, neverHasSideEffects = 1 in
1509 def LDriw_indexed_cdnPt : LDInst<(outs IntRegs:$dst),
1510 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1511 "if ($src1.new) $dst=memw($src2+#$src3)",
1514 let mayLoad = 1, neverHasSideEffects = 1 in
1515 def LDriw_indexed_cdnNotPt : LDInst<(outs IntRegs:$dst),
1516 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
1517 "if (!$src1.new) $dst=memw($src2+#$src3)",
1520 // Deallocate stack frame.
1521 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1522 def DEALLOCFRAME : LDInst<(outs), (ins i32imm:$amt1),
1527 // Load and unpack bytes to halfwords.
1528 //===----------------------------------------------------------------------===//
1530 //===----------------------------------------------------------------------===//
1532 //===----------------------------------------------------------------------===//
1534 //===----------------------------------------------------------------------===//
1535 //===----------------------------------------------------------------------===//
1537 //===----------------------------------------------------------------------===//
1539 //===----------------------------------------------------------------------===//
1541 //===----------------------------------------------------------------------===//
1542 //===----------------------------------------------------------------------===//
1544 //===----------------------------------------------------------------------===//
1546 //===----------------------------------------------------------------------===//
1548 //===----------------------------------------------------------------------===//
1549 // Multiply and use lower result.
1551 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1552 "$dst =+ mpyi($src1, #$src2)",
1553 [(set IntRegs:$dst, (mul IntRegs:$src1, u8ImmPred:$src2))]>;
1556 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, n8Imm:$src2),
1557 "$dst =- mpyi($src1, #$src2)",
1559 (mul IntRegs:$src1, n8ImmPred:$src2))]>;
1562 // s9 is NOT the same as m9 - but it works.. so far.
1563 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1564 // depending on the value of m9. See Arch Spec.
1565 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1566 "$dst = mpyi($src1, #$src2)",
1567 [(set IntRegs:$dst, (mul IntRegs:$src1, s9ImmPred:$src2))]>;
1570 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1571 "$dst = mpyi($src1, $src2)",
1572 [(set IntRegs:$dst, (mul IntRegs:$src1, IntRegs:$src2))]>;
1575 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1576 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1577 "$dst += mpyi($src2, #$src3)",
1579 (add (mul IntRegs:$src2, u8ImmPred:$src3), IntRegs:$src1))],
1583 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1584 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1585 "$dst += mpyi($src2, $src3)",
1587 (add (mul IntRegs:$src2, IntRegs:$src3), IntRegs:$src1))],
1591 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1592 (ins IntRegs:$src1, IntRegs:$src2, u8Imm:$src3),
1593 "$dst -= mpyi($src2, #$src3)",
1595 (sub IntRegs:$src1, (mul IntRegs:$src2, u8ImmPred:$src3)))],
1598 // Multiply and use upper result.
1599 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1600 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1602 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1603 "$dst = mpy($src1, $src2)",
1604 [(set IntRegs:$dst, (mulhs IntRegs:$src1, IntRegs:$src2))]>;
1606 // Rd=mpy(Rs,Rt):rnd
1608 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1609 "$dst = mpyu($src1, $src2)",
1610 [(set IntRegs:$dst, (mulhu IntRegs:$src1, IntRegs:$src2))]>;
1612 // Multiply and use full result.
1614 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1615 "$dst = mpyu($src1, $src2)",
1616 [(set DoubleRegs:$dst, (mul (i64 (anyext IntRegs:$src1)),
1617 (i64 (anyext IntRegs:$src2))))]>;
1620 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1621 "$dst = mpy($src1, $src2)",
1622 [(set DoubleRegs:$dst, (mul (i64 (sext IntRegs:$src1)),
1623 (i64 (sext IntRegs:$src2))))]>;
1626 // Multiply and accumulate, use full result.
1627 // Rxx[+-]=mpy(Rs,Rt)
1629 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1630 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1631 "$dst += mpy($src2, $src3)",
1632 [(set DoubleRegs:$dst,
1633 (add (mul (i64 (sext IntRegs:$src2)), (i64 (sext IntRegs:$src3))),
1634 DoubleRegs:$src1))],
1638 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1639 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1640 "$dst -= mpy($src2, $src3)",
1641 [(set DoubleRegs:$dst,
1642 (sub DoubleRegs:$src1,
1643 (mul (i64 (sext IntRegs:$src2)), (i64 (sext IntRegs:$src3)))))],
1646 // Rxx[+-]=mpyu(Rs,Rt)
1648 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1649 IntRegs:$src2, IntRegs:$src3),
1650 "$dst += mpyu($src2, $src3)",
1651 [(set DoubleRegs:$dst, (add (mul (i64 (anyext IntRegs:$src2)),
1652 (i64 (anyext IntRegs:$src3))),
1653 DoubleRegs:$src1))],"$src1 = $dst">;
1656 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1657 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1658 "$dst += mpyu($src2, $src3)",
1659 [(set DoubleRegs:$dst,
1660 (sub DoubleRegs:$src1,
1661 (mul (i64 (anyext IntRegs:$src2)),
1662 (i64 (anyext IntRegs:$src3)))))],
1666 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1667 IntRegs:$src2, IntRegs:$src3),
1668 "$dst += add($src2, $src3)",
1669 [(set IntRegs:$dst, (add (add IntRegs:$src2, IntRegs:$src3),
1673 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1674 IntRegs:$src2, s8Imm:$src3),
1675 "$dst += add($src2, #$src3)",
1676 [(set IntRegs:$dst, (add (add IntRegs:$src2, s8ImmPred:$src3),
1680 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1681 IntRegs:$src2, IntRegs:$src3),
1682 "$dst -= add($src2, $src3)",
1683 [(set IntRegs:$dst, (sub IntRegs:$src1, (add IntRegs:$src2,
1687 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1688 IntRegs:$src2, s8Imm:$src3),
1689 "$dst -= add($src2, #$src3)",
1690 [(set IntRegs:$dst, (sub IntRegs:$src1,
1691 (add IntRegs:$src2, s8ImmPred:$src3)))],
1694 //===----------------------------------------------------------------------===//
1696 //===----------------------------------------------------------------------===//
1698 //===----------------------------------------------------------------------===//
1700 //===----------------------------------------------------------------------===//
1701 //===----------------------------------------------------------------------===//
1703 //===----------------------------------------------------------------------===//
1705 //===----------------------------------------------------------------------===//
1707 //===----------------------------------------------------------------------===//
1708 //===----------------------------------------------------------------------===//
1710 //===----------------------------------------------------------------------===//
1712 //===----------------------------------------------------------------------===//
1714 //===----------------------------------------------------------------------===//
1715 //===----------------------------------------------------------------------===//
1717 //===----------------------------------------------------------------------===//
1719 //===----------------------------------------------------------------------===//
1721 //===----------------------------------------------------------------------===//
1723 /// Assumptions::: ****** DO NOT IGNORE ********
1724 /// 1. Make sure that in post increment store, the zero'th operand is always the
1725 /// post increment operand.
1726 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1729 // Store doubleword.
1730 let isPredicable = 1 in
1731 def STrid : STInst<(outs),
1732 (ins MEMri:$addr, DoubleRegs:$src1),
1733 "memd($addr) = $src1",
1734 [(store DoubleRegs:$src1, ADDRriS11_3:$addr)]>;
1736 // Indexed store double word.
1737 let AddedComplexity = 10, isPredicable = 1 in
1738 def STrid_indexed : STInst<(outs),
1739 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
1740 "memd($src1+#$src2) = $src3",
1741 [(store DoubleRegs:$src3,
1742 (add IntRegs:$src1, s11_3ImmPred:$src2))]>;
1744 let mayStore = 1, neverHasSideEffects = 1 in
1745 def STrid_GP : STInst<(outs),
1746 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1747 "memd(#$global+$offset) = $src",
1750 let hasCtrlDep = 1, isPredicable = 1 in
1751 def POST_STdri : STInstPI<(outs IntRegs:$dst),
1752 (ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1753 "memd($src2++#$offset) = $src1",
1755 (post_store DoubleRegs:$src1, IntRegs:$src2, s4_3ImmPred:$offset))],
1758 // Store doubleword conditionally.
1759 // if ([!]Pv) memd(Rs+#u6:3)=Rtt
1760 // if (Pv) memd(Rs+#u6:3)=Rtt
1761 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1762 def STrid_cPt : STInst<(outs),
1763 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1764 "if ($src1) memd($addr) = $src2",
1767 // if (!Pv) memd(Rs+#u6:3)=Rtt
1768 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1769 def STrid_cNotPt : STInst<(outs),
1770 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1771 "if (!$src1) memd($addr) = $src2",
1774 // if (Pv) memd(Rs+#u6:3)=Rtt
1775 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1776 def STrid_indexed_cPt : STInst<(outs),
1777 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1779 "if ($src1) memd($src2+#$src3) = $src4",
1782 // if (!Pv) memd(Rs+#u6:3)=Rtt
1783 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1784 def STrid_indexed_cNotPt : STInst<(outs),
1785 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1787 "if (!$src1) memd($src2+#$src3) = $src4",
1790 // if ([!]Pv) memd(Rx++#s4:3)=Rtt
1791 // if (Pv) memd(Rx++#s4:3)=Rtt
1792 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1793 def POST_STdri_cPt : STInstPI<(outs IntRegs:$dst),
1794 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1796 "if ($src1) memd($src3++#$offset) = $src2",
1800 // if (!Pv) memd(Rx++#s4:3)=Rtt
1801 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,
1803 def POST_STdri_cNotPt : STInstPI<(outs IntRegs:$dst),
1804 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1806 "if (!$src1) memd($src3++#$offset) = $src2",
1812 // memb(Rs+#s11:0)=Rt
1813 let isPredicable = 1 in
1814 def STrib : STInst<(outs),
1815 (ins MEMri:$addr, IntRegs:$src1),
1816 "memb($addr) = $src1",
1817 [(truncstorei8 IntRegs:$src1, ADDRriS11_0:$addr)]>;
1819 let AddedComplexity = 10, isPredicable = 1 in
1820 def STrib_indexed : STInst<(outs),
1821 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1822 "memb($src1+#$src2) = $src3",
1823 [(truncstorei8 IntRegs:$src3, (add IntRegs:$src1,
1824 s11_0ImmPred:$src2))]>;
1826 // memb(gp+#u16:0)=Rt
1827 let mayStore = 1, neverHasSideEffects = 1 in
1828 def STrib_GP : STInst<(outs),
1829 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1830 "memb(#$global+$offset) = $src",
1833 let mayStore = 1, neverHasSideEffects = 1 in
1834 def STb_GP : STInst<(outs),
1835 (ins globaladdress:$global, IntRegs:$src),
1836 "memb(#$global) = $src",
1839 // memb(Rx++#s4:0)=Rt
1840 let hasCtrlDep = 1, isPredicable = 1 in
1841 def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
1844 "memb($src2++#$offset) = $src1",
1846 (post_truncsti8 IntRegs:$src1, IntRegs:$src2,
1847 s4_0ImmPred:$offset))],
1850 // Store byte conditionally.
1851 // if ([!]Pv) memb(Rs+#u6:0)=Rt
1852 // if (Pv) memb(Rs+#u6:0)=Rt
1853 let mayStore = 1, neverHasSideEffects = 1 in
1854 def STrib_cPt : STInst<(outs),
1855 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1856 "if ($src1) memb($addr) = $src2",
1859 // if (!Pv) memb(Rs+#u6:0)=Rt
1860 let mayStore = 1, neverHasSideEffects = 1 in
1861 def STrib_cNotPt : STInst<(outs),
1862 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1863 "if (!$src1) memb($addr) = $src2",
1866 // if (Pv) memb(Rs+#u6:0)=Rt
1867 let mayStore = 1, neverHasSideEffects = 1 in
1868 def STrib_indexed_cPt : STInst<(outs),
1869 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1870 "if ($src1) memb($src2+#$src3) = $src4",
1873 // if (!Pv) memb(Rs+#u6:0)=Rt
1874 let mayStore = 1, neverHasSideEffects = 1 in
1875 def STrib_indexed_cNotPt : STInst<(outs),
1876 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1877 "if (!$src1) memb($src2+#$src3) = $src4",
1880 // if ([!]Pv) memb(Rx++#s4:0)=Rt
1881 // if (Pv) memb(Rx++#s4:0)=Rt
1882 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1883 def POST_STbri_cPt : STInstPI<(outs IntRegs:$dst),
1884 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1885 "if ($src1) memb($src3++#$offset) = $src2",
1888 // if (!Pv) memb(Rx++#s4:0)=Rt
1889 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1890 def POST_STbri_cNotPt : STInstPI<(outs IntRegs:$dst),
1891 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1892 "if (!$src1) memb($src3++#$offset) = $src2",
1897 // memh(Rs+#s11:1)=Rt
1898 let isPredicable = 1 in
1899 def STrih : STInst<(outs),
1900 (ins MEMri:$addr, IntRegs:$src1),
1901 "memh($addr) = $src1",
1902 [(truncstorei16 IntRegs:$src1, ADDRriS11_1:$addr)]>;
1905 let AddedComplexity = 10, isPredicable = 1 in
1906 def STrih_indexed : STInst<(outs),
1907 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1908 "memh($src1+#$src2) = $src3",
1909 [(truncstorei16 IntRegs:$src3, (add IntRegs:$src1,
1910 s11_1ImmPred:$src2))]>;
1912 let mayStore = 1, neverHasSideEffects = 1 in
1913 def STrih_GP : STInst<(outs),
1914 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1915 "memh(#$global+$offset) = $src",
1918 let mayStore = 1, neverHasSideEffects = 1 in
1919 def STh_GP : STInst<(outs),
1920 (ins globaladdress:$global, IntRegs:$src),
1921 "memh(#$global) = $src",
1924 // memh(Rx++#s4:1)=Rt.H
1925 // memh(Rx++#s4:1)=Rt
1926 let hasCtrlDep = 1, isPredicable = 1 in
1927 def POST_SThri : STInstPI<(outs IntRegs:$dst),
1928 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
1929 "memh($src2++#$offset) = $src1",
1931 (post_truncsti16 IntRegs:$src1, IntRegs:$src2,
1932 s4_1ImmPred:$offset))],
1935 // Store halfword conditionally.
1936 // if ([!]Pv) memh(Rs+#u6:1)=Rt
1937 // if (Pv) memh(Rs+#u6:1)=Rt
1938 let mayStore = 1, neverHasSideEffects = 1 in
1939 def STrih_cPt : STInst<(outs),
1940 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1941 "if ($src1) memh($addr) = $src2",
1944 // if (!Pv) memh(Rs+#u6:1)=Rt
1945 let mayStore = 1, neverHasSideEffects = 1 in
1946 def STrih_cNotPt : STInst<(outs),
1947 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1948 "if (!$src1) memh($addr) = $src2",
1951 // if (Pv) memh(Rs+#u6:1)=Rt
1952 let mayStore = 1, neverHasSideEffects = 1 in
1953 def STrih_indexed_cPt : STInst<(outs),
1954 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1955 "if ($src1) memh($src2+#$src3) = $src4",
1958 // if (!Pv) memh(Rs+#u6:1)=Rt
1959 let mayStore = 1, neverHasSideEffects = 1 in
1960 def STrih_indexed_cNotPt : STInst<(outs),
1961 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1962 "if (!$src1) memh($src2+#$src3) = $src4",
1965 // if ([!]Pv) memh(Rx++#s4:1)=Rt
1966 // if (Pv) memh(Rx++#s4:1)=Rt
1967 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1968 def POST_SThri_cPt : STInstPI<(outs IntRegs:$dst),
1969 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1970 "if ($src1) memh($src3++#$offset) = $src2",
1973 // if (!Pv) memh(Rx++#s4:1)=Rt
1974 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
1975 def POST_SThri_cNotPt : STInstPI<(outs IntRegs:$dst),
1976 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1977 "if (!$src1) memh($src3++#$offset) = $src2",
1983 let Defs = [R10,R11] in
1984 def STriw_pred : STInst<(outs),
1985 (ins MEMri:$addr, PredRegs:$src1),
1986 "Error; should not emit",
1989 // memw(Rs+#s11:2)=Rt
1990 let isPredicable = 1 in
1991 def STriw : STInst<(outs),
1992 (ins MEMri:$addr, IntRegs:$src1),
1993 "memw($addr) = $src1",
1994 [(store IntRegs:$src1, ADDRriS11_2:$addr)]>;
1996 let AddedComplexity = 10, isPredicable = 1 in
1997 def STriw_indexed : STInst<(outs),
1998 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
1999 "memw($src1+#$src2) = $src3",
2000 [(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>;
2002 let mayStore = 1, neverHasSideEffects = 1 in
2003 def STriw_GP : STInst<(outs),
2004 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2005 "memw(#$global+$offset) = $src",
2008 let hasCtrlDep = 1, isPredicable = 1 in
2009 def POST_STwri : STInstPI<(outs IntRegs:$dst),
2010 (ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
2011 "memw($src2++#$offset) = $src1",
2013 (post_store IntRegs:$src1, IntRegs:$src2, s4_2ImmPred:$offset))],
2016 // Store word conditionally.
2017 // if ([!]Pv) memw(Rs+#u6:2)=Rt
2018 // if (Pv) memw(Rs+#u6:2)=Rt
2019 let mayStore = 1, neverHasSideEffects = 1 in
2020 def STriw_cPt : STInst<(outs),
2021 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2022 "if ($src1) memw($addr) = $src2",
2025 // if (!Pv) memw(Rs+#u6:2)=Rt
2026 let mayStore = 1, neverHasSideEffects = 1 in
2027 def STriw_cNotPt : STInst<(outs),
2028 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2029 "if (!$src1) memw($addr) = $src2",
2032 // if (Pv) memw(Rs+#u6:2)=Rt
2033 let mayStore = 1, neverHasSideEffects = 1 in
2034 def STriw_indexed_cPt : STInst<(outs),
2035 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2036 "if ($src1) memw($src2+#$src3) = $src4",
2039 // if (!Pv) memw(Rs+#u6:2)=Rt
2040 let mayStore = 1, neverHasSideEffects = 1 in
2041 def STriw_indexed_cNotPt : STInst<(outs),
2042 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2043 "if (!$src1) memw($src2+#$src3) = $src4",
2046 // if ([!]Pv) memw(Rx++#s4:2)=Rt
2047 // if (Pv) memw(Rx++#s4:2)=Rt
2048 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
2049 def POST_STwri_cPt : STInstPI<(outs IntRegs:$dst),
2050 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2051 "if ($src1) memw($src3++#$offset) = $src2",
2054 // if (!Pv) memw(Rx++#s4:2)=Rt
2055 let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
2056 def POST_STwri_cNotPt : STInstPI<(outs IntRegs:$dst),
2057 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2058 "if (!$src1) memw($src3++#$offset) = $src2",
2063 // Allocate stack frame.
2064 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
2065 def ALLOCFRAME : STInst<(outs),
2067 "allocframe(#$amt)",
2070 //===----------------------------------------------------------------------===//
2072 //===----------------------------------------------------------------------===//
2074 //===----------------------------------------------------------------------===//
2076 //===----------------------------------------------------------------------===//
2078 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2079 "$dst = not($src1)",
2080 [(set DoubleRegs:$dst, (not DoubleRegs:$src1))]>;
2083 // Sign extend word to doubleword.
2084 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2085 "$dst = sxtw($src1)",
2086 [(set DoubleRegs:$dst, (sext IntRegs:$src1))]>;
2087 //===----------------------------------------------------------------------===//
2089 //===----------------------------------------------------------------------===//
2091 //===----------------------------------------------------------------------===//
2093 //===----------------------------------------------------------------------===//
2094 //===----------------------------------------------------------------------===//
2096 //===----------------------------------------------------------------------===//
2099 //===----------------------------------------------------------------------===//
2101 //===----------------------------------------------------------------------===//
2102 //===----------------------------------------------------------------------===//
2104 //===----------------------------------------------------------------------===//
2106 //===----------------------------------------------------------------------===//
2108 //===----------------------------------------------------------------------===//
2109 //===----------------------------------------------------------------------===//
2111 //===----------------------------------------------------------------------===//
2113 //===----------------------------------------------------------------------===//
2115 //===----------------------------------------------------------------------===//
2116 // Predicate transfer.
2117 let neverHasSideEffects = 1 in
2118 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
2119 "$dst = $src1 // Should almost never emit this",
2122 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
2123 "$dst = $src1 // Should almost never emit!",
2124 [(set PredRegs:$dst, (trunc IntRegs:$src1))]>;
2125 //===----------------------------------------------------------------------===//
2127 //===----------------------------------------------------------------------===//
2129 //===----------------------------------------------------------------------===//
2131 //===----------------------------------------------------------------------===//
2132 // Shift by immediate.
2133 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2134 "$dst = asr($src1, #$src2)",
2135 [(set IntRegs:$dst, (sra IntRegs:$src1, u5ImmPred:$src2))]>;
2137 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2138 "$dst = asr($src1, #$src2)",
2139 [(set DoubleRegs:$dst, (sra DoubleRegs:$src1, u6ImmPred:$src2))]>;
2141 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2142 "$dst = asl($src1, #$src2)",
2143 [(set IntRegs:$dst, (shl IntRegs:$src1, u5ImmPred:$src2))]>;
2145 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2146 "$dst = lsr($src1, #$src2)",
2147 [(set IntRegs:$dst, (srl IntRegs:$src1, u5ImmPred:$src2))]>;
2149 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2150 "$dst = lsr($src1, #$src2)",
2151 [(set DoubleRegs:$dst, (srl DoubleRegs:$src1, u6ImmPred:$src2))]>;
2153 def LSRd_ri_acc : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2156 "$dst += lsr($src2, #$src3)",
2157 [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
2158 (srl DoubleRegs:$src2,
2159 u6ImmPred:$src3)))],
2162 // Shift by immediate and accumulate.
2163 def ASR_rr_acc : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1,
2166 "$dst += asr($src2, $src3)",
2167 [], "$src1 = $dst">;
2169 // Shift by immediate and add.
2170 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2172 "$dst = addasl($src1, $src2, #$src3)",
2173 [(set IntRegs:$dst, (add IntRegs:$src1,
2175 u3ImmPred:$src3)))]>;
2177 // Shift by register.
2178 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2179 "$dst = asl($src1, $src2)",
2180 [(set IntRegs:$dst, (shl IntRegs:$src1, IntRegs:$src2))]>;
2182 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2183 "$dst = asr($src1, $src2)",
2184 [(set IntRegs:$dst, (sra IntRegs:$src1, IntRegs:$src2))]>;
2187 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2188 "$dst = lsr($src1, $src2)",
2189 [(set IntRegs:$dst, (srl IntRegs:$src1, IntRegs:$src2))]>;
2191 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2192 "$dst = lsl($src1, $src2)",
2193 [(set DoubleRegs:$dst, (shl DoubleRegs:$src1, IntRegs:$src2))]>;
2195 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2197 "$dst = asr($src1, $src2)",
2198 [(set DoubleRegs:$dst, (sra DoubleRegs:$src1, IntRegs:$src2))]>;
2200 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2202 "$dst = lsr($src1, $src2)",
2203 [(set DoubleRegs:$dst, (srl DoubleRegs:$src1, IntRegs:$src2))]>;
2205 //===----------------------------------------------------------------------===//
2207 //===----------------------------------------------------------------------===//
2209 //===----------------------------------------------------------------------===//
2211 //===----------------------------------------------------------------------===//
2212 //===----------------------------------------------------------------------===//
2214 //===----------------------------------------------------------------------===//
2216 //===----------------------------------------------------------------------===//
2218 //===----------------------------------------------------------------------===//
2219 //===----------------------------------------------------------------------===//
2221 //===----------------------------------------------------------------------===//
2223 //===----------------------------------------------------------------------===//
2225 //===----------------------------------------------------------------------===//
2227 //===----------------------------------------------------------------------===//
2229 //===----------------------------------------------------------------------===//
2230 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2231 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2234 let hasSideEffects = 1 in
2235 def BARRIER : STInst<(outs), (ins),
2237 [(HexagonBARRIER)]>;
2239 //===----------------------------------------------------------------------===//
2241 //===----------------------------------------------------------------------===//
2243 // TFRI64 - assembly mapped.
2244 let isReMaterializable = 1 in
2245 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2247 [(set DoubleRegs:$dst, s8Imm64Pred:$src1)]>;
2249 // Pseudo instruction to encode a set of conditional transfers.
2250 // This instruction is used instead of a mux and trades-off codesize
2251 // for performance. We conduct this transformation optimistically in
2252 // the hope that these instructions get promoted to dot-new transfers.
2253 let AddedComplexity = 100 in
2254 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
2257 "Error; should not emit",
2258 [(set IntRegs:$dst, (select PredRegs:$src1, IntRegs:$src2,
2261 let AddedComplexity = 100 in
2262 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2263 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2264 "Error; should not emit",
2266 (select PredRegs:$src1, IntRegs:$src2, s12ImmPred:$src3))]>;
2268 let AddedComplexity = 100 in
2269 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2270 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2271 "Error; should not emit",
2273 (select PredRegs:$src1, s12ImmPred:$src2, IntRegs:$src3))]>;
2275 let AddedComplexity = 100 in
2276 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2277 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2278 "Error; should not emit",
2279 [(set IntRegs:$dst, (select PredRegs:$src1,
2281 s12ImmPred:$src3))]>;
2283 // Generate frameindex addresses.
2284 let isReMaterializable = 1 in
2285 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2286 "$dst = add($src1)",
2287 [(set IntRegs:$dst, ADDRri:$src1)]>;
2292 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2293 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2294 "loop0($offset, #$src2)",
2298 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
2299 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2300 "loop0($offset, $src2)",
2304 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
2305 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2306 def ENDLOOP0 : CRInst<(outs), (ins brtarget:$offset),
2311 // Support for generating global address.
2312 // Taken from X86InstrInfo.td.
2313 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
2315 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2316 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2318 // This pattern is incorrect. When we add small data, we should change
2319 // this pattern to use memw(#foo).
2320 let isMoveImm = 1 in
2321 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2322 "$dst = CONST32(#$global)",
2324 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2326 let isReMaterializable = 1, isMoveImm = 1 in
2327 def CONST32_set : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2328 "$dst = CONST32(#$global)",
2330 (HexagonCONST32 tglobaladdr:$global))]>;
2332 let isReMaterializable = 1, isMoveImm = 1 in
2333 def CONST32_set_jt : LDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2334 "$dst = CONST32(#$jt)",
2336 (HexagonCONST32 tjumptable:$jt))]>;
2338 let isReMaterializable = 1, isMoveImm = 1 in
2339 def CONST32GP_set : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2340 "$dst = CONST32(#$global)",
2342 (HexagonCONST32_GP tglobaladdr:$global))]>;
2344 let isReMaterializable = 1, isMoveImm = 1 in
2345 def CONST32_Int_Real : LDInst<(outs IntRegs:$dst), (ins i32imm:$global),
2346 "$dst = CONST32(#$global)",
2347 [(set IntRegs:$dst, imm:$global) ]>;
2349 let isReMaterializable = 1, isMoveImm = 1 in
2350 def CONST32_Label : LDInst<(outs IntRegs:$dst), (ins bblabel:$label),
2351 "$dst = CONST32($label)",
2352 [(set IntRegs:$dst, (HexagonCONST32 bbl:$label))]>;
2354 let isReMaterializable = 1, isMoveImm = 1 in
2355 def CONST64_Int_Real : LDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
2356 "$dst = CONST64(#$global)",
2357 [(set DoubleRegs:$dst, imm:$global) ]>;
2359 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2360 "$dst = xor($dst, $dst)",
2361 [(set PredRegs:$dst, 0)]>;
2363 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2364 "$dst = mpy($src1, $src2)",
2366 (trunc (i64 (srl (i64 (mul (i64 (sext IntRegs:$src1)),
2367 (i64 (sext IntRegs:$src2)))),
2370 // Pseudo instructions.
2371 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2373 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2374 SDTCisVT<1, i32> ]>;
2376 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2377 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2379 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2380 [SDNPHasChain, SDNPOutGlue]>;
2382 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2384 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2385 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2387 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2388 // Optional Flag and Variable Arguments.
2389 // Its 1 Operand has pointer type.
2390 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2391 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2393 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2394 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2395 "Should never be emitted",
2396 [(callseq_start timm:$amt)]>;
2399 let Defs = [R29, R30, R31], Uses = [R29] in {
2400 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2401 "Should never be emitted",
2402 [(callseq_end timm:$amt1, timm:$amt2)]>;
2405 let isCall = 1, neverHasSideEffects = 1,
2406 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2407 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2408 def CALL : JInst<(outs), (ins calltarget:$dst, variable_ops),
2412 // Call subroutine from register.
2413 let isCall = 1, neverHasSideEffects = 1,
2414 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2415 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2416 def CALLR : JRInst<(outs), (ins IntRegs:$dst, variable_ops),
2422 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2423 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2424 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2425 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst, variable_ops),
2426 "jump $dst // TAILCALL", []>;
2428 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2429 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2430 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2431 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst, variable_ops),
2432 "jump $dst // TAILCALL", []>;
2435 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2436 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2437 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2438 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst, variable_ops),
2439 "jumpr $dst // TAILCALL", []>;
2441 // Map call instruction.
2442 def : Pat<(call IntRegs:$dst),
2443 (CALLR IntRegs:$dst)>, Requires<[HasV2TOnly]>;
2444 def : Pat<(call tglobaladdr:$dst),
2445 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2446 def : Pat<(call texternalsym:$dst),
2447 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2449 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2450 (TCRETURNtg tglobaladdr:$dst)>;
2451 def : Pat<(HexagonTCRet texternalsym:$dst),
2452 (TCRETURNtext texternalsym:$dst)>;
2453 def : Pat<(HexagonTCRet IntRegs:$dst),
2454 (TCRETURNR IntRegs:$dst)>;
2456 // Map from r0 = and(r1, 65535) to r0 = zxth(r1).
2457 def : Pat <(and IntRegs:$src1, 65535),
2458 (ZXTH IntRegs:$src1)>;
2460 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2461 def : Pat <(and IntRegs:$src1, 255),
2462 (ZXTB IntRegs:$src1)>;
2464 // Map Add(p1, true) to p1 = not(p1).
2465 // Add(p1, false) should never be produced,
2466 // if it does, it got to be mapped to NOOP.
2467 def : Pat <(add PredRegs:$src1, -1),
2468 (NOT_p PredRegs:$src1)>;
2470 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2471 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2472 def : Pat <(select (i1 (setlt IntRegs:$src1, IntRegs:$src2)), IntRegs:$src3,
2474 (TFR_condset_rr (CMPLTrr IntRegs:$src1, IntRegs:$src2), IntRegs:$src4,
2475 IntRegs:$src3)>, Requires<[HasV2TOnly]>;
2477 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2478 def : Pat <(select (not PredRegs:$src1), s8ImmPred:$src2, s8ImmPred:$src3),
2479 (TFR_condset_ii PredRegs:$src1, s8ImmPred:$src3, s8ImmPred:$src2)>;
2481 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2482 def : Pat <(brcond (not PredRegs:$src1), bb:$offset),
2483 (JMP_cNot PredRegs:$src1, bb:$offset)>;
2485 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2486 def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)),
2487 (AND_pnotp PredRegs:$src1, PredRegs:$src2)>;
2489 // Map from store(globaladdress + x) -> memd(#foo + x).
2490 let AddedComplexity = 100 in
2491 def : Pat <(store DoubleRegs:$src1,
2492 (add (HexagonCONST32_GP tglobaladdr:$global),
2493 u16ImmPred:$offset)),
2494 (STrid_GP tglobaladdr:$global, u16ImmPred:$offset, DoubleRegs:$src1)>;
2496 // Map from store(globaladdress) -> memd(#foo + 0).
2497 let AddedComplexity = 100 in
2498 def : Pat <(store DoubleRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2499 (STrid_GP tglobaladdr:$global, 0, DoubleRegs:$src1)>;
2501 // Map from store(globaladdress + x) -> memw(#foo + x).
2502 let AddedComplexity = 100 in
2503 def : Pat <(store IntRegs:$src1, (add (HexagonCONST32_GP tglobaladdr:$global),
2504 u16ImmPred:$offset)),
2505 (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2507 // Map from store(globaladdress) -> memw(#foo + 0).
2508 let AddedComplexity = 100 in
2509 def : Pat <(store IntRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2510 (STriw_GP tglobaladdr:$global, 0, IntRegs:$src1)>;
2512 // Map from store(globaladdress) -> memw(#foo + 0).
2513 let AddedComplexity = 100 in
2514 def : Pat <(store IntRegs:$src1, (HexagonCONST32_GP tglobaladdr:$global)),
2515 (STriw_GP tglobaladdr:$global, 0, IntRegs:$src1)>;
2517 // Map from store(globaladdress + x) -> memh(#foo + x).
2518 let AddedComplexity = 100 in
2519 def : Pat <(truncstorei16 IntRegs:$src1,
2520 (add (HexagonCONST32_GP tglobaladdr:$global),
2521 u16ImmPred:$offset)),
2522 (STrih_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2524 // Map from store(globaladdress) -> memh(#foo).
2525 let AddedComplexity = 100 in
2526 def : Pat <(truncstorei16 IntRegs:$src1,
2527 (HexagonCONST32_GP tglobaladdr:$global)),
2528 (STh_GP tglobaladdr:$global, IntRegs:$src1)>;
2530 // Map from store(globaladdress + x) -> memb(#foo + x).
2531 let AddedComplexity = 100 in
2532 def : Pat <(truncstorei8 IntRegs:$src1,
2533 (add (HexagonCONST32_GP tglobaladdr:$global),
2534 u16ImmPred:$offset)),
2535 (STrib_GP tglobaladdr:$global, u16ImmPred:$offset, IntRegs:$src1)>;
2537 // Map from store(globaladdress) -> memb(#foo).
2538 let AddedComplexity = 100 in
2539 def : Pat <(truncstorei8 IntRegs:$src1,
2540 (HexagonCONST32_GP tglobaladdr:$global)),
2541 (STb_GP tglobaladdr:$global, IntRegs:$src1)>;
2543 // Map from load(globaladdress + x) -> memw(#foo + x).
2544 let AddedComplexity = 100 in
2545 def : Pat <(load (add (HexagonCONST32_GP tglobaladdr:$global),
2546 u16ImmPred:$offset)),
2547 (LDriw_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2549 // Map from load(globaladdress) -> memw(#foo + 0).
2550 let AddedComplexity = 100 in
2551 def : Pat <(load (HexagonCONST32_GP tglobaladdr:$global)),
2552 (LDw_GP tglobaladdr:$global)>;
2554 // Map from load(globaladdress + x) -> memd(#foo + x).
2555 let AddedComplexity = 100 in
2556 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
2557 u16ImmPred:$offset))),
2558 (LDrid_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2560 // Map from load(globaladdress) -> memw(#foo + 0).
2561 let AddedComplexity = 100 in
2562 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
2563 (LDd_GP tglobaladdr:$global)>;
2566 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress + 0), Pd = Rd.
2567 let AddedComplexity = 100 in
2568 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
2569 (TFR_PdRs (LDrib_GP tglobaladdr:$global, 0))>;
2571 // Map from load(globaladdress + x) -> memh(#foo + x).
2572 let AddedComplexity = 100 in
2573 def : Pat <(sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2574 u16ImmPred:$offset)),
2575 (LDrih_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2577 // Map from load(globaladdress) -> memh(#foo + 0).
2578 let AddedComplexity = 100 in
2579 def : Pat <(sextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2580 (LDrih_GP tglobaladdr:$global, 0)>;
2582 // Map from load(globaladdress + x) -> memuh(#foo + x).
2583 let AddedComplexity = 100 in
2584 def : Pat <(zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2585 u16ImmPred:$offset)),
2586 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2588 // Map from load(globaladdress) -> memuh(#foo + 0).
2589 let AddedComplexity = 100 in
2590 def : Pat <(zextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2591 (LDriuh_GP tglobaladdr:$global, 0)>;
2593 // Map from load(globaladdress + x) -> memuh(#foo + x).
2594 let AddedComplexity = 100 in
2595 def : Pat <(extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
2596 u16ImmPred:$offset)),
2597 (LDriuh_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2599 // Map from load(globaladdress) -> memuh(#foo + 0).
2600 let AddedComplexity = 100 in
2601 def : Pat <(extloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2602 (LDriuh_GP tglobaladdr:$global, 0)>;
2603 // Map from load(globaladdress + x) -> memub(#foo + x).
2604 let AddedComplexity = 100 in
2605 def : Pat <(zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2606 u16ImmPred:$offset)),
2607 (LDriub_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2609 // Map from load(globaladdress) -> memuh(#foo + 0).
2610 let AddedComplexity = 100 in
2611 def : Pat <(zextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2612 (LDriub_GP tglobaladdr:$global, 0)>;
2614 // Map from load(globaladdress + x) -> memb(#foo + x).
2615 let AddedComplexity = 100 in
2616 def : Pat <(sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
2617 u16ImmPred:$offset)),
2618 (LDrib_GP tglobaladdr:$global, u16ImmPred:$offset)>;
2620 // Map from load(globaladdress) -> memb(#foo).
2621 let AddedComplexity = 100 in
2622 def : Pat <(extloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2623 (LDb_GP tglobaladdr:$global)>;
2625 // Map from load(globaladdress) -> memb(#foo).
2626 let AddedComplexity = 100 in
2627 def : Pat <(sextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2628 (LDb_GP tglobaladdr:$global)>;
2630 // Map from load(globaladdress) -> memub(#foo).
2631 let AddedComplexity = 100 in
2632 def : Pat <(zextloadi8 (HexagonCONST32_GP tglobaladdr:$global)),
2633 (LDub_GP tglobaladdr:$global)>;
2635 // When the Interprocedural Global Variable optimizer realizes that a
2636 // certain global variable takes only two constant values, it shrinks the
2637 // global to a boolean. Catch those loads here in the following 3 patterns.
2638 let AddedComplexity = 100 in
2639 def : Pat <(extloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2640 (LDb_GP tglobaladdr:$global)>;
2642 let AddedComplexity = 100 in
2643 def : Pat <(sextloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2644 (LDb_GP tglobaladdr:$global)>;
2646 let AddedComplexity = 100 in
2647 def : Pat <(zextloadi1 (HexagonCONST32_GP tglobaladdr:$global)),
2648 (LDub_GP tglobaladdr:$global)>;
2650 // Map from load(globaladdress) -> memh(#foo).
2651 let AddedComplexity = 100 in
2652 def : Pat <(extloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2653 (LDh_GP tglobaladdr:$global)>;
2655 // Map from load(globaladdress) -> memh(#foo).
2656 let AddedComplexity = 100 in
2657 def : Pat <(sextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2658 (LDh_GP tglobaladdr:$global)>;
2660 // Map from load(globaladdress) -> memuh(#foo).
2661 let AddedComplexity = 100 in
2662 def : Pat <(zextloadi16 (HexagonCONST32_GP tglobaladdr:$global)),
2663 (LDuh_GP tglobaladdr:$global)>;
2665 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2666 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2667 (AND_rr (LDrib ADDRriS11_0:$addr), (TFRI 0x1))>;
2669 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2670 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i32)),
2671 (i64 (SXTW (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg)))>;
2673 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2674 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i16)),
2675 (i64 (SXTW (SXTH (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2677 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2678 def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i8)),
2679 (i64 (SXTW (SXTB (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>;
2681 // We want to prevent emiting pnot's as much as possible.
2682 // Map brcond with an unsupported setcc to a JMP_cNot.
2683 def : Pat <(brcond (i1 (setne IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2684 (JMP_cNot (CMPEQrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2686 def : Pat <(brcond (i1 (setne IntRegs:$src1, s10ImmPred:$src2)), bb:$offset),
2687 (JMP_cNot (CMPEQri IntRegs:$src1, s10ImmPred:$src2), bb:$offset)>;
2689 def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 -1))), bb:$offset),
2690 (JMP_cNot PredRegs:$src1, bb:$offset)>;
2692 def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 0))), bb:$offset),
2693 (JMP_c PredRegs:$src1, bb:$offset)>;
2695 def : Pat <(brcond (i1 (setlt IntRegs:$src1, s8ImmPred:$src2)), bb:$offset),
2696 (JMP_cNot (CMPGEri IntRegs:$src1, s8ImmPred:$src2), bb:$offset)>;
2698 def : Pat <(brcond (i1 (setlt IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2699 (JMP_c (CMPLTrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2701 def : Pat <(brcond (i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)),
2703 (JMP_cNot (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1),
2706 def : Pat <(brcond (i1 (setule IntRegs:$src1, IntRegs:$src2)), bb:$offset),
2707 (JMP_cNot (CMPGTUrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>;
2709 def : Pat <(brcond (i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)),
2711 (JMP_cNot (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2),
2714 // Map from a 64-bit select to an emulated 64-bit mux.
2715 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2716 def : Pat <(select PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
2718 (MUX_rr PredRegs:$src1,
2719 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg),
2720 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_hireg)),
2721 (MUX_rr PredRegs:$src1,
2722 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_loreg),
2723 (EXTRACT_SUBREG DoubleRegs:$src3, subreg_loreg)))>;
2725 // Map from a 1-bit select to logical ops.
2726 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2727 def : Pat <(select PredRegs:$src1, PredRegs:$src2, PredRegs:$src3),
2728 (OR_pp (AND_pp PredRegs:$src1, PredRegs:$src2),
2729 (AND_pp (NOT_p PredRegs:$src1), PredRegs:$src3))>;
2731 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2732 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2733 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2735 // Map for truncating from 64 immediates to 32 bit immediates.
2736 def : Pat<(i32 (trunc DoubleRegs:$src)),
2737 (i32 (EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))>;
2739 // Map for truncating from i64 immediates to i1 bit immediates.
2740 def : Pat<(i1 (trunc DoubleRegs:$src)),
2741 (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>;
2743 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2744 def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr),
2745 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2748 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2749 def : Pat<(truncstorei16 DoubleRegs:$src, ADDRriS11_0:$addr),
2750 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2753 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2754 def : Pat<(truncstorei32 DoubleRegs:$src, ADDRriS11_0:$addr),
2755 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
2758 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2759 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2760 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2762 let AddedComplexity = 100 in
2763 // Map from i1 = constant<-1>; memw(CONST32(#foo)) = i1 -> r0 = 1;
2765 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2766 (STb_GP tglobaladdr:$global, (TFRI 1))>;
2769 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2770 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2771 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2773 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2774 def : Pat<(store PredRegs:$src1, ADDRriS11_2:$addr),
2775 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii PredRegs:$src1, 1, 0)) )>;
2777 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2778 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2779 // Better way to do this?
2780 def : Pat<(i64 (anyext IntRegs:$src1)),
2781 (i64 (SXTW IntRegs:$src1))>;
2783 // Map cmple -> cmpgt.
2784 // rs <= rt -> !(rs > rt).
2785 def : Pat<(i1 (setle IntRegs:$src1, s10ImmPred:$src2)),
2786 (i1 (NOT_p (CMPGTri IntRegs:$src1, s10ImmPred:$src2)))>;
2788 // rs <= rt -> !(rs > rt).
2789 def : Pat<(i1 (setle IntRegs:$src1, IntRegs:$src2)),
2790 (i1 (NOT_p (CMPGTrr IntRegs:$src1, IntRegs:$src2)))>;
2792 // Rss <= Rtt -> !(Rss > Rtt).
2793 def : Pat<(i1 (setle DoubleRegs:$src1, DoubleRegs:$src2)),
2794 (i1 (NOT_p (CMPGT64rr DoubleRegs:$src1, DoubleRegs:$src2)))>;
2796 // Map cmpne -> cmpeq.
2797 // Hexagon_TODO: We should improve on this.
2798 // rs != rt -> !(rs == rt).
2799 def : Pat <(i1 (setne IntRegs:$src1, s10ImmPred:$src2)),
2800 (i1 (NOT_p(i1 (CMPEQri IntRegs:$src1, s10ImmPred:$src2))))>;
2802 // Map cmpne(Rs) -> !cmpeqe(Rs).
2803 // rs != rt -> !(rs == rt).
2804 def : Pat <(i1 (setne IntRegs:$src1, IntRegs:$src2)),
2805 (i1 (NOT_p(i1 (CMPEQrr IntRegs:$src1, IntRegs:$src2))))>;
2807 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2808 def : Pat <(i1 (setne PredRegs:$src1, PredRegs:$src2)),
2809 (i1 (XOR_pp PredRegs:$src1, PredRegs:$src2))>;
2811 // Map cmpne(Rss) -> !cmpew(Rss).
2812 // rs != rt -> !(rs == rt).
2813 def : Pat <(i1 (setne DoubleRegs:$src1, DoubleRegs:$src2)),
2814 (i1 (NOT_p(i1 (CMPEHexagon4rr DoubleRegs:$src1, DoubleRegs:$src2))))>;
2816 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2817 // rs >= rt -> !(rt > rs).
2818 def : Pat <(i1 (setge IntRegs:$src1, IntRegs:$src2)),
2819 (i1 (NOT_p(i1 (CMPGTrr IntRegs:$src2, IntRegs:$src1))))>;
2821 def : Pat <(i1 (setge IntRegs:$src1, s8ImmPred:$src2)),
2822 (i1 (CMPGEri IntRegs:$src1, s8ImmPred:$src2))>;
2824 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2825 // rss >= rtt -> !(rtt > rss).
2826 def : Pat <(i1 (setge DoubleRegs:$src1, DoubleRegs:$src2)),
2827 (i1 (NOT_p(i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))))>;
2829 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2830 // rs < rt -> !(rs >= rt).
2831 def : Pat <(i1 (setlt IntRegs:$src1, s8ImmPred:$src2)),
2832 (i1 (NOT_p (CMPGEri IntRegs:$src1, s8ImmPred:$src2)))>;
2834 // Map cmplt(Rs, Rt) -> cmplt(Rs, Rt).
2835 // rs < rt -> rs < rt. Let assembler map it.
2836 def : Pat <(i1 (setlt IntRegs:$src1, IntRegs:$src2)),
2837 (i1 (CMPLTrr IntRegs:$src2, IntRegs:$src1))>;
2839 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2840 // rss < rtt -> (rtt > rss).
2841 def : Pat <(i1 (setlt DoubleRegs:$src1, DoubleRegs:$src2)),
2842 (i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))>;
2844 // Map from cmpltu(Rs, Rd) -> !cmpgtu(Rs, Rd - 1).
2845 // rs < rt -> rt > rs.
2846 def : Pat <(i1 (setult IntRegs:$src1, IntRegs:$src2)),
2847 (i1 (CMPGTUrr IntRegs:$src2, IntRegs:$src1))>;
2849 // Map from cmpltu(Rss, Rdd) -> !cmpgtu(Rss, Rdd - 1).
2850 // rs < rt -> rt > rs.
2851 def : Pat <(i1 (setult DoubleRegs:$src1, DoubleRegs:$src2)),
2852 (i1 (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1))>;
2854 // Map from Rs >= Rt -> !(Rt > Rs).
2855 // rs >= rt -> !(rt > rs).
2856 def : Pat <(i1 (setuge IntRegs:$src1, IntRegs:$src2)),
2857 (i1 (NOT_p (CMPGTUrr IntRegs:$src2, IntRegs:$src1)))>;
2859 // Map from Rs >= Rt -> !(Rt > Rs).
2860 // rs >= rt -> !(rt > rs).
2861 def : Pat <(i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)),
2862 (i1 (NOT_p (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1)))>;
2864 // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs).
2865 // Map from (Rs <= Rt) -> !(Rs > Rt).
2866 def : Pat <(i1 (setule IntRegs:$src1, IntRegs:$src2)),
2867 (i1 (NOT_p (CMPGTUrr IntRegs:$src1, IntRegs:$src2)))>;
2869 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2870 // Map from (Rs <= Rt) -> !(Rs > Rt).
2871 def : Pat <(i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)),
2872 (i1 (NOT_p (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2)))>;
2876 def : Pat <(i32 (sext PredRegs:$src1)),
2877 (i32 (MUX_ii PredRegs:$src1, -1, 0))>;
2879 // Convert sign-extended load back to load and sign extend.
2881 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2882 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2884 // Convert any-extended load back to load and sign extend.
2886 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2887 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2889 // Convert sign-extended load back to load and sign extend.
2891 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2892 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2894 // Convert sign-extended load back to load and sign extend.
2896 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2897 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2902 def : Pat <(i32 (zext PredRegs:$src1)),
2903 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2906 def : Pat <(i64 (zext PredRegs:$src1)),
2907 (i64 (COMBINE_rr (TFRI 0), (MUX_ii PredRegs:$src1, 1, 0)))>;
2910 def : Pat <(i64 (zext IntRegs:$src1)),
2911 (i64 (COMBINE_rr (TFRI 0), IntRegs:$src1))>;
2914 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2915 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>;
2918 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2919 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>;
2922 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2923 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2925 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2926 (i32 (LDriw ADDRriS11_0:$src1))>;
2928 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2929 def : Pat <(i32 (zext PredRegs:$src1)),
2930 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2932 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2933 def : Pat <(i32 (anyext PredRegs:$src1)),
2934 (i32 (MUX_ii PredRegs:$src1, 1, 0))>;
2936 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2937 def : Pat <(i64 (anyext PredRegs:$src1)),
2938 (i64 (SXTW (i32 (MUX_ii PredRegs:$src1, 1, 0))))>;
2941 // Any extended 64-bit load.
2942 // anyext i32 -> i64
2943 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2944 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>;
2946 // anyext i16 -> i64.
2947 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2948 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>;
2950 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2951 def : Pat<(i64 (zext IntRegs:$src1)),
2952 (i64 (COMBINE_rr (TFRI 0), IntRegs:$src1))>;
2954 // Multiply 64-bit unsigned and use upper result.
2955 def : Pat <(mulhu DoubleRegs:$src1, DoubleRegs:$src2),
2956 (MPYU64_acc(COMBINE_rr (TFRI 0),
2958 (LSRd_ri(MPYU64_acc(MPYU64_acc(COMBINE_rr (TFRI 0),
2959 (EXTRACT_SUBREG (LSRd_ri(MPYU64
2960 (EXTRACT_SUBREG DoubleRegs:$src1,
2962 (EXTRACT_SUBREG DoubleRegs:$src2,
2964 32) ,subreg_loreg)),
2965 (EXTRACT_SUBREG DoubleRegs:$src1,
2967 (EXTRACT_SUBREG DoubleRegs:$src2,
2969 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
2970 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)),
2972 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg),
2973 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)
2976 // Multiply 64-bit signed and use upper result.
2977 def : Pat <(mulhs DoubleRegs:$src1, DoubleRegs:$src2),
2978 (MPY64_acc(COMBINE_rr (TFRI 0),
2980 (LSRd_ri(MPY64_acc(MPY64_acc(COMBINE_rr (TFRI 0),
2981 (EXTRACT_SUBREG (LSRd_ri(MPYU64
2982 (EXTRACT_SUBREG DoubleRegs:$src1,
2984 (EXTRACT_SUBREG DoubleRegs:$src2,
2986 32) ,subreg_loreg)),
2987 (EXTRACT_SUBREG DoubleRegs:$src1,
2989 (EXTRACT_SUBREG DoubleRegs:$src2,
2991 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg),
2992 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)),
2994 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg),
2995 (EXTRACT_SUBREG DoubleRegs:$src2, subreg_hireg)
2998 // Hexagon specific ISD nodes.
2999 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3000 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3001 SDTHexagonADJDYNALLOC>;
3002 // Needed to tag these instructions for stack layout.
3003 let usesCustomInserter = 1 in
3004 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3006 "$dst = add($src1, #$src2)",
3007 [(set IntRegs:$dst, (Hexagon_ADJDYNALLOC IntRegs:$src1,
3008 s16ImmPred:$src2))]>;
3010 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, []>;
3011 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3012 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3014 [(set IntRegs:$dst, (Hexagon_ARGEXTEND IntRegs:$src1))]>;
3016 let AddedComplexity = 100 in
3017 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND IntRegs:$src1), i16)),
3018 (TFR IntRegs:$src1)>;
3021 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3022 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
3024 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
3025 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
3027 [(HexagonBR_JT IntRegs:$src)]>;
3028 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3030 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3031 (CONST32_set_jt tjumptable:$dst)>;
3034 //===----------------------------------------------------------------------===//
3035 // V3 Instructions +
3036 //===----------------------------------------------------------------------===//
3038 include "HexagonInstrInfoV3.td"
3040 //===----------------------------------------------------------------------===//
3041 // V3 Instructions -
3042 //===----------------------------------------------------------------------===//
3044 //===----------------------------------------------------------------------===//
3045 // V4 Instructions +
3046 //===----------------------------------------------------------------------===//
3048 include "HexagonInstrInfoV4.td"