1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
67 //===----------------------------------------------------------------------===//
68 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
70 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
71 : ALU32Inst <(outs PredRegs:$dst),
72 (ins IntRegs:$src1, ImmOp:$src2),
73 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
74 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
78 let CextOpcode = mnemonic;
79 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
80 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
84 let Inst{27-24} = 0b0101;
85 let Inst{23-22} = MajOp;
86 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
87 let Inst{20-16} = src1;
88 let Inst{13-5} = src2{8-0};
94 let isCodeGenOnly = 0 in {
95 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
96 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
97 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
100 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
101 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
102 (MI IntRegs:$src1, ImmPred:$src2)>;
104 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
105 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
106 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
108 //===----------------------------------------------------------------------===//
110 //===----------------------------------------------------------------------===//
111 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
112 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
114 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
116 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
117 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
119 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
120 "$Rd = "#mnemonic#"($Rs, $Rt)",
121 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
122 let isCommutable = IsComm;
123 let BaseOpcode = mnemonic#_rr;
124 let CextOpcode = mnemonic;
132 let Inst{26-24} = MajOp;
133 let Inst{23-21} = MinOp;
134 let Inst{20-16} = !if(OpsRev,Rt,Rs);
135 let Inst{12-8} = !if(OpsRev,Rs,Rt);
139 let hasSideEffects = 0, hasNewValue = 1 in
140 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
141 bit OpsRev, bit PredNot, bit PredNew>
142 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
143 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
144 "$Rd = "#mnemonic#"($Rs, $Rt)",
145 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
146 let isPredicated = 1;
147 let isPredicatedFalse = PredNot;
148 let isPredicatedNew = PredNew;
149 let BaseOpcode = mnemonic#_rr;
150 let CextOpcode = mnemonic;
159 let Inst{26-24} = MajOp;
160 let Inst{23-21} = MinOp;
161 let Inst{20-16} = !if(OpsRev,Rt,Rs);
162 let Inst{13} = PredNew;
163 let Inst{12-8} = !if(OpsRev,Rs,Rt);
164 let Inst{7} = PredNot;
169 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
171 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
172 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
175 let isCodeGenOnly = 0 in {
176 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
177 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
178 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
179 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
182 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
183 bits<3> MinOp, bit OpsRev, bit IsComm>
184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
188 let isCodeGenOnly = 0 in {
189 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
190 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
193 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
194 isCodeGenOnly = 0 in {
195 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
196 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
197 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
198 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
199 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
200 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
203 let Itinerary = ALU32_3op_tc_2_SLOT0123, isCodeGenOnly = 0 in
204 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
206 let isCodeGenOnly = 0 in {
207 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
208 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
211 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
213 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
214 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
215 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
216 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
219 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
220 bit OpsRev, bit IsComm> {
221 let isPredicable = 1 in
222 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
223 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
226 let isCodeGenOnly = 0 in {
227 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
228 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
229 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
230 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
231 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
234 // Pats for instruction selection.
235 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
236 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
237 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
239 def: BinOp32_pat<add, A2_add, i32>;
240 def: BinOp32_pat<and, A2_and, i32>;
241 def: BinOp32_pat<or, A2_or, i32>;
242 def: BinOp32_pat<sub, A2_sub, i32>;
243 def: BinOp32_pat<xor, A2_xor, i32>;
245 // A few special cases producing register pairs:
246 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
247 isCodeGenOnly = 0 in {
248 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
250 let isPredicable = 1 in
251 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
253 // Conditional combinew uses "newt/f" instead of "t/fnew".
254 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
255 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
256 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
257 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
260 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
261 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
262 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
263 "$Pd = "#mnemonic#"($Rs, $Rt)",
264 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
265 let CextOpcode = mnemonic;
266 let isCommutable = IsComm;
272 let Inst{27-24} = 0b0010;
273 let Inst{22-21} = MinOp;
274 let Inst{20-16} = Rs;
277 let Inst{3-2} = 0b00;
281 let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in {
282 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
283 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
284 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
287 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
288 // that reverse the order of the operands.
289 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
291 // Pats for compares. They use PatFrags as operands, not SDNodes,
292 // since seteq/setgt/etc. are defined as ParFrags.
293 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
294 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
295 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
297 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
298 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
299 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
301 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
302 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
304 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1,
306 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
307 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
308 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
314 let CextOpcode = "mux";
315 let InputType = "reg";
316 let hasSideEffects = 0;
319 let Inst{27-24} = 0b0100;
320 let Inst{20-16} = Rs;
326 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
327 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
329 // Combines the two immediates into a double register.
330 // Increase complexity to make it greater than any complexity of a combine
331 // that involves a register.
333 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
334 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
335 AddedComplexity = 75, isCodeGenOnly = 0 in
336 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
337 "$Rdd = combine(#$s8, #$S8)",
338 [(set (i64 DoubleRegs:$Rdd),
339 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
345 let Inst{27-23} = 0b11000;
346 let Inst{22-16} = S8{7-1};
347 let Inst{13} = S8{0};
352 //===----------------------------------------------------------------------===//
353 // Template class for predicated ADD of a reg and an Immediate value.
354 //===----------------------------------------------------------------------===//
355 let hasNewValue = 1, hasSideEffects = 0 in
356 class T_Addri_Pred <bit PredNot, bit PredNew>
357 : ALU32_ri <(outs IntRegs:$Rd),
358 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
359 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
360 ") $Rd = ")#"add($Rs, #$s8)"> {
366 let isPredicatedNew = PredNew;
369 let Inst{27-24} = 0b0100;
370 let Inst{23} = PredNot;
371 let Inst{22-21} = Pu;
372 let Inst{20-16} = Rs;
373 let Inst{13} = PredNew;
378 //===----------------------------------------------------------------------===//
379 // A2_addi: Add a signed immediate to a register.
380 //===----------------------------------------------------------------------===//
381 let hasNewValue = 1, hasSideEffects = 0 in
382 class T_Addri <Operand immOp, list<dag> pattern = [] >
383 : ALU32_ri <(outs IntRegs:$Rd),
384 (ins IntRegs:$Rs, immOp:$s16),
385 "$Rd = add($Rs, #$s16)", pattern,
386 //[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
387 "", ALU32_ADDI_tc_1_SLOT0123> {
394 let Inst{27-21} = s16{15-9};
395 let Inst{20-16} = Rs;
396 let Inst{13-5} = s16{8-0};
400 //===----------------------------------------------------------------------===//
401 // Multiclass for ADD of a register and an immediate value.
402 //===----------------------------------------------------------------------===//
403 multiclass Addri_Pred<string mnemonic, bit PredNot> {
404 let isPredicatedFalse = PredNot in {
405 def _c#NAME : T_Addri_Pred<PredNot, 0>;
407 def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
411 let isExtendable = 1, InputType = "imm" in
412 multiclass Addri_base<string mnemonic, SDNode OpNode> {
413 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
414 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
416 def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
417 [(set (i32 IntRegs:$Rd),
418 (add IntRegs:$Rs, s16ExtPred:$s16))]>;
420 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
421 hasSideEffects = 0, isPredicated = 1 in {
422 defm Pt : Addri_Pred<mnemonic, 0>;
423 defm NotPt : Addri_Pred<mnemonic, 1>;
428 let isCodeGenOnly = 0 in
429 defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
431 //===----------------------------------------------------------------------===//
432 // Template class used for the following ALU32 instructions.
435 //===----------------------------------------------------------------------===//
436 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
437 InputType = "imm", hasNewValue = 1 in
438 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
439 : ALU32_ri <(outs IntRegs:$Rd),
440 (ins IntRegs:$Rs, s10Ext:$s10),
441 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
442 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
446 let CextOpcode = mnemonic;
450 let Inst{27-24} = 0b0110;
451 let Inst{23-22} = MinOp;
452 let Inst{21} = s10{9};
453 let Inst{20-16} = Rs;
454 let Inst{13-5} = s10{8-0};
458 let isCodeGenOnly = 0 in {
459 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
460 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
463 // Subtract register from immediate
464 // Rd32=sub(#s10,Rs32)
465 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
466 CextOpcode = "sub", InputType = "imm", hasNewValue = 1, isCodeGenOnly = 0 in
467 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
468 "$Rd = sub(#$s10, $Rs)" ,
469 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
477 let Inst{27-22} = 0b011001;
478 let Inst{21} = s10{9};
479 let Inst{20-16} = Rs;
480 let Inst{13-5} = s10{8-0};
485 let hasSideEffects = 0, isCodeGenOnly = 0 in
486 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
488 let Inst{27-24} = 0b1111;
490 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
491 def : Pat<(not (i32 IntRegs:$src1)),
492 (SUB_ri -1, (i32 IntRegs:$src1))>;
494 let hasSideEffects = 0, hasNewValue = 1 in
495 class T_tfr16<bit isHi>
496 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
497 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
498 [], "$src1 = $Rx" > {
503 let Inst{27-26} = 0b00;
504 let Inst{25-24} = !if(isHi, 0b10, 0b01);
505 let Inst{23-22} = u16{15-14};
507 let Inst{20-16} = Rx;
508 let Inst{13-0} = u16{13-0};
511 let isCodeGenOnly = 0 in {
512 def A2_tfril: T_tfr16<0>;
513 def A2_tfrih: T_tfr16<1>;
516 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
517 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
518 class T_tfr_pred<bit isPredNot, bit isPredNew>
519 : ALU32Inst<(outs IntRegs:$dst),
520 (ins PredRegs:$src1, IntRegs:$src2),
521 "if ("#!if(isPredNot, "!", "")#
522 "$src1"#!if(isPredNew, ".new", "")#
528 let isPredicatedFalse = isPredNot;
529 let isPredicatedNew = isPredNew;
532 let Inst{27-24} = 0b0100;
533 let Inst{23} = isPredNot;
534 let Inst{13} = isPredNew;
537 let Inst{22-21} = src1;
538 let Inst{20-16} = src2;
541 let isPredicable = 1 in
542 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
549 let Inst{27-21} = 0b0000011;
550 let Inst{20-16} = src;
555 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
556 multiclass tfr_base<string CextOp> {
557 let CextOpcode = CextOp, BaseOpcode = CextOp in {
561 def t : T_tfr_pred<0, 0>;
562 def f : T_tfr_pred<1, 0>;
564 def tnew : T_tfr_pred<0, 1>;
565 def fnew : T_tfr_pred<1, 1>;
569 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
570 // Please don't add bits to this instruction as it'll be converted into
571 // 'combine' before object code emission.
572 let isPredicated = 1 in
573 class T_tfrp_pred<bit PredNot, bit PredNew>
574 : ALU32_rr <(outs DoubleRegs:$dst),
575 (ins PredRegs:$src1, DoubleRegs:$src2),
576 "if ("#!if(PredNot, "!", "")#"$src1"
577 #!if(PredNew, ".new", "")#") $dst = $src2" > {
578 let isPredicatedFalse = PredNot;
579 let isPredicatedNew = PredNew;
582 // Assembler mapped to A2_combinew.
583 // Please don't add bits to this instruction as it'll be converted into
584 // 'combine' before object code emission.
585 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
586 (ins DoubleRegs:$src),
589 let hasSideEffects = 0 in
590 multiclass TFR64_base<string BaseName> {
591 let BaseOpcode = BaseName in {
592 let isPredicable = 1 in
595 def t : T_tfrp_pred <0, 0>;
596 def f : T_tfrp_pred <1, 0>;
598 def tnew : T_tfrp_pred <0, 1>;
599 def fnew : T_tfrp_pred <1, 1>;
603 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
604 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
605 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
606 class T_TFRI_Pred<bit PredNot, bit PredNew>
607 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
608 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
609 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
610 let isPredicatedFalse = PredNot;
611 let isPredicatedNew = PredNew;
618 let Inst{27-24} = 0b1110;
619 let Inst{23} = PredNot;
620 let Inst{22-21} = Pu;
622 let Inst{19-16,12-5} = s12;
623 let Inst{13} = PredNew;
627 let isCodeGenOnly = 0 in {
628 def C2_cmoveit : T_TFRI_Pred<0, 0>;
629 def C2_cmoveif : T_TFRI_Pred<1, 0>;
630 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
631 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
634 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
635 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
636 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
637 isPredicated = 0, isPredicable = 1, isReMaterializable = 1,
639 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
640 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
646 let Inst{27-24} = 0b1000;
647 let Inst{23-22,20-16,13-5} = s16;
651 let isCodeGenOnly = 0 in
652 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
653 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
656 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1 in
657 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
659 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
661 // TODO: see if this instruction can be deleted..
662 let isExtendable = 1, opExtendable = 1, opExtentBits = 6 in
663 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
666 //===----------------------------------------------------------------------===//
668 //===----------------------------------------------------------------------===//
671 //===----------------------------------------------------------------------===//
673 //===----------------------------------------------------------------------===//
674 // Scalar mux register immediate.
675 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
676 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
677 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
678 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
685 let Inst{27-24} = 0b0011;
686 let Inst{23} = MajOp;
687 let Inst{22-21} = Pu;
688 let Inst{20-16} = Rs;
694 let opExtendable = 2, isCodeGenOnly = 0 in
695 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
696 "$Rd = mux($Pu, #$s8, $Rs)">;
698 let opExtendable = 3, isCodeGenOnly = 0 in
699 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
700 "$Rd = mux($Pu, $Rs, #$s8)">;
702 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
703 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
705 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
706 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
708 // C2_muxii: Scalar mux immediates.
709 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
710 opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
711 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
712 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
713 "$Rd = mux($Pu, #$s8, #$S8)" ,
714 [(set (i32 IntRegs:$Rd),
715 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
723 let Inst{27-25} = 0b101;
724 let Inst{24-23} = Pu;
725 let Inst{22-16} = S8{7-1};
726 let Inst{13} = S8{0};
731 //===----------------------------------------------------------------------===//
732 // template class for non-predicated alu32_2op instructions
733 // - aslh, asrh, sxtb, sxth, zxth
734 //===----------------------------------------------------------------------===//
735 let hasNewValue = 1, opNewValue = 0 in
736 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
737 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
738 "$Rd = "#mnemonic#"($Rs)", [] > {
744 let Inst{27-24} = 0b0000;
745 let Inst{23-21} = minOp;
748 let Inst{20-16} = Rs;
751 //===----------------------------------------------------------------------===//
752 // template class for predicated alu32_2op instructions
753 // - aslh, asrh, sxtb, sxth, zxtb, zxth
754 //===----------------------------------------------------------------------===//
755 let hasSideEffects = 0, validSubTargets = HasV4SubT,
756 hasNewValue = 1, opNewValue = 0 in
757 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
759 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
760 !if(isPredNot, "if (!$Pu", "if ($Pu")
761 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
768 let Inst{27-24} = 0b0000;
769 let Inst{23-21} = minOp;
771 let Inst{11} = isPredNot;
772 let Inst{10} = isPredNew;
775 let Inst{20-16} = Rs;
778 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
779 let isPredicatedFalse = PredNot in {
780 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
783 let isPredicatedNew = 1 in
784 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
788 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
789 let BaseOpcode = mnemonic in {
790 let isPredicable = 1, hasSideEffects = 0 in
791 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
793 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
794 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
795 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
800 let isCodeGenOnly = 0 in {
801 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
802 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
803 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
804 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
805 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
808 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
809 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
810 // predicated forms while 'and' doesn't. Since integrated assembler can't
811 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
812 // immediate operand is set to '255'.
814 let hasNewValue = 1, opNewValue = 0 in
815 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
816 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
823 let Inst{27-22} = 0b011000;
825 let Inst{20-16} = Rs;
826 let Inst{21} = s10{9};
827 let Inst{13-5} = s10{8-0};
830 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
831 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
832 let BaseOpcode = mnemonic in {
833 let isPredicable = 1, hasSideEffects = 0 in
834 def A2_#NAME : T_ZXTB;
836 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
837 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
838 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
843 let isCodeGenOnly=0 in
844 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
846 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
847 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
848 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
849 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
851 //===----------------------------------------------------------------------===//
852 // Template class for vector add and avg
853 //===----------------------------------------------------------------------===//
855 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
856 bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
857 : ALU64_rr < (outs DoubleRegs:$Rdd),
858 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
859 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
860 #!if(isCrnd,":crnd","")
861 #!if(isSat, ":sat", ""),
862 [], "", ALU64_tc_2_SLOT23 > {
869 let Inst{27-24} = 0b0011;
870 let Inst{23-21} = majOp;
871 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
872 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
873 let Inst{7-5} = minOp;
877 // ALU64 - Vector add
878 // Rdd=vadd[u][bhw](Rss,Rtt)
879 let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
880 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
881 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
882 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
885 // Rdd=vadd[u][bhw](Rss,Rtt):sat
886 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
887 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
888 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
889 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
890 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
893 // ALU64 - Vector average
894 // Rdd=vavg[u][bhw](Rss,Rtt)
895 let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
896 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
897 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
898 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
899 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
900 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
903 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
904 let isCodeGenOnly = 0 in {
905 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
906 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
907 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
908 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
911 let isCodeGenOnly = 0 in {
912 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
913 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
914 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
917 // Rdd=vnavg[bh](Rss,Rtt)
918 let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
919 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
920 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
923 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
924 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
925 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
926 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
927 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
928 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
931 // Rdd=vsub[u][bh](Rss,Rtt)
932 let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
933 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
934 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
935 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
938 // Rdd=vsub[u][bh](Rss,Rtt):sat
939 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
940 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
941 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
942 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
943 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
946 // Rdd=vmax[u][bhw](Rss,Rtt)
947 let isCodeGenOnly = 0 in {
948 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
949 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
950 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
951 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
952 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
953 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
956 // Rdd=vmin[u][bhw](Rss,Rtt)
957 let isCodeGenOnly = 0 in {
958 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
959 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
960 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
961 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
962 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
963 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
966 //===----------------------------------------------------------------------===//
967 // Template class for vector compare
968 //===----------------------------------------------------------------------===//
969 let hasSideEffects = 0 in
970 class T_vcmp <string Str, bits<4> minOp>
971 : ALU64_rr <(outs PredRegs:$Pd),
972 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
973 "$Pd = "#Str#"($Rss, $Rtt)", [],
974 "", ALU64_tc_2early_SLOT23> {
981 let Inst{27-23} = 0b00100;
982 let Inst{13} = minOp{3};
983 let Inst{7-5} = minOp{2-0};
985 let Inst{20-16} = Rss;
986 let Inst{12-8} = Rtt;
989 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
990 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
991 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
993 // Vector compare bytes
994 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
995 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
997 // Vector compare halfwords
998 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
999 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
1000 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
1002 // Vector compare words
1003 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
1004 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
1005 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
1007 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
1008 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
1009 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
1010 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
1011 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
1012 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
1013 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
1014 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
1016 //===----------------------------------------------------------------------===//
1018 //===----------------------------------------------------------------------===//
1021 //===----------------------------------------------------------------------===//
1023 //===----------------------------------------------------------------------===//
1025 //===----------------------------------------------------------------------===//
1027 //===----------------------------------------------------------------------===//
1030 //===----------------------------------------------------------------------===//
1032 //===----------------------------------------------------------------------===//// Add.
1033 //===----------------------------------------------------------------------===//
1035 // Add/Subtract halfword
1036 // Rd=add(Rt.L,Rs.[HL])[:sat]
1037 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1038 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1039 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1040 //===----------------------------------------------------------------------===//
1042 let hasNewValue = 1, opNewValue = 0 in
1043 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1044 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1045 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1046 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
1047 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
1048 #!if(isSat,":sat","")
1049 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
1053 let IClass = 0b1101;
1055 let Inst{27-23} = 0b01010;
1056 let Inst{22} = hasShift;
1057 let Inst{21} = isSub;
1058 let Inst{7} = isSat;
1059 let Inst{6-5} = LHbits;
1061 let Inst{12-8} = Rt;
1062 let Inst{20-16} = Rs;
1065 //Rd=sub(Rt.L,Rs.[LH])
1066 let isCodeGenOnly = 0 in {
1067 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1068 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1071 let isCodeGenOnly = 0 in {
1072 //Rd=add(Rt.L,Rs.[LH])
1073 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1074 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1077 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1078 //Rd=sub(Rt.L,Rs.[LH]):sat
1079 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1080 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1082 //Rd=add(Rt.L,Rs.[LH]):sat
1083 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1084 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1087 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1088 let isCodeGenOnly = 0 in {
1089 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1090 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1091 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1092 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1095 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1096 let isCodeGenOnly = 0 in {
1097 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1098 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1099 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
1100 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1103 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1104 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1105 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1106 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1107 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
1108 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1110 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1111 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1112 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1113 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
1114 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
1118 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
1119 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
1121 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
1122 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1124 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1125 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1127 // Subtract halfword.
1128 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1129 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1131 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1132 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1134 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1135 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1136 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1137 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1142 let IClass = 0b1101;
1143 let Inst{27-24} = 0b0000;
1144 let Inst{20-16} = Rs;
1145 let Inst{12-8} = Rt;
1149 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1150 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1151 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1152 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1153 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1158 let IClass = 0b1101;
1160 let Inst{27-23} = 0b01011;
1161 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1162 let Inst{7} = isUnsigned;
1164 let Inst{12-8} = !if(isMax, Rs, Rt);
1165 let Inst{20-16} = !if(isMax, Rt, Rs);
1168 let isCodeGenOnly = 0 in {
1169 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1170 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1171 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1172 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1175 // Here, depending on the operand being selected, we'll either generate a
1176 // min or max instruction.
1178 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1179 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1180 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1181 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1183 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1184 InstHexagon Inst, InstHexagon SwapInst> {
1185 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1186 (VT RC:$src1), (VT RC:$src2)),
1187 (Inst RC:$src1, RC:$src2)>;
1188 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1189 (VT RC:$src2), (VT RC:$src1)),
1190 (SwapInst RC:$src1, RC:$src2)>;
1194 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1195 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1197 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1198 (i32 PositiveHalfWord:$src2))),
1199 (i32 PositiveHalfWord:$src1),
1200 (i32 PositiveHalfWord:$src2))), i16),
1201 (Inst IntRegs:$src1, IntRegs:$src2)>;
1203 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1204 (i32 PositiveHalfWord:$src2))),
1205 (i32 PositiveHalfWord:$src2),
1206 (i32 PositiveHalfWord:$src1))), i16),
1207 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1210 let AddedComplexity = 200 in {
1211 defm: MinMax_pats<setge, A2_max, A2_min>;
1212 defm: MinMax_pats<setgt, A2_max, A2_min>;
1213 defm: MinMax_pats<setle, A2_min, A2_max>;
1214 defm: MinMax_pats<setlt, A2_min, A2_max>;
1215 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1216 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1217 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1218 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1221 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1222 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1223 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1225 let isCommutable = IsComm;
1226 let hasSideEffects = 0;
1232 let IClass = 0b1101;
1233 let Inst{27-21} = 0b0010100;
1234 let Inst{20-16} = Rs;
1235 let Inst{12-8} = Rt;
1236 let Inst{7-5} = MinOp;
1240 let isCodeGenOnly = 0 in {
1241 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1242 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1243 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1246 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1247 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1248 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1250 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1251 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1252 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1253 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1254 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1256 let isCodeGenOnly = 0 in
1257 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1258 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1259 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1260 let hasSideEffects = 0;
1267 let IClass = 0b1101;
1268 let Inst{27-24} = 0b0001;
1269 let Inst{20-16} = Rs;
1270 let Inst{12-8} = Rt;
1275 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1276 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1278 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1279 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1280 "", ALU64_tc_1_SLOT23> {
1281 let hasSideEffects = 0;
1282 let isCommutable = IsComm;
1288 let IClass = 0b1101;
1289 let Inst{27-24} = RegType;
1290 let Inst{23-21} = MajOp;
1291 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1292 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1293 let Inst{7-5} = MinOp;
1297 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1298 bit OpsRev, bit IsComm>
1299 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1302 let isCodeGenOnly = 0 in {
1303 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1304 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1307 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1308 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1310 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1312 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1315 let isCodeGenOnly = 0 in {
1316 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1317 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1318 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1321 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1322 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1323 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1325 //===----------------------------------------------------------------------===//
1327 //===----------------------------------------------------------------------===//
1329 //===----------------------------------------------------------------------===//
1331 //===----------------------------------------------------------------------===//
1333 //===----------------------------------------------------------------------===//
1335 //===----------------------------------------------------------------------===//
1337 //===----------------------------------------------------------------------===//
1339 //===----------------------------------------------------------------------===//
1341 //===----------------------------------------------------------------------===//
1343 //===----------------------------------------------------------------------===//
1345 //===----------------------------------------------------------------------===//
1347 //===----------------------------------------------------------------------===//
1348 // Logical reductions on predicates.
1350 // Looping instructions.
1352 // Pipelined looping instructions.
1354 // Logical operations on predicates.
1355 let hasSideEffects = 0 in
1356 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1357 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1358 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1362 let IClass = 0b0110;
1363 let Inst{27-23} = 0b10111;
1364 let Inst{22-21} = OpBits;
1366 let Inst{17-16} = Ps;
1371 let isCodeGenOnly = 0 in {
1372 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1373 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1374 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1377 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1378 (C2_not PredRegs:$Ps)>;
1380 let hasSideEffects = 0 in
1381 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1382 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1383 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1384 [], "", CR_tc_2early_SLOT23> {
1389 let IClass = 0b0110;
1390 let Inst{27-24} = 0b1011;
1391 let Inst{23-21} = OpBits;
1393 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1394 let Inst{13} = 0b0; // instructions.
1395 let Inst{9-8} = !if(Rev,Ps,Pt);
1399 let isCodeGenOnly = 0 in {
1400 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1401 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1402 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1403 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1404 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1407 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1408 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1409 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1410 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1411 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1413 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1414 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1415 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1420 let IClass = 0b1000;
1421 let Inst{27-24} = 0b1001;
1422 let Inst{22-21} = 0b00;
1423 let Inst{17-16} = Ps;
1428 let hasSideEffects = 0, isCodeGenOnly = 0 in
1429 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1430 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1434 let IClass = 0b1000;
1435 let Inst{27-24} = 0b0110;
1440 // User control register transfer.
1441 //===----------------------------------------------------------------------===//
1443 //===----------------------------------------------------------------------===//
1445 //===----------------------------------------------------------------------===//
1447 //===----------------------------------------------------------------------===//
1449 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1450 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1451 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1453 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1454 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1456 class CondStr<string CReg, bit True, bit New> {
1457 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1459 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1460 string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
1463 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1465 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1466 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1467 class T_JMP<string ExtStr>
1468 : JInst<(outs), (ins brtarget:$dst),
1469 "jump " # ExtStr # "$dst",
1470 [], "", J_tc_2early_SLOT23> {
1472 let IClass = 0b0101;
1474 let Inst{27-25} = 0b100;
1475 let Inst{24-16} = dst{23-15};
1476 let Inst{13-1} = dst{14-2};
1479 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1480 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1481 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1482 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1483 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1484 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1485 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1487 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1488 let isTaken = isTak;
1489 let isPredicatedFalse = PredNot;
1490 let isPredicatedNew = isPredNew;
1494 let IClass = 0b0101;
1496 let Inst{27-24} = 0b1100;
1497 let Inst{21} = PredNot;
1498 let Inst{12} = !if(isPredNew, isTak, zero);
1499 let Inst{11} = isPredNew;
1500 let Inst{9-8} = src;
1501 let Inst{23-22} = dst{16-15};
1502 let Inst{20-16} = dst{14-10};
1503 let Inst{13} = dst{9};
1504 let Inst{7-1} = dst{8-2};
1507 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1508 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
1510 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1511 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1514 multiclass JMP_base<string BaseOp, string ExtStr> {
1515 let BaseOpcode = BaseOp in {
1516 def NAME : T_JMP<ExtStr>;
1517 defm t : JMP_Pred<0, ExtStr>;
1518 defm f : JMP_Pred<1, ExtStr>;
1522 // Jumps to address stored in a register, JUMPR_MISC
1523 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1524 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1525 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1527 : JRInst<(outs), (ins IntRegs:$dst),
1528 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1531 let IClass = 0b0101;
1532 let Inst{27-21} = 0b0010100;
1533 let Inst{20-16} = dst;
1536 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1537 hasSideEffects = 0, InputType = "reg" in
1538 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1539 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1540 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1541 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1542 "", J_tc_2early_SLOT2> {
1544 let isTaken = isTak;
1545 let isPredicatedFalse = PredNot;
1546 let isPredicatedNew = isPredNew;
1550 let IClass = 0b0101;
1552 let Inst{27-22} = 0b001101;
1553 let Inst{21} = PredNot;
1554 let Inst{20-16} = dst;
1555 let Inst{12} = !if(isPredNew, isTak, zero);
1556 let Inst{11} = isPredNew;
1557 let Inst{9-8} = src;
1560 multiclass JMPR_Pred<bit PredNot> {
1561 def NAME: T_JMPr_c<PredNot, 0, 0>;
1563 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1564 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1567 multiclass JMPR_base<string BaseOp> {
1568 let BaseOpcode = BaseOp in {
1570 defm t : JMPR_Pred<0>;
1571 defm f : JMPR_Pred<1>;
1575 let isCall = 1, hasSideEffects = 1 in
1576 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1577 dag InputDag = (ins IntRegs:$Rs)>
1578 : JRInst<(outs), InputDag,
1579 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1580 "if ($Pu) callr $Rs"),
1582 [], "", J_tc_2early_SLOT2> {
1585 let isPredicated = isPred;
1586 let isPredicatedFalse = isPredNot;
1588 let IClass = 0b0101;
1589 let Inst{27-25} = 0b000;
1590 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1592 let Inst{21} = isPredNot;
1593 let Inst{9-8} = !if (isPred, Pu, 0b00);
1594 let Inst{20-16} = Rs;
1598 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
1599 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1600 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1603 let isTerminator = 1, hasSideEffects = 0, isCodeGenOnly = 0 in {
1604 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1606 // Deal with explicit assembly
1607 // - never extened a jump #, always extend a jump ##
1608 let isAsmParserOnly = 1 in {
1609 defm J2_jump_ext : JMP_base<"JMP", "##">;
1610 defm J2_jump_noext : JMP_base<"JMP", "#">;
1613 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1615 let isReturn = 1, isCodeGenOnly = 1 in
1616 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1619 def: Pat<(br bb:$dst),
1620 (J2_jump brtarget:$dst)>;
1622 (JMPret (i32 R31))>;
1623 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1624 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1626 // A return through builtin_eh_return.
1627 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1628 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1629 def EH_RETURN_JMPR : T_JMPr;
1631 def: Pat<(eh_return),
1632 (EH_RETURN_JMPR (i32 R31))>;
1633 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1634 (J2_jumpr IntRegs:$dst)>;
1635 def: Pat<(brind (i32 IntRegs:$dst)),
1636 (J2_jumpr IntRegs:$dst)>;
1638 //===----------------------------------------------------------------------===//
1640 //===----------------------------------------------------------------------===//
1642 //===----------------------------------------------------------------------===//
1644 //===----------------------------------------------------------------------===//
1645 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1646 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1648 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1649 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1654 bits<11> offsetBits;
1656 string ImmOpStr = !cast<string>(ImmOp);
1657 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1658 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1659 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1660 /* s11_0Ext */ offset{10-0})));
1661 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1662 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1663 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1664 /* s11_0Ext */ 11)));
1665 let hasNewValue = !if (!eq(ImmOpStr, "s11_3Ext"), 0, 1);
1667 let IClass = 0b1001;
1670 let Inst{26-25} = offsetBits{10-9};
1671 let Inst{24-21} = MajOp;
1672 let Inst{20-16} = src1;
1673 let Inst{13-5} = offsetBits{8-0};
1674 let Inst{4-0} = dst;
1677 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1678 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1679 Operand ImmOp, bit isNot, bit isPredNew>
1680 : LDInst<(outs RC:$dst),
1681 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1682 "if ("#!if(isNot, "!$src1", "$src1")
1683 #!if(isPredNew, ".new", "")
1684 #") $dst = "#mnemonic#"($src2 + #$offset)",
1685 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1691 string ImmOpStr = !cast<string>(ImmOp);
1693 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1694 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1695 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1696 /* u6_0Ext */ offset{5-0})));
1697 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1698 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1699 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1701 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1702 let isPredicatedNew = isPredNew;
1703 let isPredicatedFalse = isNot;
1705 let IClass = 0b0100;
1709 let Inst{26} = isNot;
1710 let Inst{25} = isPredNew;
1711 let Inst{24-21} = MajOp;
1712 let Inst{20-16} = src2;
1714 let Inst{12-11} = src1;
1715 let Inst{10-5} = offsetBits;
1716 let Inst{4-0} = dst;
1719 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1720 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1721 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1722 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1723 let isPredicable = 1 in
1724 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1727 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1728 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1731 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1732 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1736 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1737 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1738 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1741 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1742 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1743 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1746 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1747 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1749 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1750 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1752 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1753 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1754 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1757 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in {
1758 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
1759 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
1762 // Patterns to select load-indexed (i.e. load from base+offset).
1763 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1765 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1766 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1767 (VT (MI IntRegs:$Rs, imm:$Off))>;
1768 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1771 let AddedComplexity = 20 in {
1772 defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
1773 defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
1774 defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
1775 defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
1776 defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
1777 defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
1779 defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1780 defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1781 defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1782 defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
1783 defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
1784 defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1785 defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1786 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1790 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1791 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1793 let AddedComplexity = 20 in
1794 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1795 (SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1797 //===----------------------------------------------------------------------===//
1798 // Post increment load
1799 //===----------------------------------------------------------------------===//
1800 //===----------------------------------------------------------------------===//
1801 // Template class for non-predicated post increment loads with immediate offset.
1802 //===----------------------------------------------------------------------===//
1803 let hasSideEffects = 0, addrMode = PostInc in
1804 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1806 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1807 (ins IntRegs:$src1, ImmOp:$offset),
1808 "$dst = "#mnemonic#"($src1++#$offset)" ,
1817 string ImmOpStr = !cast<string>(ImmOp);
1818 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1819 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1820 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1821 /* s4_0Imm */ offset{3-0})));
1822 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1824 let IClass = 0b1001;
1826 let Inst{27-25} = 0b101;
1827 let Inst{24-21} = MajOp;
1828 let Inst{20-16} = src1;
1829 let Inst{13-12} = 0b00;
1830 let Inst{8-5} = offsetBits;
1831 let Inst{4-0} = dst;
1834 //===----------------------------------------------------------------------===//
1835 // Template class for predicated post increment loads with immediate offset.
1836 //===----------------------------------------------------------------------===//
1837 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1838 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1839 bits<4> MajOp, bit isPredNot, bit isPredNew >
1840 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1841 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1842 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1843 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1853 let isPredicatedNew = isPredNew;
1854 let isPredicatedFalse = isPredNot;
1856 string ImmOpStr = !cast<string>(ImmOp);
1857 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1858 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1859 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1860 /* s4_0Imm */ offset{3-0})));
1861 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1863 let IClass = 0b1001;
1865 let Inst{27-25} = 0b101;
1866 let Inst{24-21} = MajOp;
1867 let Inst{20-16} = src2;
1869 let Inst{12} = isPredNew;
1870 let Inst{11} = isPredNot;
1871 let Inst{10-9} = src1;
1872 let Inst{8-5} = offsetBits;
1873 let Inst{4-0} = dst;
1876 //===----------------------------------------------------------------------===//
1877 // Multiclass for post increment loads with immediate offset.
1878 //===----------------------------------------------------------------------===//
1880 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1881 Operand ImmOp, bits<4> MajOp> {
1882 let BaseOpcode = "POST_"#BaseOp in {
1883 let isPredicable = 1 in
1884 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1887 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1888 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1891 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1892 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1896 // post increment byte loads with immediate offset
1897 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1898 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1899 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1902 // post increment halfword loads with immediate offset
1903 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1904 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1905 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1908 // post increment word loads with immediate offset
1909 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1910 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1912 // post increment doubleword loads with immediate offset
1913 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1914 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1916 // Rd=memb[u]h(Rx++#s4:1)
1917 // Rdd=memb[u]h(Rx++#s4:2)
1918 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1919 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1920 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1922 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0,
1923 isCodeGenOnly = 0 in {
1924 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
1925 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
1928 //===----------------------------------------------------------------------===//
1929 // Template class for post increment loads with register offset.
1930 //===----------------------------------------------------------------------===//
1931 let hasSideEffects = 0, addrMode = PostInc in
1932 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1933 MemAccessSize AccessSz>
1934 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1935 (ins IntRegs:$src1, ModRegs:$src2),
1936 "$dst = "#mnemonic#"($src1++$src2)" ,
1937 [], "$src1 = $_dst_" > {
1942 let accessSize = AccessSz;
1943 let IClass = 0b1001;
1945 let Inst{27-25} = 0b110;
1946 let Inst{24-21} = MajOp;
1947 let Inst{20-16} = src1;
1948 let Inst{13} = src2;
1951 let Inst{4-0} = dst;
1954 let hasNewValue = 1, isCodeGenOnly = 0 in {
1955 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1956 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1957 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1958 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1959 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
1961 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
1964 let isCodeGenOnly = 0 in {
1965 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
1966 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
1970 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1971 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1972 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1974 "Error; should not emit",
1977 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0, isCodeGenOnly = 0 in
1978 def L2_deallocframe : LDInst<(outs), (ins),
1981 let IClass = 0b1001;
1983 let Inst{27-16} = 0b000000011110;
1985 let Inst{4-0} = 0b11110;
1988 // Load / Post increment circular addressing mode.
1989 let Uses = [CS], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1990 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
1991 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
1992 (ins IntRegs:$Rz, ModRegs:$Mu),
1993 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
1999 let IClass = 0b1001;
2001 let Inst{27-25} = 0b100;
2002 let Inst{24-21} = MajOp;
2003 let Inst{20-16} = Rz;
2008 let Inst{4-0} = dst;
2011 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
2012 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2013 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
2016 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
2017 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
2018 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2019 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
2020 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2023 let accessSize = WordAccess, isCodeGenOnly = 0 in {
2024 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2025 let hasNewValue = 0 in {
2026 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
2027 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
2031 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2032 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
2034 //===----------------------------------------------------------------------===//
2035 // Circular loads with immediate offset.
2036 //===----------------------------------------------------------------------===//
2037 let Uses = [CS], mayLoad = 1, hasSideEffects = 0, hasNewValue = 1 in
2038 class T_load_pci <string mnemonic, RegisterClass RC,
2039 Operand ImmOp, bits<4> MajOp>
2040 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2041 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2042 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
2050 string ImmOpStr = !cast<string>(ImmOp);
2051 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2052 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2053 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2054 /* s4_0Imm */ offset{3-0})));
2055 let IClass = 0b1001;
2056 let Inst{27-25} = 0b100;
2057 let Inst{24-21} = MajOp;
2058 let Inst{20-16} = Rz;
2062 let Inst{8-5} = offsetBits;
2063 let Inst{4-0} = dst;
2066 // Byte variants of circ load
2067 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
2068 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2069 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2072 // Half word variants of circ load
2073 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
2074 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2075 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2076 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2077 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2080 // Word variants of circ load
2081 let accessSize = WordAccess, isCodeGenOnly = 0 in
2082 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2084 let accessSize = WordAccess, hasNewValue = 0, isCodeGenOnly = 0 in {
2085 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
2086 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
2089 let accessSize = DoubleWordAccess, hasNewValue = 0, isCodeGenOnly = 0 in
2090 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2092 // L[24]_load[wd]_locked: Load word/double with lock.
2094 class T_load_locked <string mnemonic, RegisterClass RC>
2095 : LD0Inst <(outs RC:$dst),
2097 "$dst = "#mnemonic#"($src)"> {
2100 let IClass = 0b1001;
2101 let Inst{27-21} = 0b0010000;
2102 let Inst{20-16} = src;
2103 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2104 let Inst{4-0} = dst;
2106 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0, isCodeGenOnly = 0 in
2107 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2108 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2109 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
2111 // S[24]_store[wd]_locked: Store word/double conditionally.
2112 let isSoloAX = 1, isPredicateLate = 1 in
2113 class T_store_locked <string mnemonic, RegisterClass RC>
2114 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2115 mnemonic#"($Rs, $Pd) = $Rt"> {
2120 let IClass = 0b1010;
2121 let Inst{27-23} = 0b00001;
2122 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
2124 let Inst{20-16} = Rs;
2125 let Inst{12-8} = Rt;
2129 let accessSize = WordAccess, isCodeGenOnly = 0 in
2130 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2132 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2133 def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
2135 //===----------------------------------------------------------------------===//
2136 // Bit-reversed loads with auto-increment register
2137 //===----------------------------------------------------------------------===//
2138 let hasSideEffects = 0 in
2139 class T_load_pbr<string mnemonic, RegisterClass RC,
2140 MemAccessSize addrSize, bits<4> majOp>
2142 <(outs RC:$dst, IntRegs:$_dst_),
2143 (ins IntRegs:$Rz, ModRegs:$Mu),
2144 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
2145 [] , "$Rz = $_dst_" > {
2147 let accessSize = addrSize;
2153 let IClass = 0b1001;
2155 let Inst{27-25} = 0b111;
2156 let Inst{24-21} = majOp;
2157 let Inst{20-16} = Rz;
2161 let Inst{4-0} = dst;
2164 let hasNewValue =1, opNewValue = 0, isCodeGenOnly = 0 in {
2165 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2166 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2167 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2168 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2169 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2170 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2171 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2174 let isCodeGenOnly = 0 in {
2175 def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
2176 def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
2177 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2180 //===----------------------------------------------------------------------===//
2182 //===----------------------------------------------------------------------===//
2184 //===----------------------------------------------------------------------===//
2186 //===----------------------------------------------------------------------===//
2187 //===----------------------------------------------------------------------===//
2189 //===----------------------------------------------------------------------===//
2191 //===----------------------------------------------------------------------===//
2193 //===----------------------------------------------------------------------===//
2194 //===----------------------------------------------------------------------===//
2196 //===----------------------------------------------------------------------===//
2198 //===----------------------------------------------------------------------===//
2200 //===----------------------------------------------------------------------===//
2202 //===----------------------------------------------------------------------===//
2204 // MPYS / Multipy signed/unsigned halfwords
2205 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2206 //===----------------------------------------------------------------------===//
2208 let hasNewValue = 1, opNewValue = 0 in
2209 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
2210 bit hasShift, bit isUnsigned>
2211 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2212 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2213 #", $Rt."#!if(LHbits{0},"h)","l)")
2214 #!if(hasShift,":<<1","")
2215 #!if(isRnd,":rnd","")
2216 #!if(isSat,":sat",""),
2217 [], "", M_tc_3x_SLOT23 > {
2222 let IClass = 0b1110;
2224 let Inst{27-24} = 0b1100;
2225 let Inst{23} = hasShift;
2226 let Inst{22} = isUnsigned;
2227 let Inst{21} = isRnd;
2228 let Inst{7} = isSat;
2229 let Inst{6-5} = LHbits;
2231 let Inst{20-16} = Rs;
2232 let Inst{12-8} = Rt;
2235 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2236 let isCodeGenOnly = 0 in {
2237 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2238 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2239 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2240 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2241 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
2242 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
2243 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2244 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2247 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2248 let isCodeGenOnly = 0 in {
2249 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2250 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2251 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2252 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2253 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2254 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2255 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2256 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2259 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2260 let isCodeGenOnly = 0 in {
2261 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2262 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2263 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2264 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2265 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2266 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2267 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2268 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2271 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2272 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2273 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
2274 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2275 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2276 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2277 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2278 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2279 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2280 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2281 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2283 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2284 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2285 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2286 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2287 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2288 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2289 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2290 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2293 //===----------------------------------------------------------------------===//
2295 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2296 // result from the accumulator.
2297 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2298 //===----------------------------------------------------------------------===//
2300 let hasNewValue = 1, opNewValue = 0 in
2301 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2302 bit hasShift, bit isUnsigned >
2303 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2304 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2305 #"($Rs."#!if(LHbits{1},"h","l")
2306 #", $Rt."#!if(LHbits{0},"h)","l)")
2307 #!if(hasShift,":<<1","")
2308 #!if(isSat,":sat",""),
2309 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2314 let IClass = 0b1110;
2315 let Inst{27-24} = 0b1110;
2316 let Inst{23} = hasShift;
2317 let Inst{22} = isUnsigned;
2318 let Inst{21} = isNac;
2319 let Inst{7} = isSat;
2320 let Inst{6-5} = LHbits;
2322 let Inst{20-16} = Rs;
2323 let Inst{12-8} = Rt;
2326 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2327 let isCodeGenOnly = 0 in {
2328 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2329 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2330 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2331 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2332 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2333 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2334 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2335 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2338 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2339 let isCodeGenOnly = 0 in {
2340 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2341 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2342 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2343 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2344 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2345 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2346 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2347 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2350 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2351 let isCodeGenOnly = 0 in {
2352 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2353 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2354 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2355 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2356 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2357 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2358 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2359 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2362 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2363 let isCodeGenOnly = 0 in {
2364 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2365 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2366 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2367 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2368 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2369 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2370 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2371 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2374 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2375 let isCodeGenOnly = 0 in {
2376 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2377 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2378 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2379 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2380 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2381 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2382 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2383 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2386 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2387 let isCodeGenOnly = 0 in {
2388 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2389 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2390 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2391 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2392 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2393 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2394 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2395 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2398 //===----------------------------------------------------------------------===//
2400 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2401 // result from the 64-bit destination register.
2402 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2403 //===----------------------------------------------------------------------===//
2405 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2406 : MInst_acc<(outs DoubleRegs:$Rxx),
2407 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2408 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2409 #"($Rs."#!if(LHbits{1},"h","l")
2410 #", $Rt."#!if(LHbits{0},"h)","l)")
2411 #!if(hasShift,":<<1",""),
2412 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2417 let IClass = 0b1110;
2419 let Inst{27-24} = 0b0110;
2420 let Inst{23} = hasShift;
2421 let Inst{22} = isUnsigned;
2422 let Inst{21} = isNac;
2424 let Inst{6-5} = LHbits;
2425 let Inst{4-0} = Rxx;
2426 let Inst{20-16} = Rs;
2427 let Inst{12-8} = Rt;
2430 let isCodeGenOnly = 0 in {
2431 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2432 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2433 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2434 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2436 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2437 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2438 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2439 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2441 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2442 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2443 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2444 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2446 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2447 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2448 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2449 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2451 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2452 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2453 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2454 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2456 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2457 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2458 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2459 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2461 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2462 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2463 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2464 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2466 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2467 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2468 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2469 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2472 //===----------------------------------------------------------------------===//
2473 // Template Class -- Vector Multipy
2474 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2475 //===----------------------------------------------------------------------===//
2476 class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
2477 bit isRnd, bit isSat >
2478 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2479 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2480 #!if(isRnd,":rnd","")
2481 #!if(isSat,":sat",""),
2487 let IClass = 0b1110;
2489 let Inst{27-24} = 0b1000;
2490 let Inst{23-21} = MajOp;
2491 let Inst{7-5} = MinOp;
2492 let Inst{4-0} = Rdd;
2493 let Inst{20-16} = Rss;
2494 let Inst{12-8} = Rtt;
2497 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
2498 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
2499 def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
2500 def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
2503 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
2504 let isCodeGenOnly = 0 in {
2505 def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
2506 def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
2509 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
2510 let isCodeGenOnly = 0 in {
2511 def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>;
2512 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
2515 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2516 let isCodeGenOnly = 0 in {
2517 def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>;
2518 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
2521 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
2522 let isCodeGenOnly = 0 in {
2523 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
2524 def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>;
2525 def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>;
2526 def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>;
2529 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
2530 let isCodeGenOnly = 0 in {
2531 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
2532 def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>;
2533 def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>;
2534 def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>;
2537 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
2538 let isCodeGenOnly = 0 in {
2539 def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>;
2540 def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>;
2541 def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>;
2542 def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>;
2545 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
2546 let isCodeGenOnly = 0 in {
2547 def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>;
2548 def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>;
2549 def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>;
2550 def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>;
2553 let hasNewValue = 1, opNewValue = 0 in
2554 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2555 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2556 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2557 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2559 #"($src1, $src2"#op2Suffix#")"
2560 #!if(MajOp{2}, ":<<1", "")
2561 #!if(isRnd, ":rnd", "")
2562 #!if(isSat, ":sat", "")
2563 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2568 let IClass = 0b1110;
2570 let Inst{27-24} = RegTyBits;
2571 let Inst{23-21} = MajOp;
2572 let Inst{20-16} = src1;
2574 let Inst{12-8} = src2;
2575 let Inst{7-5} = MinOp;
2576 let Inst{4-0} = dst;
2579 class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
2580 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
2582 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2583 bit isSat = 0, bit isRnd = 0 >
2584 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2586 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2587 bit isSat = 0, bit isRnd = 0 >
2588 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2590 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2591 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2592 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2594 let isCodeGenOnly = 0 in {
2595 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
2596 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
2597 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
2600 let CextOpcode = "mpyi", InputType = "reg", isCodeGenOnly = 0 in
2601 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2603 let isCodeGenOnly = 0 in {
2604 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2605 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2608 let isCodeGenOnly = 0 in
2609 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2611 let isCodeGenOnly = 0 in {
2612 def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>;
2613 def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>;
2616 let isCodeGenOnly = 0 in {
2617 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2618 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2621 let isCodeGenOnly = 0 in {
2622 def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
2623 def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
2624 def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
2625 def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
2629 let isCodeGenOnly = 0 in {
2630 def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
2631 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2632 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2633 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2635 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2636 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2639 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2640 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2641 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2643 let hasNewValue = 1, opNewValue = 0 in
2644 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2645 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2646 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2647 pattern, "", M_tc_3x_SLOT23> {
2652 let IClass = 0b1110;
2654 let Inst{27-24} = 0b0000;
2655 let Inst{23} = isNeg;
2658 let Inst{20-16} = Rs;
2659 let Inst{12-5} = u8;
2662 let isExtendable = 1, opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
2663 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2664 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2666 let isCodeGenOnly = 0 in
2667 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2668 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2671 // Assember mapped to M2_mpyi
2672 let isAsmParserOnly = 1 in
2673 def M2_mpyui : MInst<(outs IntRegs:$dst),
2674 (ins IntRegs:$src1, IntRegs:$src2),
2675 "$dst = mpyui($src1, $src2)">;
2678 // s9 is NOT the same as m9 - but it works.. so far.
2679 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2680 // depending on the value of m9. See Arch Spec.
2681 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2682 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1 in
2683 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2684 "$dst = mpyi($src1, #$src2)",
2685 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2686 s9ExtPred:$src2))]>, ImmRegRel;
2688 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2689 InputType = "imm" in
2690 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2691 list<dag> pattern = []>
2692 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2693 "$dst "#mnemonic#"($src2, #$src3)",
2694 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2699 let IClass = 0b1110;
2701 let Inst{27-26} = 0b00;
2702 let Inst{25-23} = MajOp;
2703 let Inst{20-16} = src2;
2705 let Inst{12-5} = src3;
2706 let Inst{4-0} = dst;
2709 let InputType = "reg", hasNewValue = 1 in
2710 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2711 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2712 bit isSat = 0, bit isShift = 0>
2713 : MInst < (outs IntRegs:$dst),
2714 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2715 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2716 #!if(isShift, ":<<1", "")
2717 #!if(isSat, ":sat", ""),
2718 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2723 let IClass = 0b1110;
2725 let Inst{27-24} = 0b1111;
2726 let Inst{23-21} = MajOp;
2727 let Inst{20-16} = !if(isSwap, src3, src2);
2729 let Inst{12-8} = !if(isSwap, src2, src3);
2730 let Inst{7-5} = MinOp;
2731 let Inst{4-0} = dst;
2734 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2735 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2736 [(set (i32 IntRegs:$dst),
2737 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2738 IntRegs:$src1))]>, ImmRegRel;
2740 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2741 [(set (i32 IntRegs:$dst),
2742 (add (mul IntRegs:$src2, IntRegs:$src3),
2743 IntRegs:$src1))]>, ImmRegRel;
2746 let CextOpcode = "ADD_acc", isCodeGenOnly = 0 in {
2747 let isExtentSigned = 1 in
2748 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2749 [(set (i32 IntRegs:$dst),
2750 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2751 (i32 IntRegs:$src1)))]>, ImmRegRel;
2753 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2754 [(set (i32 IntRegs:$dst),
2755 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2756 (i32 IntRegs:$src1)))]>, ImmRegRel;
2759 let CextOpcode = "SUB_acc", isCodeGenOnly = 0 in {
2760 let isExtentSigned = 1 in
2761 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2763 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2766 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
2767 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2769 let isCodeGenOnly = 0 in {
2770 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2771 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2774 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2776 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2777 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2779 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2780 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2781 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2783 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2784 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2786 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2787 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2789 //===----------------------------------------------------------------------===//
2790 // Template Class -- XType Vector Instructions
2791 //===----------------------------------------------------------------------===//
2792 class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2793 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2794 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2800 let IClass = 0b1110;
2802 let Inst{27-24} = 0b1000;
2803 let Inst{23-21} = MajOp;
2804 let Inst{7-5} = MinOp;
2805 let Inst{4-0} = Rdd;
2806 let Inst{20-16} = Rss;
2807 let Inst{12-8} = Rtt;
2810 class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2811 : MInst <(outs DoubleRegs:$Rdd),
2812 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2813 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2814 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
2819 let IClass = 0b1110;
2821 let Inst{27-24} = 0b1010;
2822 let Inst{23-21} = MajOp;
2823 let Inst{7-5} = MinOp;
2824 let Inst{4-0} = Rdd;
2825 let Inst{20-16} = Rss;
2826 let Inst{12-8} = Rtt;
2829 class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
2830 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
2831 "$Rdd = "#opc#"($Rtt, $Rss)",
2832 [], "",M_tc_2_SLOT23 > {
2837 let IClass = 0b1110;
2839 let Inst{27-24} = 0b1000;
2840 let Inst{23-21} = MajOp;
2841 let Inst{7-5} = 0b000;
2842 let Inst{4-0} = Rdd;
2843 let Inst{20-16} = Rss;
2844 let Inst{12-8} = Rtt;
2847 // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
2848 let isCodeGenOnly = 0 in {
2849 def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
2850 def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
2853 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
2854 let isCodeGenOnly = 0 in {
2855 def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
2856 def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
2859 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
2860 let isCodeGenOnly = 0 in
2861 def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
2863 // Vector reduce complex multiply real or imaginary:
2864 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
2865 let isCodeGenOnly = 0 in {
2866 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
2867 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
2868 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
2869 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
2872 let isCodeGenOnly = 0 in {
2873 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
2874 def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
2875 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
2876 def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
2878 // Vector reduce halfwords:
2879 // Rdd[+]=vrmpyh(Rss,Rtt)
2880 let isCodeGenOnly = 0 in {
2881 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
2882 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
2885 //===----------------------------------------------------------------------===//
2886 // Template Class -- Vector Multipy with accumulation.
2887 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2888 //===----------------------------------------------------------------------===//
2889 let Defs = [USR_OVF] in
2890 class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
2891 bit hasShift, bit isRnd >
2892 : MInst <(outs DoubleRegs:$Rxx),
2893 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2894 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2895 #!if(isRnd,":rnd","")#":sat",
2896 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2901 let IClass = 0b1110;
2903 let Inst{27-24} = 0b1010;
2904 let Inst{23-21} = MajOp;
2905 let Inst{7-5} = MinOp;
2906 let Inst{4-0} = Rxx;
2907 let Inst{20-16} = Rss;
2908 let Inst{12-8} = Rtt;
2911 class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp,
2912 bit hasShift, bit isRnd >
2913 : MInst <(outs DoubleRegs:$Rxx),
2914 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2915 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2916 #!if(isRnd,":rnd",""),
2917 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2922 let IClass = 0b1110;
2924 let Inst{27-24} = 0b1010;
2925 let Inst{23-21} = MajOp;
2926 let Inst{7-5} = MinOp;
2927 let Inst{4-0} = Rxx;
2928 let Inst{20-16} = Rss;
2929 let Inst{12-8} = Rtt;
2932 // Vector multiply word by signed half with accumulation
2933 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
2934 let isCodeGenOnly = 0 in {
2935 def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>;
2936 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
2937 def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>;
2938 def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>;
2941 let isCodeGenOnly = 0 in {
2942 def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>;
2943 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
2944 def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>;
2945 def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>;
2948 // Vector multiply even halfwords with accumulation
2949 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
2950 let isCodeGenOnly = 0 in {
2951 def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>;
2952 def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>;
2953 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
2956 // Vector dual multiply with accumulation
2957 // Rxx+=vdmpy(Rss,Rtt)[:sat]
2958 let isCodeGenOnly = 0 in {
2959 def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>;
2960 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
2963 // Vector complex multiply real or imaginary with accumulation
2964 // Rxx+=vcmpy[ir](Rss,Rtt):sat
2965 let isCodeGenOnly = 0 in {
2966 def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
2967 def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
2970 //===----------------------------------------------------------------------===//
2971 // Template Class -- Multiply signed/unsigned halfwords with and without
2972 // saturation and rounding
2973 //===----------------------------------------------------------------------===//
2974 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
2975 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
2976 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2977 #", $Rt."#!if(LHbits{0},"h)","l)")
2978 #!if(hasShift,":<<1","")
2979 #!if(isRnd,":rnd",""),
2985 let IClass = 0b1110;
2987 let Inst{27-24} = 0b0100;
2988 let Inst{23} = hasShift;
2989 let Inst{22} = isUnsigned;
2990 let Inst{21} = isRnd;
2991 let Inst{6-5} = LHbits;
2992 let Inst{4-0} = Rdd;
2993 let Inst{20-16} = Rs;
2994 let Inst{12-8} = Rt;
2997 let isCodeGenOnly = 0 in {
2998 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
2999 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
3000 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
3001 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
3003 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
3004 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
3005 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
3006 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
3008 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
3009 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
3010 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
3011 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
3013 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
3014 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
3015 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
3016 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
3018 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
3019 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
3020 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
3021 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
3022 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
3024 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
3025 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
3026 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
3027 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
3029 //===----------------------------------------------------------------------===//
3030 // Template Class for xtype mpy:
3033 // multiply 32X32 and use full result
3034 //===----------------------------------------------------------------------===//
3035 let hasSideEffects = 0 in
3036 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3037 bit isSat, bit hasShift, bit isConj>
3038 : MInst <(outs DoubleRegs:$Rdd),
3039 (ins IntRegs:$Rs, IntRegs:$Rt),
3040 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
3041 #!if(hasShift,":<<1","")
3042 #!if(isSat,":sat",""),
3048 let IClass = 0b1110;
3050 let Inst{27-24} = 0b0101;
3051 let Inst{23-21} = MajOp;
3052 let Inst{20-16} = Rs;
3053 let Inst{12-8} = Rt;
3054 let Inst{7-5} = MinOp;
3055 let Inst{4-0} = Rdd;
3058 //===----------------------------------------------------------------------===//
3059 // Template Class for xtype mpy with accumulation into 64-bit:
3062 // multiply 32X32 and use full result
3063 //===----------------------------------------------------------------------===//
3064 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
3065 bit isSat, bit hasShift, bit isConj>
3066 : MInst <(outs DoubleRegs:$Rxx),
3067 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
3068 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
3069 #!if(hasShift,":<<1","")
3070 #!if(isSat,":sat",""),
3072 [] , "$dst2 = $Rxx" > {
3077 let IClass = 0b1110;
3079 let Inst{27-24} = 0b0111;
3080 let Inst{23-21} = MajOp;
3081 let Inst{20-16} = Rs;
3082 let Inst{12-8} = Rt;
3083 let Inst{7-5} = MinOp;
3084 let Inst{4-0} = Rxx;
3087 // MPY - Multiply and use full result
3088 // Rdd = mpy[u](Rs,Rt)
3089 let isCodeGenOnly = 0 in {
3090 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
3091 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
3093 // Rxx[+-]= mpy[u](Rs,Rt)
3094 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
3095 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
3096 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
3097 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
3099 // Complex multiply real or imaginary
3100 // Rxx=cmpy[ir](Rs,Rt)
3101 let isCodeGenOnly = 0 in {
3102 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
3103 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
3106 // Rxx+=cmpy[ir](Rs,Rt)
3107 let isCodeGenOnly = 0 in {
3108 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
3109 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
3113 // Rdd=cmpy(Rs,Rt)[:<<]:sat
3114 let isCodeGenOnly = 0 in {
3115 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
3116 def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
3119 // Rdd=cmpy(Rs,Rt*)[:<<]:sat
3120 let isCodeGenOnly = 0 in {
3121 def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
3122 def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
3125 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
3126 let isCodeGenOnly = 0 in {
3127 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
3128 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
3129 def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
3130 def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
3133 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
3134 let isCodeGenOnly = 0 in {
3135 def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
3136 def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
3137 def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
3138 def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
3140 // Vector multiply halfwords
3141 // Rdd=vmpyh(Rs,Rt)[:<<]:sat
3142 //let Defs = [USR_OVF] in {
3143 let isCodeGenOnly = 0 in {
3144 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>;
3145 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
3149 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
3150 let isCodeGenOnly = 0 in {
3151 def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>;
3152 def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>;
3153 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
3156 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3157 (i64 (anyext (i32 IntRegs:$src2))))),
3158 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3160 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3161 (i64 (sext (i32 IntRegs:$src2))))),
3162 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3164 def: Pat<(i64 (mul (is_sext_i32:$src1),
3165 (is_sext_i32:$src2))),
3166 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3168 // Multiply and accumulate, use full result.
3169 // Rxx[+-]=mpy(Rs,Rt)
3171 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3172 (mul (i64 (sext (i32 IntRegs:$src2))),
3173 (i64 (sext (i32 IntRegs:$src3)))))),
3174 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3176 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3177 (mul (i64 (sext (i32 IntRegs:$src2))),
3178 (i64 (sext (i32 IntRegs:$src3)))))),
3179 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3181 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3182 (mul (i64 (anyext (i32 IntRegs:$src2))),
3183 (i64 (anyext (i32 IntRegs:$src3)))))),
3184 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3186 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3187 (mul (i64 (zext (i32 IntRegs:$src2))),
3188 (i64 (zext (i32 IntRegs:$src3)))))),
3189 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3191 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3192 (mul (i64 (anyext (i32 IntRegs:$src2))),
3193 (i64 (anyext (i32 IntRegs:$src3)))))),
3194 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3196 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3197 (mul (i64 (zext (i32 IntRegs:$src2))),
3198 (i64 (zext (i32 IntRegs:$src3)))))),
3199 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3201 //===----------------------------------------------------------------------===//
3203 //===----------------------------------------------------------------------===//
3205 //===----------------------------------------------------------------------===//
3207 //===----------------------------------------------------------------------===//
3208 //===----------------------------------------------------------------------===//
3210 //===----------------------------------------------------------------------===//
3212 //===----------------------------------------------------------------------===//
3214 //===----------------------------------------------------------------------===//
3215 //===----------------------------------------------------------------------===//
3217 //===----------------------------------------------------------------------===//
3219 //===----------------------------------------------------------------------===//
3221 //===----------------------------------------------------------------------===//
3222 //===----------------------------------------------------------------------===//
3224 //===----------------------------------------------------------------------===//
3226 //===----------------------------------------------------------------------===//
3228 //===----------------------------------------------------------------------===//
3230 // Store doubleword.
3231 //===----------------------------------------------------------------------===//
3232 // Template class for non-predicated post increment stores with immediate offset
3233 //===----------------------------------------------------------------------===//
3234 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
3235 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3236 bits<4> MajOp, bit isHalf >
3237 : STInst <(outs IntRegs:$_dst_),
3238 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3239 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
3240 [], "$src1 = $_dst_" >,
3247 string ImmOpStr = !cast<string>(ImmOp);
3248 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3249 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3250 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3251 /* s4_0Imm */ offset{3-0})));
3252 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3254 let IClass = 0b1010;
3256 let Inst{27-25} = 0b101;
3257 let Inst{24-21} = MajOp;
3258 let Inst{20-16} = src1;
3260 let Inst{12-8} = src2;
3262 let Inst{6-3} = offsetBits;
3266 //===----------------------------------------------------------------------===//
3267 // Template class for predicated post increment stores with immediate offset
3268 //===----------------------------------------------------------------------===//
3269 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
3270 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3271 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
3272 : STInst <(outs IntRegs:$_dst_),
3273 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3274 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3275 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
3276 [], "$src2 = $_dst_" >,
3284 string ImmOpStr = !cast<string>(ImmOp);
3285 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3286 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3287 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3288 /* s4_0Imm */ offset{3-0})));
3290 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3291 let isPredicatedNew = isPredNew;
3292 let isPredicatedFalse = isPredNot;
3294 let IClass = 0b1010;
3296 let Inst{27-25} = 0b101;
3297 let Inst{24-21} = MajOp;
3298 let Inst{20-16} = src2;
3300 let Inst{12-8} = src3;
3301 let Inst{7} = isPredNew;
3302 let Inst{6-3} = offsetBits;
3303 let Inst{2} = isPredNot;
3304 let Inst{1-0} = src1;
3307 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
3308 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
3310 let BaseOpcode = "POST_"#BaseOp in {
3311 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
3314 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
3315 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
3318 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3320 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3325 let accessSize = ByteAccess, isCodeGenOnly = 0 in
3326 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3328 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3329 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3331 let accessSize = WordAccess, isCodeGenOnly = 0 in
3332 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3334 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3335 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3337 let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in
3338 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3340 // Patterns for generating stores, where the address takes different forms:
3343 // - simple (base address without offset).
3344 // These would usually be used together (via Storex_pat defined below), but
3345 // in some cases one may want to apply different properties (such as
3346 // AddedComplexity) to the individual patterns.
3347 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3348 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
3349 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3351 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3352 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3354 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3356 def: Storex_fi_pat <Store, Value, MI>;
3357 def: Storex_add_pat <Store, Value, ImmPred, MI>;
3360 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
3361 s4_3ImmPred:$offset),
3362 (S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
3364 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
3365 s4_3ImmPred:$offset),
3366 (S2_storerh_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
3368 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
3369 (S2_storeri_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
3371 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
3372 s4_3ImmPred:$offset),
3373 (S2_storerd_pi IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
3375 //===----------------------------------------------------------------------===//
3376 // Template class for post increment stores with register offset.
3377 //===----------------------------------------------------------------------===//
3378 let isNVStorable = 1 in
3379 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
3380 MemAccessSize AccessSz, bit isHalf = 0>
3381 : STInst <(outs IntRegs:$_dst_),
3382 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3383 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
3384 [], "$src1 = $_dst_" > {
3388 let accessSize = AccessSz;
3390 let IClass = 0b1010;
3392 let Inst{27-24} = 0b1101;
3393 let Inst{23-21} = MajOp;
3394 let Inst{20-16} = src1;
3395 let Inst{13} = src2;
3396 let Inst{12-8} = src3;
3400 let isCodeGenOnly = 0 in {
3401 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3402 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3403 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3404 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
3406 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3408 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
3409 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3410 bits<3>MajOp, bit isH = 0>
3412 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3413 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
3414 AddrModeRel, ImmRegRel {
3416 bits<14> src2; // Actual address offset
3418 bits<11> offsetBits; // Represents offset encoding
3420 string ImmOpStr = !cast<string>(ImmOp);
3422 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
3423 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
3424 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
3425 /* s11_0Ext */ 11)));
3426 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
3427 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
3428 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
3429 /* s11_0Ext */ src2{10-0})));
3430 let IClass = 0b1010;
3433 let Inst{26-25} = offsetBits{10-9};
3435 let Inst{23-21} = MajOp;
3436 let Inst{20-16} = src1;
3437 let Inst{13} = offsetBits{8};
3438 let Inst{12-8} = src3;
3439 let Inst{7-0} = offsetBits{7-0};
3442 let opExtendable = 2, isPredicated = 1 in
3443 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3444 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
3446 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3447 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3448 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
3449 [],"",V2LDST_tc_st_SLOT01 >,
3450 AddrModeRel, ImmRegRel {
3453 bits<9> src3; // Actual address offset
3455 bits<6> offsetBits; // Represents offset encoding
3457 let isPredicatedNew = isPredNew;
3458 let isPredicatedFalse = PredNot;
3460 string ImmOpStr = !cast<string>(ImmOp);
3461 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
3462 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
3463 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
3465 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
3466 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
3467 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
3468 /* u6_0Ext */ src3{5-0})));
3469 let IClass = 0b0100;
3472 let Inst{26} = PredNot;
3473 let Inst{25} = isPredNew;
3475 let Inst{23-21} = MajOp;
3476 let Inst{20-16} = src2;
3477 let Inst{13} = offsetBits{5};
3478 let Inst{12-8} = src4;
3479 let Inst{7-3} = offsetBits{4-0};
3480 let Inst{1-0} = src1;
3483 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
3484 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
3485 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
3486 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
3487 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
3490 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
3491 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
3494 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3496 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3501 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
3502 let accessSize = ByteAccess in
3503 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3505 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3506 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3508 let accessSize = WordAccess, opExtentAlign = 2 in
3509 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3511 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
3512 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
3515 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3516 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3520 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3521 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3522 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3524 // Regular stores in the DAG have two operands: value and address.
3525 // Atomic stores also have two, but they are reversed: address, value.
3526 // To use atomic stores with the patterns, they need to have their operands
3527 // swapped. This relies on the knowledge that the F.Fragment uses names
3529 class SwapSt<PatFrag F>
3530 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
3532 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
3533 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
3534 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
3535 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
3537 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
3538 (S2_storerb_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3540 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
3541 (S2_storerh_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3543 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
3544 (S2_storeri_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3546 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
3547 (S2_storerd_io AddrFI:$addr, 0, (i64 DoubleRegs:$src1))>;
3550 let AddedComplexity = 10 in {
3551 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
3552 s11_0ExtPred:$offset)),
3553 (S2_storerb_io IntRegs:$src2, s11_0ImmPred:$offset,
3554 (i32 IntRegs:$src1))>;
3556 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
3557 s11_1ExtPred:$offset)),
3558 (S2_storerh_io IntRegs:$src2, s11_1ImmPred:$offset,
3559 (i32 IntRegs:$src1))>;
3561 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
3562 s11_2ExtPred:$offset)),
3563 (S2_storeri_io IntRegs:$src2, s11_2ImmPred:$offset,
3564 (i32 IntRegs:$src1))>;
3566 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
3567 s11_3ExtPred:$offset)),
3568 (S2_storerd_io IntRegs:$src2, s11_3ImmPred:$offset,
3569 (i64 DoubleRegs:$src1))>;
3572 // memh(Rx++#s4:1)=Rt.H
3575 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
3576 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3577 def STriw_pred : STInst<(outs),
3578 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3579 ".error \"should not emit\"", []>;
3581 // S2_allocframe: Allocate stack frame.
3582 let Defs = [R29, R30], Uses = [R29, R31, R30],
3583 hasSideEffects = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3584 def S2_allocframe: ST0Inst <
3585 (outs), (ins u11_3Imm:$u11_3),
3586 "allocframe(#$u11_3)" > {
3589 let IClass = 0b1010;
3590 let Inst{27-16} = 0b000010011101;
3591 let Inst{13-11} = 0b000;
3592 let Inst{10-0} = u11_3{13-3};
3595 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3596 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3597 let Uses = [CS], isNVStorable = 1 in
3598 class T_store_pci <string mnemonic, RegisterClass RC,
3599 Operand Imm, bits<4>MajOp,
3600 MemAccessSize AlignSize, string RegSrc = "Rt">
3601 : STInst <(outs IntRegs:$_dst_),
3602 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3603 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3610 let accessSize = AlignSize;
3612 let IClass = 0b1010;
3613 let Inst{27-25} = 0b100;
3614 let Inst{24-21} = MajOp;
3615 let Inst{20-16} = Rz;
3617 let Inst{12-8} = Rt;
3620 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3621 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3622 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3623 /* ByteAccess */ offset{3-0})));
3627 let isCodeGenOnly = 0 in {
3628 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3630 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3632 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3633 HalfWordAccess, "Rt.h">;
3634 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3636 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3640 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3641 class T_storenew_pci <string mnemonic, Operand Imm,
3642 bits<2>MajOp, MemAccessSize AlignSize>
3643 : NVInst < (outs IntRegs:$_dst_),
3644 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3645 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3653 let accessSize = AlignSize;
3655 let IClass = 0b1010;
3656 let Inst{27-21} = 0b1001101;
3657 let Inst{20-16} = Rz;
3659 let Inst{12-11} = MajOp;
3660 let Inst{10-8} = Nt;
3663 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3664 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3665 /* ByteAccess */ offset{3-0}));
3668 let isCodeGenOnly = 0 in {
3669 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3670 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3671 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3674 //===----------------------------------------------------------------------===//
3675 // Circular stores with auto-increment register
3676 //===----------------------------------------------------------------------===//
3677 let Uses = [CS], isNVStorable = 1, isCodeGenOnly = 0 in
3678 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3679 MemAccessSize AlignSize, string RegSrc = "Rt">
3680 : STInst <(outs IntRegs:$_dst_),
3681 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3682 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3689 let accessSize = AlignSize;
3691 let IClass = 0b1010;
3692 let Inst{27-25} = 0b100;
3693 let Inst{24-21} = MajOp;
3694 let Inst{20-16} = Rz;
3696 let Inst{12-8} = Rt;
3701 let isCodeGenOnly = 0 in {
3702 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3703 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3704 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3705 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3706 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3707 HalfWordAccess, "Rt.h">;
3710 //===----------------------------------------------------------------------===//
3711 // Circular .new stores with auto-increment register
3712 //===----------------------------------------------------------------------===//
3713 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3714 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3715 MemAccessSize AlignSize>
3716 : NVInst <(outs IntRegs:$_dst_),
3717 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3718 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3725 let accessSize = AlignSize;
3727 let IClass = 0b1010;
3728 let Inst{27-21} = 0b1001101;
3729 let Inst{20-16} = Rz;
3731 let Inst{12-11} = MajOp;
3732 let Inst{10-8} = Nt;
3737 let isCodeGenOnly = 0 in {
3738 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3739 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3740 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3743 //===----------------------------------------------------------------------===//
3744 // Bit-reversed stores with auto-increment register
3745 //===----------------------------------------------------------------------===//
3746 let hasSideEffects = 0 in
3747 class T_store_pbr<string mnemonic, RegisterClass RC,
3748 MemAccessSize addrSize, bits<3> majOp,
3751 <(outs IntRegs:$_dst_),
3752 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3753 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3754 [], "$Rz = $_dst_" > {
3756 let accessSize = addrSize;
3762 let IClass = 0b1010;
3764 let Inst{27-24} = 0b1111;
3765 let Inst{23-21} = majOp;
3767 let Inst{20-16} = Rz;
3769 let Inst{12-8} = src;
3772 let isNVStorable = 1, isCodeGenOnly = 0 in {
3773 let BaseOpcode = "S2_storerb_pbr" in
3774 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3775 0b000>, NewValueRel;
3776 let BaseOpcode = "S2_storerh_pbr" in
3777 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3778 0b010>, NewValueRel;
3779 let BaseOpcode = "S2_storeri_pbr" in
3780 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3781 0b100>, NewValueRel;
3783 let isCodeGenOnly = 0 in {
3784 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3785 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3788 //===----------------------------------------------------------------------===//
3789 // Bit-reversed .new stores with auto-increment register
3790 //===----------------------------------------------------------------------===//
3791 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3792 hasSideEffects = 0 in
3793 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3794 : NVInst <(outs IntRegs:$_dst_),
3795 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3796 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3797 "$Rz = $_dst_">, NewValueRel {
3798 let accessSize = addrSize;
3803 let IClass = 0b1010;
3805 let Inst{27-21} = 0b1111101;
3806 let Inst{12-11} = majOp;
3808 let Inst{20-16} = Rz;
3810 let Inst{10-8} = Nt;
3813 let BaseOpcode = "S2_storerb_pbr", isCodeGenOnly = 0 in
3814 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3816 let BaseOpcode = "S2_storerh_pbr", isCodeGenOnly = 0 in
3817 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3819 let BaseOpcode = "S2_storeri_pbr", isCodeGenOnly = 0 in
3820 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3822 //===----------------------------------------------------------------------===//
3824 //===----------------------------------------------------------------------===//
3826 //===----------------------------------------------------------------------===//
3828 //===----------------------------------------------------------------------===//
3830 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
3831 "$dst = not($src1)",
3832 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
3835 //===----------------------------------------------------------------------===//
3837 //===----------------------------------------------------------------------===//
3839 let hasSideEffects = 0 in
3840 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3841 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3842 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3843 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3844 [], "", S_2op_tc_1_SLOT23 > {
3848 let IClass = 0b1000;
3850 let Inst{27-24} = RegTyBits;
3851 let Inst{23-22} = MajOp;
3853 let Inst{20-16} = src;
3854 let Inst{7-5} = MinOp;
3855 let Inst{4-0} = dst;
3858 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3859 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3861 let hasNewValue = 1 in
3862 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3863 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3865 let hasNewValue = 1 in
3866 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3867 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3869 // Vector sign/zero extend
3870 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 0 in {
3871 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3872 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3873 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3874 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3877 // Vector splat bytes/halfwords
3878 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 0 in {
3879 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
3880 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
3883 // Sign extend word to doubleword
3884 let isCodeGenOnly = 0 in
3885 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3887 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3889 // Vector saturate and pack
3890 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
3891 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
3892 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
3893 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3894 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3895 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3896 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
3900 let isCodeGenOnly = 0 in {
3901 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
3902 def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
3905 // Swizzle the bytes of a word
3906 let isCodeGenOnly = 0 in
3907 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3910 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
3911 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
3912 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
3913 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
3914 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
3915 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
3916 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
3919 let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
3920 // Vector round and pack
3921 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
3923 let Defs = [USR_OVF] in
3924 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
3927 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
3929 // Absolute value word
3930 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
3932 let Defs = [USR_OVF] in
3933 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
3935 // Negate with saturation
3936 let Defs = [USR_OVF] in
3937 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
3940 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
3941 (i32 (sub 0, (i32 IntRegs:$src))),
3942 (i32 IntRegs:$src))),
3943 (A2_abs IntRegs:$src)>;
3945 let AddedComplexity = 50 in
3946 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
3947 (i32 IntRegs:$src)),
3948 (sra (i32 IntRegs:$src), (i32 31)))),
3949 (A2_abs IntRegs:$src)>;
3951 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3952 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
3953 bit isSat, bit isRnd, list<dag> pattern = []>
3954 : SInst <(outs RCOut:$dst),
3955 (ins RCIn:$src, u5Imm:$u5),
3956 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
3957 #!if(isRnd, ":rnd", ""),
3958 pattern, "", S_2op_tc_2_SLOT23> {
3963 let IClass = 0b1000;
3965 let Inst{27-24} = RegTyBits;
3966 let Inst{23-21} = MajOp;
3967 let Inst{20-16} = src;
3969 let Inst{12-8} = u5;
3970 let Inst{7-5} = MinOp;
3971 let Inst{4-0} = dst;
3974 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3975 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
3977 let hasNewValue = 1 in
3978 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3979 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
3981 let hasNewValue = 1 in
3982 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3983 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
3984 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
3985 isSat, isRnd, pattern>;
3987 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
3988 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
3989 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
3990 (u5ImmPred:$u5)))]>;
3992 // Arithmetic/logical shift right/left by immediate
3993 let Itinerary = S_2op_tc_1_SLOT23, isCodeGenOnly = 0 in {
3994 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
3995 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
3996 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
3999 // Shift left by immediate with saturation
4000 let Defs = [USR_OVF], isCodeGenOnly = 0 in
4001 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
4003 // Shift right with round
4004 let isCodeGenOnly = 0 in
4005 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
4007 def S2_asr_i_r_rnd_goodsyntax
4008 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
4009 "$dst = asrrnd($src, #$u5)",
4010 [], "", S_2op_tc_1_SLOT23>;
4012 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
4015 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
4017 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
4018 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
4019 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
4022 let IClass = 0b1000;
4023 let Inst{27-24} = 0;
4024 let Inst{23-22} = MajOp;
4025 let Inst{20-16} = Rss;
4026 let Inst{7-5} = minOp;
4027 let Inst{4-0} = Rdd;
4030 let isCodeGenOnly = 0 in {
4031 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
4032 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
4033 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
4036 // Innterleave/deinterleave
4037 let isCodeGenOnly = 0 in {
4038 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
4039 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
4042 // Vector Complex conjugate
4043 let isCodeGenOnly = 0 in
4044 def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
4046 // Vector saturate without pack
4047 let isCodeGenOnly = 0 in {
4048 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
4049 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
4050 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
4051 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
4054 // Vector absolute value halfwords with and without saturation
4055 // Rdd64=vabsh(Rss64)[:sat]
4056 let isCodeGenOnly = 0 in {
4057 def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
4058 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
4061 // Vector absolute value words with and without saturation
4062 let isCodeGenOnly = 0 in {
4063 def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
4064 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
4067 //===----------------------------------------------------------------------===//
4069 //===----------------------------------------------------------------------===//
4072 let hasSideEffects = 0, hasNewValue = 1 in
4073 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
4075 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
4078 let IClass = 0b1000;
4080 let Inst{26} = Is32;
4081 let Inst{25-24} = 0b00;
4082 let Inst{23-21} = MajOp;
4083 let Inst{20-16} = Rs;
4084 let Inst{7-5} = MinOp;
4088 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
4089 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
4090 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4092 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
4093 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
4094 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4096 let isCodeGenOnly = 0 in {
4097 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
4098 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
4099 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
4100 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
4101 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
4102 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
4103 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
4104 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
4105 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
4108 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
4109 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
4110 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
4111 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
4112 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
4113 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
4115 // Bit set/clear/toggle
4117 let hasSideEffects = 0, hasNewValue = 1 in
4118 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
4119 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4120 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
4124 let IClass = 0b1000;
4125 let Inst{27-21} = 0b1100110;
4126 let Inst{20-16} = Rs;
4128 let Inst{12-8} = u5;
4129 let Inst{7-5} = MinOp;
4133 let hasSideEffects = 0, hasNewValue = 1 in
4134 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
4135 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4136 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
4140 let IClass = 0b1100;
4141 let Inst{27-22} = 0b011010;
4142 let Inst{20-16} = Rs;
4143 let Inst{12-8} = Rt;
4144 let Inst{7-6} = MinOp;
4148 let isCodeGenOnly = 0 in {
4149 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
4150 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
4151 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
4152 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
4153 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
4154 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
4157 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4158 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4159 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4160 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4161 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4162 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4163 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
4164 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4165 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4166 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4167 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4168 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4172 let hasSideEffects = 0 in
4173 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
4174 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4175 "$Pd = "#MnOp#"($Rs, #$u5)",
4176 [], "", S_2op_tc_2early_SLOT23> {
4180 let IClass = 0b1000;
4181 let Inst{27-24} = 0b0101;
4182 let Inst{23-21} = MajOp;
4183 let Inst{20-16} = Rs;
4185 let Inst{12-8} = u5;
4189 let hasSideEffects = 0 in
4190 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
4191 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4192 "$Pd = "#MnOp#"($Rs, $Rt)",
4193 [], "", S_3op_tc_2early_SLOT23> {
4197 let IClass = 0b1100;
4198 let Inst{27-22} = 0b011100;
4199 let Inst{21} = IsNeg;
4200 let Inst{20-16} = Rs;
4201 let Inst{12-8} = Rt;
4205 let isCodeGenOnly = 0 in {
4206 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
4207 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
4210 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
4211 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4212 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4213 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4214 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4215 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4216 (S2_tstbit_i IntRegs:$Rs, 0)>;
4217 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
4218 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4220 let hasSideEffects = 0 in
4221 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
4222 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4223 "$Pd = "#MnOp#"($Rs, #$u6)",
4224 [], "", S_2op_tc_2early_SLOT23> {
4228 let IClass = 0b1000;
4229 let Inst{27-24} = 0b0101;
4230 let Inst{23-22} = MajOp;
4231 let Inst{21} = IsNeg;
4232 let Inst{20-16} = Rs;
4233 let Inst{13-8} = u6;
4237 let hasSideEffects = 0 in
4238 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
4239 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4240 "$Pd = "#MnOp#"($Rs, $Rt)",
4241 [], "", S_3op_tc_2early_SLOT23> {
4245 let IClass = 0b1100;
4246 let Inst{27-24} = 0b0111;
4247 let Inst{23-22} = MajOp;
4248 let Inst{21} = IsNeg;
4249 let Inst{20-16} = Rs;
4250 let Inst{12-8} = Rt;
4254 let isCodeGenOnly = 0 in {
4255 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
4256 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
4257 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
4260 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
4261 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4262 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4263 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4264 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4267 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
4268 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4269 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4271 //===----------------------------------------------------------------------===//
4273 //===----------------------------------------------------------------------===//
4275 //===----------------------------------------------------------------------===//
4277 //===----------------------------------------------------------------------===//
4278 //===----------------------------------------------------------------------===//
4280 //===----------------------------------------------------------------------===//
4282 //===----------------------------------------------------------------------===//
4284 //===----------------------------------------------------------------------===//
4286 //===----------------------------------------------------------------------===//
4288 //===----------------------------------------------------------------------===//
4290 //===----------------------------------------------------------------------===//
4292 //===----------------------------------------------------------------------===//
4294 // Predicate transfer.
4295 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
4296 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4297 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
4301 let IClass = 0b1000;
4302 let Inst{27-24} = 0b1001;
4304 let Inst{17-16} = Ps;
4308 // Transfer general register to predicate.
4309 let hasSideEffects = 0, isCodeGenOnly = 0 in
4310 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4311 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
4315 let IClass = 0b1000;
4316 let Inst{27-21} = 0b0101010;
4317 let Inst{20-16} = Rs;
4322 //===----------------------------------------------------------------------===//
4324 //===----------------------------------------------------------------------===//
4326 //===----------------------------------------------------------------------===//
4328 //===----------------------------------------------------------------------===//
4329 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
4330 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
4331 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
4332 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
4336 let IClass = 0b1000;
4337 let Inst{27-24} = 0;
4338 let Inst{23-21} = MajOp;
4339 let Inst{20-16} = src1;
4340 let Inst{7-5} = MinOp;
4341 let Inst{4-0} = dst;
4344 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
4345 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
4346 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
4347 u6ImmPred:$src2))]> {
4349 let Inst{13-8} = src2;
4352 // Shift by immediate.
4353 let isCodeGenOnly = 0 in {
4354 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
4355 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
4356 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
4359 // Shift left by small amount and add.
4360 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0,
4361 isCodeGenOnly = 0 in
4362 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4363 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4364 "$Rd = addasl($Rt, $Rs, #$u3)" ,
4365 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4366 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4367 "", S_3op_tc_2_SLOT23> {
4373 let IClass = 0b1100;
4375 let Inst{27-21} = 0b0100000;
4376 let Inst{20-16} = Rs;
4378 let Inst{12-8} = Rt;
4383 //===----------------------------------------------------------------------===//
4385 //===----------------------------------------------------------------------===//
4387 //===----------------------------------------------------------------------===//
4389 //===----------------------------------------------------------------------===//
4390 //===----------------------------------------------------------------------===//
4392 //===----------------------------------------------------------------------===//
4394 //===----------------------------------------------------------------------===//
4396 //===----------------------------------------------------------------------===//
4397 //===----------------------------------------------------------------------===//
4399 //===----------------------------------------------------------------------===//
4401 //===----------------------------------------------------------------------===//
4403 //===----------------------------------------------------------------------===//
4405 //===----------------------------------------------------------------------===//
4407 //===----------------------------------------------------------------------===//
4408 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
4410 let hasSideEffects = 1, isSoloAX = 1, isCodeGenOnly = 0 in
4411 def BARRIER : SYSInst<(outs), (ins),
4413 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
4414 let Inst{31-28} = 0b1010;
4415 let Inst{27-21} = 0b1000000;
4418 //===----------------------------------------------------------------------===//
4420 //===----------------------------------------------------------------------===//
4421 //===----------------------------------------------------------------------===//
4423 //===----------------------------------------------------------------------===//
4425 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4426 opExtendable = 0, hasSideEffects = 0 in
4427 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4428 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
4429 #mnemonic#"($offset, #$src2)",
4430 [], "" , CR_tc_3x_SLOT3> {
4434 let IClass = 0b0110;
4436 let Inst{27-22} = 0b100100;
4437 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4438 let Inst{20-16} = src2{9-5};
4439 let Inst{12-8} = offset{8-4};
4440 let Inst{7-5} = src2{4-2};
4441 let Inst{4-3} = offset{3-2};
4442 let Inst{1-0} = src2{1-0};
4445 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4446 opExtendable = 0, hasSideEffects = 0 in
4447 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4448 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4449 #mnemonic#"($offset, $src2)",
4450 [], "" ,CR_tc_3x_SLOT3> {
4454 let IClass = 0b0110;
4456 let Inst{27-22} = 0b000000;
4457 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4458 let Inst{20-16} = src2;
4459 let Inst{12-8} = offset{8-4};
4460 let Inst{4-3} = offset{3-2};
4463 multiclass LOOP_ri<string mnemonic> {
4464 def i : LOOP_iBase<mnemonic, brtarget>;
4465 def r : LOOP_rBase<mnemonic, brtarget>;
4469 let Defs = [SA0, LC0, USR], isCodeGenOnly = 0 in
4470 defm J2_loop0 : LOOP_ri<"loop0">;
4472 // Interestingly only loop0's appear to set usr.lpcfg
4473 let Defs = [SA1, LC1], isCodeGenOnly = 0 in
4474 defm J2_loop1 : LOOP_ri<"loop1">;
4476 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4477 Defs = [PC, LC0], Uses = [SA0, LC0] in {
4478 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4483 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4484 Defs = [PC, LC1], Uses = [SA1, LC1] in {
4485 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4490 // Pipelined loop instructions, sp[123]loop0
4491 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4492 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4493 opExtendable = 0, isPredicateLate = 1 in
4494 class SPLOOP_iBase<string SP, bits<2> op>
4495 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4496 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
4500 let IClass = 0b0110;
4502 let Inst{22-21} = op;
4503 let Inst{27-23} = 0b10011;
4504 let Inst{20-16} = U10{9-5};
4505 let Inst{12-8} = r7_2{8-4};
4506 let Inst{7-5} = U10{4-2};
4507 let Inst{4-3} = r7_2{3-2};
4508 let Inst{1-0} = U10{1-0};
4511 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4512 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4513 opExtendable = 0, isPredicateLate = 1 in
4514 class SPLOOP_rBase<string SP, bits<2> op>
4515 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4516 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
4520 let IClass = 0b0110;
4522 let Inst{22-21} = op;
4523 let Inst{27-23} = 0b00001;
4524 let Inst{20-16} = Rs;
4525 let Inst{12-8} = r7_2{8-4};
4526 let Inst{4-3} = r7_2{3-2};
4529 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
4530 def i : SPLOOP_iBase<mnemonic, op>;
4531 def r : SPLOOP_rBase<mnemonic, op>;
4534 let isCodeGenOnly = 0 in {
4535 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4536 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
4537 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
4541 // if (Rs[!>=<]=#0) jump:[t/nt]
4542 let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0,
4543 hasSideEffects = 0 in
4544 class J2_jump_0_Base<string compare, bit isTak, bits<2> op>
4545 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4546 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > {
4550 let IClass = 0b0110;
4552 let Inst{27-24} = 0b0001;
4553 let Inst{23-22} = op;
4554 let Inst{12} = isTak;
4555 let Inst{21} = r13_2{14};
4556 let Inst{20-16} = Rs;
4557 let Inst{11-1} = r13_2{12-2};
4558 let Inst{13} = r13_2{13};
4561 multiclass J2_jump_compare_0<string compare, bits<2> op> {
4562 def NAME : J2_jump_0_Base<compare, 0, op>;
4563 def NAME#pt : J2_jump_0_Base<compare, 1, op>;
4565 let isCodeGenOnly = 0 in {
4566 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
4567 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
4568 defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>;
4569 defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>;
4572 // Transfer to/from Control/GPR Guest/GPR
4573 let hasSideEffects = 0 in
4574 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
4575 : CRInst <(outs CTRC:$dst), (ins RC:$src),
4576 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4580 let IClass = 0b0110;
4582 let Inst{27-25} = 0b001;
4583 let Inst{24} = isDouble;
4584 let Inst{23-21} = 0b001;
4585 let Inst{20-16} = src;
4586 let Inst{4-0} = dst;
4588 let isCodeGenOnly = 0 in
4589 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4590 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4591 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4593 let hasSideEffects = 0 in
4594 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
4595 : CRInst <(outs RC:$dst), (ins CTRC:$src),
4596 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4600 let IClass = 0b0110;
4602 let Inst{27-26} = 0b10;
4603 let Inst{25} = isSingle;
4604 let Inst{24-21} = 0b0000;
4605 let Inst{20-16} = src;
4606 let Inst{4-0} = dst;
4609 let hasNewValue = 1, opNewValue = 0, isCodeGenOnly = 0 in
4610 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4611 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4612 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4614 // Y4_trace: Send value to etm trace.
4615 let isSoloAX = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
4616 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4620 let IClass = 0b0110;
4621 let Inst{27-21} = 0b0010010;
4622 let Inst{20-16} = Rs;
4625 let AddedComplexity = 100, isPredicated = 1 in
4626 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
4627 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
4628 "Error; should not emit",
4629 [(set (i32 IntRegs:$dst),
4630 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
4631 s12ImmPred:$src3)))]>;
4633 let AddedComplexity = 100, isPredicated = 1 in
4634 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
4635 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
4636 "Error; should not emit",
4637 [(set (i32 IntRegs:$dst),
4638 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4639 (i32 IntRegs:$src3))))]>;
4641 let AddedComplexity = 100, isPredicated = 1 in
4642 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
4643 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
4644 "Error; should not emit",
4645 [(set (i32 IntRegs:$dst),
4646 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4647 s12ImmPred:$src3)))]>;
4649 // Generate frameindex addresses.
4650 let isReMaterializable = 1 in
4651 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
4652 "$dst = add($src1)",
4653 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
4655 // Support for generating global address.
4656 // Taken from X86InstrInfo.td.
4657 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
4660 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
4661 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
4663 // HI/LO Instructions
4664 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4665 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4666 "$dst.l = #LO($global)",
4669 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4670 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4671 "$dst.h = #HI($global)",
4674 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4675 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4676 "$dst.l = #LO($imm_value)",
4680 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4681 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4682 "$dst.h = #HI($imm_value)",
4685 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4686 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4687 "$dst.l = #LO($jt)",
4690 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4691 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4692 "$dst.h = #HI($jt)",
4696 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4697 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4698 "$dst.l = #LO($label)",
4701 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
4702 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4703 "$dst.h = #HI($label)",
4706 // This pattern is incorrect. When we add small data, we should change
4707 // this pattern to use memw(#foo).
4708 // This is for sdata.
4709 let isMoveImm = 1 in
4710 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4711 "$dst = CONST32(#$global)",
4712 [(set (i32 IntRegs:$dst),
4713 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4715 // This is for non-sdata.
4716 let isReMaterializable = 1, isMoveImm = 1 in
4717 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4718 "$dst = CONST32(#$global)",
4719 [(set (i32 IntRegs:$dst),
4720 (HexagonCONST32 tglobaladdr:$global))]>;
4722 let isReMaterializable = 1, isMoveImm = 1 in
4723 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4724 "$dst = CONST32(#$jt)",
4725 [(set (i32 IntRegs:$dst),
4726 (HexagonCONST32 tjumptable:$jt))]>;
4728 let isReMaterializable = 1, isMoveImm = 1 in
4729 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4730 "$dst = CONST32(#$global)",
4731 [(set (i32 IntRegs:$dst),
4732 (HexagonCONST32_GP tglobaladdr:$global))]>;
4734 let isReMaterializable = 1, isMoveImm = 1 in
4735 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
4736 "$dst = CONST32(#$global)",
4737 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4739 // Map BlockAddress lowering to CONST32_Int_Real
4740 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
4741 (CONST32_Int_Real tblockaddress:$addr)>;
4743 let isReMaterializable = 1, isMoveImm = 1 in
4744 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4745 "$dst = CONST32($label)",
4746 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4748 let isReMaterializable = 1, isMoveImm = 1 in
4749 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
4750 "$dst = CONST64(#$global)",
4751 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
4753 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
4754 "$dst = xor($dst, $dst)",
4755 [(set (i1 PredRegs:$dst), 0)]>;
4757 // Pseudo instructions.
4758 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4759 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4760 SDTCisVT<1, i32> ]>;
4762 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4763 [SDNPHasChain, SDNPOutGlue]>;
4764 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4765 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4767 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4769 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4770 // Optional Flag and Variable Arguments.
4771 // Its 1 Operand has pointer type.
4772 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4773 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4775 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
4776 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4777 "Should never be emitted",
4778 [(callseq_start timm:$amt)]>;
4781 let Defs = [R29, R30, R31], Uses = [R29] in {
4782 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4783 "Should never be emitted",
4784 [(callseq_end timm:$amt1, timm:$amt2)]>;
4787 let isCall = 1, hasSideEffects = 0,
4788 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
4789 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
4790 def CALL : JInst<(outs), (ins calltarget:$dst),
4794 // Call subroutine indirectly.
4795 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in
4796 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4798 // Indirect tail-call.
4799 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
4800 def TCRETURNR : T_JMPr;
4802 // Direct tail-calls.
4803 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4804 isTerminator = 1, isCodeGenOnly = 1 in {
4805 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4806 [], "", J_tc_2early_SLOT23>;
4807 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4808 [], "", J_tc_2early_SLOT23>;
4812 def : Pat<(HexagonTCRet tglobaladdr:$dst),
4813 (TCRETURNtg tglobaladdr:$dst)>;
4814 def : Pat<(HexagonTCRet texternalsym:$dst),
4815 (TCRETURNtext texternalsym:$dst)>;
4816 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4817 (TCRETURNR (i32 IntRegs:$dst))>;
4819 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4820 def : Pat <(and (i32 IntRegs:$src1), 65535),
4821 (A2_zxth (i32 IntRegs:$src1))>;
4823 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4824 def : Pat <(and (i32 IntRegs:$src1), 255),
4825 (A2_zxtb (i32 IntRegs:$src1))>;
4827 // Map Add(p1, true) to p1 = not(p1).
4828 // Add(p1, false) should never be produced,
4829 // if it does, it got to be mapped to NOOP.
4830 def : Pat <(add (i1 PredRegs:$src1), -1),
4831 (C2_not (i1 PredRegs:$src1))>;
4833 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4834 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
4835 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
4838 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4839 // => r0 = TFR_condset_ri(p0, r1, #i)
4840 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
4841 (i32 IntRegs:$src3)),
4842 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
4843 s12ImmPred:$src2))>;
4845 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4846 // => r0 = TFR_condset_ir(p0, #i, r1)
4847 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
4848 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
4849 (i32 IntRegs:$src2)))>;
4851 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4852 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4853 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4855 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
4856 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
4857 (i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4860 let AddedComplexity = 100 in
4861 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
4862 (i64 (A2_combinew (A2_tfrsi 0),
4863 (L2_loadrub_io (CONST32_set tglobaladdr:$global), 0)))>,
4866 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
4867 let AddedComplexity = 10 in
4868 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
4869 (i32 (A2_and (i32 (L2_loadrb_io AddrFI:$addr, 0)), (A2_tfrsi 0x1)))>;
4871 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4872 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4873 (i64 (A2_sxtw (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
4875 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(SXTH(Rss.lo)).
4876 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4877 (i64 (A2_sxtw (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4878 subreg_loreg))))))>;
4880 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(SXTB(Rss.lo)).
4881 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4882 (i64 (A2_sxtw (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4883 subreg_loreg))))))>;
4885 // We want to prevent emitting pnot's as much as possible.
4886 // Map brcond with an unsupported setcc to a J2_jumpf.
4887 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4889 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4892 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4894 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4896 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4897 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4899 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4900 (J2_jumpt (i1 PredRegs:$src1), bb:$offset)>;
4902 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4903 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
4905 (J2_jumpf (C2_cmpgti (i32 IntRegs:$src1),
4906 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
4908 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
4909 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4911 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
4913 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4915 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
4918 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4920 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4923 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4925 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4928 // Map from a 64-bit select to an emulated 64-bit mux.
4929 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4930 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4931 (i64 DoubleRegs:$src3)),
4932 (i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
4933 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4935 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4937 (i32 (C2_mux (i1 PredRegs:$src1),
4938 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4940 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4941 subreg_loreg))))))>;
4943 // Map from a 1-bit select to logical ops.
4944 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4945 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
4946 (i1 PredRegs:$src3)),
4947 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
4948 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
4950 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
4951 def : Pat<(i1 (load ADDRriS11_2:$addr)),
4952 (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
4954 // Map for truncating from 64 immediates to 32 bit immediates.
4955 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
4956 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
4958 // Map for truncating from i64 immediates to i1 bit immediates.
4959 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
4960 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4963 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
4964 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4965 (S2_storerb_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4968 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
4969 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4970 (S2_storerh_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4972 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
4973 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4974 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4977 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
4978 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4979 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4982 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
4983 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4984 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4987 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
4988 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4989 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4991 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
4992 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
4993 (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
4995 // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
4996 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
4997 // Better way to do this?
4998 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
4999 (i64 (A2_sxtw (i32 IntRegs:$src1)))>;
5001 // Map cmple -> cmpgt.
5002 // rs <= rt -> !(rs > rt).
5003 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
5004 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
5006 // rs <= rt -> !(rs > rt).
5007 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5008 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
5010 // Rss <= Rtt -> !(Rss > Rtt).
5011 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5012 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
5014 // Map cmpne -> cmpeq.
5015 // Hexagon_TODO: We should improve on this.
5016 // rs != rt -> !(rs == rt).
5017 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
5018 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
5020 // Map cmpne(Rs) -> !cmpeqe(Rs).
5021 // rs != rt -> !(rs == rt).
5022 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5023 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
5025 // Convert setne back to xor for hexagon since we compute w/ pred registers.
5026 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
5027 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
5029 // Map cmpne(Rss) -> !cmpew(Rss).
5030 // rs != rt -> !(rs == rt).
5031 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5032 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
5033 (i64 DoubleRegs:$src2)))))>;
5035 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
5036 // rs >= rt -> !(rt > rs).
5037 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5038 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
5040 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
5041 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
5042 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
5044 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
5045 // rss >= rtt -> !(rtt > rss).
5046 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5047 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
5048 (i64 DoubleRegs:$src1)))))>;
5050 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
5051 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
5052 // rs < rt -> !(rs >= rt).
5053 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
5054 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
5056 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
5057 // rs < rt -> rt > rs.
5058 // We can let assembler map it, or we can do in the compiler itself.
5059 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5060 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
5062 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
5063 // rss < rtt -> (rtt > rss).
5064 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5065 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
5067 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
5068 // rs < rt -> rt > rs.
5069 // We can let assembler map it, or we can do in the compiler itself.
5070 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5071 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
5073 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
5074 // rs < rt -> rt > rs.
5075 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5076 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
5078 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
5079 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
5080 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
5082 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
5083 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
5084 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
5086 // Generate cmpgtu(Rs, #u9)
5087 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
5088 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
5090 // Map from Rs >= Rt -> !(Rt > Rs).
5091 // rs >= rt -> !(rt > rs).
5092 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5093 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
5095 // Map from Rs >= Rt -> !(Rt > Rs).
5096 // rs >= rt -> !(rt > rs).
5097 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5098 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
5100 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
5101 // Map from (Rs <= Rt) -> !(Rs > Rt).
5102 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5103 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
5105 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
5106 // Map from (Rs <= Rt) -> !(Rs > Rt).
5107 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5108 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
5112 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
5113 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
5116 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
5117 (i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
5119 // Convert sign-extended load back to load and sign extend.
5121 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
5122 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
5124 // Convert any-extended load back to load and sign extend.
5126 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
5127 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
5129 // Convert sign-extended load back to load and sign extend.
5131 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
5132 (i64 (A2_sxtw (L2_loadrh_io AddrFI:$src1, 0)))>;
5134 // Convert sign-extended load back to load and sign extend.
5136 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
5137 (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
5142 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
5143 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
5146 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
5147 (i64 (A2_combinew (A2_tfrsi 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
5151 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
5152 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
5156 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
5157 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
5160 let AddedComplexity = 20 in
5161 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
5162 s11_0ExtPred:$offset))),
5163 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
5164 s11_0ExtPred:$offset)))>,
5168 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
5169 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
5172 let AddedComplexity = 20 in
5173 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
5174 s11_0ExtPred:$offset))),
5175 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
5176 s11_0ExtPred:$offset)))>,
5180 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
5181 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
5184 let AddedComplexity = 20 in
5185 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
5186 s11_1ExtPred:$offset))),
5187 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
5188 s11_1ExtPred:$offset)))>,
5192 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
5193 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
5196 let AddedComplexity = 100 in
5197 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
5198 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
5199 s11_2ExtPred:$offset)))>,
5202 let AddedComplexity = 10 in
5203 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
5204 (i32 (L2_loadri_io AddrFI:$src1, 0))>;
5206 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5207 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
5208 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
5210 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5211 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
5212 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
5214 // Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
5215 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
5216 (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
5219 let AddedComplexity = 100 in
5220 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5222 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
5223 s11_2ExtPred:$offset2)))))),
5224 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5225 (L2_loadri_io IntRegs:$src2,
5226 s11_2ExtPred:$offset2)))>;
5228 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5230 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
5231 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5232 (L2_loadri_io AddrFI:$srcLow, 0)))>;
5234 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5236 (i64 (zext (i32 IntRegs:$srcLow))))),
5237 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5240 let AddedComplexity = 100 in
5241 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5243 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
5244 s11_2ExtPred:$offset2)))))),
5245 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5246 (L2_loadri_io IntRegs:$src2,
5247 s11_2ExtPred:$offset2)))>;
5249 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5251 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
5252 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5253 (L2_loadri_io AddrFI:$srcLow, 0)))>;
5255 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5257 (i64 (zext (i32 IntRegs:$srcLow))))),
5258 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5261 // Any extended 64-bit load.
5262 // anyext i32 -> i64
5263 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
5264 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
5267 // When there is an offset we should prefer the pattern below over the pattern above.
5268 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
5269 // So this complexity below is comfortably higher to allow for choosing the below.
5270 // If this is not done then we generate addresses such as
5271 // ********************************************
5272 // r1 = add (r0, #4)
5273 // r1 = memw(r1 + #0)
5275 // r1 = memw(r0 + #4)
5276 // ********************************************
5277 let AddedComplexity = 100 in
5278 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
5279 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
5280 s11_2ExtPred:$offset)))>,
5283 // anyext i16 -> i64.
5284 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
5285 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io AddrFI:$src1, 0)))>,
5288 let AddedComplexity = 20 in
5289 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
5290 s11_1ExtPred:$offset))),
5291 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io IntRegs:$src1,
5292 s11_1ExtPred:$offset)))>,
5295 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
5296 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
5297 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
5300 // Multiply 64-bit unsigned and use upper result.
5301 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5316 (A2_combinew (A2_tfrsi 0),
5323 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
5325 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
5326 subreg_loreg)))), 32)),
5328 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5329 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
5330 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
5331 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
5332 32)), subreg_loreg)))),
5333 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5334 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
5336 // Multiply 64-bit signed and use upper result.
5337 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5341 (A2_combinew (A2_tfrsi 0),
5351 (A2_combinew (A2_tfrsi 0),
5358 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
5360 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
5361 subreg_loreg)))), 32)),
5363 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5364 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
5365 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
5366 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
5367 32)), subreg_loreg)))),
5368 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5369 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
5371 // Hexagon specific ISD nodes.
5372 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
5373 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
5374 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
5375 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
5376 SDTHexagonADJDYNALLOC>;
5377 // Needed to tag these instructions for stack layout.
5378 let usesCustomInserter = 1 in
5379 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
5381 "$dst = add($src1, #$src2)",
5382 [(set (i32 IntRegs:$dst),
5383 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
5384 s16ImmPred:$src2))]>;
5386 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
5387 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
5388 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5390 [(set (i32 IntRegs:$dst),
5391 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5393 let AddedComplexity = 100 in
5394 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5395 (COPY (i32 IntRegs:$src1))>;
5397 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
5399 def : Pat<(HexagonWrapperJT tjumptable:$dst),
5400 (i32 (CONST32_set_jt tjumptable:$dst))>;
5404 //===----------------------------------------------------------------------===//
5406 // Shift by immediate/register and accumulate/logical
5407 //===----------------------------------------------------------------------===//
5409 // Rx[+-&|]=asr(Rs,#u5)
5410 // Rx[+-&|^]=lsr(Rs,#u5)
5411 // Rx[+-&|^]=asl(Rs,#u5)
5413 let hasNewValue = 1, opNewValue = 0 in
5414 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5415 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5416 : SInst_acc<(outs IntRegs:$Rx),
5417 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5418 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5419 [(set (i32 IntRegs:$Rx),
5420 (OpNode2 (i32 IntRegs:$src1),
5421 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5422 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
5427 let IClass = 0b1000;
5429 let Inst{27-24} = 0b1110;
5430 let Inst{23-22} = majOp{2-1};
5432 let Inst{7} = majOp{0};
5433 let Inst{6-5} = minOp;
5435 let Inst{20-16} = Rs;
5436 let Inst{12-8} = u5;
5439 // Rx[+-&|]=asr(Rs,Rt)
5440 // Rx[+-&|^]=lsr(Rs,Rt)
5441 // Rx[+-&|^]=asl(Rs,Rt)
5443 let hasNewValue = 1, opNewValue = 0 in
5444 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5445 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
5446 : SInst_acc<(outs IntRegs:$Rx),
5447 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5448 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5449 [(set (i32 IntRegs:$Rx),
5450 (OpNode2 (i32 IntRegs:$src1),
5451 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5452 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
5457 let IClass = 0b1100;
5459 let Inst{27-24} = 0b1100;
5460 let Inst{23-22} = majOp;
5461 let Inst{7-6} = minOp;
5463 let Inst{20-16} = Rs;
5464 let Inst{12-8} = Rt;
5467 // Rxx[+-&|]=asr(Rss,#u6)
5468 // Rxx[+-&|^]=lsr(Rss,#u6)
5469 // Rxx[+-&|^]=asl(Rss,#u6)
5471 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5472 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5473 : SInst_acc<(outs DoubleRegs:$Rxx),
5474 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
5475 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5476 [(set (i64 DoubleRegs:$Rxx),
5477 (OpNode2 (i64 DoubleRegs:$src1),
5478 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
5479 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
5484 let IClass = 0b1000;
5486 let Inst{27-24} = 0b0010;
5487 let Inst{23-22} = majOp{2-1};
5488 let Inst{7} = majOp{0};
5489 let Inst{6-5} = minOp;
5490 let Inst{4-0} = Rxx;
5491 let Inst{20-16} = Rss;
5492 let Inst{13-8} = u6;
5496 // Rxx[+-&|]=asr(Rss,Rt)
5497 // Rxx[+-&|^]=lsr(Rss,Rt)
5498 // Rxx[+-&|^]=asl(Rss,Rt)
5499 // Rxx[+-&|^]=lsl(Rss,Rt)
5501 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5502 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5503 : SInst_acc<(outs DoubleRegs:$Rxx),
5504 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5505 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5506 [(set (i64 DoubleRegs:$Rxx),
5507 (OpNode2 (i64 DoubleRegs:$src1),
5508 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5509 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
5514 let IClass = 0b1100;
5516 let Inst{27-24} = 0b1011;
5517 let Inst{23-21} = majOp;
5518 let Inst{20-16} = Rss;
5519 let Inst{12-8} = Rt;
5520 let Inst{7-6} = minOp;
5521 let Inst{4-0} = Rxx;
5524 //===----------------------------------------------------------------------===//
5525 // Multi-class for the shift instructions with logical/arithmetic operators.
5526 //===----------------------------------------------------------------------===//
5528 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
5529 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
5530 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
5531 OpNode2, majOp, minOp >;
5532 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
5533 OpNode2, majOp, minOp >;
5536 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5537 let AddedComplexity = 100 in
5538 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5540 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5541 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5542 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
5545 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5546 let AddedComplexity = 100 in
5547 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
5550 let isCodeGenOnly = 0 in {
5551 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5553 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5554 xtype_xor_imm_acc<"lsr", srl, 0b01>;
5556 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5557 xtype_xor_imm_acc<"asl", shl, 0b10>;
5560 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
5561 let AddedComplexity = 100 in
5562 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
5564 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
5565 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5566 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5569 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
5570 let AddedComplexity = 100 in
5571 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
5573 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
5574 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
5575 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5576 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
5579 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5580 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5581 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
5584 let isCodeGenOnly = 0 in {
5585 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
5586 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5587 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5588 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
5591 //===----------------------------------------------------------------------===//
5592 let hasSideEffects = 0 in
5593 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
5594 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
5595 : SInst <(outs RC:$dst),
5596 (ins DoubleRegs:$src1, DoubleRegs:$src2),
5597 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
5598 #!if(hasShift,":>>1","")
5599 #!if(isSat, ":sat", ""),
5600 [], "", S_3op_tc_2_SLOT23 > {
5605 let IClass = 0b1100;
5607 let Inst{27-24} = 0b0001;
5608 let Inst{23-22} = MajOp;
5609 let Inst{20-16} = !if (SwapOps, src2, src1);
5610 let Inst{12-8} = !if (SwapOps, src1, src2);
5611 let Inst{7-5} = MinOp;
5612 let Inst{4-0} = dst;
5615 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
5616 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
5617 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
5618 isSat, isRnd, hasShift>;
5620 let Itinerary = S_3op_tc_1_SLOT23, isCodeGenOnly = 0 in {
5621 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5622 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5623 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5624 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
5626 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
5627 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
5630 let isCodeGenOnly = 0 in
5631 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
5633 let hasSideEffects = 0 in
5634 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
5635 : SInst < (outs DoubleRegs:$Rdd),
5636 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5637 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5638 [], "", S_3op_tc_1_SLOT23 > {
5644 let IClass = 0b1100;
5646 let Inst{27-24} = 0b0010;
5647 let Inst{23-21} = MajOp;
5648 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5649 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5651 let Inst{4-0} = Rdd;
5654 let isCodeGenOnly = 0 in {
5655 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5656 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
5659 //===----------------------------------------------------------------------===//
5660 // Template class used by vector shift, vector rotate, vector neg,
5661 // 32-bit shift, 64-bit shifts, etc.
5662 //===----------------------------------------------------------------------===//
5664 let hasSideEffects = 0 in
5665 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
5666 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
5667 : SInst <(outs RC:$dst),
5668 (ins RC:$src1, IntRegs:$src2),
5669 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
5670 pattern, "", S_3op_tc_1_SLOT23> {
5675 let IClass = 0b1100;
5677 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5678 let Inst{23-22} = MajOp;
5679 let Inst{20-16} = src1;
5680 let Inst{12-8} = src2;
5681 let Inst{7-6} = MinOp;
5682 let Inst{4-0} = dst;
5685 let hasNewValue = 1 in
5686 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5687 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5688 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5689 (i32 IntRegs:$src2)))]>;
5691 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
5692 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
5693 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5696 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5697 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5698 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5699 (i32 IntRegs:$src2)))]>;
5702 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5703 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5706 // Shift by register
5707 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5709 let isCodeGenOnly = 0 in {
5710 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5711 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5712 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5713 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5716 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5718 let isCodeGenOnly = 0 in {
5719 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5720 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5721 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5722 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5725 // Shift by register with saturation
5726 // Rd=asr(Rs,Rt):sat
5727 // Rd=asl(Rs,Rt):sat
5729 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
5730 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5731 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5734 let hasNewValue = 1, hasSideEffects = 0 in
5735 class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
5736 : SInst < (outs IntRegs:$Rd),
5737 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5738 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5739 #!if(hasShift, ":<<1", "")
5740 #!if(isRnd, ":rnd", "")
5741 #!if(isSat, ":sat", ""),
5742 [], "", S_3op_tc_1_SLOT23 > {
5747 let IClass = 0b1100;
5749 let Inst{27-24} = 0b0101;
5750 let Inst{20-16} = Rss;
5751 let Inst{12-8} = Rt;
5752 let Inst{7-5} = MinOp;
5756 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in
5757 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5759 let hasSideEffects = 0 in
5760 class T_S3op_7 <string mnemonic, bit MajOp >
5761 : SInst <(outs DoubleRegs:$Rdd),
5762 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
5763 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
5764 [], "", S_3op_tc_1_SLOT23 > {
5770 let IClass = 0b1100;
5772 let Inst{27-24} = 0b0000;
5773 let Inst{23} = MajOp;
5774 let Inst{20-16} = !if(MajOp, Rss, Rtt);
5775 let Inst{12-8} = !if(MajOp, Rtt, Rss);
5777 let Inst{4-0} = Rdd;
5780 let isCodeGenOnly = 0 in {
5781 def S2_valignib : T_S3op_7 < "valignb", 0>;
5782 def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
5785 //===----------------------------------------------------------------------===//
5786 // Template class for 'insert bitfield' instructions
5787 //===----------------------------------------------------------------------===//
5788 let hasSideEffects = 0 in
5789 class T_S3op_insert <string mnemonic, RegisterClass RC>
5790 : SInst <(outs RC:$dst),
5791 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5792 "$dst = "#mnemonic#"($src2, $src3)" ,
5793 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5798 let IClass = 0b1100;
5800 let Inst{27-26} = 0b10;
5801 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5803 let Inst{20-16} = src2;
5804 let Inst{12-8} = src3;
5805 let Inst{4-0} = dst;
5808 let hasSideEffects = 0 in
5809 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5810 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5811 "$dst = insert($src1, #$src2, #$src3)",
5812 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5819 string ImmOpStr = !cast<string>(ImmOp);
5821 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5822 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5824 let IClass = 0b1000;
5826 let Inst{27-24} = RegTyBits;
5827 let Inst{23} = bit23;
5828 let Inst{22-21} = src3{4-3};
5829 let Inst{20-16} = src1;
5830 let Inst{13} = bit13;
5831 let Inst{12-8} = src2{4-0};
5832 let Inst{7-5} = src3{2-0};
5833 let Inst{4-0} = dst;
5836 // Rx=insert(Rs,Rtt)
5837 // Rx=insert(Rs,#u5,#U5)
5838 let hasNewValue = 1, isCodeGenOnly = 0 in {
5839 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5840 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5843 // Rxx=insert(Rss,Rtt)
5844 // Rxx=insert(Rss,#u6,#U6)
5845 let isCodeGenOnly = 0 in {
5846 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5847 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5850 //===----------------------------------------------------------------------===//
5851 // Template class for 'extract bitfield' instructions
5852 //===----------------------------------------------------------------------===//
5853 let hasNewValue = 1, hasSideEffects = 0 in
5854 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5855 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5856 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5857 [], "", S_3op_tc_2_SLOT23 > {
5862 let IClass = 0b1100;
5864 let Inst{27-22} = 0b100100;
5865 let Inst{20-16} = Rs;
5866 let Inst{12-8} = Rtt;
5867 let Inst{7-6} = MinOp;
5871 let hasSideEffects = 0 in
5872 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5873 RegisterClass RC, Operand ImmOp>
5874 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5875 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5876 [], "", S_2op_tc_2_SLOT23> {
5883 string ImmOpStr = !cast<string>(ImmOp);
5885 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5886 !if (!eq(mnemonic, "extractu"), 0, 1));
5888 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5890 let IClass = 0b1000;
5892 let Inst{27-24} = RegTyBits;
5893 let Inst{23} = bit23;
5894 let Inst{22-21} = src3{4-3};
5895 let Inst{20-16} = src1;
5896 let Inst{13} = bit13;
5897 let Inst{12-8} = src2{4-0};
5898 let Inst{7-5} = src3{2-0};
5899 let Inst{4-0} = dst;
5904 // Rdd=extractu(Rss,Rtt)
5905 // Rdd=extractu(Rss,#u6,#U6)
5906 let isCodeGenOnly = 0 in {
5907 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5908 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5911 // Rd=extractu(Rs,Rtt)
5912 // Rd=extractu(Rs,#u5,#U5)
5913 let hasNewValue = 1, isCodeGenOnly = 0 in {
5914 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5915 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5918 //===----------------------------------------------------------------------===//
5919 // :raw for of tableindx[bdhw] insns
5920 //===----------------------------------------------------------------------===//
5922 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5923 class tableidxRaw<string OpStr, bits<2>MinOp>
5924 : SInst <(outs IntRegs:$Rx),
5925 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5926 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5927 [], "$Rx = $_dst_" > {
5933 let IClass = 0b1000;
5935 let Inst{27-24} = 0b0111;
5936 let Inst{23-22} = MinOp;
5937 let Inst{21} = u4{3};
5938 let Inst{20-16} = Rs;
5939 let Inst{13-8} = S6;
5940 let Inst{7-5} = u4{2-0};
5944 let isCodeGenOnly = 0 in {
5945 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5946 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5947 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5948 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5951 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5952 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5953 (i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
5955 //===----------------------------------------------------------------------===//
5956 // V3 Instructions +
5957 //===----------------------------------------------------------------------===//
5959 include "HexagonInstrInfoV3.td"
5961 //===----------------------------------------------------------------------===//
5962 // V3 Instructions -
5963 //===----------------------------------------------------------------------===//
5965 //===----------------------------------------------------------------------===//
5966 // V4 Instructions +
5967 //===----------------------------------------------------------------------===//
5969 include "HexagonInstrInfoV4.td"
5971 //===----------------------------------------------------------------------===//
5972 // V4 Instructions -
5973 //===----------------------------------------------------------------------===//
5975 //===----------------------------------------------------------------------===//
5976 // V5 Instructions +
5977 //===----------------------------------------------------------------------===//
5979 include "HexagonInstrInfoV5.td"
5981 //===----------------------------------------------------------------------===//
5982 // V5 Instructions -
5983 //===----------------------------------------------------------------------===//