1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
66 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
69 : ALU32Inst <(outs PredRegs:$dst),
70 (ins IntRegs:$src1, ImmOp:$src2),
71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
72 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
76 let CextOpcode = mnemonic;
77 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
78 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
82 let Inst{27-24} = 0b0101;
83 let Inst{23-22} = MajOp;
84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
85 let Inst{20-16} = src1;
86 let Inst{13-5} = src2{8-0};
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
94 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
96 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
100 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
101 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
102 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
109 def SDT_Int32Leaf : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
110 def SDT_Int32Unary : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
112 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
113 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
115 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
116 def HexagonPACKHL : SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>;
118 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
119 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
123 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
124 let isCommutable = IsComm;
125 let BaseOpcode = mnemonic#_rr;
126 let CextOpcode = mnemonic;
134 let Inst{26-24} = MajOp;
135 let Inst{23-21} = MinOp;
136 let Inst{20-16} = !if(OpsRev,Rt,Rs);
137 let Inst{12-8} = !if(OpsRev,Rs,Rt);
141 let hasSideEffects = 0, hasNewValue = 1 in
142 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
143 bit OpsRev, bit PredNot, bit PredNew>
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
145 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
146 "$Rd = "#mnemonic#"($Rs, $Rt)",
147 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
148 let isPredicated = 1;
149 let isPredicatedFalse = PredNot;
150 let isPredicatedNew = PredNew;
151 let BaseOpcode = mnemonic#_rr;
152 let CextOpcode = mnemonic;
161 let Inst{26-24} = MajOp;
162 let Inst{23-21} = MinOp;
163 let Inst{20-16} = !if(OpsRev,Rt,Rs);
164 let Inst{13} = PredNew;
165 let Inst{12-8} = !if(OpsRev,Rs,Rt);
166 let Inst{7} = PredNot;
171 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
173 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
174 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
177 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
178 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
179 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
180 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
182 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
183 bits<3> MinOp, bit OpsRev, bit IsComm>
184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
189 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
191 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in {
192 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
194 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
195 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
196 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
197 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
200 let Itinerary = ALU32_3op_tc_2_SLOT0123 in
201 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
204 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
206 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
208 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
209 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
210 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
211 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
214 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
215 bit OpsRev, bit IsComm> {
216 let isPredicable = 1 in
217 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
218 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
223 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
224 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
225 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
227 // Pats for instruction selection.
228 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
232 def: BinOp32_pat<add, A2_add, i32>;
233 def: BinOp32_pat<and, A2_and, i32>;
234 def: BinOp32_pat<or, A2_or, i32>;
235 def: BinOp32_pat<sub, A2_sub, i32>;
236 def: BinOp32_pat<xor, A2_xor, i32>;
238 // A few special cases producing register pairs:
239 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
240 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
242 let isPredicable = 1 in
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
245 // Conditional combinew uses "newt/f" instead of "t/fnew".
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
252 def: BinOp32_pat<HexagonCOMBINE, A2_combinew, i64>;
253 def: BinOp32_pat<HexagonPACKHL, S2_packhl, i64>;
255 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
256 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
258 "$Pd = "#mnemonic#"($Rs, $Rt)",
259 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
260 let CextOpcode = mnemonic;
261 let isCommutable = IsComm;
267 let Inst{27-24} = 0b0010;
268 let Inst{22-21} = MinOp;
269 let Inst{20-16} = Rs;
272 let Inst{3-2} = 0b00;
276 let Itinerary = ALU32_3op_tc_2early_SLOT0123 in {
277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
278 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
279 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
282 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
283 // that reverse the order of the operands.
284 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
286 // Pats for compares. They use PatFrags as operands, not SDNodes,
287 // since seteq/setgt/etc. are defined as ParFrags.
288 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
292 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
293 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
294 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
296 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
297 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
299 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in
300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
302 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
308 let CextOpcode = "mux";
309 let InputType = "reg";
310 let hasSideEffects = 0;
313 let Inst{27-24} = 0b0100;
314 let Inst{20-16} = Rs;
320 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
323 // Combines the two immediates into a double register.
324 // Increase complexity to make it greater than any complexity of a combine
325 // that involves a register.
327 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
328 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
329 AddedComplexity = 75 in
330 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
331 "$Rdd = combine(#$s8, #$S8)",
332 [(set (i64 DoubleRegs:$Rdd),
333 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
339 let Inst{27-23} = 0b11000;
340 let Inst{22-16} = S8{7-1};
341 let Inst{13} = S8{0};
346 //===----------------------------------------------------------------------===//
347 // Template class for predicated ADD of a reg and an Immediate value.
348 //===----------------------------------------------------------------------===//
349 let hasNewValue = 1, hasSideEffects = 0 in
350 class T_Addri_Pred <bit PredNot, bit PredNew>
351 : ALU32_ri <(outs IntRegs:$Rd),
352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
353 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
354 ") $Rd = ")#"add($Rs, #$s8)"> {
360 let isPredicatedNew = PredNew;
363 let Inst{27-24} = 0b0100;
364 let Inst{23} = PredNot;
365 let Inst{22-21} = Pu;
366 let Inst{20-16} = Rs;
367 let Inst{13} = PredNew;
372 //===----------------------------------------------------------------------===//
373 // A2_addi: Add a signed immediate to a register.
374 //===----------------------------------------------------------------------===//
375 let hasNewValue = 1, hasSideEffects = 0 in
376 class T_Addri <Operand immOp>
377 : ALU32_ri <(outs IntRegs:$Rd),
378 (ins IntRegs:$Rs, immOp:$s16),
379 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
386 let Inst{27-21} = s16{15-9};
387 let Inst{20-16} = Rs;
388 let Inst{13-5} = s16{8-0};
392 //===----------------------------------------------------------------------===//
393 // Multiclass for ADD of a register and an immediate value.
394 //===----------------------------------------------------------------------===//
395 multiclass Addri_Pred<string mnemonic, bit PredNot> {
396 let isPredicatedFalse = PredNot in {
397 def NAME : T_Addri_Pred<PredNot, 0>;
399 def NAME#new : T_Addri_Pred<PredNot, 1>;
403 let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
404 multiclass Addri_base<string mnemonic, SDNode OpNode> {
405 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
406 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
407 def A2_#NAME : T_Addri<s16Ext>;
409 let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
410 defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
411 defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
416 defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
418 def: Pat<(i32 (add I32:$Rs, s16ExtPred:$s16)),
419 (i32 (A2_addi I32:$Rs, imm:$s16))>;
421 //===----------------------------------------------------------------------===//
422 // Template class used for the following ALU32 instructions.
425 //===----------------------------------------------------------------------===//
426 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
427 InputType = "imm", hasNewValue = 1 in
428 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
429 : ALU32_ri <(outs IntRegs:$Rd),
430 (ins IntRegs:$Rs, s10Ext:$s10),
431 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
436 let CextOpcode = mnemonic;
440 let Inst{27-24} = 0b0110;
441 let Inst{23-22} = MinOp;
442 let Inst{21} = s10{9};
443 let Inst{20-16} = Rs;
444 let Inst{13-5} = s10{8-0};
448 def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
449 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
451 // Subtract register from immediate
452 // Rd32=sub(#s10,Rs32)
453 let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1,
454 opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
455 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
456 "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
463 let Inst{27-22} = 0b011001;
464 let Inst{21} = s10{9};
465 let Inst{20-16} = Rs;
466 let Inst{13-5} = s10{8-0};
471 let hasSideEffects = 0 in
472 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
474 let Inst{27-24} = 0b1111;
477 def: Pat<(sub s10ExtPred:$s10, IntRegs:$Rs),
478 (A2_subri imm:$s10, IntRegs:$Rs)>;
480 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
481 def: Pat<(not (i32 IntRegs:$src1)),
482 (A2_subri -1, IntRegs:$src1)>;
484 let hasSideEffects = 0, hasNewValue = 1 in
485 class T_tfr16<bit isHi>
486 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
487 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
488 [], "$src1 = $Rx" > {
493 let Inst{27-26} = 0b00;
494 let Inst{25-24} = !if(isHi, 0b10, 0b01);
495 let Inst{23-22} = u16{15-14};
497 let Inst{20-16} = Rx;
498 let Inst{13-0} = u16{13-0};
501 def A2_tfril: T_tfr16<0>;
502 def A2_tfrih: T_tfr16<1>;
504 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
505 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
506 class T_tfr_pred<bit isPredNot, bit isPredNew>
507 : ALU32Inst<(outs IntRegs:$dst),
508 (ins PredRegs:$src1, IntRegs:$src2),
509 "if ("#!if(isPredNot, "!", "")#
510 "$src1"#!if(isPredNew, ".new", "")#
516 let isPredicatedFalse = isPredNot;
517 let isPredicatedNew = isPredNew;
520 let Inst{27-24} = 0b0100;
521 let Inst{23} = isPredNot;
522 let Inst{13} = isPredNew;
525 let Inst{22-21} = src1;
526 let Inst{20-16} = src2;
529 let isPredicable = 1 in
530 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
537 let Inst{27-21} = 0b0000011;
538 let Inst{20-16} = src;
543 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
544 multiclass tfr_base<string CextOp> {
545 let CextOpcode = CextOp, BaseOpcode = CextOp in {
549 def t : T_tfr_pred<0, 0>;
550 def f : T_tfr_pred<1, 0>;
552 def tnew : T_tfr_pred<0, 1>;
553 def fnew : T_tfr_pred<1, 1>;
557 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
558 // Please don't add bits to this instruction as it'll be converted into
559 // 'combine' before object code emission.
560 let isPredicated = 1 in
561 class T_tfrp_pred<bit PredNot, bit PredNew>
562 : ALU32_rr <(outs DoubleRegs:$dst),
563 (ins PredRegs:$src1, DoubleRegs:$src2),
564 "if ("#!if(PredNot, "!", "")#"$src1"
565 #!if(PredNew, ".new", "")#") $dst = $src2" > {
566 let isPredicatedFalse = PredNot;
567 let isPredicatedNew = PredNew;
570 // Assembler mapped to A2_combinew.
571 // Please don't add bits to this instruction as it'll be converted into
572 // 'combine' before object code emission.
573 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
574 (ins DoubleRegs:$src),
577 let hasSideEffects = 0 in
578 multiclass TFR64_base<string BaseName> {
579 let BaseOpcode = BaseName in {
580 let isPredicable = 1 in
583 def t : T_tfrp_pred <0, 0>;
584 def f : T_tfrp_pred <1, 0>;
586 def tnew : T_tfrp_pred <0, 1>;
587 def fnew : T_tfrp_pred <1, 1>;
591 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
592 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
593 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
594 class T_TFRI_Pred<bit PredNot, bit PredNew>
595 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
596 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
597 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
598 let isPredicatedFalse = PredNot;
599 let isPredicatedNew = PredNew;
606 let Inst{27-24} = 0b1110;
607 let Inst{23} = PredNot;
608 let Inst{22-21} = Pu;
610 let Inst{19-16,12-5} = s12;
611 let Inst{13} = PredNew;
615 def C2_cmoveit : T_TFRI_Pred<0, 0>;
616 def C2_cmoveif : T_TFRI_Pred<1, 0>;
617 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
618 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
620 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
621 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
622 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
623 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
624 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
625 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
631 let Inst{27-24} = 0b1000;
632 let Inst{23-22,20-16,13-5} = s16;
636 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
637 let isAsmParserOnly = 1 in
638 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
641 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
642 isAsmParserOnly = 1 in
643 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
645 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
647 // TODO: see if this instruction can be deleted..
648 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
649 isAsmParserOnly = 1 in {
650 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64Imm:$src1),
652 def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
653 (ins s8Ext:$src1, s8Imm:$src2),
654 "$dst = combine(##$src1, #$src2)">;
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
665 // Scalar mux register immediate.
666 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
667 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
668 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
669 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
676 let Inst{27-24} = 0b0011;
677 let Inst{23} = MajOp;
678 let Inst{22-21} = Pu;
679 let Inst{20-16} = Rs;
685 let opExtendable = 2 in
686 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
687 "$Rd = mux($Pu, #$s8, $Rs)">;
689 let opExtendable = 3 in
690 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
691 "$Rd = mux($Pu, $Rs, #$s8)">;
693 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
694 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
696 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
697 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
699 // C2_muxii: Scalar mux immediates.
700 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
701 opExtentBits = 8, opExtendable = 2 in
702 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
703 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
704 "$Rd = mux($Pu, #$s8, #$S8)" ,
705 [(set (i32 IntRegs:$Rd),
706 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
714 let Inst{27-25} = 0b101;
715 let Inst{24-23} = Pu;
716 let Inst{22-16} = S8{7-1};
717 let Inst{13} = S8{0};
722 let isCodeGenOnly = 1, isPseudo = 1 in
723 def MUX64_rr : ALU64_rr<(outs DoubleRegs:$Rd),
724 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
725 ".error \"should not emit\" ", []>;
728 //===----------------------------------------------------------------------===//
729 // template class for non-predicated alu32_2op instructions
730 // - aslh, asrh, sxtb, sxth, zxth
731 //===----------------------------------------------------------------------===//
732 let hasNewValue = 1, opNewValue = 0 in
733 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
734 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
735 "$Rd = "#mnemonic#"($Rs)", [] > {
741 let Inst{27-24} = 0b0000;
742 let Inst{23-21} = minOp;
745 let Inst{20-16} = Rs;
748 //===----------------------------------------------------------------------===//
749 // template class for predicated alu32_2op instructions
750 // - aslh, asrh, sxtb, sxth, zxtb, zxth
751 //===----------------------------------------------------------------------===//
752 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
753 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
755 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
756 !if(isPredNot, "if (!$Pu", "if ($Pu")
757 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
764 let Inst{27-24} = 0b0000;
765 let Inst{23-21} = minOp;
767 let Inst{11} = isPredNot;
768 let Inst{10} = isPredNew;
771 let Inst{20-16} = Rs;
774 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
775 let isPredicatedFalse = PredNot in {
776 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
779 let isPredicatedNew = 1 in
780 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
784 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
785 let BaseOpcode = mnemonic in {
786 let isPredicable = 1, hasSideEffects = 0 in
787 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
789 let isPredicated = 1, hasSideEffects = 0 in {
790 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
791 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
796 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
797 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
798 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
799 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
800 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
802 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
803 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
804 // predicated forms while 'and' doesn't. Since integrated assembler can't
805 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
806 // immediate operand is set to '255'.
808 let hasNewValue = 1, opNewValue = 0 in
809 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
810 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
817 let Inst{27-22} = 0b011000;
819 let Inst{20-16} = Rs;
820 let Inst{21} = s10{9};
821 let Inst{13-5} = s10{8-0};
824 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
825 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
826 let BaseOpcode = mnemonic in {
827 let isPredicable = 1, hasSideEffects = 0 in
828 def A2_#NAME : T_ZXTB;
830 let isPredicated = 1, hasSideEffects = 0 in {
831 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
832 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
837 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
839 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
840 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
841 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
842 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
844 //===----------------------------------------------------------------------===//
845 // Template class for vector add and avg
846 //===----------------------------------------------------------------------===//
848 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
849 bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
850 : ALU64_rr < (outs DoubleRegs:$Rdd),
851 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
852 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
853 #!if(isCrnd,":crnd","")
854 #!if(isSat, ":sat", ""),
855 [], "", ALU64_tc_2_SLOT23 > {
862 let Inst{27-24} = 0b0011;
863 let Inst{23-21} = majOp;
864 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
865 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
866 let Inst{7-5} = minOp;
870 // ALU64 - Vector add
871 // Rdd=vadd[u][bhw](Rss,Rtt)
872 let Itinerary = ALU64_tc_1_SLOT23 in {
873 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
874 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
875 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
878 // Rdd=vadd[u][bhw](Rss,Rtt):sat
879 let Defs = [USR_OVF] in {
880 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
881 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
882 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
883 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
886 // ALU64 - Vector average
887 // Rdd=vavg[u][bhw](Rss,Rtt)
888 let Itinerary = ALU64_tc_1_SLOT23 in {
889 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
890 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
891 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
892 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
893 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
896 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
897 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
898 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
899 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
900 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
902 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
903 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
904 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
906 // Rdd=vnavg[bh](Rss,Rtt)
907 let Itinerary = ALU64_tc_1_SLOT23 in {
908 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
909 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
912 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
913 let Defs = [USR_OVF] in {
914 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
915 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
916 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
917 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
920 // Rdd=vsub[u][bh](Rss,Rtt)
921 let Itinerary = ALU64_tc_1_SLOT23 in {
922 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
923 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
924 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
927 // Rdd=vsub[u][bh](Rss,Rtt):sat
928 let Defs = [USR_OVF] in {
929 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
930 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
931 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
932 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
935 // Rdd=vmax[u][bhw](Rss,Rtt)
936 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
937 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
938 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
939 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
940 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
941 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
943 // Rdd=vmin[u][bhw](Rss,Rtt)
944 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
945 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
946 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
947 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
948 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
949 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
951 //===----------------------------------------------------------------------===//
952 // Template class for vector compare
953 //===----------------------------------------------------------------------===//
954 let hasSideEffects = 0 in
955 class T_vcmp <string Str, bits<4> minOp>
956 : ALU64_rr <(outs PredRegs:$Pd),
957 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
958 "$Pd = "#Str#"($Rss, $Rtt)", [],
959 "", ALU64_tc_2early_SLOT23> {
966 let Inst{27-23} = 0b00100;
967 let Inst{13} = minOp{3};
968 let Inst{7-5} = minOp{2-0};
970 let Inst{20-16} = Rss;
971 let Inst{12-8} = Rtt;
974 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
975 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
976 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
978 // Vector compare bytes
979 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
980 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
982 // Vector compare halfwords
983 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
984 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
985 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
987 // Vector compare words
988 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
989 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
990 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
992 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
993 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
994 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
995 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
996 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
997 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
998 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
999 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
1001 //===----------------------------------------------------------------------===//
1003 //===----------------------------------------------------------------------===//
1006 //===----------------------------------------------------------------------===//
1008 //===----------------------------------------------------------------------===//
1009 // No bits needed. If cmp.ge is found the assembler parser will
1010 // transform it to cmp.gt subtracting 1 from the immediate.
1011 let isPseudo = 1 in {
1012 def C2_cmpgei: ALU32Inst <
1013 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8),
1014 "$Pd = cmp.ge($Rs, #$s8)">;
1015 def C2_cmpgeui: ALU32Inst <
1016 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8),
1017 "$Pd = cmp.geu($Rs, #$s8)">;
1021 //===----------------------------------------------------------------------===//
1023 //===----------------------------------------------------------------------===//
1026 //===----------------------------------------------------------------------===//
1028 //===----------------------------------------------------------------------===//
1030 //===----------------------------------------------------------------------===//
1032 // Add/Subtract halfword
1033 // Rd=add(Rt.L,Rs.[HL])[:sat]
1034 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1035 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1036 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1037 //===----------------------------------------------------------------------===//
1039 let hasNewValue = 1, opNewValue = 0 in
1040 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1041 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1042 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1043 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
1044 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
1045 #!if(isSat,":sat","")
1046 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
1050 let IClass = 0b1101;
1052 let Inst{27-23} = 0b01010;
1053 let Inst{22} = hasShift;
1054 let Inst{21} = isSub;
1055 let Inst{7} = isSat;
1056 let Inst{6-5} = LHbits;
1058 let Inst{12-8} = Rt;
1059 let Inst{20-16} = Rs;
1062 //Rd=sub(Rt.L,Rs.[LH])
1063 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1064 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1066 //Rd=add(Rt.L,Rs.[LH])
1067 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1068 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1070 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1071 //Rd=sub(Rt.L,Rs.[LH]):sat
1072 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1073 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1075 //Rd=add(Rt.L,Rs.[LH]):sat
1076 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1077 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1080 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1081 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1082 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1083 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1084 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1086 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1087 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1088 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1089 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
1090 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1092 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1093 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1094 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1095 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1096 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
1097 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1099 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1100 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1101 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1102 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
1103 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
1107 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
1108 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
1110 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
1111 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1113 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1114 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1116 // Subtract halfword.
1117 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1118 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1120 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1121 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1123 let hasSideEffects = 0, hasNewValue = 1 in
1124 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1125 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1126 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1131 let IClass = 0b1101;
1132 let Inst{27-24} = 0b0000;
1133 let Inst{20-16} = Rs;
1134 let Inst{12-8} = Rt;
1138 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1139 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1140 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1141 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1142 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1147 let IClass = 0b1101;
1149 let Inst{27-23} = 0b01011;
1150 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1151 let Inst{7} = isUnsigned;
1153 let Inst{12-8} = !if(isMax, Rs, Rt);
1154 let Inst{20-16} = !if(isMax, Rt, Rs);
1157 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1158 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1159 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1160 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1162 // Here, depending on the operand being selected, we'll either generate a
1163 // min or max instruction.
1165 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1166 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1167 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1168 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1170 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1171 InstHexagon Inst, InstHexagon SwapInst> {
1172 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1173 (VT RC:$src1), (VT RC:$src2)),
1174 (Inst RC:$src1, RC:$src2)>;
1175 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1176 (VT RC:$src2), (VT RC:$src1)),
1177 (SwapInst RC:$src1, RC:$src2)>;
1181 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1182 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1184 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1185 (i32 PositiveHalfWord:$src2))),
1186 (i32 PositiveHalfWord:$src1),
1187 (i32 PositiveHalfWord:$src2))), i16),
1188 (Inst IntRegs:$src1, IntRegs:$src2)>;
1190 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1191 (i32 PositiveHalfWord:$src2))),
1192 (i32 PositiveHalfWord:$src2),
1193 (i32 PositiveHalfWord:$src1))), i16),
1194 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1197 let AddedComplexity = 200 in {
1198 defm: MinMax_pats<setge, A2_max, A2_min>;
1199 defm: MinMax_pats<setgt, A2_max, A2_min>;
1200 defm: MinMax_pats<setle, A2_min, A2_max>;
1201 defm: MinMax_pats<setlt, A2_min, A2_max>;
1202 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1203 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1204 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1205 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1208 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1209 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1210 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1212 let isCommutable = IsComm;
1213 let hasSideEffects = 0;
1219 let IClass = 0b1101;
1220 let Inst{27-21} = 0b0010100;
1221 let Inst{20-16} = Rs;
1222 let Inst{12-8} = Rt;
1223 let Inst{7-5} = MinOp;
1227 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1228 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1229 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1231 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1232 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1233 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1235 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1236 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1237 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1238 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1239 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1241 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1242 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1243 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1244 let hasSideEffects = 0;
1251 let IClass = 0b1101;
1252 let Inst{27-24} = 0b0001;
1253 let Inst{20-16} = Rs;
1254 let Inst{12-8} = Rt;
1259 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1260 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1262 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1263 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1264 "", ALU64_tc_1_SLOT23> {
1265 let hasSideEffects = 0;
1266 let isCommutable = IsComm;
1272 let IClass = 0b1101;
1273 let Inst{27-24} = RegType;
1274 let Inst{23-21} = MajOp;
1275 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1276 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1277 let Inst{7-5} = MinOp;
1281 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1282 bit OpsRev, bit IsComm>
1283 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1286 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1287 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1289 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1290 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1292 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1294 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1297 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1298 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1299 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1301 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1302 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1303 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1305 //===----------------------------------------------------------------------===//
1307 //===----------------------------------------------------------------------===//
1309 //===----------------------------------------------------------------------===//
1311 //===----------------------------------------------------------------------===//
1313 //===----------------------------------------------------------------------===//
1315 //===----------------------------------------------------------------------===//
1317 //===----------------------------------------------------------------------===//
1319 //===----------------------------------------------------------------------===//
1321 //===----------------------------------------------------------------------===//
1323 //===----------------------------------------------------------------------===//
1325 //===----------------------------------------------------------------------===//
1327 //===----------------------------------------------------------------------===//
1328 // Logical reductions on predicates.
1330 // Looping instructions.
1332 // Pipelined looping instructions.
1334 // Logical operations on predicates.
1335 let hasSideEffects = 0 in
1336 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1337 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1338 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1342 let IClass = 0b0110;
1343 let Inst{27-23} = 0b10111;
1344 let Inst{22-21} = OpBits;
1346 let Inst{17-16} = Ps;
1351 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1352 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1353 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1355 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1356 (C2_not PredRegs:$Ps)>;
1358 let hasSideEffects = 0 in
1359 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1360 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1361 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1362 [], "", CR_tc_2early_SLOT23> {
1367 let IClass = 0b0110;
1368 let Inst{27-24} = 0b1011;
1369 let Inst{23-21} = OpBits;
1371 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1372 let Inst{13} = 0b0; // instructions.
1373 let Inst{9-8} = !if(Rev,Ps,Pt);
1377 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1378 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1379 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1380 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1381 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1383 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1384 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1385 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1386 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1387 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1389 let hasSideEffects = 0, hasNewValue = 1 in
1390 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1391 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1396 let IClass = 0b1000;
1397 let Inst{27-24} = 0b1001;
1398 let Inst{22-21} = 0b00;
1399 let Inst{17-16} = Ps;
1404 let hasSideEffects = 0 in
1405 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1406 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1410 let IClass = 0b1000;
1411 let Inst{27-24} = 0b0110;
1416 // User control register transfer.
1417 //===----------------------------------------------------------------------===//
1419 //===----------------------------------------------------------------------===//
1421 //===----------------------------------------------------------------------===//
1423 //===----------------------------------------------------------------------===//
1425 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1426 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1427 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1429 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1430 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1432 class CondStr<string CReg, bit True, bit New> {
1433 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1435 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1436 string S = Mnemonic # !if(Taken, ":t", !if(New, ":nt", ""));
1439 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1441 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1442 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1443 class T_JMP<string ExtStr>
1444 : JInst<(outs), (ins brtarget:$dst),
1445 "jump " # ExtStr # "$dst",
1446 [], "", J_tc_2early_SLOT23> {
1448 let IClass = 0b0101;
1450 let Inst{27-25} = 0b100;
1451 let Inst{24-16} = dst{23-15};
1452 let Inst{13-1} = dst{14-2};
1455 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1456 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1457 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1458 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1459 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1460 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1461 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1463 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1464 let isTaken = isTak;
1465 let isPredicatedFalse = PredNot;
1466 let isPredicatedNew = isPredNew;
1470 let IClass = 0b0101;
1472 let Inst{27-24} = 0b1100;
1473 let Inst{21} = PredNot;
1474 let Inst{12} = isTak;
1475 let Inst{11} = isPredNew;
1476 let Inst{9-8} = src;
1477 let Inst{23-22} = dst{16-15};
1478 let Inst{20-16} = dst{14-10};
1479 let Inst{13} = dst{9};
1480 let Inst{7-1} = dst{8-2};
1483 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1484 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken
1486 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1487 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1490 multiclass JMP_base<string BaseOp, string ExtStr> {
1491 let BaseOpcode = BaseOp in {
1492 def NAME : T_JMP<ExtStr>;
1493 defm t : JMP_Pred<0, ExtStr>;
1494 defm f : JMP_Pred<1, ExtStr>;
1498 // Jumps to address stored in a register, JUMPR_MISC
1499 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1500 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1501 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1503 : JRInst<(outs), (ins IntRegs:$dst),
1504 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1507 let IClass = 0b0101;
1508 let Inst{27-21} = 0b0010100;
1509 let Inst{20-16} = dst;
1512 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1513 hasSideEffects = 0, InputType = "reg" in
1514 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1515 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1516 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1517 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1518 "", J_tc_2early_SLOT2> {
1520 let isTaken = isTak;
1521 let isPredicatedFalse = PredNot;
1522 let isPredicatedNew = isPredNew;
1526 let IClass = 0b0101;
1528 let Inst{27-22} = 0b001101;
1529 let Inst{21} = PredNot;
1530 let Inst{20-16} = dst;
1531 let Inst{12} = isTak;
1532 let Inst{11} = isPredNew;
1533 let Inst{9-8} = src;
1536 multiclass JMPR_Pred<bit PredNot> {
1537 def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
1539 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1540 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1543 multiclass JMPR_base<string BaseOp> {
1544 let BaseOpcode = BaseOp in {
1546 defm t : JMPR_Pred<0>;
1547 defm f : JMPR_Pred<1>;
1551 let isCall = 1, hasSideEffects = 1 in
1552 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1553 dag InputDag = (ins IntRegs:$Rs)>
1554 : JRInst<(outs), InputDag,
1555 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1556 "if ($Pu) callr $Rs"),
1558 [], "", J_tc_2early_SLOT2> {
1561 let isPredicated = isPred;
1562 let isPredicatedFalse = isPredNot;
1564 let IClass = 0b0101;
1565 let Inst{27-25} = 0b000;
1566 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1568 let Inst{21} = isPredNot;
1569 let Inst{9-8} = !if (isPred, Pu, 0b00);
1570 let Inst{20-16} = Rs;
1574 let Defs = VolatileV3.Regs in {
1575 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1576 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1579 let isTerminator = 1, hasSideEffects = 0 in {
1580 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1582 // Deal with explicit assembly
1583 // - never extened a jump #, always extend a jump ##
1584 let isAsmParserOnly = 1 in {
1585 defm J2_jump_ext : JMP_base<"JMP", "##">;
1586 defm J2_jump_noext : JMP_base<"JMP", "#">;
1589 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1591 let isReturn = 1, isCodeGenOnly = 1 in
1592 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1595 def: Pat<(br bb:$dst),
1596 (J2_jump brtarget:$dst)>;
1598 (JMPret (i32 R31))>;
1599 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1600 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1602 // A return through builtin_eh_return.
1603 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1604 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1605 def EH_RETURN_JMPR : T_JMPr;
1607 def: Pat<(eh_return),
1608 (EH_RETURN_JMPR (i32 R31))>;
1609 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1610 (J2_jumpr IntRegs:$dst)>;
1611 def: Pat<(brind (i32 IntRegs:$dst)),
1612 (J2_jumpr IntRegs:$dst)>;
1614 //===----------------------------------------------------------------------===//
1616 //===----------------------------------------------------------------------===//
1618 //===----------------------------------------------------------------------===//
1620 //===----------------------------------------------------------------------===//
1622 // Load - Base with Immediate offset addressing mode
1623 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1624 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1626 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1627 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1632 bits<11> offsetBits;
1634 string ImmOpStr = !cast<string>(ImmOp);
1635 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1636 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1637 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1638 /* s11_0Ext */ offset{10-0})));
1639 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1640 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1641 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1642 /* s11_0Ext */ 11)));
1643 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
1645 let IClass = 0b1001;
1648 let Inst{26-25} = offsetBits{10-9};
1649 let Inst{24-21} = MajOp;
1650 let Inst{20-16} = src1;
1651 let Inst{13-5} = offsetBits{8-0};
1652 let Inst{4-0} = dst;
1655 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1656 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1657 Operand ImmOp, bit isNot, bit isPredNew>
1658 : LDInst<(outs RC:$dst),
1659 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1660 "if ("#!if(isNot, "!$src1", "$src1")
1661 #!if(isPredNew, ".new", "")
1662 #") $dst = "#mnemonic#"($src2 + #$offset)",
1663 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1669 string ImmOpStr = !cast<string>(ImmOp);
1671 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1672 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1673 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1674 /* u6_0Ext */ offset{5-0})));
1675 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1676 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1677 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1679 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1680 let isPredicatedNew = isPredNew;
1681 let isPredicatedFalse = isNot;
1683 let IClass = 0b0100;
1687 let Inst{26} = isNot;
1688 let Inst{25} = isPredNew;
1689 let Inst{24-21} = MajOp;
1690 let Inst{20-16} = src2;
1692 let Inst{12-11} = src1;
1693 let Inst{10-5} = offsetBits;
1694 let Inst{4-0} = dst;
1697 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1698 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1699 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1700 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1701 let isPredicable = 1 in
1702 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1705 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1706 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1709 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1710 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1714 let accessSize = ByteAccess in {
1715 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1716 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1719 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1720 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1721 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1724 let accessSize = WordAccess, opExtentAlign = 2 in
1725 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1727 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1728 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1730 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1731 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1732 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1735 let accessSize = WordAccess, opExtentAlign = 2 in {
1736 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
1737 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
1740 let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0,
1741 opExtendable = 3, isExtentSigned = 1 in
1742 class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp>
1743 : LDInst<(outs DoubleRegs:$dst),
1744 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1745 "$dst = "#str#"($src2 + #$offset)", [],
1746 "$src1 = $dst">, AddrModeRel {
1751 bits<11> offsetBits;
1753 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1},
1754 /* s11_0Ext */ offset{10-0});
1755 let IClass = 0b1001;
1758 let Inst{26-25} = offsetBits{10-9};
1759 let Inst{24-21} = MajOp;
1760 let Inst{20-16} = src2;
1761 let Inst{13-5} = offsetBits{8-0};
1762 let Inst{4-0} = dst;
1765 let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in
1766 def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>;
1768 let accessSize = ByteAccess, opExtentBits = 11 in
1769 def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
1771 // Patterns to select load-indexed (i.e. load from base+offset).
1772 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1774 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1775 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1776 (VT (MI IntRegs:$Rs, imm:$Off))>;
1777 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1780 let AddedComplexity = 20 in {
1781 defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
1782 defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
1783 defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
1784 defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
1785 defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
1786 defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
1788 defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1789 defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1790 defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1791 defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
1792 defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
1793 defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1794 defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1795 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1799 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1800 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1802 let AddedComplexity = 20 in
1803 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1804 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1806 //===----------------------------------------------------------------------===//
1807 // Post increment load
1808 //===----------------------------------------------------------------------===//
1809 //===----------------------------------------------------------------------===//
1810 // Template class for non-predicated post increment loads with immediate offset.
1811 //===----------------------------------------------------------------------===//
1812 let hasSideEffects = 0, addrMode = PostInc in
1813 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1815 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1816 (ins IntRegs:$src1, ImmOp:$offset),
1817 "$dst = "#mnemonic#"($src1++#$offset)" ,
1826 string ImmOpStr = !cast<string>(ImmOp);
1827 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1828 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1829 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1830 /* s4_0Imm */ offset{3-0})));
1831 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1833 let IClass = 0b1001;
1835 let Inst{27-25} = 0b101;
1836 let Inst{24-21} = MajOp;
1837 let Inst{20-16} = src1;
1838 let Inst{13-12} = 0b00;
1839 let Inst{8-5} = offsetBits;
1840 let Inst{4-0} = dst;
1843 //===----------------------------------------------------------------------===//
1844 // Template class for predicated post increment loads with immediate offset.
1845 //===----------------------------------------------------------------------===//
1846 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1847 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1848 bits<4> MajOp, bit isPredNot, bit isPredNew >
1849 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1850 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1851 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1852 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1862 let isPredicatedNew = isPredNew;
1863 let isPredicatedFalse = isPredNot;
1865 string ImmOpStr = !cast<string>(ImmOp);
1866 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1867 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1868 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1869 /* s4_0Imm */ offset{3-0})));
1870 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1872 let IClass = 0b1001;
1874 let Inst{27-25} = 0b101;
1875 let Inst{24-21} = MajOp;
1876 let Inst{20-16} = src2;
1878 let Inst{12} = isPredNew;
1879 let Inst{11} = isPredNot;
1880 let Inst{10-9} = src1;
1881 let Inst{8-5} = offsetBits;
1882 let Inst{4-0} = dst;
1885 //===----------------------------------------------------------------------===//
1886 // Multiclass for post increment loads with immediate offset.
1887 //===----------------------------------------------------------------------===//
1889 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1890 Operand ImmOp, bits<4> MajOp> {
1891 let BaseOpcode = "POST_"#BaseOp in {
1892 let isPredicable = 1 in
1893 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1896 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1897 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1900 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1901 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1905 // post increment byte loads with immediate offset
1906 let accessSize = ByteAccess in {
1907 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1908 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1911 // post increment halfword loads with immediate offset
1912 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1913 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1914 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1917 // post increment word loads with immediate offset
1918 let accessSize = WordAccess, opExtentAlign = 2 in
1919 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1921 // post increment doubleword loads with immediate offset
1922 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1923 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1925 // Rd=memb[u]h(Rx++#s4:1)
1926 // Rdd=memb[u]h(Rx++#s4:2)
1927 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1928 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1929 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1931 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in {
1932 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
1933 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
1936 //===----------------------------------------------------------------------===//
1937 // Template class for post increment fifo loads with immediate offset.
1938 //===----------------------------------------------------------------------===//
1939 let hasSideEffects = 0, addrMode = PostInc in
1940 class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp >
1941 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
1942 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1943 "$dst = "#mnemonic#"($src2++#$offset)" ,
1944 [], "$src2 = $dst2, $src1 = $dst" > ,
1951 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1},
1952 /* s4_0Imm */ offset{3-0});
1953 let IClass = 0b1001;
1955 let Inst{27-25} = 0b101;
1956 let Inst{24-21} = MajOp;
1957 let Inst{20-16} = src2;
1958 let Inst{13-12} = 0b00;
1959 let Inst{8-5} = offsetBits;
1960 let Inst{4-0} = dst;
1963 // Ryy=memh_fifo(Rx++#s4:1)
1964 // Ryy=memb_fifo(Rx++#s4:0)
1965 let accessSize = ByteAccess in
1966 def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>;
1968 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1969 def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>;
1971 //===----------------------------------------------------------------------===//
1972 // Template class for post increment loads with register offset.
1973 //===----------------------------------------------------------------------===//
1974 let hasSideEffects = 0, addrMode = PostInc in
1975 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1976 MemAccessSize AccessSz>
1977 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1978 (ins IntRegs:$src1, ModRegs:$src2),
1979 "$dst = "#mnemonic#"($src1++$src2)" ,
1980 [], "$src1 = $_dst_" > {
1985 let accessSize = AccessSz;
1986 let IClass = 0b1001;
1988 let Inst{27-25} = 0b110;
1989 let Inst{24-21} = MajOp;
1990 let Inst{20-16} = src1;
1991 let Inst{13} = src2;
1994 let Inst{4-0} = dst;
1997 let hasNewValue = 1 in {
1998 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1999 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
2000 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
2001 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
2002 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2004 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2007 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
2008 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
2011 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
2012 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
2013 def LDriw_pred : LDInst<(outs PredRegs:$dst),
2014 (ins IntRegs:$addr, s11_2Ext:$off),
2015 ".error \"should not emit\"", []>;
2017 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
2018 def L2_deallocframe : LDInst<(outs), (ins),
2021 let IClass = 0b1001;
2023 let Inst{27-16} = 0b000000011110;
2025 let Inst{4-0} = 0b11110;
2028 // Load / Post increment circular addressing mode.
2029 let Uses = [CS], hasSideEffects = 0 in
2030 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
2031 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
2032 (ins IntRegs:$Rz, ModRegs:$Mu),
2033 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
2039 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
2040 let IClass = 0b1001;
2042 let Inst{27-25} = 0b100;
2043 let Inst{24-21} = MajOp;
2044 let Inst{20-16} = Rz;
2049 let Inst{4-0} = dst;
2052 let accessSize = ByteAccess in {
2053 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2054 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
2057 let accessSize = HalfWordAccess in {
2058 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
2059 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2060 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
2061 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2064 let accessSize = WordAccess in {
2065 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2066 let hasNewValue = 0 in {
2067 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
2068 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
2072 let accessSize = DoubleWordAccess in
2073 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
2075 // Load / Post increment circular addressing mode.
2076 let Uses = [CS], hasSideEffects = 0 in
2077 class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz >
2078 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
2079 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
2080 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
2081 "$Rz = $_dst_, $dst = $_src_" > {
2086 let accessSize = AccessSz;
2087 let IClass = 0b1001;
2089 let Inst{27-25} = 0b100;
2090 let Inst{24-21} = MajOp;
2091 let Inst{20-16} = Rz;
2096 let Inst{4-0} = dst;
2099 def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>;
2100 def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>;
2102 //===----------------------------------------------------------------------===//
2103 // Circular loads with immediate offset.
2104 //===----------------------------------------------------------------------===//
2105 let Uses = [CS], mayLoad = 1, hasSideEffects = 0 in
2106 class T_load_pci <string mnemonic, RegisterClass RC,
2107 Operand ImmOp, bits<4> MajOp>
2108 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2109 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2110 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
2118 string ImmOpStr = !cast<string>(ImmOp);
2119 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
2120 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2121 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2122 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2123 /* s4_0Imm */ offset{3-0})));
2124 let IClass = 0b1001;
2125 let Inst{27-25} = 0b100;
2126 let Inst{24-21} = MajOp;
2127 let Inst{20-16} = Rz;
2131 let Inst{8-5} = offsetBits;
2132 let Inst{4-0} = dst;
2135 // Byte variants of circ load
2136 let accessSize = ByteAccess in {
2137 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2138 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2141 // Half word variants of circ load
2142 let accessSize = HalfWordAccess in {
2143 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2144 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2145 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2146 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2149 // Word variants of circ load
2150 let accessSize = WordAccess in
2151 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2153 let accessSize = WordAccess, hasNewValue = 0 in {
2154 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
2155 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
2158 let accessSize = DoubleWordAccess, hasNewValue = 0 in
2159 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2161 //===----------------------------------------------------------------------===//
2162 // Circular loads - Pseudo
2164 // Please note that the input operand order in the pseudo instructions
2165 // doesn't match with the real instructions. Pseudo instructions operand
2166 // order should mimics the ordering in the intrinsics. Also, 'src2' doesn't
2167 // appear in the AsmString because it's same as 'dst'.
2168 //===----------------------------------------------------------------------===//
2169 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
2170 class T_load_pci_pseudo <string opc, RegisterClass RC>
2171 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2172 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4Imm:$src4),
2173 ".error \"$dst = "#opc#"($src1++#$src4:circ($src3))\"",
2174 [], "$src1 = $_dst_">;
2176 def L2_loadrb_pci_pseudo : T_load_pci_pseudo <"memb", IntRegs>;
2177 def L2_loadrub_pci_pseudo : T_load_pci_pseudo <"memub", IntRegs>;
2178 def L2_loadrh_pci_pseudo : T_load_pci_pseudo <"memh", IntRegs>;
2179 def L2_loadruh_pci_pseudo : T_load_pci_pseudo <"memuh", IntRegs>;
2180 def L2_loadri_pci_pseudo : T_load_pci_pseudo <"memw", IntRegs>;
2181 def L2_loadrd_pci_pseudo : T_load_pci_pseudo <"memd", DoubleRegs>;
2184 // TODO: memb_fifo and memh_fifo must take destination register as input.
2185 // One-off circ loads - not enough in common to break into a class.
2186 let accessSize = ByteAccess in
2187 def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>;
2189 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2190 def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>;
2192 // L[24]_load[wd]_locked: Load word/double with lock.
2194 class T_load_locked <string mnemonic, RegisterClass RC>
2195 : LD0Inst <(outs RC:$dst),
2197 "$dst = "#mnemonic#"($src)"> {
2200 let IClass = 0b1001;
2201 let Inst{27-21} = 0b0010000;
2202 let Inst{20-16} = src;
2203 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2205 let Inst{4-0} = dst;
2207 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in
2208 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2209 let accessSize = DoubleWordAccess in
2210 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
2212 // S[24]_store[wd]_locked: Store word/double conditionally.
2213 let isSoloAX = 1, isPredicateLate = 1 in
2214 class T_store_locked <string mnemonic, RegisterClass RC>
2215 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2216 mnemonic#"($Rs, $Pd) = $Rt"> {
2221 let IClass = 0b1010;
2222 let Inst{27-23} = 0b00001;
2223 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
2225 let Inst{20-16} = Rs;
2226 let Inst{12-8} = Rt;
2230 let accessSize = WordAccess in
2231 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2233 let accessSize = DoubleWordAccess in
2234 def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
2236 //===----------------------------------------------------------------------===//
2237 // Bit-reversed loads with auto-increment register
2238 //===----------------------------------------------------------------------===//
2239 let hasSideEffects = 0 in
2240 class T_load_pbr<string mnemonic, RegisterClass RC,
2241 MemAccessSize addrSize, bits<4> majOp>
2243 <(outs RC:$dst, IntRegs:$_dst_),
2244 (ins IntRegs:$Rz, ModRegs:$Mu),
2245 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
2246 [] , "$Rz = $_dst_" > {
2248 let accessSize = addrSize;
2254 let IClass = 0b1001;
2256 let Inst{27-25} = 0b111;
2257 let Inst{24-21} = majOp;
2258 let Inst{20-16} = Rz;
2262 let Inst{4-0} = dst;
2265 let hasNewValue =1, opNewValue = 0 in {
2266 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2267 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2268 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2269 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2270 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2271 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2272 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2275 def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
2276 def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
2277 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2279 def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>;
2280 def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs,
2281 HalfWordAccess, 0b0010>;
2283 //===----------------------------------------------------------------------===//
2284 // Bit-reversed loads - Pseudo
2286 // Please note that 'src2' doesn't appear in the AsmString because
2287 // it's same as 'dst'.
2288 //===----------------------------------------------------------------------===//
2289 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
2290 class T_load_pbr_pseudo <string opc, RegisterClass RC>
2291 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2292 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2293 ".error \"$dst = "#opc#"($src1++$src3:brev)\"",
2294 [], "$src1 = $_dst_">;
2296 def L2_loadrb_pbr_pseudo : T_load_pbr_pseudo <"memb", IntRegs>;
2297 def L2_loadrub_pbr_pseudo : T_load_pbr_pseudo <"memub", IntRegs>;
2298 def L2_loadrh_pbr_pseudo : T_load_pbr_pseudo <"memh", IntRegs>;
2299 def L2_loadruh_pbr_pseudo : T_load_pbr_pseudo <"memuh", IntRegs>;
2300 def L2_loadri_pbr_pseudo : T_load_pbr_pseudo <"memw", IntRegs>;
2301 def L2_loadrd_pbr_pseudo : T_load_pbr_pseudo <"memd", DoubleRegs>;
2303 //===----------------------------------------------------------------------===//
2305 //===----------------------------------------------------------------------===//
2307 //===----------------------------------------------------------------------===//
2309 //===----------------------------------------------------------------------===//
2310 //===----------------------------------------------------------------------===//
2312 //===----------------------------------------------------------------------===//
2314 //===----------------------------------------------------------------------===//
2316 //===----------------------------------------------------------------------===//
2317 //===----------------------------------------------------------------------===//
2319 //===----------------------------------------------------------------------===//
2321 //===----------------------------------------------------------------------===//
2323 //===----------------------------------------------------------------------===//
2325 //===----------------------------------------------------------------------===//
2327 // MPYS / Multipy signed/unsigned halfwords
2328 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2329 //===----------------------------------------------------------------------===//
2331 let hasNewValue = 1, opNewValue = 0 in
2332 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
2333 bit hasShift, bit isUnsigned>
2334 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2335 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2336 #", $Rt."#!if(LHbits{0},"h)","l)")
2337 #!if(hasShift,":<<1","")
2338 #!if(isRnd,":rnd","")
2339 #!if(isSat,":sat",""),
2340 [], "", M_tc_3x_SLOT23 > {
2345 let IClass = 0b1110;
2347 let Inst{27-24} = 0b1100;
2348 let Inst{23} = hasShift;
2349 let Inst{22} = isUnsigned;
2350 let Inst{21} = isRnd;
2351 let Inst{7} = isSat;
2352 let Inst{6-5} = LHbits;
2354 let Inst{20-16} = Rs;
2355 let Inst{12-8} = Rt;
2358 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2359 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2360 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2361 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2362 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2363 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
2364 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
2365 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2366 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2368 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2369 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2370 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2371 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2372 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2373 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2374 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2375 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2376 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2378 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2379 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2380 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2381 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2382 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2383 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2384 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2385 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2386 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2388 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2389 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2390 let Defs = [USR_OVF] in {
2391 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2392 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2393 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2394 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2395 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2396 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2397 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2398 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2400 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2401 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2402 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2403 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2404 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2405 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2406 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2407 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2410 //===----------------------------------------------------------------------===//
2412 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2413 // result from the accumulator.
2414 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2415 //===----------------------------------------------------------------------===//
2417 let hasNewValue = 1, opNewValue = 0 in
2418 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2419 bit hasShift, bit isUnsigned >
2420 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2421 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2422 #"($Rs."#!if(LHbits{1},"h","l")
2423 #", $Rt."#!if(LHbits{0},"h)","l)")
2424 #!if(hasShift,":<<1","")
2425 #!if(isSat,":sat",""),
2426 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2431 let IClass = 0b1110;
2432 let Inst{27-24} = 0b1110;
2433 let Inst{23} = hasShift;
2434 let Inst{22} = isUnsigned;
2435 let Inst{21} = isNac;
2436 let Inst{7} = isSat;
2437 let Inst{6-5} = LHbits;
2439 let Inst{20-16} = Rs;
2440 let Inst{12-8} = Rt;
2443 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2444 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2445 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2446 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2447 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2448 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2449 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2450 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2451 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2453 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2454 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2455 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2456 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2457 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2458 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2459 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2460 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2461 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2463 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2464 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2465 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2466 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2467 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2468 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2469 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2470 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2471 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2473 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2474 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2475 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2476 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2477 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2478 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2479 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2480 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2481 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2483 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2484 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2485 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2486 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2487 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2488 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2489 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2490 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2491 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2493 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2494 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2495 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2496 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2497 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2498 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2499 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2500 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2501 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2503 //===----------------------------------------------------------------------===//
2505 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2506 // result from the 64-bit destination register.
2507 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2508 //===----------------------------------------------------------------------===//
2510 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2511 : MInst_acc<(outs DoubleRegs:$Rxx),
2512 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2513 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2514 #"($Rs."#!if(LHbits{1},"h","l")
2515 #", $Rt."#!if(LHbits{0},"h)","l)")
2516 #!if(hasShift,":<<1",""),
2517 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2522 let IClass = 0b1110;
2524 let Inst{27-24} = 0b0110;
2525 let Inst{23} = hasShift;
2526 let Inst{22} = isUnsigned;
2527 let Inst{21} = isNac;
2529 let Inst{6-5} = LHbits;
2530 let Inst{4-0} = Rxx;
2531 let Inst{20-16} = Rs;
2532 let Inst{12-8} = Rt;
2535 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2536 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2537 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2538 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2540 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2541 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2542 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2543 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2545 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2546 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2547 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2548 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2550 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2551 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2552 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2553 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2555 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2556 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2557 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2558 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2560 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2561 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2562 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2563 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2565 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2566 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2567 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2568 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2570 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2571 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2572 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2573 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2575 //===----------------------------------------------------------------------===//
2576 // Template Class -- Vector Multipy
2577 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2578 //===----------------------------------------------------------------------===//
2579 class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
2580 bit isRnd, bit isSat >
2581 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2582 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2583 #!if(isRnd,":rnd","")
2584 #!if(isSat,":sat",""),
2590 let IClass = 0b1110;
2592 let Inst{27-24} = 0b1000;
2593 let Inst{23-21} = MajOp;
2594 let Inst{7-5} = MinOp;
2595 let Inst{4-0} = Rdd;
2596 let Inst{20-16} = Rss;
2597 let Inst{12-8} = Rtt;
2600 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
2601 let Defs = [USR_OVF] in {
2602 def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
2603 def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
2605 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
2606 def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
2607 def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
2609 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
2610 def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>;
2611 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
2613 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2614 def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>;
2615 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
2617 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
2618 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
2619 def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>;
2620 def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>;
2621 def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>;
2623 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
2624 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
2625 def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>;
2626 def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>;
2627 def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>;
2629 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
2630 def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>;
2631 def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>;
2632 def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>;
2633 def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>;
2635 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
2636 def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>;
2637 def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>;
2638 def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>;
2639 def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>;
2642 let hasNewValue = 1, opNewValue = 0 in
2643 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2644 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2645 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2646 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2648 #"($src1, $src2"#op2Suffix#")"
2649 #!if(MajOp{2}, ":<<1", "")
2650 #!if(isRnd, ":rnd", "")
2651 #!if(isSat, ":sat", "")
2652 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2657 let IClass = 0b1110;
2659 let Inst{27-24} = RegTyBits;
2660 let Inst{23-21} = MajOp;
2661 let Inst{20-16} = src1;
2663 let Inst{12-8} = src2;
2664 let Inst{7-5} = MinOp;
2665 let Inst{4-0} = dst;
2668 class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
2669 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
2671 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2672 bit isSat = 0, bit isRnd = 0 >
2673 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2675 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2676 bit isSat = 0, bit isRnd = 0 >
2677 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2679 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2680 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2681 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2683 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
2684 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
2685 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
2687 let CextOpcode = "mpyi", InputType = "reg" in
2688 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2690 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2691 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2693 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2695 def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>;
2696 def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>;
2698 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2699 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2701 def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
2702 def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
2703 def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
2704 def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
2707 def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
2708 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2709 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2710 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2712 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2713 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2715 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2716 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2717 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2719 let hasNewValue = 1, opNewValue = 0 in
2720 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2721 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2722 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2723 pattern, "", M_tc_3x_SLOT23> {
2728 let IClass = 0b1110;
2730 let Inst{27-24} = 0b0000;
2731 let Inst{23} = isNeg;
2734 let Inst{20-16} = Rs;
2735 let Inst{12-5} = u8;
2738 let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
2739 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2740 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2742 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2743 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2746 // Assember mapped to M2_mpyi
2747 let isAsmParserOnly = 1 in
2748 def M2_mpyui : MInst<(outs IntRegs:$dst),
2749 (ins IntRegs:$src1, IntRegs:$src2),
2750 "$dst = mpyui($src1, $src2)">;
2753 // s9 is NOT the same as m9 - but it works.. so far.
2754 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2755 // depending on the value of m9. See Arch Spec.
2756 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2757 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
2758 isAsmParserOnly = 1 in
2759 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2760 "$dst = mpyi($src1, #$src2)",
2761 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2762 s9ExtPred:$src2))]>, ImmRegRel;
2764 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2765 InputType = "imm" in
2766 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2767 list<dag> pattern = []>
2768 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2769 "$dst "#mnemonic#"($src2, #$src3)",
2770 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2775 let IClass = 0b1110;
2777 let Inst{27-26} = 0b00;
2778 let Inst{25-23} = MajOp;
2779 let Inst{20-16} = src2;
2781 let Inst{12-5} = src3;
2782 let Inst{4-0} = dst;
2785 let InputType = "reg", hasNewValue = 1 in
2786 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2787 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2788 bit isSat = 0, bit isShift = 0>
2789 : MInst < (outs IntRegs:$dst),
2790 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2791 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2792 #!if(isShift, ":<<1", "")
2793 #!if(isSat, ":sat", ""),
2794 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2799 let IClass = 0b1110;
2801 let Inst{27-24} = 0b1111;
2802 let Inst{23-21} = MajOp;
2803 let Inst{20-16} = !if(isSwap, src3, src2);
2805 let Inst{12-8} = !if(isSwap, src2, src3);
2806 let Inst{7-5} = MinOp;
2807 let Inst{4-0} = dst;
2810 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
2811 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2812 [(set (i32 IntRegs:$dst),
2813 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2814 IntRegs:$src1))]>, ImmRegRel;
2816 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2817 [(set (i32 IntRegs:$dst),
2818 (add (mul IntRegs:$src2, IntRegs:$src3),
2819 IntRegs:$src1))]>, ImmRegRel;
2822 let CextOpcode = "ADD_acc" in {
2823 let isExtentSigned = 1 in
2824 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2825 [(set (i32 IntRegs:$dst),
2826 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2827 (i32 IntRegs:$src1)))]>, ImmRegRel;
2829 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2830 [(set (i32 IntRegs:$dst),
2831 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2832 (i32 IntRegs:$src1)))]>, ImmRegRel;
2835 let CextOpcode = "SUB_acc" in {
2836 let isExtentSigned = 1 in
2837 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2839 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2842 let Itinerary = M_tc_3x_SLOT23 in
2843 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2845 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2846 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2848 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2850 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2851 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2853 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2854 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2855 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2857 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2858 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2860 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2861 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2863 //===----------------------------------------------------------------------===//
2864 // Template Class -- XType Vector Instructions
2865 //===----------------------------------------------------------------------===//
2866 class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2867 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2868 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2874 let IClass = 0b1110;
2876 let Inst{27-24} = 0b1000;
2877 let Inst{23-21} = MajOp;
2878 let Inst{7-5} = MinOp;
2879 let Inst{4-0} = Rdd;
2880 let Inst{20-16} = Rss;
2881 let Inst{12-8} = Rtt;
2884 class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2885 : MInst <(outs DoubleRegs:$Rdd),
2886 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2887 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2888 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
2893 let IClass = 0b1110;
2895 let Inst{27-24} = 0b1010;
2896 let Inst{23-21} = MajOp;
2897 let Inst{7-5} = MinOp;
2898 let Inst{4-0} = Rdd;
2899 let Inst{20-16} = Rss;
2900 let Inst{12-8} = Rtt;
2903 class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
2904 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
2905 "$Rdd = "#opc#"($Rtt, $Rss)",
2906 [], "",M_tc_2_SLOT23 > {
2911 let IClass = 0b1110;
2913 let Inst{27-24} = 0b1000;
2914 let Inst{23-21} = MajOp;
2915 let Inst{7-5} = 0b000;
2916 let Inst{4-0} = Rdd;
2917 let Inst{20-16} = Rss;
2918 let Inst{12-8} = Rtt;
2921 // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
2922 def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
2923 def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
2925 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
2926 def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
2927 def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
2929 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
2930 def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
2932 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
2933 def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">;
2935 // Vector reduce complex multiply real or imaginary:
2936 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
2937 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
2938 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
2939 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
2940 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
2942 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
2943 def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
2944 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
2945 def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
2947 // Vector reduce halfwords:
2948 // Rdd[+]=vrmpyh(Rss,Rtt)
2949 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
2950 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
2952 //===----------------------------------------------------------------------===//
2953 // Template Class -- Vector Multipy with accumulation.
2954 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2955 //===----------------------------------------------------------------------===//
2956 let Defs = [USR_OVF] in
2957 class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
2958 bit hasShift, bit isRnd >
2959 : MInst <(outs DoubleRegs:$Rxx),
2960 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2961 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2962 #!if(isRnd,":rnd","")#":sat",
2963 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2968 let IClass = 0b1110;
2970 let Inst{27-24} = 0b1010;
2971 let Inst{23-21} = MajOp;
2972 let Inst{7-5} = MinOp;
2973 let Inst{4-0} = Rxx;
2974 let Inst{20-16} = Rss;
2975 let Inst{12-8} = Rtt;
2978 class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp,
2979 bit hasShift, bit isRnd >
2980 : MInst <(outs DoubleRegs:$Rxx),
2981 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2982 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2983 #!if(isRnd,":rnd",""),
2984 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2989 let IClass = 0b1110;
2991 let Inst{27-24} = 0b1010;
2992 let Inst{23-21} = MajOp;
2993 let Inst{7-5} = MinOp;
2994 let Inst{4-0} = Rxx;
2995 let Inst{20-16} = Rss;
2996 let Inst{12-8} = Rtt;
2999 // Vector multiply word by signed half with accumulation
3000 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
3001 def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>;
3002 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
3003 def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>;
3004 def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>;
3006 def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>;
3007 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
3008 def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>;
3009 def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>;
3011 // Vector multiply word by unsigned half with accumulation
3012 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
3013 def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>;
3014 def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>;
3015 def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>;
3016 def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>;
3018 def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>;
3019 def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>;
3020 def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>;
3021 def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>;
3023 // Vector multiply even halfwords with accumulation
3024 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
3025 def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>;
3026 def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>;
3027 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
3029 // Vector dual multiply with accumulation
3030 // Rxx+=vdmpy(Rss,Rtt)[:sat]
3031 def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>;
3032 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
3034 // Vector complex multiply real or imaginary with accumulation
3035 // Rxx+=vcmpy[ir](Rss,Rtt):sat
3036 def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
3037 def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
3039 //===----------------------------------------------------------------------===//
3040 // Template Class -- Multiply signed/unsigned halfwords with and without
3041 // saturation and rounding
3042 //===----------------------------------------------------------------------===//
3043 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
3044 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
3045 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
3046 #", $Rt."#!if(LHbits{0},"h)","l)")
3047 #!if(hasShift,":<<1","")
3048 #!if(isRnd,":rnd",""),
3054 let IClass = 0b1110;
3056 let Inst{27-24} = 0b0100;
3057 let Inst{23} = hasShift;
3058 let Inst{22} = isUnsigned;
3059 let Inst{21} = isRnd;
3060 let Inst{6-5} = LHbits;
3061 let Inst{4-0} = Rdd;
3062 let Inst{20-16} = Rs;
3063 let Inst{12-8} = Rt;
3066 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
3067 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
3068 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
3069 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
3071 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
3072 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
3073 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
3074 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
3076 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
3077 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
3078 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
3079 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
3081 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
3082 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
3083 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
3084 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
3086 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
3087 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
3088 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
3089 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
3090 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
3092 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
3093 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
3094 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
3095 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
3097 //===----------------------------------------------------------------------===//
3098 // Template Class for xtype mpy:
3101 // multiply 32X32 and use full result
3102 //===----------------------------------------------------------------------===//
3103 let hasSideEffects = 0 in
3104 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3105 bit isSat, bit hasShift, bit isConj>
3106 : MInst <(outs DoubleRegs:$Rdd),
3107 (ins IntRegs:$Rs, IntRegs:$Rt),
3108 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
3109 #!if(hasShift,":<<1","")
3110 #!if(isSat,":sat",""),
3116 let IClass = 0b1110;
3118 let Inst{27-24} = 0b0101;
3119 let Inst{23-21} = MajOp;
3120 let Inst{20-16} = Rs;
3121 let Inst{12-8} = Rt;
3122 let Inst{7-5} = MinOp;
3123 let Inst{4-0} = Rdd;
3126 //===----------------------------------------------------------------------===//
3127 // Template Class for xtype mpy with accumulation into 64-bit:
3130 // multiply 32X32 and use full result
3131 //===----------------------------------------------------------------------===//
3132 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
3133 bit isSat, bit hasShift, bit isConj>
3134 : MInst <(outs DoubleRegs:$Rxx),
3135 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
3136 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
3137 #!if(hasShift,":<<1","")
3138 #!if(isSat,":sat",""),
3140 [] , "$dst2 = $Rxx" > {
3145 let IClass = 0b1110;
3147 let Inst{27-24} = 0b0111;
3148 let Inst{23-21} = MajOp;
3149 let Inst{20-16} = Rs;
3150 let Inst{12-8} = Rt;
3151 let Inst{7-5} = MinOp;
3152 let Inst{4-0} = Rxx;
3155 // MPY - Multiply and use full result
3156 // Rdd = mpy[u](Rs,Rt)
3157 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
3158 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
3160 // Rxx[+-]= mpy[u](Rs,Rt)
3161 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
3162 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
3163 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
3164 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
3166 // Complex multiply real or imaginary
3167 // Rxx=cmpy[ir](Rs,Rt)
3168 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
3169 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
3171 // Rxx+=cmpy[ir](Rs,Rt)
3172 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
3173 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
3176 // Rdd=cmpy(Rs,Rt)[:<<]:sat
3177 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
3178 def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
3180 // Rdd=cmpy(Rs,Rt*)[:<<]:sat
3181 def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
3182 def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
3184 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
3185 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
3186 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
3187 def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
3188 def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
3190 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
3191 def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
3192 def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
3193 def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
3194 def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
3196 // Vector multiply halfwords
3197 // Rdd=vmpyh(Rs,Rt)[:<<]:sat
3198 //let Defs = [USR_OVF] in {
3199 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>;
3200 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
3203 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
3204 def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>;
3205 def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>;
3206 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
3208 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3209 (i64 (anyext (i32 IntRegs:$src2))))),
3210 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3212 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3213 (i64 (sext (i32 IntRegs:$src2))))),
3214 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3216 def: Pat<(i64 (mul (is_sext_i32:$src1),
3217 (is_sext_i32:$src2))),
3218 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3220 // Multiply and accumulate, use full result.
3221 // Rxx[+-]=mpy(Rs,Rt)
3223 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3224 (mul (i64 (sext (i32 IntRegs:$src2))),
3225 (i64 (sext (i32 IntRegs:$src3)))))),
3226 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3228 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3229 (mul (i64 (sext (i32 IntRegs:$src2))),
3230 (i64 (sext (i32 IntRegs:$src3)))))),
3231 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3233 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3234 (mul (i64 (anyext (i32 IntRegs:$src2))),
3235 (i64 (anyext (i32 IntRegs:$src3)))))),
3236 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3238 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3239 (mul (i64 (zext (i32 IntRegs:$src2))),
3240 (i64 (zext (i32 IntRegs:$src3)))))),
3241 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3243 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3244 (mul (i64 (anyext (i32 IntRegs:$src2))),
3245 (i64 (anyext (i32 IntRegs:$src3)))))),
3246 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3248 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3249 (mul (i64 (zext (i32 IntRegs:$src2))),
3250 (i64 (zext (i32 IntRegs:$src3)))))),
3251 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3253 //===----------------------------------------------------------------------===//
3255 //===----------------------------------------------------------------------===//
3257 //===----------------------------------------------------------------------===//
3259 //===----------------------------------------------------------------------===//
3260 //===----------------------------------------------------------------------===//
3262 //===----------------------------------------------------------------------===//
3264 //===----------------------------------------------------------------------===//
3266 //===----------------------------------------------------------------------===//
3267 //===----------------------------------------------------------------------===//
3269 //===----------------------------------------------------------------------===//
3271 //===----------------------------------------------------------------------===//
3273 //===----------------------------------------------------------------------===//
3274 //===----------------------------------------------------------------------===//
3276 //===----------------------------------------------------------------------===//
3278 //===----------------------------------------------------------------------===//
3280 //===----------------------------------------------------------------------===//
3282 // Store doubleword.
3283 //===----------------------------------------------------------------------===//
3284 // Template class for non-predicated post increment stores with immediate offset
3285 //===----------------------------------------------------------------------===//
3286 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
3287 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3288 bits<4> MajOp, bit isHalf >
3289 : STInst <(outs IntRegs:$_dst_),
3290 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3291 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
3292 [], "$src1 = $_dst_" >,
3299 string ImmOpStr = !cast<string>(ImmOp);
3300 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3301 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3302 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3303 /* s4_0Imm */ offset{3-0})));
3304 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3306 let IClass = 0b1010;
3308 let Inst{27-25} = 0b101;
3309 let Inst{24-21} = MajOp;
3310 let Inst{20-16} = src1;
3312 let Inst{12-8} = src2;
3314 let Inst{6-3} = offsetBits;
3318 //===----------------------------------------------------------------------===//
3319 // Template class for predicated post increment stores with immediate offset
3320 //===----------------------------------------------------------------------===//
3321 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
3322 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3323 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
3324 : STInst <(outs IntRegs:$_dst_),
3325 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3326 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3327 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
3328 [], "$src2 = $_dst_" >,
3336 string ImmOpStr = !cast<string>(ImmOp);
3337 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3338 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3339 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3340 /* s4_0Imm */ offset{3-0})));
3342 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3343 let isPredicatedNew = isPredNew;
3344 let isPredicatedFalse = isPredNot;
3346 let IClass = 0b1010;
3348 let Inst{27-25} = 0b101;
3349 let Inst{24-21} = MajOp;
3350 let Inst{20-16} = src2;
3352 let Inst{12-8} = src3;
3353 let Inst{7} = isPredNew;
3354 let Inst{6-3} = offsetBits;
3355 let Inst{2} = isPredNot;
3356 let Inst{1-0} = src1;
3359 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
3360 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
3362 let BaseOpcode = "POST_"#BaseOp in {
3363 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
3366 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
3367 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
3370 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3372 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3377 let accessSize = ByteAccess in
3378 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3380 let accessSize = HalfWordAccess in
3381 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3383 let accessSize = WordAccess in
3384 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3386 let accessSize = DoubleWordAccess in
3387 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3389 let accessSize = HalfWordAccess, isNVStorable = 0 in
3390 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3392 class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset,
3394 : Pat<(Store Value:$src1, I32:$src2, Offset:$offset),
3395 (MI I32:$src2, imm:$offset, Value:$src1)>;
3397 def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>;
3398 def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>;
3399 def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>;
3400 def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>;
3402 //===----------------------------------------------------------------------===//
3403 // Template class for post increment stores with register offset.
3404 //===----------------------------------------------------------------------===//
3405 let isNVStorable = 1 in
3406 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
3407 MemAccessSize AccessSz, bit isHalf = 0>
3408 : STInst <(outs IntRegs:$_dst_),
3409 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3410 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
3411 [], "$src1 = $_dst_" > {
3415 let accessSize = AccessSz;
3417 let IClass = 0b1010;
3419 let Inst{27-24} = 0b1101;
3420 let Inst{23-21} = MajOp;
3421 let Inst{20-16} = src1;
3422 let Inst{13} = src2;
3423 let Inst{12-8} = src3;
3427 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3428 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3429 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3430 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
3432 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3434 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
3435 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3436 bits<3>MajOp, bit isH = 0>
3438 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3439 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
3440 AddrModeRel, ImmRegRel {
3442 bits<14> src2; // Actual address offset
3444 bits<11> offsetBits; // Represents offset encoding
3446 string ImmOpStr = !cast<string>(ImmOp);
3448 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
3449 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
3450 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
3451 /* s11_0Ext */ 11)));
3452 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
3453 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
3454 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
3455 /* s11_0Ext */ src2{10-0})));
3456 let IClass = 0b1010;
3459 let Inst{26-25} = offsetBits{10-9};
3461 let Inst{23-21} = MajOp;
3462 let Inst{20-16} = src1;
3463 let Inst{13} = offsetBits{8};
3464 let Inst{12-8} = src3;
3465 let Inst{7-0} = offsetBits{7-0};
3468 let opExtendable = 2, isPredicated = 1 in
3469 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3470 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
3472 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3473 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3474 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
3475 [],"",V2LDST_tc_st_SLOT01 >,
3476 AddrModeRel, ImmRegRel {
3479 bits<9> src3; // Actual address offset
3481 bits<6> offsetBits; // Represents offset encoding
3483 let isPredicatedNew = isPredNew;
3484 let isPredicatedFalse = PredNot;
3486 string ImmOpStr = !cast<string>(ImmOp);
3487 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
3488 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
3489 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
3491 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
3492 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
3493 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
3494 /* u6_0Ext */ src3{5-0})));
3495 let IClass = 0b0100;
3498 let Inst{26} = PredNot;
3499 let Inst{25} = isPredNew;
3501 let Inst{23-21} = MajOp;
3502 let Inst{20-16} = src2;
3503 let Inst{13} = offsetBits{5};
3504 let Inst{12-8} = src4;
3505 let Inst{7-3} = offsetBits{4-0};
3506 let Inst{1-0} = src1;
3509 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
3510 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
3511 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
3512 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
3513 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
3516 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
3517 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
3520 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3522 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3527 let addrMode = BaseImmOffset, InputType = "imm" in {
3528 let accessSize = ByteAccess in
3529 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3531 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3532 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3534 let accessSize = WordAccess, opExtentAlign = 2 in
3535 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3537 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
3538 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
3541 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3542 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3546 // Patterns for generating stores, where the address takes different forms:
3549 // - simple (base address without offset).
3550 // These would usually be used together (via Storex_pat defined below), but
3551 // in some cases one may want to apply different properties (such as
3552 // AddedComplexity) to the individual patterns.
3553 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3554 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
3555 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3557 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3558 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3559 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3560 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3561 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3563 // Patterns for generating stores, where the address takes different forms,
3564 // and where the value being stored is transformed through the value modifier
3565 // ValueMod. The address forms are same as above.
3566 class Storexm_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
3568 : Pat<(Store Value:$Rs, AddrFI:$fi),
3569 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
3570 class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3571 PatFrag ValueMod, InstHexagon MI>
3572 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3573 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
3574 class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
3576 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3577 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
3579 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3581 def: Storex_fi_pat <Store, Value, MI>;
3582 def: Storex_add_pat <Store, Value, ImmPred, MI>;
3585 multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3586 PatFrag ValueMod, InstHexagon MI> {
3587 def: Storexm_fi_pat <Store, Value, ValueMod, MI>;
3588 def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>;
3591 // Regular stores in the DAG have two operands: value and address.
3592 // Atomic stores also have two, but they are reversed: address, value.
3593 // To use atomic stores with the patterns, they need to have their operands
3594 // swapped. This relies on the knowledge that the F.Fragment uses names
3596 class SwapSt<PatFrag F>
3597 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
3599 let AddedComplexity = 20 in {
3600 defm: Storex_pat<truncstorei8, I32, s11_0ExtPred, S2_storerb_io>;
3601 defm: Storex_pat<truncstorei16, I32, s11_1ExtPred, S2_storerh_io>;
3602 defm: Storex_pat<store, I32, s11_2ExtPred, S2_storeri_io>;
3603 defm: Storex_pat<store, I64, s11_3ExtPred, S2_storerd_io>;
3605 defm: Storex_pat<SwapSt<atomic_store_8>, I32, s11_0ExtPred, S2_storerb_io>;
3606 defm: Storex_pat<SwapSt<atomic_store_16>, I32, s11_1ExtPred, S2_storerh_io>;
3607 defm: Storex_pat<SwapSt<atomic_store_32>, I32, s11_2ExtPred, S2_storeri_io>;
3608 defm: Storex_pat<SwapSt<atomic_store_64>, I64, s11_3ExtPred, S2_storerd_io>;
3611 // Simple patterns should be tried with the least priority.
3612 def: Storex_simple_pat<truncstorei8, I32, S2_storerb_io>;
3613 def: Storex_simple_pat<truncstorei16, I32, S2_storerh_io>;
3614 def: Storex_simple_pat<store, I32, S2_storeri_io>;
3615 def: Storex_simple_pat<store, I64, S2_storerd_io>;
3617 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
3618 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
3619 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
3620 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
3622 let AddedComplexity = 20 in {
3623 defm: Storexm_pat<truncstorei8, I64, s11_0ExtPred, LoReg, S2_storerb_io>;
3624 defm: Storexm_pat<truncstorei16, I64, s11_1ExtPred, LoReg, S2_storerh_io>;
3625 defm: Storexm_pat<truncstorei32, I64, s11_2ExtPred, LoReg, S2_storeri_io>;
3628 def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>;
3629 def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>;
3630 def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
3633 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
3634 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3635 def STriw_pred : STInst<(outs),
3636 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3637 ".error \"should not emit\"", []>;
3639 // S2_allocframe: Allocate stack frame.
3640 let Defs = [R29, R30], Uses = [R29, R31, R30],
3641 hasSideEffects = 0, accessSize = DoubleWordAccess in
3642 def S2_allocframe: ST0Inst <
3643 (outs), (ins u11_3Imm:$u11_3),
3644 "allocframe(#$u11_3)" > {
3647 let IClass = 0b1010;
3648 let Inst{27-16} = 0b000010011101;
3649 let Inst{13-11} = 0b000;
3650 let Inst{10-0} = u11_3{13-3};
3653 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3654 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3655 let Uses = [CS], isNVStorable = 1 in
3656 class T_store_pci <string mnemonic, RegisterClass RC,
3657 Operand Imm, bits<4>MajOp,
3658 MemAccessSize AlignSize, string RegSrc = "Rt">
3659 : STInst <(outs IntRegs:$_dst_),
3660 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3661 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3668 let accessSize = AlignSize;
3670 let IClass = 0b1010;
3671 let Inst{27-25} = 0b100;
3672 let Inst{24-21} = MajOp;
3673 let Inst{20-16} = Rz;
3675 let Inst{12-8} = Rt;
3678 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3679 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3680 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3681 /* ByteAccess */ offset{3-0})));
3685 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3687 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3689 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3690 HalfWordAccess, "Rt.h">;
3691 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3693 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3696 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3697 class T_storenew_pci <string mnemonic, Operand Imm,
3698 bits<2>MajOp, MemAccessSize AlignSize>
3699 : NVInst < (outs IntRegs:$_dst_),
3700 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3701 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3709 let accessSize = AlignSize;
3711 let IClass = 0b1010;
3712 let Inst{27-21} = 0b1001101;
3713 let Inst{20-16} = Rz;
3715 let Inst{12-11} = MajOp;
3716 let Inst{10-8} = Nt;
3719 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3720 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3721 /* ByteAccess */ offset{3-0}));
3725 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3726 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3727 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3729 //===----------------------------------------------------------------------===//
3730 // Circular stores - Pseudo
3732 // Please note that the input operand order in the pseudo instructions
3733 // doesn't match with the real instructions. Pseudo instructions operand
3734 // order should mimics the ordering in the intrinsics.
3735 //===----------------------------------------------------------------------===//
3736 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
3737 class T_store_pci_pseudo <string opc, RegisterClass RC>
3738 : STInstPI<(outs IntRegs:$_dst_),
3739 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3, s4Imm:$src4),
3740 ".error \""#opc#"($src1++#$src4:circ($src3)) = $src2\"",
3741 [], "$_dst_ = $src1">;
3743 def S2_storerb_pci_pseudo : T_store_pci_pseudo <"memb", IntRegs>;
3744 def S2_storerh_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3745 def S2_storerf_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3746 def S2_storeri_pci_pseudo : T_store_pci_pseudo <"memw", IntRegs>;
3747 def S2_storerd_pci_pseudo : T_store_pci_pseudo <"memd", DoubleRegs>;
3749 //===----------------------------------------------------------------------===//
3750 // Circular stores with auto-increment register
3751 //===----------------------------------------------------------------------===//
3752 let Uses = [CS], isNVStorable = 1 in
3753 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3754 MemAccessSize AlignSize, string RegSrc = "Rt">
3755 : STInst <(outs IntRegs:$_dst_),
3756 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3757 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3764 let accessSize = AlignSize;
3766 let IClass = 0b1010;
3767 let Inst{27-25} = 0b100;
3768 let Inst{24-21} = MajOp;
3769 let Inst{20-16} = Rz;
3771 let Inst{12-8} = Rt;
3776 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3777 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3778 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3779 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3780 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3781 HalfWordAccess, "Rt.h">;
3783 //===----------------------------------------------------------------------===//
3784 // Circular .new stores with auto-increment register
3785 //===----------------------------------------------------------------------===//
3786 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3787 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3788 MemAccessSize AlignSize>
3789 : NVInst <(outs IntRegs:$_dst_),
3790 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3791 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3798 let accessSize = AlignSize;
3800 let IClass = 0b1010;
3801 let Inst{27-21} = 0b1001101;
3802 let Inst{20-16} = Rz;
3804 let Inst{12-11} = MajOp;
3805 let Inst{10-8} = Nt;
3810 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3811 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3812 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3814 //===----------------------------------------------------------------------===//
3815 // Bit-reversed stores with auto-increment register
3816 //===----------------------------------------------------------------------===//
3817 let hasSideEffects = 0 in
3818 class T_store_pbr<string mnemonic, RegisterClass RC,
3819 MemAccessSize addrSize, bits<3> majOp,
3822 <(outs IntRegs:$_dst_),
3823 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3824 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3825 [], "$Rz = $_dst_" > {
3827 let accessSize = addrSize;
3833 let IClass = 0b1010;
3835 let Inst{27-24} = 0b1111;
3836 let Inst{23-21} = majOp;
3838 let Inst{20-16} = Rz;
3840 let Inst{12-8} = src;
3843 let isNVStorable = 1 in {
3844 let BaseOpcode = "S2_storerb_pbr" in
3845 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3846 0b000>, NewValueRel;
3847 let BaseOpcode = "S2_storerh_pbr" in
3848 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3849 0b010>, NewValueRel;
3850 let BaseOpcode = "S2_storeri_pbr" in
3851 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3852 0b100>, NewValueRel;
3855 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3856 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3858 //===----------------------------------------------------------------------===//
3859 // Bit-reversed .new stores with auto-increment register
3860 //===----------------------------------------------------------------------===//
3861 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3862 hasSideEffects = 0 in
3863 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3864 : NVInst <(outs IntRegs:$_dst_),
3865 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3866 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3867 "$Rz = $_dst_">, NewValueRel {
3868 let accessSize = addrSize;
3873 let IClass = 0b1010;
3875 let Inst{27-21} = 0b1111101;
3876 let Inst{12-11} = majOp;
3878 let Inst{20-16} = Rz;
3880 let Inst{10-8} = Nt;
3883 let BaseOpcode = "S2_storerb_pbr" in
3884 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3886 let BaseOpcode = "S2_storerh_pbr" in
3887 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3889 let BaseOpcode = "S2_storeri_pbr" in
3890 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3892 //===----------------------------------------------------------------------===//
3893 // Bit-reversed stores - Pseudo
3895 // Please note that the input operand order in the pseudo instructions
3896 // doesn't match with the real instructions. Pseudo instructions operand
3897 // order should mimics the ordering in the intrinsics.
3898 //===----------------------------------------------------------------------===//
3899 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
3900 class T_store_pbr_pseudo <string opc, RegisterClass RC>
3901 : STInstPI<(outs IntRegs:$_dst_),
3902 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3),
3903 ".error \""#opc#"($src1++$src3:brev) = $src2\"",
3904 [], "$_dst_ = $src1">;
3906 def S2_storerb_pbr_pseudo : T_store_pbr_pseudo <"memb", IntRegs>;
3907 def S2_storerh_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3908 def S2_storeri_pbr_pseudo : T_store_pbr_pseudo <"memw", IntRegs>;
3909 def S2_storerf_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3910 def S2_storerd_pbr_pseudo : T_store_pbr_pseudo <"memd", DoubleRegs>;
3912 //===----------------------------------------------------------------------===//
3914 //===----------------------------------------------------------------------===//
3916 //===----------------------------------------------------------------------===//
3917 // Template class for S_2op instructions.
3918 //===----------------------------------------------------------------------===//
3919 let hasSideEffects = 0 in
3920 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3921 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3922 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3923 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3924 [], "", S_2op_tc_1_SLOT23 > {
3928 let IClass = 0b1000;
3930 let Inst{27-24} = RegTyBits;
3931 let Inst{23-22} = MajOp;
3933 let Inst{20-16} = src;
3934 let Inst{7-5} = MinOp;
3935 let Inst{4-0} = dst;
3938 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3939 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3941 let hasNewValue = 1 in
3942 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3943 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3945 let hasNewValue = 1 in
3946 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3947 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3949 // Vector sign/zero extend
3950 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3951 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3952 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3953 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3954 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3957 // Vector splat bytes/halfwords
3958 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3959 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
3960 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
3963 // Sign extend word to doubleword
3964 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3966 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3968 // Vector saturate and pack
3969 let Defs = [USR_OVF] in {
3970 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
3971 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
3972 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3973 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3974 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3975 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
3979 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
3980 def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
3982 // Swizzle the bytes of a word
3983 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3986 let Defs = [USR_OVF] in {
3987 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
3988 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
3989 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
3990 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
3991 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
3992 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
3995 let Itinerary = S_2op_tc_2_SLOT23 in {
3996 // Vector round and pack
3997 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
3999 let Defs = [USR_OVF] in
4000 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
4003 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
4005 // Absolute value word
4006 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
4008 let Defs = [USR_OVF] in
4009 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
4011 // Negate with saturation
4012 let Defs = [USR_OVF] in
4013 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
4016 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
4017 (i32 (sub 0, (i32 IntRegs:$src))),
4018 (i32 IntRegs:$src))),
4019 (A2_abs IntRegs:$src)>;
4021 let AddedComplexity = 50 in
4022 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
4023 (i32 IntRegs:$src)),
4024 (sra (i32 IntRegs:$src), (i32 31)))),
4025 (A2_abs IntRegs:$src)>;
4027 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
4028 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
4029 bit isSat, bit isRnd, list<dag> pattern = []>
4030 : SInst <(outs RCOut:$dst),
4031 (ins RCIn:$src, u5Imm:$u5),
4032 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
4033 #!if(isRnd, ":rnd", ""),
4034 pattern, "", S_2op_tc_2_SLOT23> {
4039 let IClass = 0b1000;
4041 let Inst{27-24} = RegTyBits;
4042 let Inst{23-21} = MajOp;
4043 let Inst{20-16} = src;
4045 let Inst{12-8} = u5;
4046 let Inst{7-5} = MinOp;
4047 let Inst{4-0} = dst;
4050 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
4051 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
4053 let hasNewValue = 1 in
4054 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
4055 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
4057 let hasNewValue = 1 in
4058 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
4059 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
4060 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
4061 isSat, isRnd, pattern>;
4063 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
4064 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
4065 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
4066 (u5ImmPred:$u5)))]>;
4068 // Vector arithmetic shift right by immediate with truncate and pack
4069 def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>;
4071 // Arithmetic/logical shift right/left by immediate
4072 let Itinerary = S_2op_tc_1_SLOT23 in {
4073 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
4074 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
4075 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
4078 // Shift left by immediate with saturation
4079 let Defs = [USR_OVF] in
4080 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
4082 // Shift right with round
4083 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
4085 let isAsmParserOnly = 1 in
4086 def S2_asr_i_r_rnd_goodsyntax
4087 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
4088 "$dst = asrrnd($src, #$u5)",
4089 [], "", S_2op_tc_1_SLOT23>;
4091 let isAsmParserOnly = 1 in
4092 def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
4093 "$dst = not($src)">;
4095 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
4098 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
4100 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
4101 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
4102 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
4105 let IClass = 0b1000;
4106 let Inst{27-24} = 0;
4107 let Inst{23-22} = MajOp;
4108 let Inst{20-16} = Rss;
4109 let Inst{7-5} = minOp;
4110 let Inst{4-0} = Rdd;
4113 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
4114 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
4115 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
4117 // Innterleave/deinterleave
4118 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
4119 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
4121 // Vector Complex conjugate
4122 def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
4124 // Vector saturate without pack
4125 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
4126 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
4127 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
4128 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
4130 // Vector absolute value halfwords with and without saturation
4131 // Rdd64=vabsh(Rss64)[:sat]
4132 def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
4133 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
4135 // Vector absolute value words with and without saturation
4136 def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
4137 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
4139 def : Pat<(not (i64 DoubleRegs:$src1)),
4140 (A2_notp DoubleRegs:$src1)>;
4142 //===----------------------------------------------------------------------===//
4144 //===----------------------------------------------------------------------===//
4147 let hasSideEffects = 0, hasNewValue = 1 in
4148 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
4150 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
4153 let IClass = 0b1000;
4155 let Inst{26} = Is32;
4156 let Inst{25-24} = 0b00;
4157 let Inst{23-21} = MajOp;
4158 let Inst{20-16} = Rs;
4159 let Inst{7-5} = MinOp;
4163 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
4164 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
4165 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4167 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
4168 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
4169 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4171 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
4172 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
4173 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
4174 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
4175 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
4176 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
4177 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
4178 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
4179 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
4181 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
4182 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
4183 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
4184 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
4185 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
4186 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
4188 // Bit set/clear/toggle
4190 let hasSideEffects = 0, hasNewValue = 1 in
4191 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
4192 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4193 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
4197 let IClass = 0b1000;
4198 let Inst{27-21} = 0b1100110;
4199 let Inst{20-16} = Rs;
4201 let Inst{12-8} = u5;
4202 let Inst{7-5} = MinOp;
4206 let hasSideEffects = 0, hasNewValue = 1 in
4207 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
4208 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4209 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
4213 let IClass = 0b1100;
4214 let Inst{27-22} = 0b011010;
4215 let Inst{20-16} = Rs;
4216 let Inst{12-8} = Rt;
4217 let Inst{7-6} = MinOp;
4221 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
4222 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
4223 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
4224 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
4225 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
4226 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
4228 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4229 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4230 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4231 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4232 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4233 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4234 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
4235 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4236 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4237 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4238 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4239 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4243 let hasSideEffects = 0 in
4244 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
4245 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4246 "$Pd = "#MnOp#"($Rs, #$u5)",
4247 [], "", S_2op_tc_2early_SLOT23> {
4251 let IClass = 0b1000;
4252 let Inst{27-24} = 0b0101;
4253 let Inst{23-21} = MajOp;
4254 let Inst{20-16} = Rs;
4256 let Inst{12-8} = u5;
4260 let hasSideEffects = 0 in
4261 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
4262 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4263 "$Pd = "#MnOp#"($Rs, $Rt)",
4264 [], "", S_3op_tc_2early_SLOT23> {
4268 let IClass = 0b1100;
4269 let Inst{27-22} = 0b011100;
4270 let Inst{21} = IsNeg;
4271 let Inst{20-16} = Rs;
4272 let Inst{12-8} = Rt;
4276 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
4277 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
4279 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
4280 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4281 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4282 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4283 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4284 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4285 (S2_tstbit_i IntRegs:$Rs, 0)>;
4286 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
4287 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4290 let hasSideEffects = 0 in
4291 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
4292 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4293 "$Pd = "#MnOp#"($Rs, #$u6)",
4294 [], "", S_2op_tc_2early_SLOT23> {
4298 let IClass = 0b1000;
4299 let Inst{27-24} = 0b0101;
4300 let Inst{23-22} = MajOp;
4301 let Inst{21} = IsNeg;
4302 let Inst{20-16} = Rs;
4303 let Inst{13-8} = u6;
4307 let hasSideEffects = 0 in
4308 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
4309 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4310 "$Pd = "#MnOp#"($Rs, $Rt)",
4311 [], "", S_3op_tc_2early_SLOT23> {
4315 let IClass = 0b1100;
4316 let Inst{27-24} = 0b0111;
4317 let Inst{23-22} = MajOp;
4318 let Inst{21} = IsNeg;
4319 let Inst{20-16} = Rs;
4320 let Inst{12-8} = Rt;
4324 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
4325 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
4326 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
4328 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
4329 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4330 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4331 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4332 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4335 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
4336 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4337 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4339 //===----------------------------------------------------------------------===//
4341 //===----------------------------------------------------------------------===//
4343 //===----------------------------------------------------------------------===//
4345 //===----------------------------------------------------------------------===//
4346 //===----------------------------------------------------------------------===//
4348 //===----------------------------------------------------------------------===//
4350 //===----------------------------------------------------------------------===//
4352 //===----------------------------------------------------------------------===//
4354 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))),
4356 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))),
4358 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))),
4359 (zextloadi8 (i32 IntRegs:$b))),
4360 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
4362 //===----------------------------------------------------------------------===//
4364 //===----------------------------------------------------------------------===//
4366 //===----------------------------------------------------------------------===//
4368 //===----------------------------------------------------------------------===//
4370 // Predicate transfer.
4371 let hasSideEffects = 0, hasNewValue = 1 in
4372 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4373 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
4377 let IClass = 0b1000;
4378 let Inst{27-24} = 0b1001;
4380 let Inst{17-16} = Ps;
4384 // Transfer general register to predicate.
4385 let hasSideEffects = 0 in
4386 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4387 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
4391 let IClass = 0b1000;
4392 let Inst{27-21} = 0b0101010;
4393 let Inst{20-16} = Rs;
4397 let hasSideEffects = 0, isCodeGenOnly = 1 in
4398 def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src),
4402 // Patterns for loads of i1:
4403 def: Pat<(i1 (load AddrFI:$fi)),
4404 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
4405 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s11_0ExtPred:$Off))),
4406 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
4407 def: Pat<(i1 (load (i32 IntRegs:$Rs))),
4408 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
4410 def I1toI32: OutPatFrag<(ops node:$Rs),
4411 (C2_muxii (i1 $Rs), 1, 0)>;
4413 def I32toI1: OutPatFrag<(ops node:$Rs),
4414 (i1 (C2_tfrrp (i32 $Rs)))>;
4416 defm: Storexm_pat<store, I1, s11_0ExtPred, I1toI32, S2_storerb_io>;
4417 def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
4419 //===----------------------------------------------------------------------===//
4421 //===----------------------------------------------------------------------===//
4423 //===----------------------------------------------------------------------===//
4425 //===----------------------------------------------------------------------===//
4426 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
4427 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
4428 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
4429 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
4433 let IClass = 0b1000;
4434 let Inst{27-24} = 0;
4435 let Inst{23-21} = MajOp;
4436 let Inst{20-16} = src1;
4437 let Inst{7-5} = MinOp;
4438 let Inst{4-0} = dst;
4441 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
4442 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
4443 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
4444 u6ImmPred:$src2))]> {
4446 let Inst{13-8} = src2;
4449 // Shift by immediate.
4450 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
4451 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
4452 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
4454 // Shift left by small amount and add.
4455 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in
4456 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4457 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4458 "$Rd = addasl($Rt, $Rs, #$u3)" ,
4459 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4460 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4461 "", S_3op_tc_2_SLOT23> {
4467 let IClass = 0b1100;
4469 let Inst{27-21} = 0b0100000;
4470 let Inst{20-16} = Rs;
4472 let Inst{12-8} = Rt;
4477 //===----------------------------------------------------------------------===//
4479 //===----------------------------------------------------------------------===//
4481 //===----------------------------------------------------------------------===//
4483 //===----------------------------------------------------------------------===//
4484 //===----------------------------------------------------------------------===//
4486 //===----------------------------------------------------------------------===//
4488 //===----------------------------------------------------------------------===//
4490 //===----------------------------------------------------------------------===//
4491 //===----------------------------------------------------------------------===//
4493 //===----------------------------------------------------------------------===//
4495 //===----------------------------------------------------------------------===//
4497 //===----------------------------------------------------------------------===//
4499 //===----------------------------------------------------------------------===//
4501 //===----------------------------------------------------------------------===//
4502 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
4504 let hasSideEffects = 1, isSoloAX = 1 in
4505 def Y2_barrier : SYSInst<(outs), (ins),
4507 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
4508 let Inst{31-28} = 0b1010;
4509 let Inst{27-21} = 0b1000000;
4512 //===----------------------------------------------------------------------===//
4514 //===----------------------------------------------------------------------===//
4516 // Generate frameindex addresses.
4517 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
4518 isPseudo = 1, isCodeGenOnly = 1 in
4519 def TFR_FI: ALU32_ri<(outs IntRegs:$Rd), (ins FrameIndex:$fi),
4521 [(set (i32 IntRegs:$Rd), ADDRri:$fi)]>;
4523 //===----------------------------------------------------------------------===//
4525 //===----------------------------------------------------------------------===//
4527 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4528 opExtendable = 0, hasSideEffects = 0 in
4529 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4530 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
4531 #mnemonic#"($offset, #$src2)",
4532 [], "" , CR_tc_3x_SLOT3> {
4536 let IClass = 0b0110;
4538 let Inst{27-22} = 0b100100;
4539 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4540 let Inst{20-16} = src2{9-5};
4541 let Inst{12-8} = offset{8-4};
4542 let Inst{7-5} = src2{4-2};
4543 let Inst{4-3} = offset{3-2};
4544 let Inst{1-0} = src2{1-0};
4547 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4548 opExtendable = 0, hasSideEffects = 0 in
4549 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4550 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4551 #mnemonic#"($offset, $src2)",
4552 [], "" ,CR_tc_3x_SLOT3> {
4556 let IClass = 0b0110;
4558 let Inst{27-22} = 0b000000;
4559 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4560 let Inst{20-16} = src2;
4561 let Inst{12-8} = offset{8-4};
4562 let Inst{4-3} = offset{3-2};
4565 multiclass LOOP_ri<string mnemonic> {
4566 def i : LOOP_iBase<mnemonic, brtarget>;
4567 def r : LOOP_rBase<mnemonic, brtarget>;
4569 let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
4570 def iext: LOOP_iBase<mnemonic, brtargetExt, 1>;
4571 def rext: LOOP_rBase<mnemonic, brtargetExt, 1>;
4576 let Defs = [SA0, LC0, USR] in
4577 defm J2_loop0 : LOOP_ri<"loop0">;
4579 // Interestingly only loop0's appear to set usr.lpcfg
4580 let Defs = [SA1, LC1] in
4581 defm J2_loop1 : LOOP_ri<"loop1">;
4583 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4584 Defs = [PC, LC0], Uses = [SA0, LC0] in {
4585 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4590 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4591 Defs = [PC, LC1], Uses = [SA1, LC1] in {
4592 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4597 // Pipelined loop instructions, sp[123]loop0
4598 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4599 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4600 opExtendable = 0, isPredicateLate = 1 in
4601 class SPLOOP_iBase<string SP, bits<2> op>
4602 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4603 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
4607 let IClass = 0b0110;
4609 let Inst{22-21} = op;
4610 let Inst{27-23} = 0b10011;
4611 let Inst{20-16} = U10{9-5};
4612 let Inst{12-8} = r7_2{8-4};
4613 let Inst{7-5} = U10{4-2};
4614 let Inst{4-3} = r7_2{3-2};
4615 let Inst{1-0} = U10{1-0};
4618 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4619 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4620 opExtendable = 0, isPredicateLate = 1 in
4621 class SPLOOP_rBase<string SP, bits<2> op>
4622 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4623 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
4627 let IClass = 0b0110;
4629 let Inst{22-21} = op;
4630 let Inst{27-23} = 0b00001;
4631 let Inst{20-16} = Rs;
4632 let Inst{12-8} = r7_2{8-4};
4633 let Inst{4-3} = r7_2{3-2};
4636 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
4637 def i : SPLOOP_iBase<mnemonic, op>;
4638 def r : SPLOOP_rBase<mnemonic, op>;
4641 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4642 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
4643 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
4645 // if (Rs[!>=<]=#0) jump:[t/nt]
4646 let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0,
4647 hasSideEffects = 0 in
4648 class J2_jump_0_Base<string compare, bit isTak, bits<2> op>
4649 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4650 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > {
4654 let IClass = 0b0110;
4656 let Inst{27-24} = 0b0001;
4657 let Inst{23-22} = op;
4658 let Inst{12} = isTak;
4659 let Inst{21} = r13_2{14};
4660 let Inst{20-16} = Rs;
4661 let Inst{11-1} = r13_2{12-2};
4662 let Inst{13} = r13_2{13};
4665 multiclass J2_jump_compare_0<string compare, bits<2> op> {
4666 def NAME : J2_jump_0_Base<compare, 0, op>;
4667 def NAME#pt : J2_jump_0_Base<compare, 1, op>;
4670 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
4671 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
4672 defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>;
4673 defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>;
4675 // Transfer to/from Control/GPR Guest/GPR
4676 let hasSideEffects = 0 in
4677 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
4678 : CRInst <(outs CTRC:$dst), (ins RC:$src),
4679 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4683 let IClass = 0b0110;
4685 let Inst{27-25} = 0b001;
4686 let Inst{24} = isDouble;
4687 let Inst{23-21} = 0b001;
4688 let Inst{20-16} = src;
4689 let Inst{4-0} = dst;
4692 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4693 def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>;
4694 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4695 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4697 let hasSideEffects = 0 in
4698 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
4699 : CRInst <(outs RC:$dst), (ins CTRC:$src),
4700 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4704 let IClass = 0b0110;
4706 let Inst{27-26} = 0b10;
4707 let Inst{25} = isSingle;
4708 let Inst{24-21} = 0b0000;
4709 let Inst{20-16} = src;
4710 let Inst{4-0} = dst;
4713 let hasNewValue = 1, opNewValue = 0 in
4714 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4715 def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>;
4716 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4717 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4719 // Y4_trace: Send value to etm trace.
4720 let isSoloAX = 1, hasSideEffects = 0 in
4721 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4725 let IClass = 0b0110;
4726 let Inst{27-21} = 0b0010010;
4727 let Inst{20-16} = Rs;
4730 // Support for generating global address.
4731 // Taken from X86InstrInfo.td.
4732 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
4735 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
4736 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
4738 // HI/LO Instructions
4739 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4740 hasNewValue = 1, opNewValue = 0 in
4741 class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp>
4742 : ALU32_ri<(outs IntRegs:$dst),
4743 (ins i32imm:$imm_value),
4744 "$dst"#RegHalf#" = #"#Op#"($imm_value)", []> {
4747 let IClass = 0b0111;
4750 let Inst{26-24} = MajOp;
4751 let Inst{21} = MinOp;
4752 let Inst{20-16} = dst;
4753 let Inst{23-22} = !if (!eq(Op, "LO"), imm_value{15-14}, imm_value{31-30});
4754 let Inst{13-0} = !if (!eq(Op, "LO"), imm_value{13-0}, imm_value{29-16});
4757 let isAsmParserOnly = 1 in {
4758 def LO : REG_IMMED<".l", "LO", 0b0, 0b001, 0b1>;
4759 def LO_H : REG_IMMED<".l", "HI", 0b0, 0b001, 0b1>;
4760 def HI : REG_IMMED<".h", "HI", 0b0, 0b010, 0b1>;
4761 def HI_L : REG_IMMED<".h", "LO", 0b0, 0b010, 0b1>;
4764 let isMoveImm = 1, isCodeGenOnly = 1 in
4765 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4766 "$dst.l = #LO($label@GOTREL)",
4769 let isMoveImm = 1, isCodeGenOnly = 1 in
4770 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4771 "$dst.h = #HI($label@GOTREL)",
4774 let isReMaterializable = 1, isMoveImm = 1,
4775 isCodeGenOnly = 1, hasSideEffects = 0 in
4776 def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4777 "$dst.h = #HI($global@GOT)",
4780 let isReMaterializable = 1, isMoveImm = 1,
4781 isCodeGenOnly = 1, hasSideEffects = 0 in
4782 def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4783 "$dst.l = #LO($global@GOT)",
4786 let isReMaterializable = 1, isMoveImm = 1,
4787 isCodeGenOnly = 1, hasSideEffects = 0 in
4788 def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4789 "$dst.h = #HI($global@GOTREL)",
4792 let isReMaterializable = 1, isMoveImm = 1,
4793 isCodeGenOnly = 1, hasSideEffects = 0 in
4794 def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4795 "$dst.l = #LO($global@GOTREL)",
4798 // This pattern is incorrect. When we add small data, we should change
4799 // this pattern to use memw(#foo).
4800 // This is for sdata.
4801 let isMoveImm = 1, isAsmParserOnly = 1 in
4802 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4803 "$dst = CONST32(#$global)",
4804 [(set (i32 IntRegs:$dst),
4805 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4807 let isReMaterializable = 1, isMoveImm = 1 in
4808 def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4809 "$dst = CONST32(#$jt)",
4810 [(set (i32 IntRegs:$dst),
4811 (HexagonCONST32 tjumptable:$jt))]>;
4813 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4814 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
4815 "$dst = CONST32(#$global)",
4816 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4818 // Map TLS addressses to a CONST32 instruction
4819 def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>;
4820 def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
4822 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4823 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4824 "$dst = CONST32($label)",
4825 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4827 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4828 def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
4829 "$dst = CONST64(#$global)",
4830 [(set (i64 DoubleRegs:$dst), imm:$global)]>;
4832 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
4833 isCodeGenOnly = 1 in
4834 def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "",
4835 [(set (i1 PredRegs:$dst), 1)]>;
4837 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
4838 isCodeGenOnly = 1 in
4839 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)",
4840 [(set (i1 PredRegs:$dst), 0)]>;
4842 // Pseudo instructions.
4843 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4844 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4845 SDTCisVT<1, i32> ]>;
4847 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4848 [SDNPHasChain, SDNPOutGlue]>;
4849 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4850 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4852 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4854 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4855 // Optional Flag and Variable Arguments.
4856 // Its 1 Operand has pointer type.
4857 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4858 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4860 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
4861 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4862 ".error \"should not emit\" ",
4863 [(callseq_start timm:$amt)]>;
4865 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
4866 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4867 ".error \"should not emit\" ",
4868 [(callseq_end timm:$amt1, timm:$amt2)]>;
4870 // Call subroutine indirectly.
4871 let Defs = VolatileV3.Regs in
4872 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4874 // Indirect tail-call.
4875 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4876 isTerminator = 1, isCodeGenOnly = 1 in
4877 def TCRETURNr : T_JMPr;
4879 // Direct tail-calls.
4880 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4881 isTerminator = 1, isCodeGenOnly = 1 in {
4882 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4883 [], "", J_tc_2early_SLOT23>;
4884 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4885 [], "", J_tc_2early_SLOT23>;
4889 def: Pat<(HexagonTCRet tglobaladdr:$dst),
4890 (TCRETURNtg tglobaladdr:$dst)>;
4891 def: Pat<(HexagonTCRet texternalsym:$dst),
4892 (TCRETURNtext texternalsym:$dst)>;
4893 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4894 (TCRETURNr (i32 IntRegs:$dst))>;
4896 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4897 def: Pat<(and (i32 IntRegs:$src1), 65535),
4898 (A2_zxth IntRegs:$src1)>;
4900 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4901 def: Pat<(and (i32 IntRegs:$src1), 255),
4902 (A2_zxtb IntRegs:$src1)>;
4904 // Map Add(p1, true) to p1 = not(p1).
4905 // Add(p1, false) should never be produced,
4906 // if it does, it got to be mapped to NOOP.
4907 def: Pat<(add (i1 PredRegs:$src1), -1),
4908 (C2_not PredRegs:$src1)>;
4910 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4911 def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ExtPred:$src3),
4912 (C2_muxii PredRegs:$src1, s8ExtPred:$src3, s8ImmPred:$src2)>;
4914 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4915 // => r0 = C2_muxir(p0, r1, #i)
4916 def: Pat<(select (not (i1 PredRegs:$src1)), s8ExtPred:$src2,
4917 (i32 IntRegs:$src3)),
4918 (C2_muxir PredRegs:$src1, IntRegs:$src3, s8ExtPred:$src2)>;
4920 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4921 // => r0 = C2_muxri (p0, #i, r1)
4922 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s8ExtPred:$src3),
4923 (C2_muxri PredRegs:$src1, s8ExtPred:$src3, IntRegs:$src2)>;
4925 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4926 def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4927 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4929 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4930 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4931 (A2_sxtw (LoReg DoubleRegs:$src1))>;
4933 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)).
4934 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4935 (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>;
4937 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)).
4938 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4939 (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>;
4941 // We want to prevent emitting pnot's as much as possible.
4942 // Map brcond with an unsupported setcc to a J2_jumpf.
4943 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4945 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4948 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4950 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4952 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4953 (J2_jumpf PredRegs:$src1, bb:$offset)>;
4955 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4956 (J2_jumpt PredRegs:$src1, bb:$offset)>;
4958 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4959 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
4960 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
4963 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
4964 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4966 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
4968 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4970 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
4973 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4975 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4978 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4980 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4983 // Map from a 64-bit select to an emulated 64-bit mux.
4984 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4985 def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4986 (i64 DoubleRegs:$src3)),
4987 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2),
4988 (HiReg DoubleRegs:$src3)),
4989 (C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2),
4990 (LoReg DoubleRegs:$src3)))>;
4992 // Map from a 1-bit select to logical ops.
4993 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4994 def: Pat<(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), (i1 PredRegs:$src3)),
4995 (C2_or (C2_and PredRegs:$src1, PredRegs:$src2),
4996 (C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>;
4998 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
4999 def : Pat<(i1 (load ADDRriS11_2:$addr)),
5000 (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
5002 // Map for truncating from 64 immediates to 32 bit immediates.
5003 def: Pat<(i32 (trunc (i64 DoubleRegs:$src))),
5004 (LoReg DoubleRegs:$src)>;
5006 // Map for truncating from i64 immediates to i1 bit immediates.
5007 def: Pat<(i1 (trunc (i64 DoubleRegs:$src))),
5008 (C2_tfrrp (LoReg DoubleRegs:$src))>;
5010 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
5011 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
5012 (S2_storerb_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
5015 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
5016 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
5017 (S2_storerh_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
5019 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
5020 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
5021 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
5024 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
5025 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
5026 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
5029 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
5030 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
5031 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
5034 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
5035 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
5036 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
5038 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
5039 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
5040 (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
5042 // rs <= rt -> !(rs > rt).
5043 let AddedComplexity = 30 in
5044 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
5045 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
5047 // rs <= rt -> !(rs > rt).
5048 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5049 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
5051 // Rss <= Rtt -> !(Rss > Rtt).
5052 def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5053 (C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>;
5055 // Map cmpne -> cmpeq.
5056 // Hexagon_TODO: We should improve on this.
5057 // rs != rt -> !(rs == rt).
5058 let AddedComplexity = 30 in
5059 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
5060 (C2_not (C2_cmpeqi IntRegs:$src1, s10ExtPred:$src2))>;
5062 // Map cmpne(Rs) -> !cmpeqe(Rs).
5063 // rs != rt -> !(rs == rt).
5064 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5065 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
5067 // Convert setne back to xor for hexagon since we compute w/ pred registers.
5068 def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
5069 (C2_xor PredRegs:$src1, PredRegs:$src2)>;
5071 // Map cmpne(Rss) -> !cmpew(Rss).
5072 // rs != rt -> !(rs == rt).
5073 def: Pat<(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5074 (C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>;
5076 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
5077 // rs >= rt -> !(rt > rs).
5078 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5079 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
5081 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
5082 let AddedComplexity = 30 in
5083 def: Pat<(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
5084 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
5086 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
5087 // rss >= rtt -> !(rtt > rss).
5088 def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5089 (C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>;
5091 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
5092 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
5093 // rs < rt -> !(rs >= rt).
5094 let AddedComplexity = 30 in
5095 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
5096 (C2_not (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
5098 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
5099 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
5100 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
5102 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
5103 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
5104 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u8ExtPred:$src2))>;
5106 // Generate cmpgtu(Rs, #u9)
5107 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
5108 (C2_cmpgtui IntRegs:$src1, u9ExtPred:$src2)>;
5110 // Map from Rs >= Rt -> !(Rt > Rs).
5111 // rs >= rt -> !(rt > rs).
5112 def: Pat<(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5113 (C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>;
5115 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
5116 // Map from (Rs <= Rt) -> !(Rs > Rt).
5117 def: Pat<(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
5118 (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>;
5122 def: Pat<(i32 (sext (i1 PredRegs:$src1))),
5123 (C2_muxii PredRegs:$src1, -1, 0)>;
5126 def: Pat<(i64 (sext (i1 PredRegs:$src1))),
5127 (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>;
5129 // Convert sign-extended load back to load and sign extend.
5131 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
5132 (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
5136 def: Pat<(i32 (zext (i1 PredRegs:$src1))),
5137 (C2_muxii PredRegs:$src1, 1, 0)>;
5139 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5140 def: Pat<(i32 (anyext (i1 PredRegs:$src1))),
5141 (C2_muxii PredRegs:$src1, 1, 0)>;
5143 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
5144 def: Pat<(i64 (anyext (i1 PredRegs:$src1))),
5145 (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>;
5147 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5149 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
5150 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5151 (L2_loadri_io AddrFI:$srcLow, 0)))>;
5153 // Multiply 64-bit unsigned and use upper result.
5154 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5160 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (LoReg $src2)), 32),
5163 (A2_combinew (A2_tfrsi 0),
5164 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))),
5168 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32)
5171 // Hexagon specific ISD nodes.
5172 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
5174 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
5176 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
5177 SDTHexagonADJDYNALLOC>;
5178 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
5180 // Needed to tag these instructions for stack layout.
5181 let isCodeGenOnly = 1, usesCustomInserter = 1 in
5182 def ADJDYNALLOC : T_Addri<s6Imm>;
5184 def: Pat<(Hexagon_ADJDYNALLOC I32:$Rs, s16ImmPred:$s16),
5185 (ADJDYNALLOC I32:$Rs, imm:$s16)>;
5187 let isCodeGenOnly = 1 in
5188 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5190 [(set (i32 IntRegs:$dst),
5191 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5193 let AddedComplexity = 100 in
5194 def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5195 (i32 IntRegs:$src1)>;
5197 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
5199 def : Pat<(HexagonWrapperJT tjumptable:$dst),
5200 (i32 (CONST32_set_jt tjumptable:$dst))>;
5204 //===----------------------------------------------------------------------===//
5206 // Shift by immediate/register and accumulate/logical
5207 //===----------------------------------------------------------------------===//
5209 // Rx[+-&|]=asr(Rs,#u5)
5210 // Rx[+-&|^]=lsr(Rs,#u5)
5211 // Rx[+-&|^]=asl(Rs,#u5)
5213 let hasNewValue = 1, opNewValue = 0 in
5214 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5215 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5216 : SInst_acc<(outs IntRegs:$Rx),
5217 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5218 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5219 [(set (i32 IntRegs:$Rx),
5220 (OpNode2 (i32 IntRegs:$src1),
5221 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5222 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
5227 let IClass = 0b1000;
5229 let Inst{27-24} = 0b1110;
5230 let Inst{23-22} = majOp{2-1};
5232 let Inst{7} = majOp{0};
5233 let Inst{6-5} = minOp;
5235 let Inst{20-16} = Rs;
5236 let Inst{12-8} = u5;
5239 // Rx[+-&|]=asr(Rs,Rt)
5240 // Rx[+-&|^]=lsr(Rs,Rt)
5241 // Rx[+-&|^]=asl(Rs,Rt)
5243 let hasNewValue = 1, opNewValue = 0 in
5244 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5245 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
5246 : SInst_acc<(outs IntRegs:$Rx),
5247 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5248 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5249 [(set (i32 IntRegs:$Rx),
5250 (OpNode2 (i32 IntRegs:$src1),
5251 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5252 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
5257 let IClass = 0b1100;
5259 let Inst{27-24} = 0b1100;
5260 let Inst{23-22} = majOp;
5261 let Inst{7-6} = minOp;
5263 let Inst{20-16} = Rs;
5264 let Inst{12-8} = Rt;
5267 // Rxx[+-&|]=asr(Rss,#u6)
5268 // Rxx[+-&|^]=lsr(Rss,#u6)
5269 // Rxx[+-&|^]=asl(Rss,#u6)
5271 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5272 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5273 : SInst_acc<(outs DoubleRegs:$Rxx),
5274 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
5275 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5276 [(set (i64 DoubleRegs:$Rxx),
5277 (OpNode2 (i64 DoubleRegs:$src1),
5278 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
5279 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
5284 let IClass = 0b1000;
5286 let Inst{27-24} = 0b0010;
5287 let Inst{23-22} = majOp{2-1};
5288 let Inst{7} = majOp{0};
5289 let Inst{6-5} = minOp;
5290 let Inst{4-0} = Rxx;
5291 let Inst{20-16} = Rss;
5292 let Inst{13-8} = u6;
5296 // Rxx[+-&|]=asr(Rss,Rt)
5297 // Rxx[+-&|^]=lsr(Rss,Rt)
5298 // Rxx[+-&|^]=asl(Rss,Rt)
5299 // Rxx[+-&|^]=lsl(Rss,Rt)
5301 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5302 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5303 : SInst_acc<(outs DoubleRegs:$Rxx),
5304 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5305 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5306 [(set (i64 DoubleRegs:$Rxx),
5307 (OpNode2 (i64 DoubleRegs:$src1),
5308 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5309 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
5314 let IClass = 0b1100;
5316 let Inst{27-24} = 0b1011;
5317 let Inst{23-21} = majOp;
5318 let Inst{20-16} = Rss;
5319 let Inst{12-8} = Rt;
5320 let Inst{7-6} = minOp;
5321 let Inst{4-0} = Rxx;
5324 //===----------------------------------------------------------------------===//
5325 // Multi-class for the shift instructions with logical/arithmetic operators.
5326 //===----------------------------------------------------------------------===//
5328 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
5329 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
5330 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
5331 OpNode2, majOp, minOp >;
5332 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
5333 OpNode2, majOp, minOp >;
5336 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5337 let AddedComplexity = 100 in
5338 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5340 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5341 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5342 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
5345 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5346 let AddedComplexity = 100 in
5347 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
5350 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5352 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5353 xtype_xor_imm_acc<"lsr", srl, 0b01>;
5355 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5356 xtype_xor_imm_acc<"asl", shl, 0b10>;
5358 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
5359 let AddedComplexity = 100 in
5360 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
5362 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
5363 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5364 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5367 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
5368 let AddedComplexity = 100 in
5369 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
5371 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
5372 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
5373 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5374 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
5377 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5378 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5379 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
5382 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
5383 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5384 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5385 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
5387 //===----------------------------------------------------------------------===//
5388 let hasSideEffects = 0 in
5389 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
5390 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
5391 : SInst <(outs RC:$dst),
5392 (ins DoubleRegs:$src1, DoubleRegs:$src2),
5393 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
5394 #!if(hasShift,":>>1","")
5395 #!if(isSat, ":sat", ""),
5396 [], "", S_3op_tc_2_SLOT23 > {
5401 let IClass = 0b1100;
5403 let Inst{27-24} = 0b0001;
5404 let Inst{23-22} = MajOp;
5405 let Inst{20-16} = !if (SwapOps, src2, src1);
5406 let Inst{12-8} = !if (SwapOps, src1, src2);
5407 let Inst{7-5} = MinOp;
5408 let Inst{4-0} = dst;
5411 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
5412 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
5413 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
5414 isSat, isRnd, hasShift>;
5416 let Itinerary = S_3op_tc_1_SLOT23 in {
5417 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5418 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5419 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5420 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
5422 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
5423 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
5426 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
5428 let hasSideEffects = 0 in
5429 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
5430 : SInst < (outs DoubleRegs:$Rdd),
5431 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5432 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5433 [], "", S_3op_tc_1_SLOT23 > {
5439 let IClass = 0b1100;
5441 let Inst{27-24} = 0b0010;
5442 let Inst{23-21} = MajOp;
5443 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5444 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5446 let Inst{4-0} = Rdd;
5449 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5450 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
5452 //===----------------------------------------------------------------------===//
5453 // Template class used by vector shift, vector rotate, vector neg,
5454 // 32-bit shift, 64-bit shifts, etc.
5455 //===----------------------------------------------------------------------===//
5457 let hasSideEffects = 0 in
5458 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
5459 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
5460 : SInst <(outs RC:$dst),
5461 (ins RC:$src1, IntRegs:$src2),
5462 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
5463 pattern, "", S_3op_tc_1_SLOT23> {
5468 let IClass = 0b1100;
5470 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5471 let Inst{23-22} = MajOp;
5472 let Inst{20-16} = src1;
5473 let Inst{12-8} = src2;
5474 let Inst{7-6} = MinOp;
5475 let Inst{4-0} = dst;
5478 let hasNewValue = 1 in
5479 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5480 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5481 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5482 (i32 IntRegs:$src2)))]>;
5484 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
5485 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
5486 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5489 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5490 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5491 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5492 (i32 IntRegs:$src2)))]>;
5495 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5496 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5499 // Shift by register
5500 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5502 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5503 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5504 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5505 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5507 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5509 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5510 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5511 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5512 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5514 // Shift by register with saturation
5515 // Rd=asr(Rs,Rt):sat
5516 // Rd=asl(Rs,Rt):sat
5518 let Defs = [USR_OVF] in {
5519 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5520 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5523 let hasNewValue = 1, hasSideEffects = 0 in
5524 class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
5525 : SInst < (outs IntRegs:$Rd),
5526 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5527 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5528 #!if(hasShift, ":<<1", "")
5529 #!if(isRnd, ":rnd", "")
5530 #!if(isSat, ":sat", ""),
5531 [], "", S_3op_tc_1_SLOT23 > {
5536 let IClass = 0b1100;
5538 let Inst{27-24} = 0b0101;
5539 let Inst{20-16} = Rss;
5540 let Inst{12-8} = Rt;
5541 let Inst{7-5} = MinOp;
5545 def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>;
5547 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
5548 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5550 let hasSideEffects = 0 in
5551 class T_S3op_7 <string mnemonic, bit MajOp >
5552 : SInst <(outs DoubleRegs:$Rdd),
5553 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
5554 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
5555 [], "", S_3op_tc_1_SLOT23 > {
5561 let IClass = 0b1100;
5563 let Inst{27-24} = 0b0000;
5564 let Inst{23} = MajOp;
5565 let Inst{20-16} = !if(MajOp, Rss, Rtt);
5566 let Inst{12-8} = !if(MajOp, Rtt, Rss);
5568 let Inst{4-0} = Rdd;
5571 def S2_valignib : T_S3op_7 < "valignb", 0>;
5572 def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
5574 //===----------------------------------------------------------------------===//
5575 // Template class for 'insert bitfield' instructions
5576 //===----------------------------------------------------------------------===//
5577 let hasSideEffects = 0 in
5578 class T_S3op_insert <string mnemonic, RegisterClass RC>
5579 : SInst <(outs RC:$dst),
5580 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5581 "$dst = "#mnemonic#"($src2, $src3)" ,
5582 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5587 let IClass = 0b1100;
5589 let Inst{27-26} = 0b10;
5590 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5592 let Inst{20-16} = src2;
5593 let Inst{12-8} = src3;
5594 let Inst{4-0} = dst;
5597 let hasSideEffects = 0 in
5598 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5599 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5600 "$dst = insert($src1, #$src2, #$src3)",
5601 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5608 string ImmOpStr = !cast<string>(ImmOp);
5610 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5611 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5613 let IClass = 0b1000;
5615 let Inst{27-24} = RegTyBits;
5616 let Inst{23} = bit23;
5617 let Inst{22-21} = src3{4-3};
5618 let Inst{20-16} = src1;
5619 let Inst{13} = bit13;
5620 let Inst{12-8} = src2{4-0};
5621 let Inst{7-5} = src3{2-0};
5622 let Inst{4-0} = dst;
5625 // Rx=insert(Rs,Rtt)
5626 // Rx=insert(Rs,#u5,#U5)
5627 let hasNewValue = 1 in {
5628 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5629 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5632 // Rxx=insert(Rss,Rtt)
5633 // Rxx=insert(Rss,#u6,#U6)
5634 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5635 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5637 //===----------------------------------------------------------------------===//
5638 // Template class for 'extract bitfield' instructions
5639 //===----------------------------------------------------------------------===//
5640 let hasNewValue = 1, hasSideEffects = 0 in
5641 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5642 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5643 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5644 [], "", S_3op_tc_2_SLOT23 > {
5649 let IClass = 0b1100;
5651 let Inst{27-22} = 0b100100;
5652 let Inst{20-16} = Rs;
5653 let Inst{12-8} = Rtt;
5654 let Inst{7-6} = MinOp;
5658 let hasSideEffects = 0 in
5659 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5660 RegisterClass RC, Operand ImmOp>
5661 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5662 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5663 [], "", S_2op_tc_2_SLOT23> {
5670 string ImmOpStr = !cast<string>(ImmOp);
5672 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5673 !if (!eq(mnemonic, "extractu"), 0, 1));
5675 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5677 let IClass = 0b1000;
5679 let Inst{27-24} = RegTyBits;
5680 let Inst{23} = bit23;
5681 let Inst{22-21} = src3{4-3};
5682 let Inst{20-16} = src1;
5683 let Inst{13} = bit13;
5684 let Inst{12-8} = src2{4-0};
5685 let Inst{7-5} = src3{2-0};
5686 let Inst{4-0} = dst;
5691 // Rdd=extractu(Rss,Rtt)
5692 // Rdd=extractu(Rss,#u6,#U6)
5693 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5694 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5696 // Rd=extractu(Rs,Rtt)
5697 // Rd=extractu(Rs,#u5,#U5)
5698 let hasNewValue = 1 in {
5699 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5700 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5703 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5704 def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5705 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
5707 //===----------------------------------------------------------------------===//
5708 // :raw for of tableindx[bdhw] insns
5709 //===----------------------------------------------------------------------===//
5711 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5712 class tableidxRaw<string OpStr, bits<2>MinOp>
5713 : SInst <(outs IntRegs:$Rx),
5714 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5715 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5716 [], "$Rx = $_dst_" > {
5722 let IClass = 0b1000;
5724 let Inst{27-24} = 0b0111;
5725 let Inst{23-22} = MinOp;
5726 let Inst{21} = u4{3};
5727 let Inst{20-16} = Rs;
5728 let Inst{13-8} = S6;
5729 let Inst{7-5} = u4{2-0};
5733 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5734 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5735 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5736 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5738 //===----------------------------------------------------------------------===//
5739 // V3 Instructions +
5740 //===----------------------------------------------------------------------===//
5742 include "HexagonInstrInfoV3.td"
5744 //===----------------------------------------------------------------------===//
5745 // V3 Instructions -
5746 //===----------------------------------------------------------------------===//
5748 //===----------------------------------------------------------------------===//
5749 // V4 Instructions +
5750 //===----------------------------------------------------------------------===//
5752 include "HexagonInstrInfoV4.td"
5754 //===----------------------------------------------------------------------===//
5755 // V4 Instructions -
5756 //===----------------------------------------------------------------------===//
5758 //===----------------------------------------------------------------------===//
5759 // V5 Instructions +
5760 //===----------------------------------------------------------------------===//
5762 include "HexagonInstrInfoV5.td"
5764 //===----------------------------------------------------------------------===//
5765 // V5 Instructions -
5766 //===----------------------------------------------------------------------===//
5768 //===----------------------------------------------------------------------===//
5769 // ALU32/64/Vector +
5770 //===----------------------------------------------------------------------===///
5772 include "HexagonInstrInfoVector.td"