1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
15 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
17 def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
18 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
25 isExtended = 0, isExtendable = 1, opExtendable = 0,
26 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
27 class T_Call<string ExtStr>
28 : JInst<(outs), (ins calltarget:$dst),
29 "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
30 let BaseOpcode = "call";
34 let Inst{27-25} = 0b101;
35 let Inst{24-16,13-1} = dst{23-2};
39 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicated = 1,
40 isExtended = 0, isExtendable = 1, opExtendable = 1,
41 isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
42 class T_CallPred<bit IfTrue, string ExtStr>
43 : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
44 CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
45 [], "", J_tc_2early_SLOT23> {
46 let BaseOpcode = "call";
47 let isPredicatedFalse = !if(IfTrue,0,1);
52 let Inst{27-24} = 0b1101;
53 let Inst{23-22,20-16,13,7-1} = dst{16-2};
54 let Inst{21} = !if(IfTrue,0,1);
59 multiclass T_Calls<string ExtStr> {
60 def NAME : T_Call<ExtStr>;
61 def t : T_CallPred<1, ExtStr>;
62 def f : T_CallPred<0, ExtStr>;
65 defm J2_call: T_Calls<"">, PredRel;
67 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
68 def CALLv3nr : T_Call<"">, PredRel;
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 //===----------------------------------------------------------------------===//
78 // Call subroutine from register.
80 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
81 def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
84 //===----------------------------------------------------------------------===//
86 //===----------------------------------------------------------------------===//
88 //===----------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
92 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
93 def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
95 class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
96 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
98 def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
99 def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
101 let hasSideEffects = 0, isAsmParserOnly = 1 in
102 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
103 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
104 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
105 (i64 DoubleRegs:$Rt))))],
106 "", ALU64_tc_1_SLOT23>;
109 let hasSideEffects = 0 in
110 class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
111 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
112 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
113 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
120 let Inst{27-23} = 0b00111;
121 let Inst{22-21} = !if(isMax, 0b10, 0b01);
122 let Inst{20-16} = !if(isMax, Rt, Rs);
123 let Inst{12-8} = !if(isMax, Rs, Rt);
125 let Inst{6} = !if(isMax, 0b0, 0b1);
126 let Inst{5} = isUnsigned;
130 def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>;
131 def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
132 def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>;
133 def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
135 multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
136 defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
139 let AddedComplexity = 200 in {
140 defm: MinMax_pats_p<setge, A2_maxp, A2_minp>;
141 defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>;
142 defm: MinMax_pats_p<setle, A2_minp, A2_maxp>;
143 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
144 defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>;
145 defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>;
146 defm: MinMax_pats_p<setule, A2_minup, A2_maxup>;
147 defm: MinMax_pats_p<setult, A2_minup, A2_maxup>;
150 //===----------------------------------------------------------------------===//
152 //===----------------------------------------------------------------------===//
157 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
158 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>;
160 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
161 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>;
163 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
164 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>;
166 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
167 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
169 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
170 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
172 // Map call instruction
173 def : Pat<(callv3 (i32 IntRegs:$dst)),
174 (J2_callr (i32 IntRegs:$dst))>;
175 def : Pat<(callv3 tglobaladdr:$dst),
176 (J2_call tglobaladdr:$dst)>;
177 def : Pat<(callv3 texternalsym:$dst),
178 (J2_call texternalsym:$dst)>;
179 def : Pat<(callv3 tglobaltlsaddr:$dst),
180 (J2_call tglobaltlsaddr:$dst)>;
182 def : Pat<(callv3nr (i32 IntRegs:$dst)),
183 (CALLRv3nr (i32 IntRegs:$dst))>;
184 def : Pat<(callv3nr tglobaladdr:$dst),
185 (CALLv3nr tglobaladdr:$dst)>;
186 def : Pat<(callv3nr texternalsym:$dst),
187 (CALLv3nr texternalsym:$dst)>;
189 //===----------------------------------------------------------------------===//
190 // :raw form of vrcmpys:hi/lo insns
191 //===----------------------------------------------------------------------===//
192 // Vector reduce complex multiply by scalar.
193 let Defs = [USR_OVF], hasSideEffects = 0 in
194 class T_vrcmpRaw<string HiLo, bits<3>MajOp>:
195 MInst<(outs DoubleRegs:$Rdd),
196 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
197 "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
204 let Inst{27-24} = 0b1000;
205 let Inst{23-21} = MajOp;
206 let Inst{20-16} = Rss;
207 let Inst{12-8} = Rtt;
208 let Inst{7-5} = 0b100;
212 def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
213 def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
215 // Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
216 let hasSideEffects = 0, isAsmParserOnly = 1 in
218 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
219 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
221 // Vector reduce complex multiply by scalar with accumulation.
222 let Defs = [USR_OVF], hasSideEffects = 0 in
223 class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
224 MInst <(outs DoubleRegs:$Rxx),
225 (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
226 "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
234 let Inst{27-24} = 0b1010;
235 let Inst{23-21} = MajOp;
236 let Inst{20-16} = Rss;
237 let Inst{12-8} = Rtt;
238 let Inst{7-5} = 0b100;
242 def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
243 def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
245 // Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
247 let isAsmParserOnly = 1 in
248 def M2_vrcmpys_acc_s1
249 : MInst <(outs DoubleRegs:$dst),
250 (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
251 "$dst += vrcmpys($src1, $src2):<<1:sat", [],
254 def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
255 def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
257 // Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
258 let isAsmParserOnly = 1 in
260 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
261 "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
264 // S2_cabacdecbin: Cabac decode bin.
265 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
266 def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>;