1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 let isCall = 1, neverHasSideEffects = 1,
20 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
21 P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
22 def CALLv3 : JInst<(outs), (ins calltarget:$dst, variable_ops),
23 "call $dst", []>, Requires<[HasV3T]>;
26 //===----------------------------------------------------------------------===//
28 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
33 //===----------------------------------------------------------------------===//
34 // Call subroutine from register.
35 let isCall = 1, neverHasSideEffects = 1,
36 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
37 P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
38 def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst, variable_ops),
40 []>, Requires<[HasV3TOnly]>;
44 // Jump to address from register
45 // if(p?.new) jumpr:t r?
46 let isReturn = 1, isTerminator = 1, isBarrier = 1,
47 Defs = [PC], Uses = [R31] in {
48 def JMPR_cdnPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
49 "if ($src1.new) jumpr:t $src2",
50 []>, Requires<[HasV3T]>;
53 // if (!p?.new) jumpr:t r?
54 let isReturn = 1, isTerminator = 1, isBarrier = 1,
55 Defs = [PC], Uses = [R31] in {
56 def JMPR_cdnNotPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
57 "if (!$src1.new) jumpr:t $src2",
58 []>, Requires<[HasV3T]>;
62 // if(p?.new) jumpr:nt r?
63 let isReturn = 1, isTerminator = 1, isBarrier = 1,
64 Defs = [PC], Uses = [R31] in {
65 def JMPR_cdnPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
66 "if ($src1.new) jumpr:nt $src2",
67 []>, Requires<[HasV3T]>;
70 // if (!p?.new) jumpr:nt r?
71 let isReturn = 1, isTerminator = 1, isBarrier = 1,
72 Defs = [PC], Uses = [R31] in {
73 def JMPR_cdnNotPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
74 "if (!$src1.new) jumpr:nt $src2",
75 []>, Requires<[HasV3T]>;
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let AddedComplexity = 200 in
87 def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
89 "$dst = max($src2, $src1)",
90 [(set (i64 DoubleRegs:$dst),
91 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
92 (i64 DoubleRegs:$src1))),
93 (i64 DoubleRegs:$src1),
94 (i64 DoubleRegs:$src2))))]>,
97 let AddedComplexity = 200 in
98 def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
100 "$dst = min($src2, $src1)",
101 [(set (i64 DoubleRegs:$dst),
102 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
103 (i64 DoubleRegs:$src1))),
104 (i64 DoubleRegs:$src1),
105 (i64 DoubleRegs:$src2))))]>,
108 //===----------------------------------------------------------------------===//
110 //===----------------------------------------------------------------------===//
115 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
116 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
118 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
119 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
121 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
122 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
124 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
125 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
127 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
128 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
131 // Map call instruction
132 def : Pat<(call (i32 IntRegs:$dst)),
133 (CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
134 def : Pat<(call tglobaladdr:$dst),
135 (CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
136 def : Pat<(call texternalsym:$dst),
137 (CALLv3 texternalsym:$dst)>, Requires<[HasV3T]>;