1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Hexagon V4 Architecture spec defines 8 instruction classes:
15 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
19 // ========================================
20 // Loads (8/16/32/64 bit)
24 // ========================================
25 // Stores (8/16/32/64 bit)
28 // ALU32 Instructions:
29 // ========================================
30 // Arithmetic / Logical (32 bit)
33 // XTYPE Instructions (32/64 bit):
34 // ========================================
35 // Arithmetic, Logical, Bit Manipulation
36 // Multiply (Integer, Fractional, Complex)
37 // Permute / Vector Permute Operations
38 // Predicate Operations
39 // Shift / Shift with Add/Sub/Logical
41 // Vector Halfword (ALU, Shift, Multiply)
42 // Vector Word (ALU, Shift)
45 // ========================================
46 // Jump/Call PC-relative
49 // ========================================
52 // MEMOP Instructions:
53 // ========================================
54 // Operation on memory (8/16/32 bit)
57 // ========================================
62 // ========================================
63 // Control-Register Transfers
64 // Hardware Loop Setup
65 // Predicate Logicals & Reductions
67 // SYSTEM Instructions (not implemented in the compiler):
68 // ========================================
74 //===----------------------------------------------------------------------===//
76 //===----------------------------------------------------------------------===//
80 let isPredicated = 1 in
81 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
82 (ins PredRegs:$src1, IntRegs:$src2),
83 "if ($src1) $dst = aslh($src2)",
87 let isPredicated = 1 in
88 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
89 (ins PredRegs:$src1, IntRegs:$src2),
90 "if (!$src1) $dst = aslh($src2)",
94 let isPredicated = 1 in
95 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
96 (ins PredRegs:$src1, IntRegs:$src2),
97 "if ($src1.new) $dst = aslh($src2)",
101 let isPredicated = 1 in
102 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2),
104 "if (!$src1.new) $dst = aslh($src2)",
108 let isPredicated = 1 in
109 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
110 (ins PredRegs:$src1, IntRegs:$src2),
111 "if ($src1) $dst = asrh($src2)",
115 let isPredicated = 1 in
116 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
117 (ins PredRegs:$src1, IntRegs:$src2),
118 "if (!$src1) $dst = asrh($src2)",
122 let isPredicated = 1 in
123 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
124 (ins PredRegs:$src1, IntRegs:$src2),
125 "if ($src1.new) $dst = asrh($src2)",
129 let isPredicated = 1 in
130 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
131 (ins PredRegs:$src1, IntRegs:$src2),
132 "if (!$src1.new) $dst = asrh($src2)",
138 let isPredicated = 1 in
139 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
140 (ins PredRegs:$src1, IntRegs:$src2),
141 "if ($src1) $dst = sxtb($src2)",
145 let isPredicated = 1 in
146 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
147 (ins PredRegs:$src1, IntRegs:$src2),
148 "if (!$src1) $dst = sxtb($src2)",
152 let isPredicated = 1 in
153 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
154 (ins PredRegs:$src1, IntRegs:$src2),
155 "if ($src1.new) $dst = sxtb($src2)",
159 let isPredicated = 1 in
160 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
161 (ins PredRegs:$src1, IntRegs:$src2),
162 "if (!$src1.new) $dst = sxtb($src2)",
167 let isPredicated = 1 in
168 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
169 (ins PredRegs:$src1, IntRegs:$src2),
170 "if ($src1) $dst = sxth($src2)",
174 let isPredicated = 1 in
175 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
176 (ins PredRegs:$src1, IntRegs:$src2),
177 "if (!$src1) $dst = sxth($src2)",
181 let isPredicated = 1 in
182 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
183 (ins PredRegs:$src1, IntRegs:$src2),
184 "if ($src1.new) $dst = sxth($src2)",
188 let isPredicated = 1 in
189 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
190 (ins PredRegs:$src1, IntRegs:$src2),
191 "if (!$src1.new) $dst = sxth($src2)",
197 let neverHasSideEffects = 1, isPredicated = 1 in
198 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
199 (ins PredRegs:$src1, IntRegs:$src2),
200 "if ($src1) $dst = zxtb($src2)",
204 let neverHasSideEffects = 1, isPredicated = 1 in
205 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
206 (ins PredRegs:$src1, IntRegs:$src2),
207 "if (!$src1) $dst = zxtb($src2)",
211 let neverHasSideEffects = 1, isPredicated = 1 in
212 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
213 (ins PredRegs:$src1, IntRegs:$src2),
214 "if ($src1.new) $dst = zxtb($src2)",
218 let neverHasSideEffects = 1, isPredicated = 1 in
219 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
220 (ins PredRegs:$src1, IntRegs:$src2),
221 "if (!$src1.new) $dst = zxtb($src2)",
225 let neverHasSideEffects = 1, isPredicated = 1 in
226 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
227 (ins PredRegs:$src1, IntRegs:$src2),
228 "if ($src1) $dst = zxth($src2)",
232 let neverHasSideEffects = 1, isPredicated = 1 in
233 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
234 (ins PredRegs:$src1, IntRegs:$src2),
235 "if (!$src1) $dst = zxth($src2)",
239 let neverHasSideEffects = 1, isPredicated = 1 in
240 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
241 (ins PredRegs:$src1, IntRegs:$src2),
242 "if ($src1.new) $dst = zxth($src2)",
246 let neverHasSideEffects = 1, isPredicated = 1 in
247 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
248 (ins PredRegs:$src1, IntRegs:$src2),
249 "if (!$src1.new) $dst = zxth($src2)",
254 //===----------------------------------------------------------------------===//
256 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 //===----------------------------------------------------------------------===//
264 /// Make sure that in post increment load, the first operand is always the post
265 /// increment operand.
267 //// Load doubleword.
270 // Rdd=memd(Rs+Rt<<#u2)
271 // Special case pattern for indexed load without offset which is easier to
272 // match. AddedComplexity of this pattern should be lower than base+offset load
273 // and lower yet than the more generic version with offset/shift below
274 // Similar approach is taken for all other base+index loads.
275 let AddedComplexity = 10, isPredicable = 1 in
276 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
277 (ins IntRegs:$src1, IntRegs:$src2),
278 "$dst=memd($src1+$src2<<#0)",
279 [(set DoubleRegs:$dst, (load (add IntRegs:$src1,
283 let AddedComplexity = 40, isPredicable = 1 in
284 def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst),
285 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
286 "$dst=memd($src1+$src2<<#$offset)",
287 [(set DoubleRegs:$dst, (load (add IntRegs:$src1,
289 u2ImmPred:$offset))))]>,
292 //// Load doubleword conditionally.
293 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
294 // if (Pv) Rd=memd(Rs+Rt<<#u2)
295 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
296 def LDrid_indexed_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
297 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
298 "if ($src1) $dst=memd($src2+$src3<<#0)",
302 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
303 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
304 def LDrid_indexed_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
305 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
306 "if ($src1.new) $dst=memd($src2+$src3<<#0)",
310 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
311 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
312 def LDrid_indexed_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
313 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
314 "if (!$src1) $dst=memd($src2+$src3<<#0)",
318 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
319 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
320 def LDrid_indexed_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
321 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
322 "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
326 // if (Pv) Rd=memd(Rs+Rt<<#u2)
327 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
328 def LDrid_indexed_shl_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
329 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
331 "if ($src1) $dst=memd($src2+$src3<<#$offset)",
335 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
336 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
337 def LDrid_indexed_shl_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
338 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
340 "if ($src1.new) $dst=memd($src2+$src3<<#$offset)",
344 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
345 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
346 def LDrid_indexed_shl_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
347 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
349 "if (!$src1) $dst=memd($src2+$src3<<#$offset)",
353 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
354 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
355 def LDrid_indexed_shl_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
356 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
358 "if (!$src1.new) $dst=memd($src2+$src3<<#$offset)",
362 // Rdd=memd(Rt<<#u2+#U6)
367 // Rd=memb(Rs+Rt<<#u2)
368 let AddedComplexity = 10, isPredicable = 1 in
369 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
370 (ins IntRegs:$src1, IntRegs:$src2),
371 "$dst=memb($src1+$src2<<#0)",
372 [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,
376 let AddedComplexity = 10, isPredicable = 1 in
377 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
378 (ins IntRegs:$src1, IntRegs:$src2),
379 "$dst=memub($src1+$src2<<#0)",
380 [(set IntRegs:$dst, (zextloadi8 (add IntRegs:$src1,
384 let AddedComplexity = 10, isPredicable = 1 in
385 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
386 (ins IntRegs:$src1, IntRegs:$src2),
387 "$dst=memub($src1+$src2<<#0)",
388 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
392 let AddedComplexity = 40, isPredicable = 1 in
393 def LDrib_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
394 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
395 "$dst=memb($src1+$src2<<#$offset)",
397 (sextloadi8 (add IntRegs:$src1,
399 u2ImmPred:$offset))))]>,
402 let AddedComplexity = 40, isPredicable = 1 in
403 def LDriub_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
404 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
405 "$dst=memub($src1+$src2<<#$offset)",
407 (zextloadi8 (add IntRegs:$src1,
409 u2ImmPred:$offset))))]>,
412 let AddedComplexity = 40, isPredicable = 1 in
413 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
414 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
415 "$dst=memub($src1+$src2<<#$offset)",
416 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
418 u2ImmPred:$offset))))]>,
421 //// Load byte conditionally.
422 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
423 // if (Pv) Rd=memb(Rs+Rt<<#u2)
424 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
425 def LDrib_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
426 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
427 "if ($src1) $dst=memb($src2+$src3<<#0)",
431 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
432 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
433 def LDrib_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
434 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
435 "if ($src1.new) $dst=memb($src2+$src3<<#0)",
439 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
440 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
441 def LDrib_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
442 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
443 "if (!$src1) $dst=memb($src2+$src3<<#0)",
447 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
448 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
449 def LDrib_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
450 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
451 "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
455 // if (Pv) Rd=memb(Rs+Rt<<#u2)
456 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
457 def LDrib_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
458 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
460 "if ($src1) $dst=memb($src2+$src3<<#$offset)",
464 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
465 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
466 def LDrib_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
469 "if ($src1.new) $dst=memb($src2+$src3<<#$offset)",
473 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
474 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
475 def LDrib_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
476 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
478 "if (!$src1) $dst=memb($src2+$src3<<#$offset)",
482 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
483 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
484 def LDrib_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
485 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
487 "if (!$src1.new) $dst=memb($src2+$src3<<#$offset)",
491 //// Load unsigned byte conditionally.
492 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
493 // if (Pv) Rd=memub(Rs+Rt<<#u2)
494 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
495 def LDriub_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
496 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
497 "if ($src1) $dst=memub($src2+$src3<<#0)",
501 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
502 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
503 def LDriub_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
504 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
505 "if ($src1.new) $dst=memub($src2+$src3<<#0)",
509 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
510 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
511 def LDriub_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
512 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
513 "if (!$src1) $dst=memub($src2+$src3<<#0)",
517 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
518 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
519 def LDriub_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
520 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
521 "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
525 // if (Pv) Rd=memub(Rs+Rt<<#u2)
526 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
527 def LDriub_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
528 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
530 "if ($src1) $dst=memub($src2+$src3<<#$offset)",
534 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
535 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
536 def LDriub_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
537 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
539 "if ($src1.new) $dst=memub($src2+$src3<<#$offset)",
543 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
544 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
545 def LDriub_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
546 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
548 "if (!$src1) $dst=memub($src2+$src3<<#$offset)",
552 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
553 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
554 def LDriub_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
555 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
557 "if (!$src1.new) $dst=memub($src2+$src3<<#$offset)",
561 // Rd=memb(Rt<<#u2+#U6)
566 // Rd=memh(Rs+Rt<<#u2)
567 let AddedComplexity = 10, isPredicable = 1 in
568 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
569 (ins IntRegs:$src1, IntRegs:$src2),
570 "$dst=memh($src1+$src2<<#0)",
571 [(set IntRegs:$dst, (sextloadi16 (add IntRegs:$src1,
575 let AddedComplexity = 10, isPredicable = 1 in
576 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
577 (ins IntRegs:$src1, IntRegs:$src2),
578 "$dst=memuh($src1+$src2<<#0)",
579 [(set IntRegs:$dst, (zextloadi16 (add IntRegs:$src1,
583 let AddedComplexity = 10, isPredicable = 1 in
584 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
585 (ins IntRegs:$src1, IntRegs:$src2),
586 "$dst=memuh($src1+$src2<<#0)",
587 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
591 // Rd=memh(Rs+Rt<<#u2)
592 let AddedComplexity = 40, isPredicable = 1 in
593 def LDrih_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
594 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
595 "$dst=memh($src1+$src2<<#$offset)",
597 (sextloadi16 (add IntRegs:$src1,
599 u2ImmPred:$offset))))]>,
602 let AddedComplexity = 40, isPredicable = 1 in
603 def LDriuh_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
604 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
605 "$dst=memuh($src1+$src2<<#$offset)",
607 (zextloadi16 (add IntRegs:$src1,
609 u2ImmPred:$offset))))]>,
612 let AddedComplexity = 40, isPredicable = 1 in
613 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
614 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
615 "$dst=memuh($src1+$src2<<#$offset)",
617 (extloadi16 (add IntRegs:$src1,
619 u2ImmPred:$offset))))]>,
622 //// Load halfword conditionally.
623 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
624 // if (Pv) Rd=memh(Rs+Rt<<#u2)
625 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
626 def LDrih_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
627 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
628 "if ($src1) $dst=memh($src2+$src3<<#0)",
632 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
633 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
634 def LDrih_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
635 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
636 "if ($src1.new) $dst=memh($src2+$src3<<#0)",
640 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
641 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
642 def LDrih_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
643 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
644 "if (!$src1) $dst=memh($src2+$src3<<#0)",
648 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
649 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
650 def LDrih_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
651 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
652 "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
656 // if (Pv) Rd=memh(Rs+Rt<<#u2)
657 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
658 def LDrih_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
659 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
661 "if ($src1) $dst=memh($src2+$src3<<#$offset)",
665 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
666 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
667 def LDrih_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
668 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
670 "if ($src1.new) $dst=memh($src2+$src3<<#$offset)",
674 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
675 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
676 def LDrih_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
677 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
679 "if (!$src1) $dst=memh($src2+$src3<<#$offset)",
683 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
684 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
685 def LDrih_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
686 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
688 "if (!$src1.new) $dst=memh($src2+$src3<<#$offset)",
692 //// Load unsigned halfword conditionally.
693 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
694 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
695 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
696 def LDriuh_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
697 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
698 "if ($src1) $dst=memuh($src2+$src3<<#0)",
702 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
703 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
704 def LDriuh_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
705 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
706 "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
710 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
711 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
712 def LDriuh_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
713 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
714 "if (!$src1) $dst=memuh($src2+$src3<<#0)",
718 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
719 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
720 def LDriuh_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
721 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
722 "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
726 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
727 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
728 def LDriuh_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
729 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
731 "if ($src1) $dst=memuh($src2+$src3<<#$offset)",
735 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
736 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
737 def LDriuh_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
738 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
740 "if ($src1.new) $dst=memuh($src2+$src3<<#$offset)",
744 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
745 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
746 def LDriuh_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
747 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
749 "if (!$src1) $dst=memuh($src2+$src3<<#$offset)",
753 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
754 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
755 def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
756 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
758 "if (!$src1.new) $dst=memuh($src2+$src3<<#$offset)",
762 // Rd=memh(Rt<<#u2+#U6)
767 // Rd=memw(Rs+Rt<<#u2)
768 let AddedComplexity = 10, isPredicable = 1 in
769 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
770 (ins IntRegs:$src1, IntRegs:$src2),
771 "$dst=memw($src1+$src2<<#0)",
772 [(set IntRegs:$dst, (load (add IntRegs:$src1,
776 // Rd=memw(Rs+Rt<<#u2)
777 let AddedComplexity = 40, isPredicable = 1 in
778 def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
779 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
780 "$dst=memw($src1+$src2<<#$offset)",
781 [(set IntRegs:$dst, (load (add IntRegs:$src1,
783 u2ImmPred:$offset))))]>,
786 //// Load word conditionally.
787 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
788 // if (Pv) Rd=memw(Rs+Rt<<#u2)
789 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
790 def LDriw_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
791 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
792 "if ($src1) $dst=memw($src2+$src3<<#0)",
796 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
797 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
798 def LDriw_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
799 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
800 "if ($src1.new) $dst=memw($src2+$src3<<#0)",
804 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
805 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
806 def LDriw_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
807 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
808 "if (!$src1) $dst=memw($src2+$src3<<#0)",
812 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
813 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
814 def LDriw_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
815 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
816 "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
820 // if (Pv) Rd=memh(Rs+Rt<<#u2)
821 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
822 def LDriw_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
823 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
825 "if ($src1) $dst=memw($src2+$src3<<#$offset)",
829 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
830 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
831 def LDriw_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
832 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
834 "if ($src1.new) $dst=memw($src2+$src3<<#$offset)",
838 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
839 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
840 def LDriw_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
841 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
843 "if (!$src1) $dst=memw($src2+$src3<<#$offset)",
847 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
848 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
849 def LDriw_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
850 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
852 "if (!$src1.new) $dst=memw($src2+$src3<<#$offset)",
856 // Rd=memw(Rt<<#u2+#U6)
859 // Post-inc Load, Predicated, Dot new
862 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
863 def POST_LDrid_cdnPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
864 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
865 "if ($src1.new) $dst1 = memd($src2++#$src3)",
870 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
871 def POST_LDrid_cdnNotPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
872 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
873 "if (!$src1.new) $dst1 = memd($src2++#$src3)",
878 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
879 def POST_LDrib_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
880 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
881 "if ($src1.new) $dst1 = memb($src2++#$src3)",
886 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
887 def POST_LDrib_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
888 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
889 "if (!$src1.new) $dst1 = memb($src2++#$src3)",
894 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
895 def POST_LDrih_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
896 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
897 "if ($src1.new) $dst1 = memh($src2++#$src3)",
902 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
903 def POST_LDrih_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
904 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
905 "if (!$src1.new) $dst1 = memh($src2++#$src3)",
910 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
911 def POST_LDriub_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
912 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
913 "if ($src1.new) $dst1 = memub($src2++#$src3)",
918 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
919 def POST_LDriub_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
920 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
921 "if (!$src1.new) $dst1 = memub($src2++#$src3)",
926 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
927 def POST_LDriuh_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
928 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
929 "if ($src1.new) $dst1 = memuh($src2++#$src3)",
934 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
935 def POST_LDriuh_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
936 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
937 "if (!$src1.new) $dst1 = memuh($src2++#$src3)",
942 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
943 def POST_LDriw_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
944 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
945 "if ($src1.new) $dst1 = memw($src2++#$src3)",
950 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
951 def POST_LDriw_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
952 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
953 "if (!$src1.new) $dst1 = memw($src2++#$src3)",
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
963 //===----------------------------------------------------------------------===//
965 //===----------------------------------------------------------------------===//
967 /// Assumptions::: ****** DO NOT IGNORE ********
968 /// 1. Make sure that in post increment store, the zero'th operand is always the
969 /// post increment operand.
970 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
976 // TODO: needs to be implemented
978 // memd(Rs+#s11:3)=Rtt
979 // memd(Rs+Ru<<#u2)=Rtt
980 let AddedComplexity = 10, isPredicable = 1 in
981 def STrid_indexed_shl_V4 : STInst<(outs),
982 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),
983 "memd($src1+$src2<<#$src3) = $src4",
984 [(store DoubleRegs:$src4, (add IntRegs:$src1,
985 (shl IntRegs:$src2, u2ImmPred:$src3)))]>,
988 // memd(Ru<<#u2+#U6)=Rtt
989 let AddedComplexity = 10 in
990 def STrid_shl_V4 : STInst<(outs),
991 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
992 "memd($src1<<#$src2+#$src3) = $src4",
993 [(store DoubleRegs:$src4, (shl IntRegs:$src1,
994 (add u2ImmPred:$src2,
995 u6ImmPred:$src3)))]>,
998 // memd(Rx++#s4:3)=Rtt
999 // memd(Rx++#s4:3:circ(Mu))=Rtt
1000 // memd(Rx++I:circ(Mu))=Rtt
1002 // memd(Rx++Mu:brev)=Rtt
1003 // memd(gp+#u16:3)=Rtt
1005 // Store doubleword conditionally.
1006 // if ([!]Pv[.new]) memd(#u6)=Rtt
1007 // TODO: needs to be implemented.
1009 // if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt
1010 // if (Pv) memd(Rs+#u6:3)=Rtt
1011 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1012 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1013 def STrid_cdnPt_V4 : STInst<(outs),
1014 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1015 "if ($src1.new) memd($addr) = $src2",
1019 // if (!Pv) memd(Rs+#u6:3)=Rtt
1020 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1021 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1022 def STrid_cdnNotPt_V4 : STInst<(outs),
1023 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1024 "if (!$src1.new) memd($addr) = $src2",
1028 // if (Pv) memd(Rs+#u6:3)=Rtt
1029 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1030 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1031 def STrid_indexed_cdnPt_V4 : STInst<(outs),
1032 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1034 "if ($src1.new) memd($src2+#$src3) = $src4",
1038 // if (!Pv) memd(Rs+#u6:3)=Rtt
1039 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1040 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1041 def STrid_indexed_cdnNotPt_V4 : STInst<(outs),
1042 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1044 "if (!$src1.new) memd($src2+#$src3) = $src4",
1048 // if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt
1049 // if (Pv) memd(Rs+Ru<<#u2)=Rtt
1050 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1051 def STrid_indexed_shl_cPt_V4 : STInst<(outs),
1052 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1054 "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1058 // if (Pv.new) memd(Rs+Ru<<#u2)=Rtt
1059 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1060 def STrid_indexed_shl_cdnPt_V4 : STInst<(outs),
1061 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1063 "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1066 // if (!Pv) memd(Rs+Ru<<#u2)=Rtt
1067 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1068 def STrid_indexed_shl_cNotPt_V4 : STInst<(outs),
1069 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1071 "if (!$src1) memd($src2+$src3<<#$src4) = $src5",
1074 // if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt
1075 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1076 def STrid_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1077 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1079 "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",
1083 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1084 // if (Pv) memd(Rx++#s4:3)=Rtt
1085 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1086 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1087 def POST_STdri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1088 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1090 "if ($src1.new) memd($src3++#$offset) = $src2",
1095 // if (!Pv) memd(Rx++#s4:3)=Rtt
1096 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1097 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1098 def POST_STdri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1099 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1101 "if (!$src1.new) memd($src3++#$offset) = $src2",
1109 // TODO: needs to be implemented.
1110 // memb(Rs+#s11:0)=Rt
1111 // memb(Rs+#u6:0)=#S8
1112 let AddedComplexity = 10, isPredicable = 1 in
1113 def STrib_imm_V4 : STInst<(outs),
1114 (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
1115 "memb($src1+#$src2) = #$src3",
1116 [(truncstorei8 s8ImmPred:$src3, (add IntRegs:$src1,
1117 u6_0ImmPred:$src2))]>,
1120 // memb(Rs+Ru<<#u2)=Rt
1121 let AddedComplexity = 10, isPredicable = 1 in
1122 def STrib_indexed_shl_V4 : STInst<(outs),
1123 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1124 "memb($src1+$src2<<#$src3) = $src4",
1125 [(truncstorei8 IntRegs:$src4, (add IntRegs:$src1,
1127 u2ImmPred:$src3)))]>,
1130 // memb(Ru<<#u2+#U6)=Rt
1131 let AddedComplexity = 10 in
1132 def STrib_shl_V4 : STInst<(outs),
1133 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1134 "memb($src1<<#$src2+#$src3) = $src4",
1135 [(truncstorei8 IntRegs:$src4, (shl IntRegs:$src1,
1136 (add u2ImmPred:$src2,
1137 u6ImmPred:$src3)))]>,
1140 // memb(Rx++#s4:0:circ(Mu))=Rt
1141 // memb(Rx++I:circ(Mu))=Rt
1143 // memb(Rx++Mu:brev)=Rt
1144 // memb(gp+#u16:0)=Rt
1147 // Store byte conditionally.
1148 // if ([!]Pv[.new]) memb(#u6)=Rt
1149 // if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6
1150 // if (Pv) memb(Rs+#u6:0)=#S6
1151 let mayStore = 1, neverHasSideEffects = 1 in
1152 def STrib_imm_cPt_V4 : STInst<(outs),
1153 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1154 "if ($src1) memb($src2+#$src3) = #$src4",
1158 // if (Pv.new) memb(Rs+#u6:0)=#S6
1159 let mayStore = 1, neverHasSideEffects = 1 in
1160 def STrib_imm_cdnPt_V4 : STInst<(outs),
1161 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1162 "if ($src1.new) memb($src2+#$src3) = #$src4",
1166 // if (!Pv) memb(Rs+#u6:0)=#S6
1167 let mayStore = 1, neverHasSideEffects = 1 in
1168 def STrib_imm_cNotPt_V4 : STInst<(outs),
1169 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1170 "if (!$src1) memb($src2+#$src3) = #$src4",
1174 // if (!Pv.new) memb(Rs+#u6:0)=#S6
1175 let mayStore = 1, neverHasSideEffects = 1 in
1176 def STrib_imm_cdnNotPt_V4 : STInst<(outs),
1177 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1178 "if (!$src1.new) memb($src2+#$src3) = #$src4",
1182 // if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt
1183 // if (Pv) memb(Rs+#u6:0)=Rt
1184 // if (Pv.new) memb(Rs+#u6:0)=Rt
1185 let mayStore = 1, neverHasSideEffects = 1 in
1186 def STrib_cdnPt_V4 : STInst<(outs),
1187 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1188 "if ($src1.new) memb($addr) = $src2",
1192 // if (!Pv) memb(Rs+#u6:0)=Rt
1193 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1194 let mayStore = 1, neverHasSideEffects = 1 in
1195 def STrib_cdnNotPt_V4 : STInst<(outs),
1196 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1197 "if (!$src1.new) memb($addr) = $src2",
1201 // if (Pv) memb(Rs+#u6:0)=Rt
1202 // if (!Pv) memb(Rs+#u6:0)=Rt
1203 // if (Pv.new) memb(Rs+#u6:0)=Rt
1204 let mayStore = 1, neverHasSideEffects = 1 in
1205 def STrib_indexed_cdnPt_V4 : STInst<(outs),
1206 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1207 "if ($src1.new) memb($src2+#$src3) = $src4",
1211 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1212 let mayStore = 1, neverHasSideEffects = 1 in
1213 def STrib_indexed_cdnNotPt_V4 : STInst<(outs),
1214 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1215 "if (!$src1.new) memb($src2+#$src3) = $src4",
1219 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt
1220 // if (Pv) memb(Rs+Ru<<#u2)=Rt
1221 let mayStore = 1, AddedComplexity = 10 in
1222 def STrib_indexed_shl_cPt_V4 : STInst<(outs),
1223 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1225 "if ($src1) memb($src2+$src3<<#$src4) = $src5",
1229 // if (Pv.new) memb(Rs+Ru<<#u2)=Rt
1230 let mayStore = 1, AddedComplexity = 10 in
1231 def STrib_indexed_shl_cdnPt_V4 : STInst<(outs),
1232 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1234 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5",
1238 // if (!Pv) memb(Rs+Ru<<#u2)=Rt
1239 let mayStore = 1, AddedComplexity = 10 in
1240 def STrib_indexed_shl_cNotPt_V4 : STInst<(outs),
1241 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1243 "if (!$src1) memb($src2+$src3<<#$src4) = $src5",
1247 // if (!Pv.new) memb(Rs+Ru<<#u2)=Rt
1248 let mayStore = 1, AddedComplexity = 10 in
1249 def STrib_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1250 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1252 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5",
1256 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1257 // if (Pv) memb(Rx++#s4:0)=Rt
1258 // if (Pv.new) memb(Rx++#s4:0)=Rt
1259 let mayStore = 1, hasCtrlDep = 1 in
1260 def POST_STbri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1261 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1262 "if ($src1.new) memb($src3++#$offset) = $src2",
1266 // if (!Pv) memb(Rx++#s4:0)=Rt
1267 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1268 let mayStore = 1, hasCtrlDep = 1 in
1269 def POST_STbri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1270 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1271 "if (!$src1.new) memb($src3++#$offset) = $src2",
1277 // memh(Re=#U6)=Rt.H
1278 // TODO: needs to be implemented
1281 // TODO: needs to be implemented
1283 // memh(Rs+#s11:1)=Rt.H
1284 // memh(Rs+#s11:1)=Rt
1285 // memh(Rs+#u6:1)=#S8
1286 let AddedComplexity = 10, isPredicable = 1 in
1287 def STrih_imm_V4 : STInst<(outs),
1288 (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
1289 "memh($src1+#$src2) = #$src3",
1290 [(truncstorei16 s8ImmPred:$src3, (add IntRegs:$src1,
1291 u6_1ImmPred:$src2))]>,
1294 // memh(Rs+Ru<<#u2)=Rt.H
1295 // TODO: needs to be implemented.
1297 // memh(Rs+Ru<<#u2)=Rt
1298 let AddedComplexity = 10, isPredicable = 1 in
1299 def STrih_indexed_shl_V4 : STInst<(outs),
1300 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1301 "memh($src1+$src2<<#$src3) = $src4",
1302 [(truncstorei16 IntRegs:$src4, (add IntRegs:$src1,
1304 u2ImmPred:$src3)))]>,
1307 // memh(Ru<<#u2+#U6)=Rt.H
1308 // memh(Ru<<#u2+#U6)=Rt
1309 let AddedComplexity = 10 in
1310 def STrih_shl_V4 : STInst<(outs),
1311 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1312 "memh($src1<<#$src2+#$src3) = $src4",
1313 [(truncstorei16 IntRegs:$src4, (shl IntRegs:$src1,
1314 (add u2ImmPred:$src2,
1315 u6ImmPred:$src3)))]>,
1318 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1319 // memh(Rx++#s4:1:circ(Mu))=Rt
1320 // memh(Rx++I:circ(Mu))=Rt.H
1321 // memh(Rx++I:circ(Mu))=Rt
1322 // memh(Rx++Mu)=Rt.H
1324 // memh(Rx++Mu:brev)=Rt.H
1325 // memh(Rx++Mu:brev)=Rt
1326 // memh(gp+#u16:1)=Rt.H
1327 // memh(gp+#u16:1)=Rt
1330 // Store halfword conditionally.
1331 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1332 // if ([!]Pv[.new]) memh(#u6)=Rt
1334 // if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6
1335 // if (Pv) memh(Rs+#u6:1)=#S6
1336 let mayStore = 1, neverHasSideEffects = 1 in
1337 def STrih_imm_cPt_V4 : STInst<(outs),
1338 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1339 "if ($src1) memh($src2+#$src3) = #$src4",
1343 // if (Pv.new) memh(Rs+#u6:1)=#S6
1344 let mayStore = 1, neverHasSideEffects = 1 in
1345 def STrih_imm_cdnPt_V4 : STInst<(outs),
1346 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1347 "if ($src1.new) memh($src2+#$src3) = #$src4",
1351 // if (!Pv) memh(Rs+#u6:1)=#S6
1352 let mayStore = 1, neverHasSideEffects = 1 in
1353 def STrih_imm_cNotPt_V4 : STInst<(outs),
1354 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1355 "if (!$src1) memh($src2+#$src3) = #$src4",
1359 // if (!Pv.new) memh(Rs+#u6:1)=#S6
1360 let mayStore = 1, neverHasSideEffects = 1 in
1361 def STrih_imm_cdnNotPt_V4 : STInst<(outs),
1362 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1363 "if (!$src1.new) memh($src2+#$src3) = #$src4",
1367 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1368 // TODO: needs to be implemented.
1370 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt
1371 // if (Pv) memh(Rs+#u6:1)=Rt
1372 // if (Pv.new) memh(Rs+#u6:1)=Rt
1373 let mayStore = 1, neverHasSideEffects = 1 in
1374 def STrih_cdnPt_V4 : STInst<(outs),
1375 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1376 "if ($src1.new) memh($addr) = $src2",
1380 // if (!Pv) memh(Rs+#u6:1)=Rt
1381 // if (!Pv.new) memh(Rs+#u6:1)=Rt
1382 let mayStore = 1, neverHasSideEffects = 1 in
1383 def STrih_cdnNotPt_V4 : STInst<(outs),
1384 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1385 "if (!$src1.new) memh($addr) = $src2",
1389 // if (Pv.new) memh(Rs+#u6:1)=Rt
1390 let mayStore = 1, neverHasSideEffects = 1 in
1391 def STrih_indexed_cdnPt_V4 : STInst<(outs),
1392 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1393 "if ($src1.new) memh($src2+#$src3) = $src4",
1397 // if (!Pv.new) memh(Rs+#u6:1)=Rt
1398 let mayStore = 1, neverHasSideEffects = 1 in
1399 def STrih_indexed_cdnNotPt_V4 : STInst<(outs),
1400 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1401 "if (!$src1.new) memh($src2+#$src3) = $src4",
1405 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H
1406 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt
1407 // if (Pv) memh(Rs+Ru<<#u2)=Rt
1408 let mayStore = 1, AddedComplexity = 10 in
1409 def STrih_indexed_shl_cPt_V4 : STInst<(outs),
1410 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1412 "if ($src1) memh($src2+$src3<<#$src4) = $src5",
1416 // if (Pv.new) memh(Rs+Ru<<#u2)=Rt
1417 def STrih_indexed_shl_cdnPt_V4 : STInst<(outs),
1418 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1420 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5",
1424 // if (!Pv) memh(Rs+Ru<<#u2)=Rt
1425 let mayStore = 1, AddedComplexity = 10 in
1426 def STrih_indexed_shl_cNotPt_V4 : STInst<(outs),
1427 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1429 "if (!$src1) memh($src2+$src3<<#$src4) = $src5",
1433 // if (!Pv.new) memh(Rs+Ru<<#u2)=Rt
1434 let mayStore = 1, AddedComplexity = 10 in
1435 def STrih_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1436 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1438 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5",
1442 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1443 // TODO: Needs to be implemented.
1445 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1446 // if (Pv) memh(Rx++#s4:1)=Rt
1447 // if (Pv.new) memh(Rx++#s4:1)=Rt
1448 let mayStore = 1, hasCtrlDep = 1 in
1449 def POST_SThri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1450 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1451 "if ($src1.new) memh($src3++#$offset) = $src2",
1455 // if (!Pv) memh(Rx++#s4:1)=Rt
1456 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1457 let mayStore = 1, hasCtrlDep = 1 in
1458 def POST_SThri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1459 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1460 "if (!$src1.new) memh($src3++#$offset) = $src2",
1467 // TODO: Needs to be implemented.
1469 // memw(Rs+#s11:2)=Rt
1470 // memw(Rs+#u6:2)=#S8
1471 let AddedComplexity = 10, isPredicable = 1 in
1472 def STriw_imm_V4 : STInst<(outs),
1473 (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
1474 "memw($src1+#$src2) = #$src3",
1475 [(store s8ImmPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
1478 // memw(Rs+Ru<<#u2)=Rt
1479 let AddedComplexity = 10, isPredicable = 1 in
1480 def STriw_indexed_shl_V4 : STInst<(outs),
1481 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1482 "memw($src1+$src2<<#$src3) = $src4",
1483 [(store IntRegs:$src4, (add IntRegs:$src1,
1484 (shl IntRegs:$src2, u2ImmPred:$src3)))]>,
1487 // memw(Ru<<#u2+#U6)=Rt
1488 let AddedComplexity = 10 in
1489 def STriw_shl_V4 : STInst<(outs),
1490 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1491 "memw($src1<<#$src2+#$src3) = $src4",
1492 [(store IntRegs:$src4, (shl IntRegs:$src1,
1493 (add u2ImmPred:$src2, u6ImmPred:$src3)))]>,
1496 // memw(Rx++#s4:2)=Rt
1497 // memw(Rx++#s4:2:circ(Mu))=Rt
1498 // memw(Rx++I:circ(Mu))=Rt
1500 // memw(Rx++Mu:brev)=Rt
1501 // memw(gp+#u16:2)=Rt
1504 // Store word conditionally.
1505 // if ([!]Pv[.new]) memw(#u6)=Rt
1506 // TODO: Needs to be implemented.
1508 // if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6
1509 // if (Pv) memw(Rs+#u6:2)=#S6
1510 let mayStore = 1, neverHasSideEffects = 1 in
1511 def STriw_imm_cPt_V4 : STInst<(outs),
1512 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1513 "if ($src1) memw($src2+#$src3) = #$src4",
1517 // if (Pv.new) memw(Rs+#u6:2)=#S6
1518 let mayStore = 1, neverHasSideEffects = 1 in
1519 def STriw_imm_cdnPt_V4 : STInst<(outs),
1520 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1521 "if ($src1.new) memw($src2+#$src3) = #$src4",
1525 // if (!Pv) memw(Rs+#u6:2)=#S6
1526 let mayStore = 1, neverHasSideEffects = 1 in
1527 def STriw_imm_cNotPt_V4 : STInst<(outs),
1528 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1529 "if (!$src1) memw($src2+#$src3) = #$src4",
1533 // if (!Pv.new) memw(Rs+#u6:2)=#S6
1534 let mayStore = 1, neverHasSideEffects = 1 in
1535 def STriw_imm_cdnNotPt_V4 : STInst<(outs),
1536 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1537 "if (!$src1.new) memw($src2+#$src3) = #$src4",
1541 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt
1542 // if (Pv) memw(Rs+#u6:2)=Rt
1543 // if (Pv.new) memw(Rs+#u6:2)=Rt
1544 let mayStore = 1, neverHasSideEffects = 1 in
1545 def STriw_cdnPt_V4 : STInst<(outs),
1546 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1547 "if ($src1.new) memw($addr) = $src2",
1551 // if (!Pv) memw(Rs+#u6:2)=Rt
1552 // if (!Pv.new) memw(Rs+#u6:2)=Rt
1553 let mayStore = 1, neverHasSideEffects = 1 in
1554 def STriw_cdnNotPt_V4 : STInst<(outs),
1555 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1556 "if (!$src1.new) memw($addr) = $src2",
1560 // if (Pv) memw(Rs+#u6:2)=Rt
1561 // if (!Pv) memw(Rs+#u6:2)=Rt
1562 // if (Pv.new) memw(Rs+#u6:2)=Rt
1563 let mayStore = 1, neverHasSideEffects = 1 in
1564 def STriw_indexed_cdnPt_V4 : STInst<(outs),
1565 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
1566 "if ($src1.new) memw($src2+#$src3) = $src4",
1570 // if (!Pv.new) memw(Rs+#u6:2)=Rt
1571 let mayStore = 1, neverHasSideEffects = 1 in
1572 def STriw_indexed_cdnNotPt_V4 : STInst<(outs),
1573 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
1574 "if (!$src1.new) memw($src2+#$src3) = $src4",
1578 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt
1579 // if (Pv) memw(Rs+Ru<<#u2)=Rt
1580 let mayStore = 1, AddedComplexity = 10 in
1581 def STriw_indexed_shl_cPt_V4 : STInst<(outs),
1582 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1584 "if ($src1) memw($src2+$src3<<#$src4) = $src5",
1588 // if (Pv.new) memw(Rs+Ru<<#u2)=Rt
1589 let mayStore = 1, AddedComplexity = 10 in
1590 def STriw_indexed_shl_cdnPt_V4 : STInst<(outs),
1591 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1593 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5",
1597 // if (!Pv) memw(Rs+Ru<<#u2)=Rt
1598 let mayStore = 1, AddedComplexity = 10 in
1599 def STriw_indexed_shl_cNotPt_V4 : STInst<(outs),
1600 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1602 "if (!$src1) memw($src2+$src3<<#$src4) = $src5",
1606 // if (!Pv.new) memw(Rs+Ru<<#u2)=Rt
1607 let mayStore = 1, AddedComplexity = 10 in
1608 def STriw_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1609 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1611 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5",
1615 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
1616 // if (Pv) memw(Rx++#s4:2)=Rt
1617 // if (Pv.new) memw(Rx++#s4:2)=Rt
1618 let mayStore = 1, hasCtrlDep = 1 in
1619 def POST_STwri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1620 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1621 "if ($src1.new) memw($src3++#$offset) = $src2",
1625 // if (!Pv) memw(Rx++#s4:2)=Rt
1626 // if (!Pv.new) memw(Rx++#s4:2)=Rt
1627 let mayStore = 1, hasCtrlDep = 1 in
1628 def POST_STwri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1629 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1630 "if (!$src1.new) memw($src3++#$offset) = $src2",
1635 //===----------------------------------------------------------------------===
1637 //===----------------------------------------------------------------------===
1640 //===----------------------------------------------------------------------===//
1642 //===----------------------------------------------------------------------===//
1644 // Store new-value byte.
1646 // memb(Re=#U6)=Nt.new
1647 // memb(Rs+#s11:0)=Nt.new
1648 let mayStore = 1, isPredicable = 1 in
1649 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
1650 "memb($addr) = $src1.new",
1654 let mayStore = 1, isPredicable = 1 in
1655 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
1656 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1657 "memb($src1+#$src2) = $src3.new",
1661 // memb(Rs+Ru<<#u2)=Nt.new
1662 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
1663 def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs),
1664 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1665 "memb($src1+$src2<<#$src3) = $src4.new",
1669 // memb(Ru<<#u2+#U6)=Nt.new
1670 let mayStore = 1, AddedComplexity = 10 in
1671 def STrib_shl_nv_V4 : NVInst_V4<(outs),
1672 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1673 "memb($src1<<#$src2+#$src3) = $src4.new",
1677 // memb(Rx++#s4:0)=Nt.new
1678 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
1679 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1680 (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
1681 "memb($src2++#$offset) = $src1.new",
1686 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1687 // memb(Rx++I:circ(Mu))=Nt.new
1688 // memb(Rx++Mu)=Nt.new
1689 // memb(Rx++Mu:brev)=Nt.new
1691 // memb(gp+#u16:0)=Nt.new
1692 let mayStore = 1, neverHasSideEffects = 1 in
1693 def STrib_GP_nv_V4 : NVInst_V4<(outs),
1694 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1695 "memb(#$global+$offset) = $src.new",
1700 // Store new-value byte conditionally.
1701 // if ([!]Pv[.new]) memb(#u6)=Nt.new
1702 // if (Pv) memb(Rs+#u6:0)=Nt.new
1703 let mayStore = 1, neverHasSideEffects = 1 in
1704 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
1705 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1706 "if ($src1) memb($addr) = $src2.new",
1710 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
1711 let mayStore = 1, neverHasSideEffects = 1 in
1712 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
1713 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1714 "if ($src1.new) memb($addr) = $src2.new",
1718 // if (!Pv) memb(Rs+#u6:0)=Nt.new
1719 let mayStore = 1, neverHasSideEffects = 1 in
1720 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
1721 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1722 "if (!$src1) memb($addr) = $src2.new",
1726 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
1727 let mayStore = 1, neverHasSideEffects = 1 in
1728 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1729 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1730 "if (!$src1.new) memb($addr) = $src2.new",
1734 // if (Pv) memb(Rs+#u6:0)=Nt.new
1735 let mayStore = 1, neverHasSideEffects = 1 in
1736 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
1737 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1738 "if ($src1) memb($src2+#$src3) = $src4.new",
1742 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
1743 let mayStore = 1, neverHasSideEffects = 1 in
1744 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
1745 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1746 "if ($src1.new) memb($src2+#$src3) = $src4.new",
1750 // if (!Pv) memb(Rs+#u6:0)=Nt.new
1751 let mayStore = 1, neverHasSideEffects = 1 in
1752 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
1753 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1754 "if (!$src1) memb($src2+#$src3) = $src4.new",
1758 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
1759 let mayStore = 1, neverHasSideEffects = 1 in
1760 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1761 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1762 "if (!$src1.new) memb($src2+#$src3) = $src4.new",
1767 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new
1768 // if (Pv) memb(Rs+Ru<<#u2)=Nt.new
1769 let mayStore = 1, AddedComplexity = 10 in
1770 def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
1771 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1773 "if ($src1) memb($src2+$src3<<#$src4) = $src5.new",
1777 // if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new
1778 let mayStore = 1, AddedComplexity = 10 in
1779 def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
1780 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1782 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5.new",
1786 // if (!Pv) memb(Rs+Ru<<#u2)=Nt.new
1787 let mayStore = 1, AddedComplexity = 10 in
1788 def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
1789 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1791 "if (!$src1) memb($src2+$src3<<#$src4) = $src5.new",
1795 // if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new
1796 let mayStore = 1, AddedComplexity = 10 in
1797 def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1798 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1800 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5.new",
1804 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
1805 // if (Pv) memb(Rx++#s4:0)=Nt.new
1806 let mayStore = 1, hasCtrlDep = 1 in
1807 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1808 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1809 "if ($src1) memb($src3++#$offset) = $src2.new",
1813 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
1814 let mayStore = 1, hasCtrlDep = 1 in
1815 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1816 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1817 "if ($src1.new) memb($src3++#$offset) = $src2.new",
1821 // if (!Pv) memb(Rx++#s4:0)=Nt.new
1822 let mayStore = 1, hasCtrlDep = 1 in
1823 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1824 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1825 "if (!$src1) memb($src3++#$offset) = $src2.new",
1829 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
1830 let mayStore = 1, hasCtrlDep = 1 in
1831 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1832 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1833 "if (!$src1.new) memb($src3++#$offset) = $src2.new",
1838 // Store new-value halfword.
1839 // memh(Re=#U6)=Nt.new
1840 // memh(Rs+#s11:1)=Nt.new
1841 let mayStore = 1, isPredicable = 1 in
1842 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
1843 "memh($addr) = $src1.new",
1847 let mayStore = 1, isPredicable = 1 in
1848 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
1849 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1850 "memh($src1+#$src2) = $src3.new",
1854 // memh(Rs+Ru<<#u2)=Nt.new
1855 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
1856 def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs),
1857 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1858 "memh($src1+$src2<<#$src3) = $src4.new",
1862 // memh(Ru<<#u2+#U6)=Nt.new
1863 let mayStore = 1, AddedComplexity = 10 in
1864 def STrih_shl_nv_V4 : NVInst_V4<(outs),
1865 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1866 "memh($src1<<#$src2+#$src3) = $src4.new",
1870 // memh(Rx++#s4:1)=Nt.new
1871 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
1872 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1873 (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
1874 "memh($src2++#$offset) = $src1.new",
1879 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1880 // memh(Rx++I:circ(Mu))=Nt.new
1881 // memh(Rx++Mu)=Nt.new
1882 // memh(Rx++Mu:brev)=Nt.new
1884 // memh(gp+#u16:1)=Nt.new
1885 let mayStore = 1, neverHasSideEffects = 1 in
1886 def STrih_GP_nv_V4 : NVInst_V4<(outs),
1887 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1888 "memh(#$global+$offset) = $src.new",
1893 // Store new-value halfword conditionally.
1895 // if ([!]Pv[.new]) memh(#u6)=Nt.new
1897 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
1898 // if (Pv) memh(Rs+#u6:1)=Nt.new
1899 let mayStore = 1, neverHasSideEffects = 1 in
1900 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
1901 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1902 "if ($src1) memh($addr) = $src2.new",
1906 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
1907 let mayStore = 1, neverHasSideEffects = 1 in
1908 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
1909 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1910 "if ($src1.new) memh($addr) = $src2.new",
1914 // if (!Pv) memh(Rs+#u6:1)=Nt.new
1915 let mayStore = 1, neverHasSideEffects = 1 in
1916 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
1917 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1918 "if (!$src1) memh($addr) = $src2.new",
1922 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
1923 let mayStore = 1, neverHasSideEffects = 1 in
1924 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1925 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1926 "if (!$src1.new) memh($addr) = $src2.new",
1930 // if (Pv) memh(Rs+#u6:1)=Nt.new
1931 let mayStore = 1, neverHasSideEffects = 1 in
1932 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
1933 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1934 "if ($src1) memh($src2+#$src3) = $src4.new",
1938 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
1939 let mayStore = 1, neverHasSideEffects = 1 in
1940 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
1941 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1942 "if ($src1.new) memh($src2+#$src3) = $src4.new",
1946 // if (!Pv) memh(Rs+#u6:1)=Nt.new
1947 let mayStore = 1, neverHasSideEffects = 1 in
1948 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
1949 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1950 "if (!$src1) memh($src2+#$src3) = $src4.new",
1954 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
1955 let mayStore = 1, neverHasSideEffects = 1 in
1956 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1957 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1958 "if (!$src1.new) memh($src2+#$src3) = $src4.new",
1962 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new
1963 // if (Pv) memh(Rs+Ru<<#u2)=Nt.new
1964 let mayStore = 1, AddedComplexity = 10 in
1965 def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
1966 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1968 "if ($src1) memh($src2+$src3<<#$src4) = $src5.new",
1972 // if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new
1973 let mayStore = 1, AddedComplexity = 10 in
1974 def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
1975 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1977 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5.new",
1981 // if (!Pv) memh(Rs+Ru<<#u2)=Nt.new
1982 let mayStore = 1, AddedComplexity = 10 in
1983 def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
1984 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1986 "if (!$src1) memh($src2+$src3<<#$src4) = $src5.new",
1990 // if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new
1991 let mayStore = 1, AddedComplexity = 10 in
1992 def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1993 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1995 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5.new",
1999 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2000 // if (Pv) memh(Rx++#s4:1)=Nt.new
2001 let mayStore = 1, hasCtrlDep = 1 in
2002 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2003 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2004 "if ($src1) memh($src3++#$offset) = $src2.new",
2008 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2009 let mayStore = 1, hasCtrlDep = 1 in
2010 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2011 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2012 "if ($src1.new) memh($src3++#$offset) = $src2.new",
2016 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2017 let mayStore = 1, hasCtrlDep = 1 in
2018 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2019 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2020 "if (!$src1) memh($src3++#$offset) = $src2.new",
2024 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2025 let mayStore = 1, hasCtrlDep = 1 in
2026 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2027 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2028 "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2033 // Store new-value word.
2035 // memw(Re=#U6)=Nt.new
2036 // memw(Rs+#s11:2)=Nt.new
2037 let mayStore = 1, isPredicable = 1 in
2038 def STriw_nv_V4 : NVInst_V4<(outs),
2039 (ins MEMri:$addr, IntRegs:$src1),
2040 "memw($addr) = $src1.new",
2044 let mayStore = 1, isPredicable = 1 in
2045 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
2046 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2047 "memw($src1+#$src2) = $src3.new",
2051 // memw(Rs+Ru<<#u2)=Nt.new
2052 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2053 def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs),
2054 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2055 "memw($src1+$src2<<#$src3) = $src4.new",
2059 // memw(Ru<<#u2+#U6)=Nt.new
2060 let mayStore = 1, AddedComplexity = 10 in
2061 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2062 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2063 "memw($src1<<#$src2+#$src3) = $src4.new",
2067 // memw(Rx++#s4:2)=Nt.new
2068 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
2069 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2070 (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
2071 "memw($src2++#$offset) = $src1.new",
2076 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2077 // memw(Rx++I:circ(Mu))=Nt.new
2078 // memw(Rx++Mu)=Nt.new
2079 // memw(Rx++Mu:brev)=Nt.new
2080 // memw(gp+#u16:2)=Nt.new
2081 let mayStore = 1, neverHasSideEffects = 1 in
2082 def STriw_GP_nv_V4 : NVInst_V4<(outs),
2083 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2084 "memw(#$global+$offset) = $src.new",
2089 // Store new-value word conditionally.
2091 // if ([!]Pv[.new]) memw(#u6)=Nt.new
2093 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
2094 // if (Pv) memw(Rs+#u6:2)=Nt.new
2095 let mayStore = 1, neverHasSideEffects = 1 in
2096 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
2097 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2098 "if ($src1) memw($addr) = $src2.new",
2102 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
2103 let mayStore = 1, neverHasSideEffects = 1 in
2104 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
2105 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2106 "if ($src1.new) memw($addr) = $src2.new",
2110 // if (!Pv) memw(Rs+#u6:2)=Nt.new
2111 let mayStore = 1, neverHasSideEffects = 1 in
2112 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
2113 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2114 "if (!$src1) memw($addr) = $src2.new",
2118 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
2119 let mayStore = 1, neverHasSideEffects = 1 in
2120 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2121 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2122 "if (!$src1.new) memw($addr) = $src2.new",
2126 // if (Pv) memw(Rs+#u6:2)=Nt.new
2127 let mayStore = 1, neverHasSideEffects = 1 in
2128 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2129 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2130 "if ($src1) memw($src2+#$src3) = $src4.new",
2134 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
2135 let mayStore = 1, neverHasSideEffects = 1 in
2136 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2137 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2138 "if ($src1.new) memw($src2+#$src3) = $src4.new",
2142 // if (!Pv) memw(Rs+#u6:2)=Nt.new
2143 let mayStore = 1, neverHasSideEffects = 1 in
2144 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2145 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2146 "if (!$src1) memw($src2+#$src3) = $src4.new",
2150 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
2151 let mayStore = 1, neverHasSideEffects = 1 in
2152 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2153 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2154 "if (!$src1.new) memw($src2+#$src3) = $src4.new",
2159 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new
2160 // if (Pv) memw(Rs+Ru<<#u2)=Nt.new
2161 let mayStore = 1, AddedComplexity = 10 in
2162 def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
2163 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2165 "if ($src1) memw($src2+$src3<<#$src4) = $src5.new",
2169 // if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new
2170 let mayStore = 1, AddedComplexity = 10 in
2171 def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
2172 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2174 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5.new",
2178 // if (!Pv) memw(Rs+Ru<<#u2)=Nt.new
2179 let mayStore = 1, AddedComplexity = 10 in
2180 def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
2181 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2183 "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",
2187 // if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new
2188 let mayStore = 1, AddedComplexity = 10 in
2189 def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2190 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2192 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",
2196 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
2197 // if (Pv) memw(Rx++#s4:2)=Nt.new
2198 let mayStore = 1, hasCtrlDep = 1 in
2199 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2200 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2201 "if ($src1) memw($src3++#$offset) = $src2.new",
2205 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
2206 let mayStore = 1, hasCtrlDep = 1 in
2207 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2208 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2209 "if ($src1.new) memw($src3++#$offset) = $src2.new",
2213 // if (!Pv) memw(Rx++#s4:2)=Nt.new
2214 let mayStore = 1, hasCtrlDep = 1 in
2215 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2216 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2217 "if (!$src1) memw($src3++#$offset) = $src2.new",
2221 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
2222 let mayStore = 1, hasCtrlDep = 1 in
2223 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2224 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2225 "if (!$src1.new) memw($src3++#$offset) = $src2.new",
2230 //===----------------------------------------------------------------------===//
2232 //===----------------------------------------------------------------------===//
2235 //===----------------------------------------------------------------------===//
2237 //===----------------------------------------------------------------------===//
2239 // Add and accumulate.
2240 // Rd=add(Rs,add(Ru,#s6))
2241 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
2242 (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
2243 "$dst = add($src1, add($src2, #$src3))",
2245 (add IntRegs:$src1, (add IntRegs:$src2, s6ImmPred:$src3)))]>,
2248 // Rd=add(Rs,sub(#s6,Ru))
2249 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
2250 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
2251 "$dst = add($src1, sub(#$src2, $src3))",
2253 (add IntRegs:$src1, (sub s6ImmPred:$src2, IntRegs:$src3)))]>,
2256 // Generates the same instruction as ADDr_SUBri_V4 but matches different
2258 // Rd=add(Rs,sub(#s6,Ru))
2259 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
2260 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
2261 "$dst = add($src1, sub(#$src2, $src3))",
2263 (sub (add IntRegs:$src1, s6ImmPred:$src2), IntRegs:$src3))]>,
2267 // Add or subtract doublewords with carry.
2269 // Rdd=add(Rss,Rtt,Px):carry
2271 // Rdd=sub(Rss,Rtt,Px):carry
2274 // Logical doublewords.
2275 // Rdd=and(Rtt,~Rss)
2276 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2277 (ins DoubleRegs:$src1, DoubleRegs:$src2),
2278 "$dst = and($src1, ~$src2)",
2279 [(set DoubleRegs:$dst, (and DoubleRegs:$src1,
2280 (not DoubleRegs:$src2)))]>,
2284 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2285 (ins DoubleRegs:$src1, DoubleRegs:$src2),
2286 "$dst = or($src1, ~$src2)",
2287 [(set DoubleRegs:$dst,
2288 (or DoubleRegs:$src1, (not DoubleRegs:$src2)))]>,
2292 // Logical-logical doublewords.
2293 // Rxx^=xor(Rss,Rtt)
2294 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
2295 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
2296 "$dst ^= xor($src2, $src3)",
2297 [(set DoubleRegs:$dst,
2298 (xor DoubleRegs:$src1, (xor DoubleRegs:$src2, DoubleRegs:$src3)))],
2303 // Logical-logical words.
2304 // Rx=or(Ru,and(Rx,#s10))
2305 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
2306 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
2307 "$dst = or($src1, and($src2, #$src3))",
2309 (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],
2313 // Rx[&|^]=and(Rs,Rt)
2315 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2316 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2317 "$dst &= and($src2, $src3)",
2319 (and IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],
2324 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2325 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2326 "$dst |= and($src2, $src3)",
2328 (or IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],
2333 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2334 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2335 "$dst ^= and($src2, $src3)",
2337 (xor IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],
2341 // Rx[&|^]=and(Rs,~Rt)
2343 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2344 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2345 "$dst &= and($src2, ~$src3)",
2347 (and IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],
2352 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2353 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2354 "$dst |= and($src2, ~$src3)",
2356 (or IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],
2361 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2362 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2363 "$dst ^= and($src2, ~$src3)",
2365 (xor IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],
2369 // Rx[&|^]=or(Rs,Rt)
2371 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2372 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2373 "$dst &= or($src2, $src3)",
2375 (and IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],
2380 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2381 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2382 "$dst |= or($src2, $src3)",
2384 (or IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],
2389 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2390 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2391 "$dst ^= or($src2, $src3)",
2393 (xor IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],
2397 // Rx[&|^]=xor(Rs,Rt)
2399 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2400 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2401 "$dst &= xor($src2, $src3)",
2403 (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],
2408 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2409 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2410 "$dst |= xor($src2, $src3)",
2412 (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],
2417 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2418 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2419 "$dst ^= xor($src2, $src3)",
2421 (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],
2426 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
2427 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
2428 "$dst |= and($src2, #$src3)",
2430 (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],
2435 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
2436 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
2437 "$dst |= or($src2, #$src3)",
2439 (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],
2445 // Rd=modwrap(Rs,Rt)
2447 // Rd=cround(Rs,#u5)
2449 // Rd=round(Rs,#u5)[:sat]
2450 // Rd=round(Rs,Rt)[:sat]
2451 // Vector reduce add unsigned halfwords
2452 // Rd=vraddh(Rss,Rtt)
2454 // Rdd=vaddb(Rss,Rtt)
2455 // Vector conditional negate
2456 // Rdd=vcnegh(Rss,Rt)
2457 // Rxx+=vrcnegh(Rss,Rt)
2458 // Vector maximum bytes
2459 // Rdd=vmaxb(Rtt,Rss)
2460 // Vector reduce maximum halfwords
2461 // Rxx=vrmaxh(Rss,Ru)
2462 // Rxx=vrmaxuh(Rss,Ru)
2463 // Vector reduce maximum words
2464 // Rxx=vrmaxuw(Rss,Ru)
2465 // Rxx=vrmaxw(Rss,Ru)
2466 // Vector minimum bytes
2467 // Rdd=vminb(Rtt,Rss)
2468 // Vector reduce minimum halfwords
2469 // Rxx=vrminh(Rss,Ru)
2470 // Rxx=vrminuh(Rss,Ru)
2471 // Vector reduce minimum words
2472 // Rxx=vrminuw(Rss,Ru)
2473 // Rxx=vrminw(Rss,Ru)
2474 // Vector subtract bytes
2475 // Rdd=vsubb(Rss,Rtt)
2477 //===----------------------------------------------------------------------===//
2479 //===----------------------------------------------------------------------===//
2482 //===----------------------------------------------------------------------===//
2484 //===----------------------------------------------------------------------===//
2486 // Multiply and user lower result.
2487 // Rd=add(#u6,mpyi(Rs,#U6))
2488 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
2489 (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
2490 "$dst = add(#$src1, mpyi($src2, #$src3))",
2492 (add (mul IntRegs:$src2, u6ImmPred:$src3), u6ImmPred:$src1))]>,
2495 // Rd=add(#u6,mpyi(Rs,Rt))
2497 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
2498 (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
2499 "$dst = add(#$src1, mpyi($src2, $src3))",
2501 (add (mul IntRegs:$src2, IntRegs:$src3), u6ImmPred:$src1))]>,
2504 // Rd=add(Ru,mpyi(#u6:2,Rs))
2505 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
2506 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
2507 "$dst = add($src1, mpyi(#$src2, $src3))",
2509 (add IntRegs:$src1, (mul IntRegs:$src3, u6_2ImmPred:$src2)))]>,
2512 // Rd=add(Ru,mpyi(Rs,#u6))
2513 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
2514 (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
2515 "$dst = add($src1, mpyi($src2, #$src3))",
2517 (add IntRegs:$src1, (mul IntRegs:$src2, u6ImmPred:$src3)))]>,
2520 // Rx=add(Ru,mpyi(Rx,Rs))
2521 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
2522 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2523 "$dst = add($src1, mpyi($src2, $src3))",
2525 (add IntRegs:$src1, (mul IntRegs:$src2, IntRegs:$src3)))],
2530 // Polynomial multiply words
2532 // Rxx^=pmpyw(Rs,Rt)
2534 // Vector reduce multiply word by signed half (32x16)
2535 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2536 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2537 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
2538 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
2540 // Multiply and use upper result
2541 // Rd=mpy(Rs,Rt.H):<<1:sat
2542 // Rd=mpy(Rs,Rt.L):<<1:sat
2543 // Rd=mpy(Rs,Rt):<<1
2544 // Rd=mpy(Rs,Rt):<<1:sat
2546 // Rx+=mpy(Rs,Rt):<<1:sat
2547 // Rx-=mpy(Rs,Rt):<<1:sat
2549 // Vector multiply bytes
2550 // Rdd=vmpybsu(Rs,Rt)
2551 // Rdd=vmpybu(Rs,Rt)
2552 // Rxx+=vmpybsu(Rs,Rt)
2553 // Rxx+=vmpybu(Rs,Rt)
2555 // Vector polynomial multiply halfwords
2556 // Rdd=vpmpyh(Rs,Rt)
2557 // Rxx^=vpmpyh(Rs,Rt)
2559 //===----------------------------------------------------------------------===//
2561 //===----------------------------------------------------------------------===//
2564 //===----------------------------------------------------------------------===//
2566 //===----------------------------------------------------------------------===//
2568 // Shift by immediate and accumulate.
2569 // Rx=add(#u8,asl(Rx,#U5))
2570 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2571 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2572 "$dst = add(#$src1, asl($src2, #$src3))",
2574 (add (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2578 // Rx=add(#u8,lsr(Rx,#U5))
2579 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2580 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2581 "$dst = add(#$src1, lsr($src2, #$src3))",
2583 (add (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2587 // Rx=sub(#u8,asl(Rx,#U5))
2588 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2589 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2590 "$dst = sub(#$src1, asl($src2, #$src3))",
2592 (sub (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2596 // Rx=sub(#u8,lsr(Rx,#U5))
2597 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2598 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2599 "$dst = sub(#$src1, lsr($src2, #$src3))",
2601 (sub (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2606 //Shift by immediate and logical.
2607 //Rx=and(#u8,asl(Rx,#U5))
2608 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2609 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2610 "$dst = and(#$src1, asl($src2, #$src3))",
2612 (and (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2616 //Rx=and(#u8,lsr(Rx,#U5))
2617 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2618 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2619 "$dst = and(#$src1, lsr($src2, #$src3))",
2621 (and (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2625 //Rx=or(#u8,asl(Rx,#U5))
2626 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2627 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2628 "$dst = or(#$src1, asl($src2, #$src3))",
2630 (or (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2634 //Rx=or(#u8,lsr(Rx,#U5))
2635 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2636 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2637 "$dst = or(#$src1, lsr($src2, #$src3))",
2639 (or (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2644 //Shift by register.
2646 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
2647 "$dst = lsl(#$src1, $src2)",
2648 [(set IntRegs:$dst, (shl s6ImmPred:$src1, IntRegs:$src2))]>,
2652 //Shift by register and logical.
2654 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2655 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2656 "$dst ^= asl($src2, $src3)",
2657 [(set DoubleRegs:$dst,
2658 (xor DoubleRegs:$src1, (shl DoubleRegs:$src2, IntRegs:$src3)))],
2663 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2664 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2665 "$dst ^= asr($src2, $src3)",
2666 [(set DoubleRegs:$dst,
2667 (xor DoubleRegs:$src1, (sra DoubleRegs:$src2, IntRegs:$src3)))],
2672 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2673 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2674 "$dst ^= lsl($src2, $src3)",
2675 [(set DoubleRegs:$dst,
2676 (xor DoubleRegs:$src1, (shl DoubleRegs:$src2, IntRegs:$src3)))],
2681 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2682 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2683 "$dst ^= lsr($src2, $src3)",
2684 [(set DoubleRegs:$dst,
2685 (xor DoubleRegs:$src1, (srl DoubleRegs:$src2, IntRegs:$src3)))],
2690 //===----------------------------------------------------------------------===//
2692 //===----------------------------------------------------------------------===//
2694 //===----------------------------------------------------------------------===//
2695 // MEMOP: Word, Half, Byte
2696 //===----------------------------------------------------------------------===//
2698 //===----------------------------------------------------------------------===//
2702 // MEMw_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
2703 // MEMw_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
2704 // MEMw_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
2705 // MEMw_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
2706 // MEMw_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
2707 // MEMw_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
2708 // MEMw_ADDi_V4 : memw(Rs+#u6:2)+=#U5
2709 // MEMw_SUBi_V4 : memw(Rs+#u6:2)-=#U5
2710 // MEMw_ADDr_V4 : memw(Rs+#u6:2)+=Rt
2711 // MEMw_SUBr_V4 : memw(Rs+#u6:2)-=Rt
2712 // MEMw_CLRr_V4 : memw(Rs+#u6:2)&=Rt
2713 // MEMw_SETr_V4 : memw(Rs+#u6:2)|=Rt
2716 // MEMw_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2717 // MEMw_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
2718 // MEMw_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2719 // MEMw_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
2720 //===----------------------------------------------------------------------===//
2723 // MEMw_ADDSUBi_indexed_V4:
2724 // pseudo operation for MEMw_ADDi_indexed_V4 and
2725 // MEMw_SUBi_indexed_V4 a later pass will change it
2726 // to the corresponding pattern.
2727 let AddedComplexity = 30 in
2728 def MEMw_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2729 (ins IntRegs:$base, u6_2Imm:$offset, m6Imm:$addend),
2730 "Error; should not emit",
2731 [(store (add (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2733 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2734 Requires<[HasV4T, UseMEMOP]>;
2736 // memw(Rs+#u6:2) += #U5
2737 let AddedComplexity = 30 in
2738 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
2739 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
2740 "memw($base+#$offset) += $addend",
2742 Requires<[HasV4T, UseMEMOP]>;
2744 // memw(Rs+#u6:2) -= #U5
2745 let AddedComplexity = 30 in
2746 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2747 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
2748 "memw($base+#$offset) -= $subend",
2750 Requires<[HasV4T, UseMEMOP]>;
2752 // memw(Rs+#u6:2) += Rt
2753 let AddedComplexity = 30 in
2754 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2755 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
2756 "memw($base+#$offset) += $addend",
2757 [(store (add (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2759 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2760 Requires<[HasV4T, UseMEMOP]>;
2762 // memw(Rs+#u6:2) -= Rt
2763 let AddedComplexity = 30 in
2764 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
2765 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
2766 "memw($base+#$offset) -= $subend",
2767 [(store (sub (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2769 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2770 Requires<[HasV4T, UseMEMOP]>;
2772 // memw(Rs+#u6:2) &= Rt
2773 let AddedComplexity = 30 in
2774 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2775 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
2776 "memw($base+#$offset) += $andend",
2777 [(store (and (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2779 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2780 Requires<[HasV4T, UseMEMOP]>;
2782 // memw(Rs+#u6:2) |= Rt
2783 let AddedComplexity = 30 in
2784 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
2785 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
2786 "memw($base+#$offset) |= $orend",
2787 [(store (or (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2789 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2790 Requires<[HasV4T, UseMEMOP]>;
2793 // Pseudo operation for MEMw_ADDi_V4 and MEMw_SUBi_V4
2794 // a later pass will change it to the right pattern.
2795 let AddedComplexity = 30 in
2796 def MEMw_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
2797 (ins MEMri:$addr, m6Imm:$addend),
2798 "Error; should not emit",
2799 [(store (add (load ADDRriU6_2:$addr), m6ImmPred:$addend),
2800 ADDRriU6_2:$addr)]>,
2801 Requires<[HasV4T, UseMEMOP]>;
2803 // memw(Rs+#u6:2) += #U5
2804 let AddedComplexity = 30 in
2805 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
2806 (ins MEMri:$addr, u5Imm:$addend),
2807 "memw($addr) += $addend",
2809 Requires<[HasV4T, UseMEMOP]>;
2811 // memw(Rs+#u6:2) -= #U5
2812 let AddedComplexity = 30 in
2813 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
2814 (ins MEMri:$addr, u5Imm:$subend),
2815 "memw($addr) -= $subend",
2817 Requires<[HasV4T, UseMEMOP]>;
2819 // memw(Rs+#u6:2) += Rt
2820 let AddedComplexity = 30 in
2821 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
2822 (ins MEMri:$addr, IntRegs:$addend),
2823 "memw($addr) += $addend",
2824 [(store (add (load ADDRriU6_2:$addr), IntRegs:$addend),
2825 ADDRriU6_2:$addr)]>,
2826 Requires<[HasV4T, UseMEMOP]>;
2828 // memw(Rs+#u6:2) -= Rt
2829 let AddedComplexity = 30 in
2830 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
2831 (ins MEMri:$addr, IntRegs:$subend),
2832 "memw($addr) -= $subend",
2833 [(store (sub (load ADDRriU6_2:$addr), IntRegs:$subend),
2834 ADDRriU6_2:$addr)]>,
2835 Requires<[HasV4T, UseMEMOP]>;
2837 // memw(Rs+#u6:2) &= Rt
2838 let AddedComplexity = 30 in
2839 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
2840 (ins MEMri:$addr, IntRegs:$andend),
2841 "memw($addr) &= $andend",
2842 [(store (and (load ADDRriU6_2:$addr), IntRegs:$andend),
2843 ADDRriU6_2:$addr)]>,
2844 Requires<[HasV4T, UseMEMOP]>;
2846 // memw(Rs+#u6:2) |= Rt
2847 let AddedComplexity = 30 in
2848 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
2849 (ins MEMri:$addr, IntRegs:$orend),
2850 "memw($addr) |= $orend",
2851 [(store (or (load ADDRriU6_2:$addr), IntRegs:$orend),
2852 ADDRriU6_2:$addr)]>,
2853 Requires<[HasV4T, UseMEMOP]>;
2855 //===----------------------------------------------------------------------===//
2859 // MEMh_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
2860 // MEMh_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
2861 // MEMh_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
2862 // MEMh_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
2863 // MEMh_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
2864 // MEMh_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
2865 // MEMh_ADDi_V4 : memw(Rs+#u6:2)+=#U5
2866 // MEMh_SUBi_V4 : memw(Rs+#u6:2)-=#U5
2867 // MEMh_ADDr_V4 : memw(Rs+#u6:2)+=Rt
2868 // MEMh_SUBr_V4 : memw(Rs+#u6:2)-=Rt
2869 // MEMh_CLRr_V4 : memw(Rs+#u6:2)&=Rt
2870 // MEMh_SETr_V4 : memw(Rs+#u6:2)|=Rt
2873 // MEMh_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2874 // MEMh_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
2875 // MEMh_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2876 // MEMh_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
2877 //===----------------------------------------------------------------------===//
2880 // MEMh_ADDSUBi_indexed_V4:
2881 // Pseudo operation for MEMh_ADDi_indexed_V4 and
2882 // MEMh_SUBi_indexed_V4 a later pass will change it
2883 // to the corresponding pattern.
2884 let AddedComplexity = 30 in
2885 def MEMh_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2886 (ins IntRegs:$base, u6_1Imm:$offset, m6Imm:$addend),
2887 "Error; should not emit",
2888 [(truncstorei16 (add (sextloadi16 (add IntRegs:$base,
2889 u6_1ImmPred:$offset)),
2891 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
2892 Requires<[HasV4T, UseMEMOP]>;
2894 // memh(Rs+#u6:1) += #U5
2895 let AddedComplexity = 30 in
2896 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
2897 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
2898 "memh($base+#$offset) += $addend",
2900 Requires<[HasV4T, UseMEMOP]>;
2902 // memh(Rs+#u6:1) -= #U5
2903 let AddedComplexity = 30 in
2904 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2905 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
2906 "memh($base+#$offset) -= $subend",
2908 Requires<[HasV4T, UseMEMOP]>;
2910 // memh(Rs+#u6:1) += Rt
2911 let AddedComplexity = 30 in
2912 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2913 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
2914 "memh($base+#$offset) += $addend",
2915 [(truncstorei16 (add (sextloadi16 (add IntRegs:$base,
2916 u6_1ImmPred:$offset)),
2918 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
2919 Requires<[HasV4T, UseMEMOP]>;
2921 // memh(Rs+#u6:1) -= Rt
2922 let AddedComplexity = 30 in
2923 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
2924 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
2925 "memh($base+#$offset) -= $subend",
2926 [(truncstorei16 (sub (sextloadi16 (add IntRegs:$base,
2927 u6_1ImmPred:$offset)),
2929 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
2930 Requires<[HasV4T, UseMEMOP]>;
2932 // memh(Rs+#u6:1) &= Rt
2933 let AddedComplexity = 30 in
2934 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2935 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
2936 "memh($base+#$offset) += $andend",
2937 [(truncstorei16 (and (sextloadi16 (add IntRegs:$base,
2938 u6_1ImmPred:$offset)),
2940 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
2941 Requires<[HasV4T, UseMEMOP]>;
2943 // memh(Rs+#u6:1) |= Rt
2944 let AddedComplexity = 30 in
2945 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
2946 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
2947 "memh($base+#$offset) |= $orend",
2948 [(truncstorei16 (or (sextloadi16 (add IntRegs:$base,
2949 u6_1ImmPred:$offset)),
2951 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
2952 Requires<[HasV4T, UseMEMOP]>;
2955 // Pseudo operation for MEMh_ADDi_V4 and MEMh_SUBi_V4
2956 // a later pass will change it to the right pattern.
2957 let AddedComplexity = 30 in
2958 def MEMh_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
2959 (ins MEMri:$addr, m6Imm:$addend),
2960 "Error; should not emit",
2961 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
2962 m6ImmPred:$addend), ADDRriU6_1:$addr)]>,
2963 Requires<[HasV4T, UseMEMOP]>;
2965 // memh(Rs+#u6:1) += #U5
2966 let AddedComplexity = 30 in
2967 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
2968 (ins MEMri:$addr, u5Imm:$addend),
2969 "memh($addr) += $addend",
2971 Requires<[HasV4T, UseMEMOP]>;
2973 // memh(Rs+#u6:1) -= #U5
2974 let AddedComplexity = 30 in
2975 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
2976 (ins MEMri:$addr, u5Imm:$subend),
2977 "memh($addr) -= $subend",
2979 Requires<[HasV4T, UseMEMOP]>;
2981 // memh(Rs+#u6:1) += Rt
2982 let AddedComplexity = 30 in
2983 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
2984 (ins MEMri:$addr, IntRegs:$addend),
2985 "memh($addr) += $addend",
2986 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
2987 IntRegs:$addend), ADDRriU6_1:$addr)]>,
2988 Requires<[HasV4T, UseMEMOP]>;
2990 // memh(Rs+#u6:1) -= Rt
2991 let AddedComplexity = 30 in
2992 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
2993 (ins MEMri:$addr, IntRegs:$subend),
2994 "memh($addr) -= $subend",
2995 [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
2996 IntRegs:$subend), ADDRriU6_1:$addr)]>,
2997 Requires<[HasV4T, UseMEMOP]>;
2999 // memh(Rs+#u6:1) &= Rt
3000 let AddedComplexity = 30 in
3001 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
3002 (ins MEMri:$addr, IntRegs:$andend),
3003 "memh($addr) &= $andend",
3004 [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
3005 IntRegs:$andend), ADDRriU6_1:$addr)]>,
3006 Requires<[HasV4T, UseMEMOP]>;
3008 // memh(Rs+#u6:1) |= Rt
3009 let AddedComplexity = 30 in
3010 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
3011 (ins MEMri:$addr, IntRegs:$orend),
3012 "memh($addr) |= $orend",
3013 [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
3014 IntRegs:$orend), ADDRriU6_1:$addr)]>,
3015 Requires<[HasV4T, UseMEMOP]>;
3018 //===----------------------------------------------------------------------===//
3022 // MEMb_ADDi_indexed_V4 : memb(Rs+#u6:0)+=#U5
3023 // MEMb_SUBi_indexed_V4 : memb(Rs+#u6:0)-=#U5
3024 // MEMb_ADDr_indexed_V4 : memb(Rs+#u6:0)+=Rt
3025 // MEMb_SUBr_indexed_V4 : memb(Rs+#u6:0)-=Rt
3026 // MEMb_CLRr_indexed_V4 : memb(Rs+#u6:0)&=Rt
3027 // MEMb_SETr_indexed_V4 : memb(Rs+#u6:0)|=Rt
3028 // MEMb_ADDi_V4 : memb(Rs+#u6:0)+=#U5
3029 // MEMb_SUBi_V4 : memb(Rs+#u6:0)-=#U5
3030 // MEMb_ADDr_V4 : memb(Rs+#u6:0)+=Rt
3031 // MEMb_SUBr_V4 : memb(Rs+#u6:0)-=Rt
3032 // MEMb_CLRr_V4 : memb(Rs+#u6:0)&=Rt
3033 // MEMb_SETr_V4 : memb(Rs+#u6:0)|=Rt
3036 // MEMb_CLRi_indexed_V4 : memb(Rs+#u6:0)=clrbit(#U5)
3037 // MEMb_SETi_indexed_V4 : memb(Rs+#u6:0)=setbit(#U5)
3038 // MEMb_CLRi_V4 : memb(Rs+#u6:0)=clrbit(#U5)
3039 // MEMb_SETi_V4 : memb(Rs+#u6:0)=setbit(#U5)
3040 //===----------------------------------------------------------------------===//
3043 // MEMb_ADDSUBi_indexed_V4:
3044 // Pseudo operation for MEMb_ADDi_indexed_V4 and
3045 // MEMb_SUBi_indexed_V4 a later pass will change it
3046 // to the corresponding pattern.
3047 let AddedComplexity = 30 in
3048 def MEMb_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3049 (ins IntRegs:$base, u6_0Imm:$offset, m6Imm:$addend),
3050 "Error; should not emit",
3051 [(truncstorei8 (add (sextloadi8 (add IntRegs:$base,
3052 u6_0ImmPred:$offset)),
3054 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3055 Requires<[HasV4T, UseMEMOP]>;
3057 // memb(Rs+#u6:0) += #U5
3058 let AddedComplexity = 30 in
3059 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3060 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
3061 "memb($base+#$offset) += $addend",
3063 Requires<[HasV4T, UseMEMOP]>;
3065 // memb(Rs+#u6:0) -= #U5
3066 let AddedComplexity = 30 in
3067 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3068 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
3069 "memb($base+#$offset) -= $subend",
3071 Requires<[HasV4T, UseMEMOP]>;
3073 // memb(Rs+#u6:0) += Rt
3074 let AddedComplexity = 30 in
3075 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3076 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
3077 "memb($base+#$offset) += $addend",
3078 [(truncstorei8 (add (sextloadi8 (add IntRegs:$base,
3079 u6_0ImmPred:$offset)),
3081 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3082 Requires<[HasV4T, UseMEMOP]>;
3084 // memb(Rs+#u6:0) -= Rt
3085 let AddedComplexity = 30 in
3086 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3087 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
3088 "memb($base+#$offset) -= $subend",
3089 [(truncstorei8 (sub (sextloadi8 (add IntRegs:$base,
3090 u6_0ImmPred:$offset)),
3092 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3093 Requires<[HasV4T, UseMEMOP]>;
3095 // memb(Rs+#u6:0) &= Rt
3096 let AddedComplexity = 30 in
3097 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3098 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
3099 "memb($base+#$offset) += $andend",
3100 [(truncstorei8 (and (sextloadi8 (add IntRegs:$base,
3101 u6_0ImmPred:$offset)),
3103 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3104 Requires<[HasV4T, UseMEMOP]>;
3106 // memb(Rs+#u6:0) |= Rt
3107 let AddedComplexity = 30 in
3108 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3109 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
3110 "memb($base+#$offset) |= $orend",
3111 [(truncstorei8 (or (sextloadi8 (add IntRegs:$base,
3112 u6_0ImmPred:$offset)),
3114 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3115 Requires<[HasV4T, UseMEMOP]>;
3118 // Pseudo operation for MEMb_ADDi_V4 and MEMb_SUBi_V4
3119 // a later pass will change it to the right pattern.
3120 let AddedComplexity = 30 in
3121 def MEMb_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
3122 (ins MEMri:$addr, m6Imm:$addend),
3123 "Error; should not emit",
3124 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3125 m6ImmPred:$addend), ADDRriU6_0:$addr)]>,
3126 Requires<[HasV4T, UseMEMOP]>;
3128 // memb(Rs+#u6:0) += #U5
3129 let AddedComplexity = 30 in
3130 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
3131 (ins MEMri:$addr, u5Imm:$addend),
3132 "memb($addr) += $addend",
3134 Requires<[HasV4T, UseMEMOP]>;
3136 // memb(Rs+#u6:0) -= #U5
3137 let AddedComplexity = 30 in
3138 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
3139 (ins MEMri:$addr, u5Imm:$subend),
3140 "memb($addr) -= $subend",
3142 Requires<[HasV4T, UseMEMOP]>;
3144 // memb(Rs+#u6:0) += Rt
3145 let AddedComplexity = 30 in
3146 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
3147 (ins MEMri:$addr, IntRegs:$addend),
3148 "memb($addr) += $addend",
3149 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3150 IntRegs:$addend), ADDRriU6_0:$addr)]>,
3151 Requires<[HasV4T, UseMEMOP]>;
3153 // memb(Rs+#u6:0) -= Rt
3154 let AddedComplexity = 30 in
3155 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
3156 (ins MEMri:$addr, IntRegs:$subend),
3157 "memb($addr) -= $subend",
3158 [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
3159 IntRegs:$subend), ADDRriU6_0:$addr)]>,
3160 Requires<[HasV4T, UseMEMOP]>;
3162 // memb(Rs+#u6:0) &= Rt
3163 let AddedComplexity = 30 in
3164 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
3165 (ins MEMri:$addr, IntRegs:$andend),
3166 "memb($addr) &= $andend",
3167 [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
3168 IntRegs:$andend), ADDRriU6_0:$addr)]>,
3169 Requires<[HasV4T, UseMEMOP]>;
3171 // memb(Rs+#u6:0) |= Rt
3172 let AddedComplexity = 30 in
3173 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
3174 (ins MEMri:$addr, IntRegs:$orend),
3175 "memb($addr) |= $orend",
3176 [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
3177 IntRegs:$orend), ADDRriU6_0:$addr)]>,
3178 Requires<[HasV4T, UseMEMOP]>;
3181 //===----------------------------------------------------------------------===//
3183 //===----------------------------------------------------------------------===//
3185 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3186 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3187 // hardware. However, compiler can still implement these patterns through
3188 // appropriate patterns combinations based on current implemented patterns.
3189 // The implemented patterns are: EQ/GT/GTU.
3190 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3192 // Pd=cmpb.eq(Rs,#u8)
3193 let isCompare = 1 in
3194 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
3195 (ins IntRegs:$src1, u8Imm:$src2),
3196 "$dst = cmpb.eq($src1, #$src2)",
3197 [(set PredRegs:$dst, (seteq (and IntRegs:$src1, 255),
3198 u8ImmPred:$src2))]>,
3201 // Pd=cmpb.eq(Rs,Rt)
3202 let isCompare = 1 in
3203 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
3204 (ins IntRegs:$src1, IntRegs:$src2),
3205 "$dst = cmpb.eq($src1, $src2)",
3206 [(set PredRegs:$dst, (seteq (and (xor IntRegs:$src1,
3212 // Pd=cmpb.eq(Rs,Rt)
3213 let isCompare = 1 in
3214 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
3215 (ins IntRegs:$src1, IntRegs:$src2),
3216 "$dst = cmpb.eq($src1, $src2)",
3217 [(set PredRegs:$dst, (seteq (shl IntRegs:$src1, (i32 24)),
3218 (shl IntRegs:$src2, (i32 24))))]>,
3221 // Pd=cmpb.gt(Rs,#s8)
3222 let isCompare = 1 in
3223 def CMPbGTri_V4 : MInst<(outs PredRegs:$dst),
3224 (ins IntRegs:$src1, s32Imm:$src2),
3225 "$dst = cmpb.gt($src1, #$src2)",
3226 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 24)),
3227 s32_24ImmPred:$src2))]>,
3230 // Pd=cmpb.gt(Rs,Rt)
3231 let isCompare = 1 in
3232 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
3233 (ins IntRegs:$src1, IntRegs:$src2),
3234 "$dst = cmpb.gt($src1, $src2)",
3235 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 24)),
3236 (shl IntRegs:$src2, (i32 24))))]>,
3239 // Pd=cmpb.gtu(Rs,#u7)
3240 let isCompare = 1 in
3241 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
3242 (ins IntRegs:$src1, u7Imm:$src2),
3243 "$dst = cmpb.gtu($src1, #$src2)",
3244 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 255),
3245 u7ImmPred:$src2))]>,
3248 // Pd=cmpb.gtu(Rs,Rt)
3249 let isCompare = 1 in
3250 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
3251 (ins IntRegs:$src1, IntRegs:$src2),
3252 "$dst = cmpb.gtu($src1, $src2)",
3253 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 255),
3254 (and IntRegs:$src2, 255)))]>,
3257 // Signed half compare(.eq) ri.
3258 // Pd=cmph.eq(Rs,#s8)
3259 let isCompare = 1 in
3260 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
3261 (ins IntRegs:$src1, u16Imm:$src2),
3262 "$dst = cmph.eq($src1, #$src2)",
3263 [(set PredRegs:$dst, (seteq (and IntRegs:$src1, 65535),
3264 u16_s8ImmPred:$src2))]>,
3267 // Signed half compare(.eq) rr.
3268 // Case 1: xor + and, then compare:
3270 // r0=and(r0,#0xffff)
3272 // Pd=cmph.eq(Rs,Rt)
3273 let isCompare = 1 in
3274 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
3275 (ins IntRegs:$src1, IntRegs:$src2),
3276 "$dst = cmph.eq($src1, $src2)",
3277 [(set PredRegs:$dst, (seteq (and (xor IntRegs:$src1,
3283 // Signed half compare(.eq) rr.
3284 // Case 2: shift left 16 bits then compare:
3288 // Pd=cmph.eq(Rs,Rt)
3289 let isCompare = 1 in
3290 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
3291 (ins IntRegs:$src1, IntRegs:$src2),
3292 "$dst = cmph.eq($src1, $src2)",
3293 [(set PredRegs:$dst, (seteq (shl IntRegs:$src1, (i32 16)),
3294 (shl IntRegs:$src2, (i32 16))))]>,
3297 // Signed half compare(.gt) ri.
3298 // Pd=cmph.gt(Rs,#s8)
3299 let isCompare = 1 in
3300 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
3301 (ins IntRegs:$src1, s32Imm:$src2),
3302 "$dst = cmph.gt($src1, #$src2)",
3303 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 16)),
3304 s32_16s8ImmPred:$src2))]>,
3307 // Signed half compare(.gt) rr.
3308 // Pd=cmph.gt(Rs,Rt)
3309 let isCompare = 1 in
3310 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
3311 (ins IntRegs:$src1, IntRegs:$src2),
3312 "$dst = cmph.gt($src1, $src2)",
3313 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 16)),
3314 (shl IntRegs:$src2, (i32 16))))]>,
3317 // Unsigned half compare rr (.gtu).
3318 // Pd=cmph.gtu(Rs,Rt)
3319 let isCompare = 1 in
3320 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
3321 (ins IntRegs:$src1, IntRegs:$src2),
3322 "$dst = cmph.gtu($src1, $src2)",
3323 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 65535),
3324 (and IntRegs:$src2, 65535)))]>,
3327 // Unsigned half compare ri (.gtu).
3328 // Pd=cmph.gtu(Rs,#u7)
3329 let isCompare = 1 in
3330 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
3331 (ins IntRegs:$src1, u7Imm:$src2),
3332 "$dst = cmph.gtu($src1, #$src2)",
3333 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 65535),
3334 u7ImmPred:$src2))]>,
3337 //===----------------------------------------------------------------------===//
3339 //===----------------------------------------------------------------------===//
3341 //Deallocate frame and return.
3343 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
3344 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3345 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
3351 // if (Ps) dealloc_return
3352 let isReturn = 1, isTerminator = 1,
3353 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3354 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, i32imm:$amt1),
3355 "if ($src1) dealloc_return",
3360 // if (!Ps) dealloc_return
3361 let isReturn = 1, isTerminator = 1,
3362 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3363 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3365 "if (!$src1) dealloc_return",
3370 // if (Ps.new) dealloc_return:nt
3371 let isReturn = 1, isTerminator = 1,
3372 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3373 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3375 "if ($src1.new) dealloc_return:nt",
3380 // if (!Ps.new) dealloc_return:nt
3381 let isReturn = 1, isTerminator = 1,
3382 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3383 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3385 "if (!$src1.new) dealloc_return:nt",
3390 // if (Ps.new) dealloc_return:t
3391 let isReturn = 1, isTerminator = 1,
3392 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3393 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3395 "if ($src1.new) dealloc_return:t",
3400 // if (!Ps.new) dealloc_return:nt
3401 let isReturn = 1, isTerminator = 1,
3402 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3403 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3405 "if (!$src1.new) dealloc_return:t",