1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def DuplexIClass0: InstDuplex < 0 >;
15 def DuplexIClass1: InstDuplex < 1 >;
16 def DuplexIClass2: InstDuplex < 2 >;
17 let isExtendable = 1 in {
18 def DuplexIClass3: InstDuplex < 3 >;
19 def DuplexIClass4: InstDuplex < 4 >;
20 def DuplexIClass5: InstDuplex < 5 >;
21 def DuplexIClass6: InstDuplex < 6 >;
22 def DuplexIClass7: InstDuplex < 7 >;
24 def DuplexIClass8: InstDuplex < 8 >;
25 def DuplexIClass9: InstDuplex < 9 >;
26 def DuplexIClassA: InstDuplex < 0xA >;
27 def DuplexIClassB: InstDuplex < 0xB >;
28 def DuplexIClassC: InstDuplex < 0xC >;
29 def DuplexIClassD: InstDuplex < 0xD >;
30 def DuplexIClassE: InstDuplex < 0xE >;
31 def DuplexIClassF: InstDuplex < 0xF >;
33 def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
34 def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
36 let hasSideEffects = 0 in
37 class T_Immext<Operand ImmType>
38 : EXTENDERInst<(outs), (ins ImmType:$imm),
39 "immext(#$imm)", []> {
43 let Inst{27-16} = imm{31-20};
44 let Inst{13-0} = imm{19-6};
47 def A4_ext : T_Immext<u26_6Imm>;
48 let isCodeGenOnly = 1 in {
50 def A4_ext_b : T_Immext<brtarget>;
52 def A4_ext_c : T_Immext<calltarget>;
53 def A4_ext_g : T_Immext<globaladdress>;
56 def BITPOS32 : SDNodeXForm<imm, [{
57 // Return the bit position we will set [0-31].
59 int32_t imm = N->getSExtValue();
60 return XformMskToBitPosU5Imm(imm, SDLoc(N));
64 // Hexagon V4 Architecture spec defines 8 instruction classes:
65 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
69 // ========================================
70 // Loads (8/16/32/64 bit)
74 // ========================================
75 // Stores (8/16/32/64 bit)
78 // ALU32 Instructions:
79 // ========================================
80 // Arithmetic / Logical (32 bit)
83 // XTYPE Instructions (32/64 bit):
84 // ========================================
85 // Arithmetic, Logical, Bit Manipulation
86 // Multiply (Integer, Fractional, Complex)
87 // Permute / Vector Permute Operations
88 // Predicate Operations
89 // Shift / Shift with Add/Sub/Logical
91 // Vector Halfword (ALU, Shift, Multiply)
92 // Vector Word (ALU, Shift)
95 // ========================================
96 // Jump/Call PC-relative
99 // ========================================
100 // Jump/Call Register
102 // MEMOP Instructions:
103 // ========================================
104 // Operation on memory (8/16/32 bit)
107 // ========================================
112 // ========================================
113 // Control-Register Transfers
114 // Hardware Loop Setup
115 // Predicate Logicals & Reductions
117 // SYSTEM Instructions (not implemented in the compiler):
118 // ========================================
124 //===----------------------------------------------------------------------===//
126 //===----------------------------------------------------------------------===//
128 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
130 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
134 let BaseOpcode = "andn_rr", CextOpcode = "andn" in
135 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
136 let BaseOpcode = "orn_rr", CextOpcode = "orn" in
137 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
139 let CextOpcode = "rcmp.eq" in
140 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
141 let CextOpcode = "!rcmp.eq" in
142 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
144 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
145 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
146 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
148 // Pats for instruction selection.
150 // A class to embed the usual comparison patfrags within a zext to i32.
151 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
152 // names, or else the frag's "body" won't match the operands.
153 class CmpInReg<PatFrag Op>
154 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
156 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
157 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
159 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
160 def: T_cmp32_rr_pat<C4_cmplteu, setule, i1>;
162 def: T_cmp32_rr_pat<C4_cmplteu, RevCmp<setuge>, i1>;
164 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
168 let InputType = "reg";
169 let CextOpcode = mnemonic;
171 let isCommutable = IsComm;
172 let hasSideEffects = 0;
179 let Inst{27-21} = 0b0111110;
180 let Inst{20-16} = Rs;
182 let Inst{7-5} = MinOp;
186 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
187 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
188 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
189 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
190 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
191 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
193 let AddedComplexity = 100 in {
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
202 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
203 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
205 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
208 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
209 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
210 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
211 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
213 let InputType = "imm";
214 let CextOpcode = mnemonic;
216 let isCommutable = IsComm;
217 let hasSideEffects = 0;
218 let isExtendable = IsImmExt;
219 let opExtendable = !if (IsImmExt, 2, 0);
220 let isExtentSigned = IsImmSigned;
221 let opExtentBits = ImmBits;
228 let Inst{27-24} = 0b1101;
229 let Inst{22-21} = MajOp;
230 let Inst{20-16} = Rs;
231 let Inst{12-5} = Imm;
233 let Inst{3} = IsHalf;
237 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
238 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
239 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
240 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
241 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
242 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
244 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
245 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
246 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
248 let InputType = "imm";
249 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
250 let isExtendable = 1;
251 let opExtendable = 2;
252 let isExtentSigned = 1;
253 let opExtentBits = 8;
261 let Inst{27-24} = 0b0011;
263 let Inst{21} = IsNeg;
264 let Inst{20-16} = Rs;
270 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
271 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
273 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
274 (A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
275 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
276 (A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
278 // Preserve the S2_tstbit_r generation
279 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
280 (i32 IntRegs:$src1))), 0)))),
281 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
283 //===----------------------------------------------------------------------===//
285 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 //===----------------------------------------------------------------------===//
292 // Combine a word and an immediate into a register pair.
293 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
295 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
296 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
302 let Inst{27-24} = 0b0011;
303 let Inst{22-21} = MajOp;
304 let Inst{20-16} = Rs;
310 let opExtendable = 2 in
311 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
312 "$Rdd = combine($Rs, #$s8)">;
314 let opExtendable = 1 in
315 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
316 "$Rdd = combine(#$s8, $Rs)">;
318 // The complexity of the combines involving immediates should be greater
319 // than the complexity of the combine with two registers.
320 let AddedComplexity = 50 in {
321 def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
322 (A4_combineri IntRegs:$r, s32ImmPred:$i)>;
324 def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
325 (A4_combineir s32ImmPred:$i, IntRegs:$r)>;
328 // A4_combineii: Set two small immediates.
329 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
330 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
331 "$Rdd = combine(#$s8, #$U6)"> {
337 let Inst{27-23} = 0b11001;
338 let Inst{20-16} = U6{5-1};
339 let Inst{13} = U6{0};
344 // The complexity of the combine with two immediates should be greater than
345 // the complexity of a combine involving a register.
346 let AddedComplexity = 75 in
347 def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u32ImmPred:$u6),
348 (A4_combineii imm:$s8, imm:$u6)>;
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 def Zext64: OutPatFrag<(ops node:$Rs),
359 (i64 (A4_combineir 0, (i32 $Rs)))>;
360 def Sext64: OutPatFrag<(ops node:$Rs),
361 (i64 (A2_sxtw (i32 $Rs)))>;
363 // Patterns to generate indexed loads with different forms of the address:
366 // - base (without offset).
367 multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
368 PatLeaf ImmPred, InstHexagon MI> {
369 def: Pat<(VT (Load AddrFI:$fi)),
370 (VT (ValueMod (MI AddrFI:$fi, 0)))>;
371 def: Pat<(VT (Load (add AddrFI:$fi, ImmPred:$Off))),
372 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
373 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
374 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
375 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
376 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
379 defm: Loadxm_pat<extloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
380 defm: Loadxm_pat<extloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
381 defm: Loadxm_pat<extloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
382 defm: Loadxm_pat<zextloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
383 defm: Loadxm_pat<zextloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
384 defm: Loadxm_pat<zextloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
385 defm: Loadxm_pat<sextloadi8, i64, Sext64, s32_0ImmPred, L2_loadrb_io>;
386 defm: Loadxm_pat<sextloadi16, i64, Sext64, s31_1ImmPred, L2_loadrh_io>;
388 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
389 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
391 //===----------------------------------------------------------------------===//
392 // Template class for load instructions with Absolute set addressing mode.
393 //===----------------------------------------------------------------------===//
394 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
395 hasSideEffects = 0 in
396 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
397 LDInst<(outs RC:$dst1, IntRegs:$dst2),
399 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
407 let Inst{27-25} = 0b101;
408 let Inst{24-21} = MajOp;
409 let Inst{13-12} = 0b01;
410 let Inst{4-0} = dst1;
411 let Inst{20-16} = dst2;
412 let Inst{11-8} = addr{5-2};
413 let Inst{6-5} = addr{1-0};
416 let accessSize = ByteAccess, hasNewValue = 1 in {
417 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
418 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
421 let accessSize = HalfWordAccess, hasNewValue = 1 in {
422 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
423 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
424 def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
425 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
428 let accessSize = WordAccess, hasNewValue = 1 in
429 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
431 let accessSize = WordAccess in {
432 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
433 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
436 let accessSize = DoubleWordAccess in
437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
439 let accessSize = ByteAccess in
440 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
442 let accessSize = HalfWordAccess in
443 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
445 // Load - Indirect with long offset
446 let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
447 opExtentBits = 6, opExtendable = 3 in
448 class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
450 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
451 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
457 let CextOpcode = CextOp;
458 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
461 let Inst{27-25} = 0b110;
462 let Inst{24-21} = MajOp;
463 let Inst{20-16} = src1;
464 let Inst{13} = src2{1};
466 let Inst{11-8} = src3{5-2};
467 let Inst{7} = src2{0};
468 let Inst{6-5} = src3{1-0};
472 let accessSize = ByteAccess in {
473 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
474 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
475 def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
479 let accessSize = HalfWordAccess in {
480 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
481 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
482 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
483 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
484 def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
488 let accessSize = WordAccess in {
489 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
490 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
491 def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
494 let accessSize = DoubleWordAccess in
495 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
498 multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
499 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
500 (HexagonCONST32 tglobaladdr:$src3)))),
501 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
502 def : Pat <(VT (ldOp (add IntRegs:$src1,
503 (HexagonCONST32 tglobaladdr:$src2)))),
504 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
506 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
507 (HexagonCONST32 tconstpool:$src3)))),
508 (MI IntRegs:$src1, u2ImmPred:$src2, tconstpool:$src3)>;
509 def : Pat <(VT (ldOp (add IntRegs:$src1,
510 (HexagonCONST32 tconstpool:$src2)))),
511 (MI IntRegs:$src1, 0, tconstpool:$src2)>;
513 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
514 (HexagonCONST32 tjumptable:$src3)))),
515 (MI IntRegs:$src1, u2ImmPred:$src2, tjumptable:$src3)>;
516 def : Pat <(VT (ldOp (add IntRegs:$src1,
517 (HexagonCONST32 tjumptable:$src2)))),
518 (MI IntRegs:$src1, 0, tjumptable:$src2)>;
521 let AddedComplexity = 60 in {
522 defm : T_LoadAbsReg_Pat <sextloadi8, L4_loadrb_ur>;
523 defm : T_LoadAbsReg_Pat <zextloadi8, L4_loadrub_ur>;
524 defm : T_LoadAbsReg_Pat <extloadi8, L4_loadrub_ur>;
526 defm : T_LoadAbsReg_Pat <sextloadi16, L4_loadrh_ur>;
527 defm : T_LoadAbsReg_Pat <zextloadi16, L4_loadruh_ur>;
528 defm : T_LoadAbsReg_Pat <extloadi16, L4_loadruh_ur>;
530 defm : T_LoadAbsReg_Pat <load, L4_loadri_ur>;
531 defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
534 //===----------------------------------------------------------------------===//
535 // Template classes for the non-predicated load instructions with
536 // base + register offset addressing mode
537 //===----------------------------------------------------------------------===//
538 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
539 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
540 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
541 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
549 let Inst{27-24} = 0b1010;
550 let Inst{23-21} = MajOp;
551 let Inst{20-16} = src1;
552 let Inst{12-8} = src2;
553 let Inst{13} = u2{1};
558 //===----------------------------------------------------------------------===//
559 // Template classes for the predicated load instructions with
560 // base + register offset addressing mode
561 //===----------------------------------------------------------------------===//
562 let isPredicated = 1 in
563 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
564 bit isNot, bit isPredNew>:
565 LDInst <(outs RC:$dst),
566 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
567 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
568 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
569 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
576 let isPredicatedFalse = isNot;
577 let isPredicatedNew = isPredNew;
581 let Inst{27-26} = 0b00;
582 let Inst{25} = isPredNew;
583 let Inst{24} = isNot;
584 let Inst{23-21} = MajOp;
585 let Inst{20-16} = src2;
586 let Inst{12-8} = src3;
587 let Inst{13} = u2{1};
589 let Inst{6-5} = src1;
593 //===----------------------------------------------------------------------===//
594 // multiclass for load instructions with base + register offset
596 //===----------------------------------------------------------------------===//
597 let hasSideEffects = 0, addrMode = BaseRegOffset in
598 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
600 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
601 InputType = "reg" in {
602 let isPredicable = 1 in
603 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
606 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
607 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
610 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
611 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
615 let hasNewValue = 1, accessSize = ByteAccess in {
616 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
617 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
620 let hasNewValue = 1, accessSize = HalfWordAccess in {
621 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
622 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
625 let hasNewValue = 1, accessSize = WordAccess in
626 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
628 let accessSize = DoubleWordAccess in
629 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
631 // 'def pats' for load instructions with base + register offset and non-zero
632 // immediate value. Immediate value is used to left-shift the second
634 class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
635 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
636 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
637 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
639 let AddedComplexity = 40 in {
640 def: Loadxs_pat<extloadi8, i32, L4_loadrub_rr>;
641 def: Loadxs_pat<zextloadi8, i32, L4_loadrub_rr>;
642 def: Loadxs_pat<sextloadi8, i32, L4_loadrb_rr>;
643 def: Loadxs_pat<extloadi16, i32, L4_loadruh_rr>;
644 def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
645 def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
646 def: Loadxs_pat<load, i32, L4_loadri_rr>;
647 def: Loadxs_pat<load, i64, L4_loadrd_rr>;
650 // 'def pats' for load instruction base + register offset and
651 // zero immediate value.
652 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
653 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
654 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
656 let AddedComplexity = 20 in {
657 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
658 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
659 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
660 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
661 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
662 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
663 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
664 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
668 def: Pat<(i64 (zext (i1 PredRegs:$src1))),
669 (Zext64 (C2_muxii PredRegs:$src1, 1, 0))>;
672 def: Pat<(i64 (zext (i32 IntRegs:$src1))),
673 (Zext64 IntRegs:$src1)>;
675 //===----------------------------------------------------------------------===//
677 //===----------------------------------------------------------------------===//
679 //===----------------------------------------------------------------------===//
681 //===----------------------------------------------------------------------===//
683 //===----------------------------------------------------------------------===//
684 // Template class for store instructions with Absolute set addressing mode.
685 //===----------------------------------------------------------------------===//
686 let isExtended = 1, opExtendable = 1, opExtentBits = 6,
687 addrMode = AbsoluteSet, isNVStorable = 1 in
688 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
689 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
690 : STInst<(outs IntRegs:$dst),
691 (ins u6Ext:$addr, RC:$src),
692 mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
696 let accessSize = AccessSz;
697 let BaseOpcode = BaseOp#"_AbsSet";
701 let Inst{27-24} = 0b1011;
702 let Inst{23-21} = MajOp;
703 let Inst{20-16} = dst;
705 let Inst{12-8} = src;
707 let Inst{5-0} = addr;
710 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
711 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
713 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
715 let isNVStorable = 0 in {
716 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
717 0b011, HalfWordAccess, 1>;
718 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
719 0b110, DoubleWordAccess>;
722 let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
723 isExtended = 1, opExtentBits= 6 in
724 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
725 MemAccessSize AccessSz >
726 : NVInst <(outs IntRegs:$dst),
727 (ins u6Ext:$addr, IntRegs:$src),
728 mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
732 let accessSize = AccessSz;
733 let BaseOpcode = BaseOp#"_AbsSet";
737 let Inst{27-21} = 0b1011101;
738 let Inst{20-16} = dst;
739 let Inst{13-11} = 0b000;
740 let Inst{12-11} = MajOp;
741 let Inst{10-8} = src;
743 let Inst{5-0} = addr;
746 let mayStore = 1, addrMode = AbsoluteSet in {
747 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
748 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
749 def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
752 let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
753 addrMode = BaseLongOffset, AddedComplexity = 40 in
754 class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
755 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
757 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
758 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
759 []>, ImmRegShl, NewValueRel {
766 let accessSize = AccessSz;
767 let CextOpcode = CextOp;
768 let BaseOpcode = CextOp#"_shl";
771 let Inst{27-24} =0b1101;
772 let Inst{23-21} = MajOp;
773 let Inst{20-16} = src1;
774 let Inst{13} = src2{1};
775 let Inst{12-8} = src4;
777 let Inst{6} = src2{0};
778 let Inst{5-0} = src3;
781 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
782 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
784 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
786 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
787 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
790 let AddedComplexity = 40 in
791 multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
793 def : Pat<(stOp (VT RC:$src4),
794 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
796 (MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
798 def : Pat<(stOp (VT RC:$src4),
799 (add (shl IntRegs:$src1, u2ImmPred:$src2),
800 (HexagonCONST32 tglobaladdr:$src3))),
801 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
803 def : Pat<(stOp (VT RC:$src4),
804 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
805 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
808 defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
809 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
810 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
811 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
813 let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
814 opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
815 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
816 MemAccessSize AccessSz>
818 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
819 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
825 let CextOpcode = CextOp;
826 let BaseOpcode = CextOp#"_shl";
829 let Inst{27-21} = 0b1101101;
830 let Inst{12-11} = 0b00;
832 let Inst{20-16} = src1;
833 let Inst{13} = src2{1};
834 let Inst{12-11} = MajOp;
835 let Inst{10-8} = src4;
836 let Inst{6} = src2{0};
837 let Inst{5-0} = src3;
840 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
841 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
842 def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
844 //===----------------------------------------------------------------------===//
845 // Template classes for the non-predicated store instructions with
846 // base + register offset addressing mode
847 //===----------------------------------------------------------------------===//
848 let isPredicable = 1 in
849 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
850 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
851 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
852 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
861 let Inst{27-24} = 0b1011;
862 let Inst{23-21} = MajOp;
863 let Inst{20-16} = Rs;
865 let Inst{13} = u2{1};
870 //===----------------------------------------------------------------------===//
871 // Template classes for the predicated store instructions with
872 // base + register offset addressing mode
873 //===----------------------------------------------------------------------===//
874 let isPredicated = 1 in
875 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
876 bit isNot, bit isPredNew, bit isH>
878 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
880 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
881 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
882 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
889 let isPredicatedFalse = isNot;
890 let isPredicatedNew = isPredNew;
894 let Inst{27-26} = 0b01;
895 let Inst{25} = isPredNew;
896 let Inst{24} = isNot;
897 let Inst{23-21} = MajOp;
898 let Inst{20-16} = Rs;
900 let Inst{13} = u2{1};
906 //===----------------------------------------------------------------------===//
907 // Template classes for the new-value store instructions with
908 // base + register offset addressing mode
909 //===----------------------------------------------------------------------===//
910 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
911 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
912 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
913 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
914 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
923 let Inst{27-21} = 0b1011101;
924 let Inst{20-16} = Rs;
926 let Inst{13} = u2{1};
928 let Inst{4-3} = MajOp;
932 //===----------------------------------------------------------------------===//
933 // Template classes for the predicated new-value store instructions with
934 // base + register offset addressing mode
935 //===----------------------------------------------------------------------===//
936 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
937 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
939 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
940 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
941 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
942 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
949 let isPredicatedFalse = isNot;
950 let isPredicatedNew = isPredNew;
953 let Inst{27-26} = 0b01;
954 let Inst{25} = isPredNew;
955 let Inst{24} = isNot;
956 let Inst{23-21} = 0b101;
957 let Inst{20-16} = Rs;
959 let Inst{13} = u2{1};
962 let Inst{4-3} = MajOp;
966 //===----------------------------------------------------------------------===//
967 // multiclass for store instructions with base + register offset addressing
969 //===----------------------------------------------------------------------===//
970 let isNVStorable = 1 in
971 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
972 bits<3> MajOp, bit isH = 0> {
973 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
974 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
977 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
978 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
981 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
982 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
986 //===----------------------------------------------------------------------===//
987 // multiclass for new-value store instructions with base + register offset
989 //===----------------------------------------------------------------------===//
990 let mayStore = 1, isNVStore = 1 in
991 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
993 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
994 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
997 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
998 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
1001 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
1002 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
1006 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
1007 let accessSize = ByteAccess in
1008 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1009 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1011 let accessSize = HalfWordAccess in
1012 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1013 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1015 let accessSize = WordAccess in
1016 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1017 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1019 let isNVStorable = 0, accessSize = DoubleWordAccess in
1020 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1022 let isNVStorable = 0, accessSize = HalfWordAccess in
1023 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1026 class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
1027 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1028 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1029 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1031 let AddedComplexity = 40 in {
1032 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1033 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1034 def: Storexs_pat<store, I32, S4_storeri_rr>;
1035 def: Storexs_pat<store, I64, S4_storerd_rr>;
1038 // memd(Rx++#s4:3)=Rtt
1039 // memd(Rx++#s4:3:circ(Mu))=Rtt
1040 // memd(Rx++I:circ(Mu))=Rtt
1042 // memd(Rx++Mu:brev)=Rtt
1043 // memd(gp+#u16:3)=Rtt
1045 // Store doubleword conditionally.
1046 // if ([!]Pv[.new]) memd(#u6)=Rtt
1047 // TODO: needs to be implemented.
1049 //===----------------------------------------------------------------------===//
1051 //===----------------------------------------------------------------------===//
1052 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1054 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1055 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1056 mnemonic#"($Rs+#$offset)=#$S8",
1057 [], "", V4LDST_tc_st_SLOT01>,
1058 ImmRegRel, PredNewRel {
1064 string OffsetOpStr = !cast<string>(OffsetOp);
1065 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1066 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1067 /* u6_0Imm */ offset{5-0}));
1069 let IClass = 0b0011;
1071 let Inst{27-25} = 0b110;
1072 let Inst{22-21} = MajOp;
1073 let Inst{20-16} = Rs;
1074 let Inst{12-7} = offsetBits;
1075 let Inst{13} = S8{7};
1076 let Inst{6-0} = S8{6-0};
1079 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
1081 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1082 bit isPredNot, bit isPredNew >
1084 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1085 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
1086 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1087 [], "", V4LDST_tc_st_SLOT01>,
1088 ImmRegRel, PredNewRel {
1095 string OffsetOpStr = !cast<string>(OffsetOp);
1096 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1097 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1098 /* u6_0Imm */ offset{5-0}));
1099 let isPredicatedNew = isPredNew;
1100 let isPredicatedFalse = isPredNot;
1102 let IClass = 0b0011;
1104 let Inst{27-25} = 0b100;
1105 let Inst{24} = isPredNew;
1106 let Inst{23} = isPredNot;
1107 let Inst{22-21} = MajOp;
1108 let Inst{20-16} = Rs;
1109 let Inst{13} = S6{5};
1110 let Inst{12-7} = offsetBits;
1112 let Inst{4-0} = S6{4-0};
1116 //===----------------------------------------------------------------------===//
1117 // multiclass for store instructions with base + immediate offset
1118 // addressing mode and immediate stored value.
1119 // mem[bhw](Rx++#s4:3)=#s8
1120 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1121 //===----------------------------------------------------------------------===//
1123 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1125 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1127 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1130 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1132 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1133 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1135 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1136 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1140 let hasSideEffects = 0, addrMode = BaseImmOffset,
1141 InputType = "imm" in {
1142 let accessSize = ByteAccess in
1143 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1145 let accessSize = HalfWordAccess in
1146 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1148 let accessSize = WordAccess in
1149 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1152 def IMM_BYTE : SDNodeXForm<imm, [{
1153 // -1 etc is represented as 255 etc
1154 // assigning to a byte restores our desired signed value.
1155 int8_t imm = N->getSExtValue();
1156 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
1159 def IMM_HALF : SDNodeXForm<imm, [{
1160 // -1 etc is represented as 65535 etc
1161 // assigning to a short restores our desired signed value.
1162 int16_t imm = N->getSExtValue();
1163 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
1166 def IMM_WORD : SDNodeXForm<imm, [{
1167 // -1 etc can be represented as 4294967295 etc
1168 // Currently, it's not doing this. But some optimization
1169 // might convert -1 to a large +ve number.
1170 // assigning to a word restores our desired signed value.
1171 int32_t imm = N->getSExtValue();
1172 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
1175 def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
1176 def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
1177 def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
1179 let AddedComplexity = 40 in {
1180 // Not using frameindex patterns for these stores, because the offset
1181 // is not extendable. This could cause problems during removing the frame
1182 // indices, since the offset with respect to R29/R30 may not fit in the
1184 def: Storexm_add_pat<truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
1186 def: Storexm_add_pat<truncstorei16, s32ImmPred, u6_1ImmPred, ToImmHalf,
1188 def: Storexm_add_pat<store, s32ImmPred, u6_2ImmPred, ToImmWord,
1192 def: Storexm_simple_pat<truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
1193 def: Storexm_simple_pat<truncstorei16, s32ImmPred, ToImmHalf, S4_storeirh_io>;
1194 def: Storexm_simple_pat<store, s32ImmPred, ToImmWord, S4_storeiri_io>;
1196 // memb(Rx++#s4:0:circ(Mu))=Rt
1197 // memb(Rx++I:circ(Mu))=Rt
1199 // memb(Rx++Mu:brev)=Rt
1200 // memb(gp+#u16:0)=Rt
1203 // TODO: needs to be implemented
1204 // memh(Re=#U6)=Rt.H
1205 // memh(Rs+#s11:1)=Rt.H
1206 // memh(Rs+Ru<<#u2)=Rt.H
1207 // TODO: needs to be implemented.
1209 // memh(Ru<<#u2+#U6)=Rt.H
1210 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1211 // memh(Rx++#s4:1:circ(Mu))=Rt
1212 // memh(Rx++I:circ(Mu))=Rt.H
1213 // memh(Rx++I:circ(Mu))=Rt
1214 // memh(Rx++Mu)=Rt.H
1216 // memh(Rx++Mu:brev)=Rt.H
1217 // memh(Rx++Mu:brev)=Rt
1218 // memh(gp+#u16:1)=Rt
1219 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1220 // if ([!]Pv[.new]) memh(#u6)=Rt
1222 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1223 // TODO: needs to be implemented.
1225 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1226 // TODO: Needs to be implemented.
1230 // TODO: Needs to be implemented.
1231 // memw(Rx++#s4:2)=Rt
1232 // memw(Rx++#s4:2:circ(Mu))=Rt
1233 // memw(Rx++I:circ(Mu))=Rt
1235 // memw(Rx++Mu:brev)=Rt
1237 //===----------------------------------------------------------------------===
1239 //===----------------------------------------------------------------------===
1242 //===----------------------------------------------------------------------===//
1244 //===----------------------------------------------------------------------===//
1246 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1247 class T_store_io_nv <string mnemonic, RegisterClass RC,
1248 Operand ImmOp, bits<2>MajOp>
1249 : NVInst_V4 <(outs),
1250 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1251 mnemonic#"($src1+#$src2) = $src3.new",
1252 [],"",ST_tc_st_SLOT0> {
1254 bits<13> src2; // Actual address offset
1256 bits<11> offsetBits; // Represents offset encoding
1258 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1259 !if (!eq(mnemonic, "memh"), 12,
1260 !if (!eq(mnemonic, "memw"), 13, 0)));
1262 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1263 !if (!eq(mnemonic, "memh"), 1,
1264 !if (!eq(mnemonic, "memw"), 2, 0)));
1266 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1267 !if (!eq(mnemonic, "memh"), src2{11-1},
1268 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1270 let IClass = 0b1010;
1273 let Inst{26-25} = offsetBits{10-9};
1274 let Inst{24-21} = 0b1101;
1275 let Inst{20-16} = src1;
1276 let Inst{13} = offsetBits{8};
1277 let Inst{12-11} = MajOp;
1278 let Inst{10-8} = src3;
1279 let Inst{7-0} = offsetBits{7-0};
1282 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1283 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1284 bits<2>MajOp, bit PredNot, bit isPredNew>
1285 : NVInst_V4 <(outs),
1286 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1287 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1288 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1289 [],"",V2LDST_tc_st_SLOT0> {
1294 bits<6> offsetBits; // Represents offset encoding
1296 let isPredicatedNew = isPredNew;
1297 let isPredicatedFalse = PredNot;
1298 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1299 !if (!eq(mnemonic, "memh"), 7,
1300 !if (!eq(mnemonic, "memw"), 8, 0)));
1302 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1303 !if (!eq(mnemonic, "memh"), 1,
1304 !if (!eq(mnemonic, "memw"), 2, 0)));
1306 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1307 !if (!eq(mnemonic, "memh"), src3{6-1},
1308 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1310 let IClass = 0b0100;
1313 let Inst{26} = PredNot;
1314 let Inst{25} = isPredNew;
1315 let Inst{24-21} = 0b0101;
1316 let Inst{20-16} = src2;
1317 let Inst{13} = offsetBits{5};
1318 let Inst{12-11} = MajOp;
1319 let Inst{10-8} = src4;
1320 let Inst{7-3} = offsetBits{4-0};
1322 let Inst{1-0} = src1;
1325 // multiclass for new-value store instructions with base + immediate offset.
1327 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1329 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1330 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1332 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1333 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1335 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1336 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1338 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1340 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1345 let addrMode = BaseImmOffset, InputType = "imm" in {
1346 let accessSize = ByteAccess in
1347 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1348 u6_0Ext, 0b00>, AddrModeRel;
1350 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1351 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1352 u6_1Ext, 0b01>, AddrModeRel;
1354 let accessSize = WordAccess, opExtentAlign = 2 in
1355 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1356 u6_2Ext, 0b10>, AddrModeRel;
1359 //===----------------------------------------------------------------------===//
1360 // Post increment loads with register offset.
1361 //===----------------------------------------------------------------------===//
1363 let hasNewValue = 1 in
1364 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1366 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1368 let hasSideEffects = 0, addrMode = PostInc in
1369 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1370 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1371 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1372 "$dst = "#mnemonic#"($src2++$src3)", [],
1373 "$src1 = $dst, $src2 = $_dst_"> {
1378 let accessSize = AccessSz;
1379 let IClass = 0b1001;
1381 let Inst{27-25} = 0b110;
1382 let Inst{24-21} = MajOp;
1383 let Inst{20-16} = src2;
1384 let Inst{13} = src3;
1387 let Inst{4-0} = dst;
1390 def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
1391 def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
1393 //===----------------------------------------------------------------------===//
1394 // Template class for non-predicated post increment .new stores
1395 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1396 //===----------------------------------------------------------------------===//
1397 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1398 isNewValue = 1, opNewValue = 3 in
1399 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1400 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1401 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1402 mnemonic#"($src1++#$offset) = $src2.new",
1403 [], "$src1 = $_dst_">,
1410 string ImmOpStr = !cast<string>(ImmOp);
1411 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1412 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1413 /* s4_0Imm */ offset{3-0}));
1414 let IClass = 0b1010;
1416 let Inst{27-21} = 0b1011101;
1417 let Inst{20-16} = src1;
1419 let Inst{12-11} = MajOp;
1420 let Inst{10-8} = src2;
1422 let Inst{6-3} = offsetBits;
1426 //===----------------------------------------------------------------------===//
1427 // Template class for predicated post increment .new stores
1428 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1429 //===----------------------------------------------------------------------===//
1430 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1431 isNewValue = 1, opNewValue = 4 in
1432 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1433 bits<2> MajOp, bit isPredNot, bit isPredNew >
1434 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1435 (ins PredRegs:$src1, IntRegs:$src2,
1436 ImmOp:$offset, IntRegs:$src3),
1437 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1438 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1439 [], "$src2 = $_dst_">,
1447 string ImmOpStr = !cast<string>(ImmOp);
1448 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1449 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1450 /* s4_0Imm */ offset{3-0}));
1451 let isPredicatedNew = isPredNew;
1452 let isPredicatedFalse = isPredNot;
1454 let IClass = 0b1010;
1456 let Inst{27-21} = 0b1011101;
1457 let Inst{20-16} = src2;
1459 let Inst{12-11} = MajOp;
1460 let Inst{10-8} = src3;
1461 let Inst{7} = isPredNew;
1462 let Inst{6-3} = offsetBits;
1463 let Inst{2} = isPredNot;
1464 let Inst{1-0} = src1;
1467 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1468 bits<2> MajOp, bit PredNot> {
1469 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1472 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1475 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1477 let BaseOpcode = "POST_"#BaseOp in {
1478 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1481 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1482 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1486 let accessSize = ByteAccess in
1487 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1489 let accessSize = HalfWordAccess in
1490 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1492 let accessSize = WordAccess in
1493 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1495 //===----------------------------------------------------------------------===//
1496 // Template class for post increment .new stores with register offset
1497 //===----------------------------------------------------------------------===//
1498 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1499 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1500 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1501 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1502 #mnemonic#"($src1++$src2) = $src3.new",
1503 [], "$src1 = $_dst_"> {
1507 let accessSize = AccessSz;
1509 let IClass = 0b1010;
1511 let Inst{27-21} = 0b1101101;
1512 let Inst{20-16} = src1;
1513 let Inst{13} = src2;
1514 let Inst{12-11} = MajOp;
1515 let Inst{10-8} = src3;
1519 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1520 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1521 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1523 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1524 // memb(Rx++I:circ(Mu))=Nt.new
1525 // memb(Rx++Mu:brev)=Nt.new
1526 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1527 // memh(Rx++I:circ(Mu))=Nt.new
1528 // memh(Rx++Mu)=Nt.new
1529 // memh(Rx++Mu:brev)=Nt.new
1531 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1532 // memw(Rx++I:circ(Mu))=Nt.new
1533 // memw(Rx++Mu)=Nt.new
1534 // memw(Rx++Mu:brev)=Nt.new
1536 //===----------------------------------------------------------------------===//
1538 //===----------------------------------------------------------------------===//
1540 //===----------------------------------------------------------------------===//
1542 //===----------------------------------------------------------------------===//
1544 //===----------------------------------------------------------------------===//
1545 // multiclass/template class for the new-value compare jumps with the register
1547 //===----------------------------------------------------------------------===//
1549 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1550 opExtentAlign = 2 in
1551 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1552 bit isNegCond, bit isTak>
1554 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1555 "if ("#!if(isNegCond, "!","")#mnemonic#
1556 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1557 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1558 #!if(isTak, "t","nt")#" $offset", []> {
1562 bits<3> Ns; // New-Value Operand
1563 bits<5> RegOp; // Non-New-Value Operand
1566 let isTaken = isTak;
1567 let isPredicatedFalse = isNegCond;
1568 let opNewValue{0} = NvOpNum;
1570 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1571 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1573 let IClass = 0b0010;
1574 let Inst{27-26} = 0b00;
1575 let Inst{25-23} = majOp;
1576 let Inst{22} = isNegCond;
1577 let Inst{18-16} = Ns;
1578 let Inst{13} = isTak;
1579 let Inst{12-8} = RegOp;
1580 let Inst{21-20} = offset{10-9};
1581 let Inst{7-1} = offset{8-2};
1585 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1587 // Branch not taken:
1588 def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1590 def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1593 // NvOpNum = 0 -> First Operand is a new-value Register
1594 // NvOpNum = 1 -> Second Operand is a new-value Register
1596 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1598 let BaseOpcode = BaseOp#_NVJ in {
1599 defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1600 defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1604 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1605 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1606 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1607 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1608 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1610 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1611 Defs = [PC], hasSideEffects = 0 in {
1612 defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1613 defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1614 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1615 defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1616 defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1619 //===----------------------------------------------------------------------===//
1620 // multiclass/template class for the new-value compare jumps instruction
1621 // with a register and an unsigned immediate (U5) operand.
1622 //===----------------------------------------------------------------------===//
1624 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1625 opExtentAlign = 2 in
1626 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1629 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1630 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1631 #!if(isTak, "t","nt")#" $offset", []> {
1633 let isTaken = isTak;
1634 let isPredicatedFalse = isNegCond;
1635 let isTaken = isTak;
1641 let IClass = 0b0010;
1643 let Inst{25-23} = majOp;
1644 let Inst{22} = isNegCond;
1645 let Inst{18-16} = src1;
1646 let Inst{13} = isTak;
1647 let Inst{12-8} = src2;
1648 let Inst{21-20} = offset{10-9};
1649 let Inst{7-1} = offset{8-2};
1652 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1653 // Branch not taken:
1654 def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1656 def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
1659 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1660 let BaseOpcode = BaseOp#_NVJri in {
1661 defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1662 defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1666 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1667 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1668 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1670 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1671 Defs = [PC], hasSideEffects = 0 in {
1672 defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1673 defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1674 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1677 //===----------------------------------------------------------------------===//
1678 // multiclass/template class for the new-value compare jumps instruction
1679 // with a register and an hardcoded 0/-1 immediate value.
1680 //===----------------------------------------------------------------------===//
1682 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1683 opExtentAlign = 2 in
1684 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1685 bit isNegCond, bit isTak>
1687 (ins IntRegs:$src1, brtarget:$offset),
1688 "if ("#!if(isNegCond, "!","")#mnemonic
1689 #"($src1.new, #"#ImmVal#")) jump:"
1690 #!if(isTak, "t","nt")#" $offset", []> {
1692 let isTaken = isTak;
1693 let isPredicatedFalse = isNegCond;
1694 let isTaken = isTak;
1698 let IClass = 0b0010;
1700 let Inst{25-23} = majOp;
1701 let Inst{22} = isNegCond;
1702 let Inst{18-16} = src1;
1703 let Inst{13} = isTak;
1704 let Inst{21-20} = offset{10-9};
1705 let Inst{7-1} = offset{8-2};
1708 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1710 // Branch not taken:
1711 def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1713 def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1716 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1718 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1719 defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1720 defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1724 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1725 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1726 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1728 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1729 Defs = [PC], hasSideEffects = 0 in {
1730 defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1731 defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1732 defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1735 // J4_hintjumpr: Hint indirect conditional jump.
1736 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
1737 def J4_hintjumpr: JRInst <
1742 let IClass = 0b0101;
1743 let Inst{27-21} = 0b0010101;
1744 let Inst{20-16} = Rs;
1747 //===----------------------------------------------------------------------===//
1749 //===----------------------------------------------------------------------===//
1751 //===----------------------------------------------------------------------===//
1753 //===----------------------------------------------------------------------===//
1756 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1757 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
1758 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1759 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1763 let IClass = 0b0110;
1764 let Inst{27-16} = 0b101001001001;
1765 let Inst{12-7} = u6;
1771 let hasSideEffects = 0 in
1772 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1773 : CRInst<(outs PredRegs:$Pd),
1774 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1775 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1776 !if (IsNeg,"!","") # "$Pu))",
1777 [], "", CR_tc_2early_SLOT23> {
1783 let IClass = 0b0110;
1784 let Inst{27-24} = 0b1011;
1785 let Inst{23} = IsNeg;
1786 let Inst{22-21} = OpBits;
1788 let Inst{17-16} = Ps;
1795 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1796 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1797 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1798 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1799 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1800 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1801 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1802 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1804 // op(Ps, op(Pt, Pu))
1805 class LogLog_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1806 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, I1:$Pu))),
1807 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1809 // op(Ps, op(Pt, ~Pu))
1810 class LogLogNot_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1811 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, (not I1:$Pu)))),
1812 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1814 def: LogLog_pat<and, and, C4_and_and>;
1815 def: LogLog_pat<and, or, C4_and_or>;
1816 def: LogLog_pat<or, and, C4_or_and>;
1817 def: LogLog_pat<or, or, C4_or_or>;
1819 def: LogLogNot_pat<and, and, C4_and_andn>;
1820 def: LogLogNot_pat<and, or, C4_and_orn>;
1821 def: LogLogNot_pat<or, and, C4_or_andn>;
1822 def: LogLogNot_pat<or, or, C4_or_orn>;
1824 //===----------------------------------------------------------------------===//
1825 // PIC: Support for PIC compilations. The patterns and SD nodes defined
1826 // below are needed to support code generation for PIC
1827 //===----------------------------------------------------------------------===//
1829 def SDT_HexagonPICAdd
1830 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1831 def SDT_HexagonGOTAdd
1832 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1834 def SDT_HexagonGOTAddInternal : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1835 def SDT_HexagonGOTAddInternalJT : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1836 def SDT_HexagonGOTAddInternalBA : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1838 def Hexagonpic_add : SDNode<"HexagonISD::PIC_ADD", SDT_HexagonPICAdd>;
1839 def Hexagonat_got : SDNode<"HexagonISD::AT_GOT", SDT_HexagonGOTAdd>;
1840 def Hexagongat_pcrel : SDNode<"HexagonISD::AT_PCREL",
1841 SDT_HexagonGOTAddInternal>;
1842 def Hexagongat_pcrel_jt : SDNode<"HexagonISD::AT_PCREL",
1843 SDT_HexagonGOTAddInternalJT>;
1844 def Hexagongat_pcrel_ba : SDNode<"HexagonISD::AT_PCREL",
1845 SDT_HexagonGOTAddInternalBA>;
1847 // PIC: Map from a block address computation to a PC-relative add
1848 def: Pat<(Hexagongat_pcrel_ba tblockaddress:$src1),
1849 (C4_addipc u32ImmPred:$src1)>;
1851 // PIC: Map from the computation to generate a GOT pointer to a PC-relative add
1852 def: Pat<(Hexagonpic_add texternalsym:$src1),
1853 (C4_addipc u32ImmPred:$src1)>;
1855 // PIC: Map from a jump table address computation to a PC-relative add
1856 def: Pat<(Hexagongat_pcrel_jt tjumptable:$src1),
1857 (C4_addipc u32ImmPred:$src1)>;
1859 // PIC: Map from a GOT-relative symbol reference to a load
1860 def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
1861 (L2_loadri_io IntRegs:$src1, s30_2ImmPred:$src2)>;
1863 // PIC: Map from a static symbol reference to a PC-relative add
1864 def: Pat<(Hexagongat_pcrel tglobaladdr:$src1),
1865 (C4_addipc u32ImmPred:$src1)>;
1867 //===----------------------------------------------------------------------===//
1869 //===----------------------------------------------------------------------===//
1871 //===----------------------------------------------------------------------===//
1873 //===----------------------------------------------------------------------===//
1875 // Logical with-not instructions.
1876 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1877 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1879 def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1880 (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1881 def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1882 (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1884 let hasNewValue = 1, hasSideEffects = 0 in
1885 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1886 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1891 let IClass = 0b1101;
1892 let Inst{27-21} = 0b0101111;
1893 let Inst{20-16} = Rs;
1894 let Inst{12-8} = Rt;
1898 // Add and accumulate.
1899 // Rd=add(Rs,add(Ru,#s6))
1900 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1902 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1903 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1904 "$Rd = add($Rs, add($Ru, #$s6))" ,
1905 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1906 (add (i32 IntRegs:$Ru), s16_16ImmPred:$s6)))],
1907 "", ALU64_tc_2_SLOT23> {
1913 let IClass = 0b1101;
1915 let Inst{27-23} = 0b10110;
1916 let Inst{22-21} = s6{5-4};
1917 let Inst{20-16} = Rs;
1918 let Inst{13} = s6{3};
1919 let Inst{12-8} = Rd;
1920 let Inst{7-5} = s6{2-0};
1924 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1925 opExtentBits = 6, opExtendable = 2 in
1926 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1927 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1928 "$Rd = add($Rs, sub(#$s6, $Ru))",
1929 [], "", ALU64_tc_2_SLOT23> {
1935 let IClass = 0b1101;
1937 let Inst{27-23} = 0b10111;
1938 let Inst{22-21} = s6{5-4};
1939 let Inst{20-16} = Rs;
1940 let Inst{13} = s6{3};
1941 let Inst{12-8} = Rd;
1942 let Inst{7-5} = s6{2-0};
1946 // Rd=add(Rs,sub(#s6,Ru))
1947 def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
1948 (i32 IntRegs:$src3))),
1949 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1951 // Rd=sub(add(Rs,#s6),Ru)
1952 def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
1953 (i32 IntRegs:$src3)),
1954 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1956 // Rd=add(sub(Rs,Ru),#s6)
1957 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1958 (s32ImmPred:$src2)),
1959 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1962 // Add or subtract doublewords with carry.
1964 // Rdd=add(Rss,Rtt,Px):carry
1966 // Rdd=sub(Rss,Rtt,Px):carry
1969 // Rdd=extract(Rss,#u6,#U6)
1970 // Rdd=extract(Rss,Rtt)
1971 // Rd=extract(Rs,Rtt)
1972 // Rd=extract(Rs,#u5,#U5)
1974 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1975 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1977 let hasNewValue = 1 in {
1978 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1979 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1982 // Complex add/sub halfwords/words
1983 let Defs = [USR_OVF] in {
1984 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1985 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1986 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1987 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1990 let Defs = [USR_OVF] in {
1991 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1992 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
1995 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in {
1996 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1997 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
2000 // Logical xor with xor accumulation.
2001 // Rxx^=xor(Rss,Rtt)
2002 let hasSideEffects = 0 in
2004 : SInst <(outs DoubleRegs:$Rxx),
2005 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2006 "$Rxx ^= xor($Rss, $Rtt)",
2007 [(set (i64 DoubleRegs:$Rxx),
2008 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
2009 (i64 DoubleRegs:$Rtt))))],
2010 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
2015 let IClass = 0b1100;
2017 let Inst{27-22} = 0b101010;
2018 let Inst{20-16} = Rss;
2019 let Inst{12-8} = Rtt;
2020 let Inst{7-5} = 0b000;
2021 let Inst{4-0} = Rxx;
2024 // Rotate and reduce bytes
2025 // Rdd=vrcrotate(Rss,Rt,#u2)
2026 let hasSideEffects = 0 in
2028 : SInst <(outs DoubleRegs:$Rdd),
2029 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2030 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
2031 [], "", S_3op_tc_3x_SLOT23> {
2037 let IClass = 0b1100;
2039 let Inst{27-22} = 0b001111;
2040 let Inst{20-16} = Rss;
2041 let Inst{13} = u2{1};
2042 let Inst{12-8} = Rt;
2043 let Inst{7-6} = 0b11;
2044 let Inst{5} = u2{0};
2045 let Inst{4-0} = Rdd;
2048 // Rotate and reduce bytes with accumulation
2049 // Rxx+=vrcrotate(Rss,Rt,#u2)
2050 let hasSideEffects = 0 in
2051 def S4_vrcrotate_acc
2052 : SInst <(outs DoubleRegs:$Rxx),
2053 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2054 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
2055 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2061 let IClass = 0b1100;
2063 let Inst{27-21} = 0b1011101;
2064 let Inst{20-16} = Rss;
2065 let Inst{13} = u2{1};
2066 let Inst{12-8} = Rt;
2067 let Inst{5} = u2{0};
2068 let Inst{4-0} = Rxx;
2071 // Vector reduce conditional negate halfwords
2072 let hasSideEffects = 0 in
2074 : SInst <(outs DoubleRegs:$Rxx),
2075 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2076 "$Rxx += vrcnegh($Rss, $Rt)", [],
2077 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2082 let IClass = 0b1100;
2084 let Inst{27-21} = 0b1011001;
2085 let Inst{20-16} = Rss;
2087 let Inst{12-8} = Rt;
2088 let Inst{7-5} = 0b111;
2089 let Inst{4-0} = Rxx;
2093 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
2095 // Arithmetic/Convergent round
2096 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
2098 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
2100 let Defs = [USR_OVF] in
2101 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
2103 // Logical-logical words.
2104 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
2105 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
2108 ALU64Inst<(outs IntRegs:$Rx),
2109 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2110 "$Rx = or($Ru, and($_src_, #$s10))" ,
2111 [(set (i32 IntRegs:$Rx),
2112 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
2113 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
2118 let IClass = 0b1101;
2120 let Inst{27-22} = 0b101001;
2121 let Inst{20-16} = Rx;
2122 let Inst{21} = s10{9};
2123 let Inst{13-5} = s10{8-0};
2127 // Miscellaneous ALU64 instructions.
2129 let hasNewValue = 1, hasSideEffects = 0 in
2130 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2131 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2136 let IClass = 0b1101;
2137 let Inst{27-21} = 0b0011111;
2138 let Inst{20-16} = Rs;
2139 let Inst{12-8} = Rt;
2140 let Inst{7-5} = 0b111;
2144 let hasSideEffects = 0 in
2145 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2146 (ins IntRegs:$Rs, IntRegs:$Rt),
2147 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2152 let IClass = 0b1101;
2153 let Inst{27-24} = 0b0100;
2155 let Inst{20-16} = Rs;
2156 let Inst{12-8} = Rt;
2160 let hasSideEffects = 0 in
2161 def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
2162 (ins IntRegs:$Rs, IntRegs:$Rt),
2163 "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
2168 let IClass = 0b1101;
2169 let Inst{27-24} = 0b0100;
2171 let Inst{20-16} = Rs;
2172 let Inst{12-8} = Rt;
2176 let hasNewValue = 1, hasSideEffects = 0 in
2177 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2178 (ins IntRegs:$Rs, IntRegs:$Rt),
2179 "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2184 let IClass = 0b1101;
2185 let Inst{27-21} = 0b0101100;
2186 let Inst{20-16} = Rs;
2187 let Inst{12-8} = Rt;
2192 let hasNewValue = 1, hasSideEffects = 0 in
2193 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2194 (ins IntRegs:$Rs, IntRegs:$Rt),
2195 "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2200 let IClass = 0b1101;
2201 let Inst{27-21} = 0b0101100;
2202 let Inst{20-16} = Rt;
2203 let Inst{12-8} = Rs;
2208 // Rx[&|]=xor(Rs,Rt)
2209 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
2210 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
2212 // Rx[&|^]=or(Rs,Rt)
2213 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
2215 let CextOpcode = "ORr_ORr" in
2216 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
2217 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
2219 // Rx[&|^]=and(Rs,Rt)
2220 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
2222 let CextOpcode = "ORr_ANDr" in
2223 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
2224 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
2226 // Rx[&|^]=and(Rs,~Rt)
2227 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
2228 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
2229 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
2231 def: T_MType_acc_pat2 <M4_or_xor, xor, or>;
2232 def: T_MType_acc_pat2 <M4_and_xor, xor, and>;
2233 def: T_MType_acc_pat2 <M4_or_and, and, or>;
2234 def: T_MType_acc_pat2 <M4_and_and, and, and>;
2235 def: T_MType_acc_pat2 <M4_xor_and, and, xor>;
2236 def: T_MType_acc_pat2 <M4_or_or, or, or>;
2237 def: T_MType_acc_pat2 <M4_and_or, or, and>;
2238 def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
2240 class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2241 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
2242 (not IntRegs:$src3)))),
2243 (i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
2245 def: T_MType_acc_pat3 <M4_or_andn, and, or>;
2246 def: T_MType_acc_pat3 <M4_and_andn, and, and>;
2247 def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
2249 // Compound or-or and or-and
2250 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
2251 opExtentBits = 10, opExtendable = 3 in
2252 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2253 : MInst_acc <(outs IntRegs:$Rx),
2254 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2255 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2256 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2257 (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
2258 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
2263 let IClass = 0b1101;
2265 let Inst{27-24} = 0b1010;
2266 let Inst{23-22} = MajOp;
2267 let Inst{20-16} = Rs;
2268 let Inst{21} = s10{9};
2269 let Inst{13-5} = s10{8-0};
2273 let CextOpcode = "ORr_ANDr" in
2274 def S4_or_andi : T_CompOR <"and", 0b00, and>;
2276 let CextOpcode = "ORr_ORr" in
2277 def S4_or_ori : T_CompOR <"or", 0b10, or>;
2280 // Rd=modwrap(Rs,Rt)
2282 // Rd=cround(Rs,#u5)
2284 // Rd=round(Rs,#u5)[:sat]
2285 // Rd=round(Rs,Rt)[:sat]
2286 // Vector reduce add unsigned halfwords
2287 // Rd=vraddh(Rss,Rtt)
2289 // Rdd=vaddb(Rss,Rtt)
2290 // Vector conditional negate
2291 // Rdd=vcnegh(Rss,Rt)
2292 // Rxx+=vrcnegh(Rss,Rt)
2293 // Vector maximum bytes
2294 // Rdd=vmaxb(Rtt,Rss)
2295 // Vector reduce maximum halfwords
2296 // Rxx=vrmaxh(Rss,Ru)
2297 // Rxx=vrmaxuh(Rss,Ru)
2298 // Vector reduce maximum words
2299 // Rxx=vrmaxuw(Rss,Ru)
2300 // Rxx=vrmaxw(Rss,Ru)
2301 // Vector minimum bytes
2302 // Rdd=vminb(Rtt,Rss)
2303 // Vector reduce minimum halfwords
2304 // Rxx=vrminh(Rss,Ru)
2305 // Rxx=vrminuh(Rss,Ru)
2306 // Vector reduce minimum words
2307 // Rxx=vrminuw(Rss,Ru)
2308 // Rxx=vrminw(Rss,Ru)
2309 // Vector subtract bytes
2310 // Rdd=vsubb(Rss,Rtt)
2312 //===----------------------------------------------------------------------===//
2314 //===----------------------------------------------------------------------===//
2316 //===----------------------------------------------------------------------===//
2318 //===----------------------------------------------------------------------===//
2321 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2324 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2325 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2326 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2328 // Count trailing zeros: 64-bit.
2329 def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>;
2330 def: Pat<(i32 (trunc (cttz_zero_undef I64:$Rss))), (S2_ct0p I64:$Rss)>;
2332 // Count trailing ones: 64-bit.
2333 def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
2334 def: Pat<(i32 (trunc (cttz_zero_undef (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
2336 // Define leading/trailing patterns that require zero-extensions to 64 bits.
2337 def: Pat<(i64 (ctlz I64:$Rss)), (Zext64 (S2_cl0p I64:$Rss))>;
2338 def: Pat<(i64 (ctlz_zero_undef I64:$Rss)), (Zext64 (S2_cl0p I64:$Rss))>;
2339 def: Pat<(i64 (cttz I64:$Rss)), (Zext64 (S2_ct0p I64:$Rss))>;
2340 def: Pat<(i64 (cttz_zero_undef I64:$Rss)), (Zext64 (S2_ct0p I64:$Rss))>;
2341 def: Pat<(i64 (ctlz (not I64:$Rss))), (Zext64 (S2_cl1p I64:$Rss))>;
2342 def: Pat<(i64 (ctlz_zero_undef (not I64:$Rss))), (Zext64 (S2_cl1p I64:$Rss))>;
2343 def: Pat<(i64 (cttz (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>;
2344 def: Pat<(i64 (cttz_zero_undef (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>;
2347 let hasSideEffects = 0, hasNewValue = 1 in
2348 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2349 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2353 let IClass = 0b1000;
2354 let Inst{27-24} = 0b1100;
2355 let Inst{23-21} = 0b001;
2356 let Inst{20-16} = Rs;
2357 let Inst{13-8} = s6;
2358 let Inst{7-5} = 0b000;
2362 let hasSideEffects = 0, hasNewValue = 1 in
2363 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2364 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2368 let IClass = 0b1000;
2369 let Inst{27-24} = 0b1000;
2370 let Inst{23-21} = 0b011;
2371 let Inst{20-16} = Rs;
2372 let Inst{13-8} = s6;
2373 let Inst{7-5} = 0b010;
2378 // Bit test/set/clear
2379 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2380 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2382 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2383 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2384 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2385 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2386 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2389 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2390 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2391 // if ([!]tstbit(...)) jump ...
2392 let AddedComplexity = 100 in
2393 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2394 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2396 let AddedComplexity = 100 in
2397 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2398 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2400 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2401 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2402 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2404 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2405 // represented as a compare against "value & 0xFF", which is an exact match
2406 // for cmpb (same for cmph). The patterns below do not contain any additional
2407 // complexity that would make them preferable, and if they were actually used
2408 // instead of cmpb/cmph, they would result in a compare against register that
2409 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2410 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2411 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2412 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2413 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2414 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2415 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2417 //===----------------------------------------------------------------------===//
2419 //===----------------------------------------------------------------------===//
2421 //===----------------------------------------------------------------------===//
2423 //===----------------------------------------------------------------------===//
2425 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2427 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2428 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2429 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2430 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2431 [(set (i32 IntRegs:$Rd),
2432 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2433 u32ImmPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2439 let IClass = 0b1101;
2441 let Inst{27-24} = 0b1000;
2442 let Inst{23} = U6{5};
2443 let Inst{22-21} = u6{5-4};
2444 let Inst{20-16} = Rs;
2445 let Inst{13} = u6{3};
2446 let Inst{12-8} = Rd;
2447 let Inst{7-5} = u6{2-0};
2448 let Inst{4-0} = U6{4-0};
2451 // Rd=add(#u6,mpyi(Rs,Rt))
2452 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2453 isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2454 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2455 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2456 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2457 [(set (i32 IntRegs:$Rd),
2458 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
2459 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2465 let IClass = 0b1101;
2467 let Inst{27-23} = 0b01110;
2468 let Inst{22-21} = u6{5-4};
2469 let Inst{20-16} = Rs;
2470 let Inst{13} = u6{3};
2471 let Inst{12-8} = Rt;
2472 let Inst{7-5} = u6{2-0};
2476 let hasNewValue = 1 in
2477 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2478 : ALU64Inst <(outs IntRegs:$dst), ins,
2479 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2481 [(set (i32 IntRegs:$dst),
2482 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2483 "", ALU64_tc_3x_SLOT23> {
2489 let IClass = 0b1101;
2491 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2493 let Inst{27-24} = 0b1111;
2494 let Inst{23} = MajOp;
2495 let Inst{22-21} = ImmValue{5-4};
2496 let Inst{20-16} = src3;
2497 let Inst{13} = ImmValue{3};
2498 let Inst{12-8} = dst;
2499 let Inst{7-5} = ImmValue{2-0};
2500 let Inst{4-0} = src1;
2503 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2504 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2506 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2507 CextOpcode = "ADD_MPY", InputType = "imm" in
2508 def M4_mpyri_addr : T_AddMpy<0b1, u32ImmPred,
2509 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2511 // Rx=add(Ru,mpyi(Rx,Rs))
2512 let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
2513 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2514 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2515 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2516 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2517 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2518 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2523 let IClass = 0b1110;
2525 let Inst{27-21} = 0b0011000;
2526 let Inst{12-8} = Rx;
2528 let Inst{20-16} = Rs;
2532 // Vector reduce multiply word by signed half (32x16)
2533 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2534 def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
2535 def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
2537 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2538 def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
2539 def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
2541 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
2542 def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
2543 def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
2545 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2546 def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
2547 def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
2549 // Vector multiply halfwords, signed by unsigned
2550 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2551 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
2552 def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
2554 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2555 def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
2556 def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
2558 // Vector polynomial multiply halfwords
2559 // Rdd=vpmpyh(Rs,Rt)
2560 def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
2562 // Rxx^=vpmpyh(Rs,Rt)
2563 def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
2565 // Polynomial multiply words
2567 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2569 // Rxx^=pmpyw(Rs,Rt)
2570 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2572 //===----------------------------------------------------------------------===//
2574 //===----------------------------------------------------------------------===//
2576 //===----------------------------------------------------------------------===//
2577 // ALU64/Vector compare
2578 //===----------------------------------------------------------------------===//
2579 //===----------------------------------------------------------------------===//
2580 // Template class for vector compare
2581 //===----------------------------------------------------------------------===//
2583 let hasSideEffects = 0 in
2584 class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
2585 : ALU64_rr <(outs PredRegs:$Pd),
2586 (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
2587 "$Pd = "#Str#"($Rss, #$Imm)",
2588 [], "", ALU64_tc_2early_SLOT23> {
2593 let ImmBits{6-0} = Imm{6-0};
2594 let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
2596 let IClass = 0b1101;
2598 let Inst{27-24} = 0b1100;
2599 let Inst{22-21} = cmpOp;
2600 let Inst{20-16} = Rss;
2601 let Inst{12-5} = ImmBits;
2602 let Inst{4-3} = minOp;
2606 // Vector compare bytes
2607 def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
2608 def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
2610 let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
2611 def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
2613 def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
2614 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2615 def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
2617 // Vector compare halfwords
2618 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2619 def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
2620 def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
2622 // Vector compare words
2623 def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
2624 def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
2625 def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
2627 //===----------------------------------------------------------------------===//
2629 //===----------------------------------------------------------------------===//
2630 // Shift by immediate and accumulate/logical.
2631 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2632 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2633 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2634 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2635 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2636 hasNewValue = 1, opNewValue = 0 in
2637 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2638 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2639 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2640 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2641 [(set (i32 IntRegs:$Rd),
2642 (Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))],
2643 "$Rd = $Rx", Itin> {
2650 let IClass = 0b1101;
2651 let Inst{27-24} = 0b1110;
2652 let Inst{23-21} = u8{7-5};
2653 let Inst{20-16} = Rd;
2654 let Inst{13} = u8{4};
2655 let Inst{12-8} = U5;
2656 let Inst{7-5} = u8{3-1};
2657 let Inst{4} = asl_lsr;
2658 let Inst{3} = u8{0};
2659 let Inst{2-1} = MajOp;
2662 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2663 InstrItinClass Itin> {
2664 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2665 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2668 let AddedComplexity = 200 in {
2669 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2670 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2673 let AddedComplexity = 30 in
2674 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2676 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2678 let AddedComplexity = 200 in {
2679 def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2680 (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2681 def: Pat<(add addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2682 (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2683 def: Pat<(sub addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2684 (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2685 def: Pat<(sub addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2686 (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2689 // Vector conditional negate
2690 // Rdd=vcnegh(Rss,Rt)
2691 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2692 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2694 // Rd=[cround|round](Rs,Rt)
2695 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in {
2696 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2697 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2700 // Rd=round(Rs,Rt):sat
2701 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2702 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2704 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2705 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
2706 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2707 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2710 // Rdd=[add|sub](Rss,Rtt,Px):carry
2711 let isPredicateLate = 1, hasSideEffects = 0 in
2712 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2713 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2714 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2715 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2716 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2722 let IClass = 0b1100;
2724 let Inst{27-24} = 0b0010;
2725 let Inst{23-21} = MajOp;
2726 let Inst{20-16} = Rss;
2727 let Inst{12-8} = Rtt;
2729 let Inst{4-0} = Rdd;
2732 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2733 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2735 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2736 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2737 : SInst <(outs DoubleRegs:$Rxx),
2738 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2739 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2740 [] , "$dst2 = $Rxx"> {
2745 let IClass = 0b1100;
2747 let Inst{27-21} = 0b1011001;
2748 let Inst{20-16} = Rss;
2749 let Inst{13} = isUnsigned;
2750 let Inst{12-8} = Rxx;
2751 let Inst{7-5} = MinOp;
2755 // Vector reduce maximum halfwords
2756 // Rxx=vrmax[u]h(Rss,Ru)
2757 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2758 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2760 // Vector reduce maximum words
2761 // Rxx=vrmax[u]w(Rss,Ru)
2762 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2763 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2765 // Vector reduce minimum halfwords
2766 // Rxx=vrmin[u]h(Rss,Ru)
2767 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2768 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2770 // Vector reduce minimum words
2771 // Rxx=vrmin[u]w(Rss,Ru)
2772 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2773 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2775 // Shift an immediate left by register amount.
2776 let hasNewValue = 1, hasSideEffects = 0 in
2777 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2778 "$Rd = lsl(#$s6, $Rt)" ,
2779 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2780 (i32 IntRegs:$Rt)))],
2781 "", S_3op_tc_1_SLOT23> {
2786 let IClass = 0b1100;
2788 let Inst{27-22} = 0b011010;
2789 let Inst{20-16} = s6{5-1};
2790 let Inst{12-8} = Rt;
2791 let Inst{7-6} = 0b11;
2793 let Inst{5} = s6{0};
2796 //===----------------------------------------------------------------------===//
2798 //===----------------------------------------------------------------------===//
2800 //===----------------------------------------------------------------------===//
2801 // MEMOP: Word, Half, Byte
2802 //===----------------------------------------------------------------------===//
2804 def MEMOPIMM : SDNodeXForm<imm, [{
2805 // Call the transformation function XformM5ToU5Imm to get the negative
2806 // immediate's positive counterpart.
2807 int32_t imm = N->getSExtValue();
2808 return XformM5ToU5Imm(imm, SDLoc(N));
2811 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2812 // -1 .. -31 represented as 65535..65515
2813 // assigning to a short restores our desired signed value.
2814 // Call the transformation function XformM5ToU5Imm to get the negative
2815 // immediate's positive counterpart.
2816 int16_t imm = N->getSExtValue();
2817 return XformM5ToU5Imm(imm, SDLoc(N));
2820 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2821 // -1 .. -31 represented as 255..235
2822 // assigning to a char restores our desired signed value.
2823 // Call the transformation function XformM5ToU5Imm to get the negative
2824 // immediate's positive counterpart.
2825 int8_t imm = N->getSExtValue();
2826 return XformM5ToU5Imm(imm, SDLoc(N));
2829 def SETMEMIMM : SDNodeXForm<imm, [{
2830 // Return the bit position we will set [0-31].
2832 int32_t imm = N->getSExtValue();
2833 return XformMskToBitPosU5Imm(imm, SDLoc(N));
2836 def CLRMEMIMM : SDNodeXForm<imm, [{
2837 // Return the bit position we will clear [0-31].
2839 // we bit negate the value first
2840 int32_t imm = ~(N->getSExtValue());
2841 return XformMskToBitPosU5Imm(imm, SDLoc(N));
2844 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2845 // Return the bit position we will set [0-15].
2847 int16_t imm = N->getSExtValue();
2848 return XformMskToBitPosU4Imm(imm, SDLoc(N));
2851 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2852 // Return the bit position we will clear [0-15].
2854 // we bit negate the value first
2855 int16_t imm = ~(N->getSExtValue());
2856 return XformMskToBitPosU4Imm(imm, SDLoc(N));
2859 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2860 // Return the bit position we will set [0-7].
2862 int8_t imm = N->getSExtValue();
2863 return XformMskToBitPosU3Imm(imm, SDLoc(N));
2866 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2867 // Return the bit position we will clear [0-7].
2869 // we bit negate the value first
2870 int8_t imm = ~(N->getSExtValue());
2871 return XformMskToBitPosU3Imm(imm, SDLoc(N));
2874 //===----------------------------------------------------------------------===//
2875 // Template class for MemOp instructions with the register value.
2876 //===----------------------------------------------------------------------===//
2877 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2878 string memOp, bits<2> memOpBits> :
2880 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2881 opc#"($base+#$offset)"#memOp#"$delta",
2883 Requires<[UseMEMOP]> {
2888 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2890 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2891 !if (!eq(opcBits, 0b01), offset{6-1},
2892 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2894 let opExtentAlign = opcBits;
2895 let IClass = 0b0011;
2896 let Inst{27-24} = 0b1110;
2897 let Inst{22-21} = opcBits;
2898 let Inst{20-16} = base;
2900 let Inst{12-7} = offsetBits;
2901 let Inst{6-5} = memOpBits;
2902 let Inst{4-0} = delta;
2905 //===----------------------------------------------------------------------===//
2906 // Template class for MemOp instructions with the immediate value.
2907 //===----------------------------------------------------------------------===//
2908 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2909 string memOp, bits<2> memOpBits> :
2911 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2912 opc#"($base+#$offset)"#memOp#"#$delta"
2913 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2915 Requires<[UseMEMOP]> {
2920 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2922 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2923 !if (!eq(opcBits, 0b01), offset{6-1},
2924 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2926 let opExtentAlign = opcBits;
2927 let IClass = 0b0011;
2928 let Inst{27-24} = 0b1111;
2929 let Inst{22-21} = opcBits;
2930 let Inst{20-16} = base;
2932 let Inst{12-7} = offsetBits;
2933 let Inst{6-5} = memOpBits;
2934 let Inst{4-0} = delta;
2937 // multiclass to define MemOp instructions with register operand.
2938 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2939 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2940 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2941 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2942 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2945 // multiclass to define MemOp instructions with immediate Operand.
2946 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2947 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2948 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2949 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2950 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2953 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2954 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2955 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2958 // Define MemOp instructions.
2959 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
2960 let opExtentBits = 6, accessSize = ByteAccess in
2961 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2963 let opExtentBits = 7, accessSize = HalfWordAccess in
2964 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2966 let opExtentBits = 8, accessSize = WordAccess in
2967 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2970 //===----------------------------------------------------------------------===//
2971 // Multiclass to define 'Def Pats' for ALU operations on the memory
2972 // Here value used for the ALU operation is an immediate value.
2973 // mem[bh](Rs+#0) += #U5
2974 // mem[bh](Rs+#u6) += #U5
2975 //===----------------------------------------------------------------------===//
2977 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
2978 InstHexagon MI, SDNode OpNode> {
2979 let AddedComplexity = 180 in
2980 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2982 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
2984 let AddedComplexity = 190 in
2985 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
2987 (add IntRegs:$base, ImmPred:$offset)),
2988 (MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
2991 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
2992 InstHexagon addMI, InstHexagon subMI> {
2993 defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, addMI, add>;
2994 defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, subMI, sub>;
2997 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2999 defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
3000 L4_iadd_memoph_io, L4_isub_memoph_io>;
3002 defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u32ImmPred,
3003 L4_iadd_memopb_io, L4_isub_memopb_io>;
3006 let Predicates = [UseMEMOP] in {
3007 defm: MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
3008 defm: MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
3009 defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
3012 defm: MemOpi_u5ALUOp <load, store, u30_2ImmPred, L4_iadd_memopw_io,
3016 //===----------------------------------------------------------------------===//
3017 // multiclass to define 'Def Pats' for ALU operations on the memory.
3018 // Here value used for the ALU operation is a negative value.
3019 // mem[bh](Rs+#0) += #m5
3020 // mem[bh](Rs+#u6) += #m5
3021 //===----------------------------------------------------------------------===//
3023 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
3024 PatLeaf immPred, SDNodeXForm xformFunc,
3026 let AddedComplexity = 190 in
3027 def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
3028 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
3030 let AddedComplexity = 195 in
3031 def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
3033 (add IntRegs:$base, ImmPred:$offset)),
3034 (MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
3037 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3039 defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u31_1ImmPred, m5HImmPred,
3040 MEMOPIMM_HALF, L4_isub_memoph_io>;
3042 defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u32ImmPred, m5BImmPred,
3043 MEMOPIMM_BYTE, L4_isub_memopb_io>;
3046 let Predicates = [UseMEMOP] in {
3047 defm: MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
3048 defm: MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
3049 defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
3052 defm: MemOpi_m5Pats <load, store, u30_2ImmPred, m5ImmPred,
3053 MEMOPIMM, L4_isub_memopw_io>;
3056 //===----------------------------------------------------------------------===//
3057 // Multiclass to define 'def Pats' for bit operations on the memory.
3058 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3059 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
3060 //===----------------------------------------------------------------------===//
3062 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
3063 PatLeaf extPred, SDNodeXForm xformFunc, InstHexagon MI,
3066 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
3067 let AddedComplexity = 250 in
3068 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3070 (add IntRegs:$base, extPred:$offset)),
3071 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
3073 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3074 let AddedComplexity = 225 in
3075 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
3076 (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
3079 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
3081 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u32ImmPred,
3082 CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
3084 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u32ImmPred,
3085 SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
3086 // Half Word - clrbit
3087 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u31_1ImmPred,
3088 CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
3089 // Half Word - setbit
3090 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u31_1ImmPred,
3091 SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
3094 let Predicates = [UseMEMOP] in {
3095 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
3096 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
3097 defm: MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
3098 defm: MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
3099 defm: MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
3101 // memw(Rs+#0) = [clrbit|setbit](#U5)
3102 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
3103 defm: MemOpi_bitPats<load, store, Clr5ImmPred, u30_2ImmPred, CLRMEMIMM,
3104 L4_iand_memopw_io, and>;
3105 defm: MemOpi_bitPats<load, store, Set5ImmPred, u30_2ImmPred, SETMEMIMM,
3106 L4_ior_memopw_io, or>;
3109 //===----------------------------------------------------------------------===//
3110 // Multiclass to define 'def Pats' for ALU operations on the memory
3111 // where addend is a register.
3112 // mem[bhw](Rs+#0) [+-&|]= Rt
3113 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3114 //===----------------------------------------------------------------------===//
3116 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3117 InstHexagon MI, SDNode OpNode> {
3118 let AddedComplexity = 141 in
3119 // mem[bhw](Rs+#0) [+-&|]= Rt
3120 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
3122 (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
3124 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3125 let AddedComplexity = 150 in
3126 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3127 (i32 IntRegs:$orend)),
3128 (add IntRegs:$base, extPred:$offset)),
3129 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
3132 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3133 InstHexagon addMI, InstHexagon subMI,
3134 InstHexagon andMI, InstHexagon orMI> {
3135 defm: MemOpr_Pats <ldOp, stOp, extPred, addMI, add>;
3136 defm: MemOpr_Pats <ldOp, stOp, extPred, subMI, sub>;
3137 defm: MemOpr_Pats <ldOp, stOp, extPred, andMI, and>;
3138 defm: MemOpr_Pats <ldOp, stOp, extPred, orMI, or>;
3141 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3143 defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
3144 L4_add_memoph_io, L4_sub_memoph_io,
3145 L4_and_memoph_io, L4_or_memoph_io>;
3147 defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u32ImmPred,
3148 L4_add_memopb_io, L4_sub_memopb_io,
3149 L4_and_memopb_io, L4_or_memopb_io>;
3152 // Define 'def Pats' for MemOps with register addend.
3153 let Predicates = [UseMEMOP] in {
3155 defm: MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
3156 defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
3157 defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
3159 defm: MemOPr_ALUOp <load, store, u30_2ImmPred, L4_add_memopw_io,
3160 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
3163 //===----------------------------------------------------------------------===//
3165 //===----------------------------------------------------------------------===//
3167 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3168 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3169 // hardware. However, compiler can still implement these patterns through
3170 // appropriate patterns combinations based on current implemented patterns.
3171 // The implemented patterns are: EQ/GT/GTU.
3172 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3174 // Following instruction is not being extended as it results into the
3175 // incorrect code for negative numbers.
3176 // Pd=cmpb.eq(Rs,#u8)
3178 // p=!cmp.eq(r1,#s10)
3179 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
3180 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
3181 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
3183 def : T_CMP_pat <C4_cmpneqi, setne, s32ImmPred>;
3184 def : T_CMP_pat <C4_cmpltei, setle, s32ImmPred>;
3185 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
3187 // rs <= rt -> !(rs > rt).
3189 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
3190 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
3191 // (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
3193 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3194 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
3195 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
3197 // rs != rt -> !(rs == rt).
3198 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
3199 (C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
3201 // SDNode for converting immediate C to C-1.
3202 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
3203 // Return the byte immediate const-1 as an SDNode.
3204 int32_t imm = N->getSExtValue();
3205 return XformU7ToU7M1Imm(imm, SDLoc(N));
3209 // zext( setult ( and(Rs, 255), u8))
3210 // Use the isdigit transformation below
3212 // Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
3213 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3214 // The isdigit transformation relies on two 'clever' aspects:
3215 // 1) The data type is unsigned which allows us to eliminate a zero test after
3216 // biasing the expression by 48. We are depending on the representation of
3217 // the unsigned types, and semantics.
3218 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3221 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3222 // The code is transformed upstream of llvm into
3223 // retval = (c-48) < 10 ? 1 : 0;
3224 let AddedComplexity = 139 in
3225 def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3226 u7StrictPosImmPred:$src2)))),
3227 (C2_muxii (A4_cmpbgtui IntRegs:$src1,
3228 (DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
3231 //===----------------------------------------------------------------------===//
3233 //===----------------------------------------------------------------------===//
3235 //===----------------------------------------------------------------------===//
3236 // Multiclass for DeallocReturn
3237 //===----------------------------------------------------------------------===//
3238 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3239 : LD0Inst<(outs), (ins PredRegs:$src),
3240 !if(isNot, "if (!$src", "if ($src")#
3241 !if(isPredNew, ".new) ", ") ")#mnemonic#
3242 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3243 [], "", LD_tc_3or4stall_SLOT0> {
3246 let BaseOpcode = "L4_RETURN";
3247 let isPredicatedFalse = isNot;
3248 let isPredicatedNew = isPredNew;
3249 let isTaken = isTak;
3250 let IClass = 0b1001;
3252 let Inst{27-16} = 0b011000011110;
3254 let Inst{13} = isNot;
3255 let Inst{12} = isTak;
3256 let Inst{11} = isPredNew;
3258 let Inst{9-8} = src;
3259 let Inst{4-0} = 0b11110;
3262 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3263 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3264 let isPredicated = 1 in {
3265 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3266 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3267 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3271 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3272 let isBarrier = 1, isPredicable = 1 in
3273 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3274 LD_tc_3or4stall_SLOT0> {
3275 let BaseOpcode = "L4_RETURN";
3276 let IClass = 0b1001;
3277 let Inst{27-16} = 0b011000011110;
3278 let Inst{13-10} = 0b0000;
3279 let Inst{4-0} = 0b11110;
3281 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3282 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3285 let isReturn = 1, isTerminator = 1,
3286 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
3287 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3289 // Restore registers and dealloc return function call.
3290 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3291 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3292 def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
3295 // Restore registers and dealloc frame before a tail call.
3296 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
3297 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
3300 // Save registers function call.
3301 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
3302 def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
3305 //===----------------------------------------------------------------------===//
3306 // Template class for non predicated store instructions with
3307 // GP-Relative or absolute addressing.
3308 //===----------------------------------------------------------------------===//
3309 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3310 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3311 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3312 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3313 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3314 [], "", V2LDST_tc_st_SLOT01> {
3317 bits<16> offsetBits;
3319 string ImmOpStr = !cast<string>(ImmOp);
3320 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3321 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3322 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3323 /* u16_0Imm */ addr{15-0})));
3324 let IClass = 0b0100;
3326 let Inst{26-25} = offsetBits{15-14};
3328 let Inst{23-22} = MajOp;
3329 let Inst{21} = isHalf;
3330 let Inst{20-16} = offsetBits{13-9};
3331 let Inst{13} = offsetBits{8};
3332 let Inst{12-8} = src;
3333 let Inst{7-0} = offsetBits{7-0};
3336 //===----------------------------------------------------------------------===//
3337 // Template class for predicated store instructions with
3338 // GP-Relative or absolute addressing.
3339 //===----------------------------------------------------------------------===//
3340 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3342 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3343 bit isHalf, bit isNot, bit isNew>
3344 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3345 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3346 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3347 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3352 let isPredicatedNew = isNew;
3353 let isPredicatedFalse = isNot;
3355 let IClass = 0b1010;
3357 let Inst{27-24} = 0b1111;
3358 let Inst{23-22} = MajOp;
3359 let Inst{21} = isHalf;
3360 let Inst{17-16} = absaddr{5-4};
3361 let Inst{13} = isNew;
3362 let Inst{12-8} = src2;
3364 let Inst{6-3} = absaddr{3-0};
3365 let Inst{2} = isNot;
3366 let Inst{1-0} = src1;
3369 //===----------------------------------------------------------------------===//
3370 // Template class for predicated store instructions with absolute addressing.
3371 //===----------------------------------------------------------------------===//
3372 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3373 bits<2> MajOp, bit isHalf>
3374 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1, isHalf>,
3376 string ImmOpStr = !cast<string>(ImmOp);
3377 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3378 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3379 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3380 /* u16_0Imm */ 16)));
3382 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3383 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3384 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3385 /* u16_0Imm */ 0)));
3388 //===----------------------------------------------------------------------===//
3389 // Multiclass for store instructions with absolute addressing.
3390 //===----------------------------------------------------------------------===//
3391 let addrMode = Absolute, isExtended = 1 in
3392 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3393 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3394 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3395 let opExtendable = 0, isPredicable = 1 in
3396 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3399 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3400 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3403 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3404 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3408 //===----------------------------------------------------------------------===//
3409 // Template class for non predicated new-value store instructions with
3410 // GP-Relative or absolute addressing.
3411 //===----------------------------------------------------------------------===//
3412 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3413 isNewValue = 1, opNewValue = 1 in
3414 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3415 : NVInst_V4<(outs), (ins u32Imm:$addr, IntRegs:$src),
3416 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3417 [], "", V2LDST_tc_st_SLOT0> {
3420 bits<16> offsetBits;
3422 string ImmOpStr = !cast<string>(ImmOp);
3423 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3424 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3425 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3426 /* u16_0Imm */ addr{15-0})));
3427 let IClass = 0b0100;
3430 let Inst{26-25} = offsetBits{15-14};
3431 let Inst{24-21} = 0b0101;
3432 let Inst{20-16} = offsetBits{13-9};
3433 let Inst{13} = offsetBits{8};
3434 let Inst{12-11} = MajOp;
3435 let Inst{10-8} = src;
3436 let Inst{7-0} = offsetBits{7-0};
3439 //===----------------------------------------------------------------------===//
3440 // Template class for predicated new-value store instructions with
3441 // absolute addressing.
3442 //===----------------------------------------------------------------------===//
3443 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3444 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3445 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3446 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3447 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3448 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3449 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3454 let isPredicatedNew = isNew;
3455 let isPredicatedFalse = isNot;
3457 let IClass = 0b1010;
3459 let Inst{27-24} = 0b1111;
3460 let Inst{23-21} = 0b101;
3461 let Inst{17-16} = absaddr{5-4};
3462 let Inst{13} = isNew;
3463 let Inst{12-11} = MajOp;
3464 let Inst{10-8} = src2;
3466 let Inst{6-3} = absaddr{3-0};
3467 let Inst{2} = isNot;
3468 let Inst{1-0} = src1;
3471 //===----------------------------------------------------------------------===//
3472 // Template class for non-predicated new-value store instructions with
3473 // absolute addressing.
3474 //===----------------------------------------------------------------------===//
3475 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3476 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3478 string ImmOpStr = !cast<string>(ImmOp);
3479 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3480 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3481 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3482 /* u16_0Imm */ 16)));
3484 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3485 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3486 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3487 /* u16_0Imm */ 0)));
3490 //===----------------------------------------------------------------------===//
3491 // Multiclass for new-value store instructions with absolute addressing.
3492 //===----------------------------------------------------------------------===//
3493 let addrMode = Absolute, isExtended = 1 in
3494 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3496 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3497 let opExtendable = 0, isPredicable = 1 in
3498 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3501 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3502 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3505 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3506 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3510 //===----------------------------------------------------------------------===//
3511 // Stores with absolute addressing
3512 //===----------------------------------------------------------------------===//
3513 let accessSize = ByteAccess in
3514 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3515 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3517 let accessSize = HalfWordAccess in
3518 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3519 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3521 let accessSize = WordAccess in
3522 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3523 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3525 let isNVStorable = 0, accessSize = DoubleWordAccess in
3526 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3528 let isNVStorable = 0, accessSize = HalfWordAccess in
3529 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3531 //===----------------------------------------------------------------------===//
3532 // GP-relative stores.
3533 // mem[bhwd](#global)=Rt
3534 // Once predicated, these instructions map to absolute addressing mode.
3535 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3536 //===----------------------------------------------------------------------===//
3538 let isAsmParserOnly = 1 in
3539 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3540 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3541 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3542 // Set BaseOpcode same as absolute addressing instructions so that
3543 // non-predicated GP-Rel instructions can have relate with predicated
3544 // Absolute instruction.
3545 let BaseOpcode = BaseOp#_abs;
3548 let isAsmParserOnly = 1 in
3549 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3550 bits<2> MajOp, bit isHalf = 0> {
3551 // Set BaseOpcode same as absolute addressing instructions so that
3552 // non-predicated GP-Rel instructions can have relate with predicated
3553 // Absolute instruction.
3554 let BaseOpcode = BaseOp#_abs in {
3555 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3556 globaladdress, 0, isHalf>;
3558 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3562 let accessSize = ByteAccess in
3563 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3565 let accessSize = HalfWordAccess in
3566 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3568 let accessSize = WordAccess in
3569 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3571 let isNVStorable = 0, accessSize = DoubleWordAccess in
3572 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3573 u16_3Imm, 0b11>, PredNewRel;
3575 let isNVStorable = 0, accessSize = HalfWordAccess in
3576 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3577 u16_1Imm, 0b01, 1>, PredNewRel;
3579 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
3580 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
3582 class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
3584 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
3586 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
3587 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
3589 class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
3591 : Pat<(Store Value:$val, Addr:$addr),
3592 (MI Addr:$addr, (ValueMod Value:$val))>;
3594 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
3595 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
3596 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
3597 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdgp>;
3599 let AddedComplexity = 100 in {
3600 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>;
3601 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>;
3602 def: Storea_pat<store, I32, addrgp, S2_storerigp>;
3603 def: Storea_pat<store, I64, addrgp, S2_storerdgp>;
3605 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3606 // to "r0 = 1; memw(#foo) = r0"
3607 let AddedComplexity = 100 in
3608 def: Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3609 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3612 //===----------------------------------------------------------------------===//
3613 // Template class for non predicated load instructions with
3614 // absolute addressing mode.
3615 //===----------------------------------------------------------------------===//
3616 let isPredicable = 1, hasSideEffects = 0 in
3617 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3618 bits<3> MajOp, Operand AddrOp, bit isAbs>
3619 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3620 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3621 [], "", V2LDST_tc_ld_SLOT01> {
3624 bits<16> offsetBits;
3626 string ImmOpStr = !cast<string>(ImmOp);
3627 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3628 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3629 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3630 /* u16_0Imm */ addr{15-0})));
3632 let IClass = 0b0100;
3635 let Inst{26-25} = offsetBits{15-14};
3637 let Inst{23-21} = MajOp;
3638 let Inst{20-16} = offsetBits{13-9};
3639 let Inst{13-5} = offsetBits{8-0};
3640 let Inst{4-0} = dst;
3643 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3645 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1>, AddrModeRel {
3647 string ImmOpStr = !cast<string>(ImmOp);
3648 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3649 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3650 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3651 /* u16_0Imm */ 16)));
3653 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3654 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3655 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3656 /* u16_0Imm */ 0)));
3659 //===----------------------------------------------------------------------===//
3660 // Template class for predicated load instructions with
3661 // absolute addressing mode.
3662 //===----------------------------------------------------------------------===//
3663 let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
3664 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3665 bit isPredNot, bit isPredNew>
3666 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3667 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3668 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3673 let isPredicatedNew = isPredNew;
3674 let isPredicatedFalse = isPredNot;
3675 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
3677 let IClass = 0b1001;
3679 let Inst{27-24} = 0b1111;
3680 let Inst{23-21} = MajOp;
3681 let Inst{20-16} = absaddr{5-1};
3683 let Inst{12} = isPredNew;
3684 let Inst{11} = isPredNot;
3685 let Inst{10-9} = src1;
3686 let Inst{8} = absaddr{0};
3688 let Inst{4-0} = dst;
3691 //===----------------------------------------------------------------------===//
3692 // Multiclass for the load instructions with absolute addressing mode.
3693 //===----------------------------------------------------------------------===//
3694 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3696 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3698 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3701 let addrMode = Absolute, isExtended = 1 in
3702 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3703 Operand ImmOp, bits<3> MajOp> {
3704 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3705 let opExtendable = 1, isPredicable = 1 in
3706 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3709 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3710 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3714 let accessSize = ByteAccess, hasNewValue = 1 in {
3715 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3716 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3719 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3720 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3721 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3724 let accessSize = WordAccess, hasNewValue = 1 in
3725 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3727 let accessSize = DoubleWordAccess in
3728 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3730 //===----------------------------------------------------------------------===//
3731 // multiclass for load instructions with GP-relative addressing mode.
3732 // Rx=mem[bhwd](##global)
3733 // Once predicated, these instructions map to absolute addressing mode.
3734 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3735 //===----------------------------------------------------------------------===//
3737 let isAsmParserOnly = 1 in
3738 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3740 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3741 let BaseOpcode = BaseOp#_abs;
3744 let accessSize = ByteAccess, hasNewValue = 1 in {
3745 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3746 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3749 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3750 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3751 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3754 let accessSize = WordAccess, hasNewValue = 1 in
3755 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3757 let accessSize = DoubleWordAccess in
3758 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3760 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
3761 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
3762 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
3763 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
3765 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3766 def: Loadam_pat<load, i1, addrga, I32toI1, L4_loadrub_abs>;
3767 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
3769 def: Stoream_pat<store, I1, addrga, I1toI32, S2_storerbabs>;
3770 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
3772 // Map from load(globaladdress) -> mem[u][bhwd](#foo)
3773 class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
3774 : Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
3775 (VT (MI tglobaladdr:$global))>;
3777 let AddedComplexity = 100 in {
3778 def: LoadGP_pats <extloadi8, L2_loadrbgp>;
3779 def: LoadGP_pats <sextloadi8, L2_loadrbgp>;
3780 def: LoadGP_pats <zextloadi8, L2_loadrubgp>;
3781 def: LoadGP_pats <extloadi16, L2_loadrhgp>;
3782 def: LoadGP_pats <sextloadi16, L2_loadrhgp>;
3783 def: LoadGP_pats <zextloadi16, L2_loadruhgp>;
3784 def: LoadGP_pats <load, L2_loadrigp>;
3785 def: LoadGP_pats <load, L2_loadrdgp, i64>;
3788 // When the Interprocedural Global Variable optimizer realizes that a certain
3789 // global variable takes only two constant values, it shrinks the global to
3790 // a boolean. Catch those loads here in the following 3 patterns.
3791 let AddedComplexity = 100 in {
3792 def: LoadGP_pats <extloadi1, L2_loadrubgp>;
3793 def: LoadGP_pats <zextloadi1, L2_loadrubgp>;
3796 // Transfer global address into a register
3797 def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3798 def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3799 def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3801 let AddedComplexity = 30 in {
3802 def: Storea_pat<truncstorei8, I32, u32ImmPred, S2_storerbabs>;
3803 def: Storea_pat<truncstorei16, I32, u32ImmPred, S2_storerhabs>;
3804 def: Storea_pat<store, I32, u32ImmPred, S2_storeriabs>;
3807 let AddedComplexity = 30 in {
3808 def: Loada_pat<load, i32, u32ImmPred, L4_loadri_abs>;
3809 def: Loada_pat<sextloadi8, i32, u32ImmPred, L4_loadrb_abs>;
3810 def: Loada_pat<zextloadi8, i32, u32ImmPred, L4_loadrub_abs>;
3811 def: Loada_pat<sextloadi16, i32, u32ImmPred, L4_loadrh_abs>;
3812 def: Loada_pat<zextloadi16, i32, u32ImmPred, L4_loadruh_abs>;
3815 // Indexed store word - global address.
3816 // memw(Rs+#u6:2)=#S8
3817 let AddedComplexity = 100 in
3818 def: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
3820 // Load from a global address that has only one use in the current basic block.
3821 let AddedComplexity = 100 in {
3822 def: Loada_pat<extloadi8, i32, addrga, L4_loadrub_abs>;
3823 def: Loada_pat<sextloadi8, i32, addrga, L4_loadrb_abs>;
3824 def: Loada_pat<zextloadi8, i32, addrga, L4_loadrub_abs>;
3826 def: Loada_pat<extloadi16, i32, addrga, L4_loadruh_abs>;
3827 def: Loada_pat<sextloadi16, i32, addrga, L4_loadrh_abs>;
3828 def: Loada_pat<zextloadi16, i32, addrga, L4_loadruh_abs>;
3830 def: Loada_pat<load, i32, addrga, L4_loadri_abs>;
3831 def: Loada_pat<load, i64, addrga, L4_loadrd_abs>;
3834 // Store to a global address that has only one use in the current basic block.
3835 let AddedComplexity = 100 in {
3836 def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
3837 def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
3838 def: Storea_pat<store, I32, addrga, S2_storeriabs>;
3839 def: Storea_pat<store, I64, addrga, S2_storerdabs>;
3841 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
3844 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3845 let AddedComplexity = 100 in
3846 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3847 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3849 // Transfer global address into a register
3850 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3851 isAsCheapAsAMove = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
3852 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3854 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>;
3856 // Transfer a block address into a register
3857 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3858 (TFRI_V4 tblockaddress:$src1)>;
3860 let AddedComplexity = 50 in
3861 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3862 (TFRI_V4 tglobaladdr:$src1)>;
3864 // i8/i16/i32 -> i64 loads
3865 // We need a complexity of 120 here to override preceding handling of
3867 let AddedComplexity = 120 in {
3868 def: Loadam_pat<extloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3869 def: Loadam_pat<sextloadi8, i64, addrga, Sext64, L4_loadrb_abs>;
3870 def: Loadam_pat<zextloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3872 def: Loadam_pat<extloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3873 def: Loadam_pat<sextloadi16, i64, addrga, Sext64, L4_loadrh_abs>;
3874 def: Loadam_pat<zextloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3876 def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3877 def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
3878 def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3881 let AddedComplexity = 100 in {
3882 def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
3883 def: Loada_pat<sextloadi8, i32, addrgp, L4_loadrb_abs>;
3884 def: Loada_pat<zextloadi8, i32, addrgp, L4_loadrub_abs>;
3886 def: Loada_pat<extloadi16, i32, addrgp, L4_loadruh_abs>;
3887 def: Loada_pat<sextloadi16, i32, addrgp, L4_loadrh_abs>;
3888 def: Loada_pat<zextloadi16, i32, addrgp, L4_loadruh_abs>;
3890 def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
3891 def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
3894 let AddedComplexity = 100 in {
3895 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
3896 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
3897 def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
3898 def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
3901 def: Loada_pat<atomic_load_8, i32, addrgp, L4_loadrub_abs>;
3902 def: Loada_pat<atomic_load_16, i32, addrgp, L4_loadruh_abs>;
3903 def: Loada_pat<atomic_load_32, i32, addrgp, L4_loadri_abs>;
3904 def: Loada_pat<atomic_load_64, i64, addrgp, L4_loadrd_abs>;
3906 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbabs>;
3907 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
3908 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
3909 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
3911 let Constraints = "@earlyclobber $dst" in
3912 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3913 IntRegs:$c, IntRegs:$d),
3914 ".error \"Should never try to emit Insert4\"",
3915 [(set (i64 DoubleRegs:$dst),
3916 (or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))),
3918 (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))),
3919 (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))),
3921 (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))))]>;
3923 //===----------------------------------------------------------------------===//
3924 // :raw for of boundscheck:hi:lo insns
3925 //===----------------------------------------------------------------------===//
3927 // A4_boundscheck_lo: Detect if a register is within bounds.
3928 let hasSideEffects = 0 in
3929 def A4_boundscheck_lo: ALU64Inst <
3930 (outs PredRegs:$Pd),
3931 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3932 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
3937 let IClass = 0b1101;
3939 let Inst{27-23} = 0b00100;
3941 let Inst{7-5} = 0b100;
3943 let Inst{20-16} = Rss;
3944 let Inst{12-8} = Rtt;
3947 // A4_boundscheck_hi: Detect if a register is within bounds.
3948 let hasSideEffects = 0 in
3949 def A4_boundscheck_hi: ALU64Inst <
3950 (outs PredRegs:$Pd),
3951 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3952 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
3957 let IClass = 0b1101;
3959 let Inst{27-23} = 0b00100;
3961 let Inst{7-5} = 0b101;
3963 let Inst{20-16} = Rss;
3964 let Inst{12-8} = Rtt;
3967 let hasSideEffects = 0, isAsmParserOnly = 1 in
3968 def A4_boundscheck : MInst <
3969 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3970 "$Pd=boundscheck($Rs,$Rtt)">;
3972 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
3973 let isPredicateLate = 1, hasSideEffects = 0 in
3974 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
3975 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3976 "$Pd = tlbmatch($Rs, $Rt)",
3977 [], "", ALU64_tc_2early_SLOT23> {
3982 let IClass = 0b1101;
3983 let Inst{27-23} = 0b00100;
3984 let Inst{20-16} = Rs;
3986 let Inst{12-8} = Rt;
3987 let Inst{7-5} = 0b011;
3991 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
3992 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
3993 // We don't really want either one here.
3994 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
3995 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
3998 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
3999 // really do a load.
4000 let hasSideEffects = 1, mayLoad = 0 in
4001 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
4002 "dcfetch($Rs + #$u11_3)",
4003 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
4004 "", LD_tc_ld_SLOT0> {
4008 let IClass = 0b1001;
4009 let Inst{27-21} = 0b0100000;
4010 let Inst{20-16} = Rs;
4012 let Inst{10-0} = u11_3{13-3};
4015 //===----------------------------------------------------------------------===//
4016 // Compound instructions
4017 //===----------------------------------------------------------------------===//
4019 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4020 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4021 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4023 class CJInst_tstbit_R0<string px, bit np, string tnt>
4024 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4025 ""#px#" = tstbit($Rs, #0); if ("
4026 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4027 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4032 let isPredicatedFalse = np;
4033 // tnt: Taken/Not Taken
4034 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4035 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4037 let IClass = 0b0001;
4038 let Inst{27-26} = 0b00;
4039 let Inst{25} = !if (!eq(px, "!p1"), 1,
4040 !if (!eq(px, "p1"), 1, 0));
4041 let Inst{24-23} = 0b11;
4043 let Inst{21-20} = r9_2{10-9};
4044 let Inst{19-16} = Rs;
4045 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4046 let Inst{9-8} = 0b11;
4047 let Inst{7-1} = r9_2{8-2};
4050 let Defs = [PC, P0], Uses = [P0] in {
4051 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4052 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4053 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4054 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4057 let Defs = [PC, P1], Uses = [P1] in {
4058 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4059 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4060 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4061 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4065 let isBranch = 1, hasSideEffects = 0,
4066 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4067 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4068 opExtendable = 2, isTerminator = 1 in
4069 class CJInst_RR<string px, string op, bit np, string tnt>
4070 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4071 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4072 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4073 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4079 let isPredicatedFalse = np;
4080 // tnt: Taken/Not Taken
4081 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4082 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4084 let IClass = 0b0001;
4085 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4086 !if (!eq(op, "gt"), 0b01001,
4087 !if (!eq(op, "gtu"), 0b01010, 0)));
4089 let Inst{21-20} = r9_2{10-9};
4090 let Inst{19-16} = Rs;
4091 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4092 // px: Predicate reg 0/1
4093 let Inst{12} = !if (!eq(px, "!p1"), 1,
4094 !if (!eq(px, "p1"), 1, 0));
4095 let Inst{11-8} = Rt;
4096 let Inst{7-1} = r9_2{8-2};
4099 // P[10] taken/not taken.
4100 multiclass T_tnt_CJInst_RR<string op, bit np> {
4101 let Defs = [PC, P0], Uses = [P0] in {
4102 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4103 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4105 let Defs = [PC, P1], Uses = [P1] in {
4106 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4107 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4110 // Predicate / !Predicate
4111 multiclass T_pnp_CJInst_RR<string op>{
4112 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4113 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4115 // TypeCJ Instructions compare RR and jump
4116 defm eq : T_pnp_CJInst_RR<"eq">;
4117 defm gt : T_pnp_CJInst_RR<"gt">;
4118 defm gtu : T_pnp_CJInst_RR<"gtu">;
4120 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4121 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4122 opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
4123 class CJInst_RU5<string px, string op, bit np, string tnt>
4124 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4125 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4126 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4127 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4133 let isPredicatedFalse = np;
4134 // tnt: Taken/Not Taken
4135 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4136 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4138 let IClass = 0b0001;
4139 let Inst{27-26} = 0b00;
4140 // px: Predicate reg 0/1
4141 let Inst{25} = !if (!eq(px, "!p1"), 1,
4142 !if (!eq(px, "p1"), 1, 0));
4143 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4144 !if (!eq(op, "gt"), 0b01,
4145 !if (!eq(op, "gtu"), 0b10, 0)));
4147 let Inst{21-20} = r9_2{10-9};
4148 let Inst{19-16} = Rs;
4149 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4150 let Inst{12-8} = U5;
4151 let Inst{7-1} = r9_2{8-2};
4153 // P[10] taken/not taken.
4154 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4155 let Defs = [PC, P0], Uses = [P0] in {
4156 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4157 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4159 let Defs = [PC, P1], Uses = [P1] in {
4160 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4161 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4164 // Predicate / !Predicate
4165 multiclass T_pnp_CJInst_RU5<string op>{
4166 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4167 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4169 // TypeCJ Instructions compare RI and jump
4170 defm eq : T_pnp_CJInst_RU5<"eq">;
4171 defm gt : T_pnp_CJInst_RU5<"gt">;
4172 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4174 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4175 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4176 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4178 class CJInst_Rn1<string px, string op, bit np, string tnt>
4179 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4180 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4181 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4182 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4187 let isPredicatedFalse = np;
4188 // tnt: Taken/Not Taken
4189 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4190 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4192 let IClass = 0b0001;
4193 let Inst{27-26} = 0b00;
4194 let Inst{25} = !if (!eq(px, "!p1"), 1,
4195 !if (!eq(px, "p1"), 1, 0));
4197 let Inst{24-23} = 0b11;
4199 let Inst{21-20} = r9_2{10-9};
4200 let Inst{19-16} = Rs;
4201 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4202 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4203 !if (!eq(op, "gt"), 0b01, 0));
4204 let Inst{7-1} = r9_2{8-2};
4207 // P[10] taken/not taken.
4208 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4209 let Defs = [PC, P0], Uses = [P0] in {
4210 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4211 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4213 let Defs = [PC, P1], Uses = [P1] in {
4214 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4215 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4218 // Predicate / !Predicate
4219 multiclass T_pnp_CJInst_Rn1<string op>{
4220 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4221 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4223 // TypeCJ Instructions compare -1 and jump
4224 defm eq : T_pnp_CJInst_Rn1<"eq">;
4225 defm gt : T_pnp_CJInst_Rn1<"gt">;
4227 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4228 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4229 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4230 opExtentAlign = 2, opExtendable = 2 in
4231 def J4_jumpseti: CJInst <
4233 (ins u6Imm:$U6, brtarget:$r9_2),
4234 "$Rd = #$U6 ; jump $r9_2"> {
4239 let IClass = 0b0001;
4240 let Inst{27-24} = 0b0110;
4241 let Inst{21-20} = r9_2{10-9};
4242 let Inst{19-16} = Rd;
4243 let Inst{13-8} = U6;
4244 let Inst{7-1} = r9_2{8-2};
4247 // J4_jumpsetr: Direct unconditional jump and transfer register.
4248 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4249 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4250 opExtentAlign = 2, opExtendable = 2 in
4251 def J4_jumpsetr: CJInst <
4253 (ins IntRegs:$Rs, brtarget:$r9_2),
4254 "$Rd = $Rs ; jump $r9_2"> {
4259 let IClass = 0b0001;
4260 let Inst{27-24} = 0b0111;
4261 let Inst{21-20} = r9_2{10-9};
4262 let Inst{11-8} = Rd;
4263 let Inst{19-16} = Rs;
4264 let Inst{7-1} = r9_2{8-2};
4267 // Duplex instructions
4268 //===----------------------------------------------------------------------===//
4269 include "HexagonIsetDx.td"