1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def DuplexIClass0: InstDuplex < 0 >;
15 def DuplexIClass1: InstDuplex < 1 >;
16 def DuplexIClass2: InstDuplex < 2 >;
17 let isExtendable = 1 in {
18 def DuplexIClass3: InstDuplex < 3 >;
19 def DuplexIClass4: InstDuplex < 4 >;
20 def DuplexIClass5: InstDuplex < 5 >;
21 def DuplexIClass6: InstDuplex < 6 >;
22 def DuplexIClass7: InstDuplex < 7 >;
24 def DuplexIClass8: InstDuplex < 8 >;
25 def DuplexIClass9: InstDuplex < 9 >;
26 def DuplexIClassA: InstDuplex < 0xA >;
27 def DuplexIClassB: InstDuplex < 0xB >;
28 def DuplexIClassC: InstDuplex < 0xC >;
29 def DuplexIClassD: InstDuplex < 0xD >;
30 def DuplexIClassE: InstDuplex < 0xE >;
31 def DuplexIClassF: InstDuplex < 0xF >;
33 def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
34 def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
36 let hasSideEffects = 0 in
37 class T_Immext<Operand ImmType>
38 : EXTENDERInst<(outs), (ins ImmType:$imm),
39 "immext(#$imm)", []> {
43 let Inst{27-16} = imm{31-20};
44 let Inst{13-0} = imm{19-6};
47 def A4_ext : T_Immext<u26_6Imm>;
48 let isCodeGenOnly = 1 in {
50 def A4_ext_b : T_Immext<brtarget>;
52 def A4_ext_c : T_Immext<calltarget>;
53 def A4_ext_g : T_Immext<globaladdress>;
56 def BITPOS32 : SDNodeXForm<imm, [{
57 // Return the bit position we will set [0-31].
59 int32_t imm = N->getSExtValue();
60 return XformMskToBitPosU5Imm(imm, SDLoc(N));
64 // Hexagon V4 Architecture spec defines 8 instruction classes:
65 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
69 // ========================================
70 // Loads (8/16/32/64 bit)
74 // ========================================
75 // Stores (8/16/32/64 bit)
78 // ALU32 Instructions:
79 // ========================================
80 // Arithmetic / Logical (32 bit)
83 // XTYPE Instructions (32/64 bit):
84 // ========================================
85 // Arithmetic, Logical, Bit Manipulation
86 // Multiply (Integer, Fractional, Complex)
87 // Permute / Vector Permute Operations
88 // Predicate Operations
89 // Shift / Shift with Add/Sub/Logical
91 // Vector Halfword (ALU, Shift, Multiply)
92 // Vector Word (ALU, Shift)
95 // ========================================
96 // Jump/Call PC-relative
99 // ========================================
100 // Jump/Call Register
102 // MEMOP Instructions:
103 // ========================================
104 // Operation on memory (8/16/32 bit)
107 // ========================================
112 // ========================================
113 // Control-Register Transfers
114 // Hardware Loop Setup
115 // Predicate Logicals & Reductions
117 // SYSTEM Instructions (not implemented in the compiler):
118 // ========================================
124 //===----------------------------------------------------------------------===//
126 //===----------------------------------------------------------------------===//
128 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
130 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
134 let BaseOpcode = "andn_rr", CextOpcode = "andn" in
135 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
136 let BaseOpcode = "orn_rr", CextOpcode = "orn" in
137 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
139 let CextOpcode = "rcmp.eq" in
140 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
141 let CextOpcode = "!rcmp.eq" in
142 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
144 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
145 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
146 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
148 // Pats for instruction selection.
150 // A class to embed the usual comparison patfrags within a zext to i32.
151 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
152 // names, or else the frag's "body" won't match the operands.
153 class CmpInReg<PatFrag Op>
154 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
156 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
157 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
159 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
160 def: T_cmp32_rr_pat<C4_cmplteu, setule, i1>;
162 def: T_cmp32_rr_pat<C4_cmplteu, RevCmp<setuge>, i1>;
164 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
168 let InputType = "reg";
169 let CextOpcode = mnemonic;
171 let isCommutable = IsComm;
172 let hasSideEffects = 0;
179 let Inst{27-21} = 0b0111110;
180 let Inst{20-16} = Rs;
182 let Inst{7-5} = MinOp;
186 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
187 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
188 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
189 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
190 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
191 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
193 let AddedComplexity = 100 in {
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
202 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
203 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
205 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
208 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
209 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
210 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
211 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
213 let InputType = "imm";
214 let CextOpcode = mnemonic;
216 let isCommutable = IsComm;
217 let hasSideEffects = 0;
218 let isExtendable = IsImmExt;
219 let opExtendable = !if (IsImmExt, 2, 0);
220 let isExtentSigned = IsImmSigned;
221 let opExtentBits = ImmBits;
228 let Inst{27-24} = 0b1101;
229 let Inst{22-21} = MajOp;
230 let Inst{20-16} = Rs;
231 let Inst{12-5} = Imm;
233 let Inst{3} = IsHalf;
237 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
238 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
239 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
240 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
241 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
242 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
244 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
245 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
246 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
248 let InputType = "imm";
249 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
250 let isExtendable = 1;
251 let opExtendable = 2;
252 let isExtentSigned = 1;
253 let opExtentBits = 8;
261 let Inst{27-24} = 0b0011;
263 let Inst{21} = IsNeg;
264 let Inst{20-16} = Rs;
270 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
271 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
273 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
274 (A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
275 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
276 (A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
278 // Preserve the S2_tstbit_r generation
279 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
280 (i32 IntRegs:$src1))), 0)))),
281 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
283 //===----------------------------------------------------------------------===//
285 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 //===----------------------------------------------------------------------===//
292 // Combine a word and an immediate into a register pair.
293 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
295 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
296 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
302 let Inst{27-24} = 0b0011;
303 let Inst{22-21} = MajOp;
304 let Inst{20-16} = Rs;
310 let opExtendable = 2 in
311 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
312 "$Rdd = combine($Rs, #$s8)">;
314 let opExtendable = 1 in
315 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
316 "$Rdd = combine(#$s8, $Rs)">;
318 // The complexity of the combines involving immediates should be greater
319 // than the complexity of the combine with two registers.
320 let AddedComplexity = 50 in {
321 def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
322 (A4_combineri IntRegs:$r, s32ImmPred:$i)>;
324 def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
325 (A4_combineir s32ImmPred:$i, IntRegs:$r)>;
328 // A4_combineii: Set two small immediates.
329 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
330 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
331 "$Rdd = combine(#$s8, #$U6)"> {
337 let Inst{27-23} = 0b11001;
338 let Inst{20-16} = U6{5-1};
339 let Inst{13} = U6{0};
344 // The complexity of the combine with two immediates should be greater than
345 // the complexity of a combine involving a register.
346 let AddedComplexity = 75 in
347 def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u32ImmPred:$u6),
348 (A4_combineii imm:$s8, imm:$u6)>;
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 def Zext64: OutPatFrag<(ops node:$Rs),
359 (i64 (A4_combineir 0, (i32 $Rs)))>;
360 def Sext64: OutPatFrag<(ops node:$Rs),
361 (i64 (A2_sxtw (i32 $Rs)))>;
363 // Patterns to generate indexed loads with different forms of the address:
366 // - base (without offset).
367 multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
368 PatLeaf ImmPred, InstHexagon MI> {
369 def: Pat<(VT (Load AddrFI:$fi)),
370 (VT (ValueMod (MI AddrFI:$fi, 0)))>;
371 def: Pat<(VT (Load (add AddrFI:$fi, ImmPred:$Off))),
372 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
373 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
374 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
375 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
376 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
379 defm: Loadxm_pat<extloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
380 defm: Loadxm_pat<extloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
381 defm: Loadxm_pat<extloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
382 defm: Loadxm_pat<zextloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
383 defm: Loadxm_pat<zextloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
384 defm: Loadxm_pat<zextloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
385 defm: Loadxm_pat<sextloadi8, i64, Sext64, s32_0ImmPred, L2_loadrb_io>;
386 defm: Loadxm_pat<sextloadi16, i64, Sext64, s31_1ImmPred, L2_loadrh_io>;
388 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
389 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
391 //===----------------------------------------------------------------------===//
392 // Template class for load instructions with Absolute set addressing mode.
393 //===----------------------------------------------------------------------===//
394 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
395 hasSideEffects = 0 in
396 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
397 LDInst<(outs RC:$dst1, IntRegs:$dst2),
399 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
407 let Inst{27-25} = 0b101;
408 let Inst{24-21} = MajOp;
409 let Inst{13-12} = 0b01;
410 let Inst{4-0} = dst1;
411 let Inst{20-16} = dst2;
412 let Inst{11-8} = addr{5-2};
413 let Inst{6-5} = addr{1-0};
416 let accessSize = ByteAccess, hasNewValue = 1 in {
417 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
418 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
421 let accessSize = HalfWordAccess, hasNewValue = 1 in {
422 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
423 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
424 def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
425 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
428 let accessSize = WordAccess, hasNewValue = 1 in
429 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
431 let accessSize = WordAccess in {
432 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
433 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
436 let accessSize = DoubleWordAccess in
437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
439 let accessSize = ByteAccess in
440 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
442 let accessSize = HalfWordAccess in
443 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
445 // Load - Indirect with long offset
446 let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
447 opExtentBits = 6, opExtendable = 3 in
448 class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
450 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
451 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
457 let CextOpcode = CextOp;
458 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
461 let Inst{27-25} = 0b110;
462 let Inst{24-21} = MajOp;
463 let Inst{20-16} = src1;
464 let Inst{13} = src2{1};
466 let Inst{11-8} = src3{5-2};
467 let Inst{7} = src2{0};
468 let Inst{6-5} = src3{1-0};
472 let accessSize = ByteAccess in {
473 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
474 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
475 def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
479 let accessSize = HalfWordAccess in {
480 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
481 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
482 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
483 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
484 def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
488 let accessSize = WordAccess in {
489 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
490 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
491 def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
494 let accessSize = DoubleWordAccess in
495 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
498 multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
499 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
500 (HexagonCONST32 tglobaladdr:$src3)))),
501 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
502 def : Pat <(VT (ldOp (add IntRegs:$src1,
503 (HexagonCONST32 tglobaladdr:$src2)))),
504 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
506 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
507 (HexagonCONST32 tconstpool:$src3)))),
508 (MI IntRegs:$src1, u2ImmPred:$src2, tconstpool:$src3)>;
509 def : Pat <(VT (ldOp (add IntRegs:$src1,
510 (HexagonCONST32 tconstpool:$src2)))),
511 (MI IntRegs:$src1, 0, tconstpool:$src2)>;
513 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
514 (HexagonCONST32 tjumptable:$src3)))),
515 (MI IntRegs:$src1, u2ImmPred:$src2, tjumptable:$src3)>;
516 def : Pat <(VT (ldOp (add IntRegs:$src1,
517 (HexagonCONST32 tjumptable:$src2)))),
518 (MI IntRegs:$src1, 0, tjumptable:$src2)>;
521 let AddedComplexity = 60 in {
522 defm : T_LoadAbsReg_Pat <sextloadi8, L4_loadrb_ur>;
523 defm : T_LoadAbsReg_Pat <zextloadi8, L4_loadrub_ur>;
524 defm : T_LoadAbsReg_Pat <extloadi8, L4_loadrub_ur>;
526 defm : T_LoadAbsReg_Pat <sextloadi16, L4_loadrh_ur>;
527 defm : T_LoadAbsReg_Pat <zextloadi16, L4_loadruh_ur>;
528 defm : T_LoadAbsReg_Pat <extloadi16, L4_loadruh_ur>;
530 defm : T_LoadAbsReg_Pat <load, L4_loadri_ur>;
531 defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
534 //===----------------------------------------------------------------------===//
535 // Template classes for the non-predicated load instructions with
536 // base + register offset addressing mode
537 //===----------------------------------------------------------------------===//
538 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
539 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
540 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
541 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
549 let Inst{27-24} = 0b1010;
550 let Inst{23-21} = MajOp;
551 let Inst{20-16} = src1;
552 let Inst{12-8} = src2;
553 let Inst{13} = u2{1};
558 //===----------------------------------------------------------------------===//
559 // Template classes for the predicated load instructions with
560 // base + register offset addressing mode
561 //===----------------------------------------------------------------------===//
562 let isPredicated = 1 in
563 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
564 bit isNot, bit isPredNew>:
565 LDInst <(outs RC:$dst),
566 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
567 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
568 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
569 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
576 let isPredicatedFalse = isNot;
577 let isPredicatedNew = isPredNew;
581 let Inst{27-26} = 0b00;
582 let Inst{25} = isPredNew;
583 let Inst{24} = isNot;
584 let Inst{23-21} = MajOp;
585 let Inst{20-16} = src2;
586 let Inst{12-8} = src3;
587 let Inst{13} = u2{1};
589 let Inst{6-5} = src1;
593 //===----------------------------------------------------------------------===//
594 // multiclass for load instructions with base + register offset
596 //===----------------------------------------------------------------------===//
597 let hasSideEffects = 0, addrMode = BaseRegOffset in
598 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
600 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
601 InputType = "reg" in {
602 let isPredicable = 1 in
603 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
606 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
607 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
610 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
611 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
615 let hasNewValue = 1, accessSize = ByteAccess in {
616 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
617 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
620 let hasNewValue = 1, accessSize = HalfWordAccess in {
621 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
622 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
625 let hasNewValue = 1, accessSize = WordAccess in
626 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
628 let accessSize = DoubleWordAccess in
629 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
631 // 'def pats' for load instructions with base + register offset and non-zero
632 // immediate value. Immediate value is used to left-shift the second
634 class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
635 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
636 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
637 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
639 let AddedComplexity = 40 in {
640 def: Loadxs_pat<extloadi8, i32, L4_loadrub_rr>;
641 def: Loadxs_pat<zextloadi8, i32, L4_loadrub_rr>;
642 def: Loadxs_pat<sextloadi8, i32, L4_loadrb_rr>;
643 def: Loadxs_pat<extloadi16, i32, L4_loadruh_rr>;
644 def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
645 def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
646 def: Loadxs_pat<load, i32, L4_loadri_rr>;
647 def: Loadxs_pat<load, i64, L4_loadrd_rr>;
650 // 'def pats' for load instruction base + register offset and
651 // zero immediate value.
652 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
653 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
654 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
656 let AddedComplexity = 20 in {
657 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
658 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
659 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
660 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
661 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
662 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
663 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
664 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
668 def: Pat<(i64 (zext (i1 PredRegs:$src1))),
669 (Zext64 (C2_muxii PredRegs:$src1, 1, 0))>;
672 def: Pat<(i64 (zext (i32 IntRegs:$src1))),
673 (Zext64 IntRegs:$src1)>;
675 //===----------------------------------------------------------------------===//
677 //===----------------------------------------------------------------------===//
679 //===----------------------------------------------------------------------===//
681 //===----------------------------------------------------------------------===//
683 //===----------------------------------------------------------------------===//
684 // Template class for store instructions with Absolute set addressing mode.
685 //===----------------------------------------------------------------------===//
686 let isExtended = 1, opExtendable = 1, opExtentBits = 6,
687 addrMode = AbsoluteSet in
688 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
689 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
690 : STInst<(outs IntRegs:$dst),
691 (ins u6Ext:$addr, RC:$src),
692 mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
696 let accessSize = AccessSz;
697 let BaseOpcode = BaseOp#"_AbsSet";
699 // Store upper-half and store doubleword cannot be NV.
700 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
704 let Inst{27-24} = 0b1011;
705 let Inst{23-21} = MajOp;
706 let Inst{20-16} = dst;
708 let Inst{12-8} = src;
710 let Inst{5-0} = addr;
713 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
714 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
716 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
718 let isNVStorable = 0 in {
719 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
720 0b011, HalfWordAccess, 1>;
721 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
722 0b110, DoubleWordAccess>;
725 let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
726 isExtended = 1, opExtentBits= 6 in
727 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
728 MemAccessSize AccessSz >
729 : NVInst <(outs IntRegs:$dst),
730 (ins u6Ext:$addr, IntRegs:$src),
731 mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
735 let accessSize = AccessSz;
736 let BaseOpcode = BaseOp#"_AbsSet";
740 let Inst{27-21} = 0b1011101;
741 let Inst{20-16} = dst;
742 let Inst{13-11} = 0b000;
743 let Inst{12-11} = MajOp;
744 let Inst{10-8} = src;
746 let Inst{5-0} = addr;
749 let mayStore = 1, addrMode = AbsoluteSet in {
750 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
751 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
752 def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
755 let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
756 addrMode = BaseLongOffset, AddedComplexity = 40 in
757 class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
758 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
760 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
761 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
762 []>, ImmRegShl, NewValueRel {
769 let accessSize = AccessSz;
770 let CextOpcode = CextOp;
771 let BaseOpcode = CextOp#"_shl";
773 // Store upper-half and store doubleword cannot be NV.
774 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
778 let Inst{27-24} =0b1101;
779 let Inst{23-21} = MajOp;
780 let Inst{20-16} = src1;
781 let Inst{13} = src2{1};
782 let Inst{12-8} = src4;
784 let Inst{6} = src2{0};
785 let Inst{5-0} = src3;
788 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
789 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
791 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
793 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
794 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
797 let AddedComplexity = 40 in
798 multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
800 def : Pat<(stOp (VT RC:$src4),
801 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
803 (MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
805 def : Pat<(stOp (VT RC:$src4),
806 (add (shl IntRegs:$src1, u2ImmPred:$src2),
807 (HexagonCONST32 tglobaladdr:$src3))),
808 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
810 def : Pat<(stOp (VT RC:$src4),
811 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
812 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
815 defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
816 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
817 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
818 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
820 let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
821 opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
822 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
823 MemAccessSize AccessSz>
825 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
826 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
832 let CextOpcode = CextOp;
833 let BaseOpcode = CextOp#"_shl";
836 let Inst{27-21} = 0b1101101;
837 let Inst{12-11} = 0b00;
839 let Inst{20-16} = src1;
840 let Inst{13} = src2{1};
841 let Inst{12-11} = MajOp;
842 let Inst{10-8} = src4;
843 let Inst{6} = src2{0};
844 let Inst{5-0} = src3;
847 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
848 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
849 def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
851 //===----------------------------------------------------------------------===//
852 // Template classes for the non-predicated store instructions with
853 // base + register offset addressing mode
854 //===----------------------------------------------------------------------===//
855 let isPredicable = 1 in
856 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
857 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
858 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
859 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
866 // Store upper-half and store doubleword cannot be NV.
867 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
871 let Inst{27-24} = 0b1011;
872 let Inst{23-21} = MajOp;
873 let Inst{20-16} = Rs;
875 let Inst{13} = u2{1};
880 //===----------------------------------------------------------------------===//
881 // Template classes for the predicated store instructions with
882 // base + register offset addressing mode
883 //===----------------------------------------------------------------------===//
884 let isPredicated = 1 in
885 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
886 bit isNot, bit isPredNew, bit isH>
888 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
890 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
891 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
892 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
899 let isPredicatedFalse = isNot;
900 let isPredicatedNew = isPredNew;
901 // Store upper-half and store doubleword cannot be NV.
902 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
906 let Inst{27-26} = 0b01;
907 let Inst{25} = isPredNew;
908 let Inst{24} = isNot;
909 let Inst{23-21} = MajOp;
910 let Inst{20-16} = Rs;
912 let Inst{13} = u2{1};
918 //===----------------------------------------------------------------------===//
919 // Template classes for the new-value store instructions with
920 // base + register offset addressing mode
921 //===----------------------------------------------------------------------===//
922 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
923 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
924 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
925 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
926 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
935 let Inst{27-21} = 0b1011101;
936 let Inst{20-16} = Rs;
938 let Inst{13} = u2{1};
940 let Inst{4-3} = MajOp;
944 //===----------------------------------------------------------------------===//
945 // Template classes for the predicated new-value store instructions with
946 // base + register offset addressing mode
947 //===----------------------------------------------------------------------===//
948 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
949 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
951 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
952 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
953 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
954 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
961 let isPredicatedFalse = isNot;
962 let isPredicatedNew = isPredNew;
965 let Inst{27-26} = 0b01;
966 let Inst{25} = isPredNew;
967 let Inst{24} = isNot;
968 let Inst{23-21} = 0b101;
969 let Inst{20-16} = Rs;
971 let Inst{13} = u2{1};
974 let Inst{4-3} = MajOp;
978 //===----------------------------------------------------------------------===//
979 // multiclass for store instructions with base + register offset addressing
981 //===----------------------------------------------------------------------===//
982 let isNVStorable = 1 in
983 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
984 bits<3> MajOp, bit isH = 0> {
985 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
986 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
989 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
990 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
993 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
994 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
998 //===----------------------------------------------------------------------===//
999 // multiclass for new-value store instructions with base + register offset
1001 //===----------------------------------------------------------------------===//
1002 let mayStore = 1, isNVStore = 1 in
1003 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
1005 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1006 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
1009 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
1010 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
1013 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
1014 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
1018 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
1019 let accessSize = ByteAccess in
1020 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1021 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1023 let accessSize = HalfWordAccess in
1024 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1025 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1027 let accessSize = WordAccess in
1028 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1029 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1031 let isNVStorable = 0, accessSize = DoubleWordAccess in
1032 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1034 let isNVStorable = 0, accessSize = HalfWordAccess in
1035 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1038 class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
1039 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1040 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1041 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1043 let AddedComplexity = 40 in {
1044 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1045 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1046 def: Storexs_pat<store, I32, S4_storeri_rr>;
1047 def: Storexs_pat<store, I64, S4_storerd_rr>;
1050 // memd(Rx++#s4:3)=Rtt
1051 // memd(Rx++#s4:3:circ(Mu))=Rtt
1052 // memd(Rx++I:circ(Mu))=Rtt
1054 // memd(Rx++Mu:brev)=Rtt
1055 // memd(gp+#u16:3)=Rtt
1057 // Store doubleword conditionally.
1058 // if ([!]Pv[.new]) memd(#u6)=Rtt
1059 // TODO: needs to be implemented.
1061 //===----------------------------------------------------------------------===//
1063 //===----------------------------------------------------------------------===//
1064 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1066 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1067 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1068 mnemonic#"($Rs+#$offset)=#$S8",
1069 [], "", V4LDST_tc_st_SLOT01>,
1070 ImmRegRel, PredNewRel {
1076 string OffsetOpStr = !cast<string>(OffsetOp);
1077 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1078 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1079 /* u6_0Imm */ offset{5-0}));
1081 let IClass = 0b0011;
1083 let Inst{27-25} = 0b110;
1084 let Inst{22-21} = MajOp;
1085 let Inst{20-16} = Rs;
1086 let Inst{12-7} = offsetBits;
1087 let Inst{13} = S8{7};
1088 let Inst{6-0} = S8{6-0};
1091 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
1093 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1094 bit isPredNot, bit isPredNew >
1096 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1097 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
1098 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1099 [], "", V4LDST_tc_st_SLOT01>,
1100 ImmRegRel, PredNewRel {
1107 string OffsetOpStr = !cast<string>(OffsetOp);
1108 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1109 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1110 /* u6_0Imm */ offset{5-0}));
1111 let isPredicatedNew = isPredNew;
1112 let isPredicatedFalse = isPredNot;
1114 let IClass = 0b0011;
1116 let Inst{27-25} = 0b100;
1117 let Inst{24} = isPredNew;
1118 let Inst{23} = isPredNot;
1119 let Inst{22-21} = MajOp;
1120 let Inst{20-16} = Rs;
1121 let Inst{13} = S6{5};
1122 let Inst{12-7} = offsetBits;
1124 let Inst{4-0} = S6{4-0};
1128 //===----------------------------------------------------------------------===//
1129 // multiclass for store instructions with base + immediate offset
1130 // addressing mode and immediate stored value.
1131 // mem[bhw](Rx++#s4:3)=#s8
1132 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1133 //===----------------------------------------------------------------------===//
1135 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1137 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1139 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1142 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1144 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1145 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1147 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1148 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1152 let hasSideEffects = 0, addrMode = BaseImmOffset,
1153 InputType = "imm" in {
1154 let accessSize = ByteAccess in
1155 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1157 let accessSize = HalfWordAccess in
1158 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1160 let accessSize = WordAccess in
1161 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1164 def IMM_BYTE : SDNodeXForm<imm, [{
1165 // -1 etc is represented as 255 etc
1166 // assigning to a byte restores our desired signed value.
1167 int8_t imm = N->getSExtValue();
1168 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
1171 def IMM_HALF : SDNodeXForm<imm, [{
1172 // -1 etc is represented as 65535 etc
1173 // assigning to a short restores our desired signed value.
1174 int16_t imm = N->getSExtValue();
1175 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
1178 def IMM_WORD : SDNodeXForm<imm, [{
1179 // -1 etc can be represented as 4294967295 etc
1180 // Currently, it's not doing this. But some optimization
1181 // might convert -1 to a large +ve number.
1182 // assigning to a word restores our desired signed value.
1183 int32_t imm = N->getSExtValue();
1184 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
1187 def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
1188 def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
1189 def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
1191 let AddedComplexity = 40 in {
1192 // Not using frameindex patterns for these stores, because the offset
1193 // is not extendable. This could cause problems during removing the frame
1194 // indices, since the offset with respect to R29/R30 may not fit in the
1196 def: Storexm_add_pat<truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
1198 def: Storexm_add_pat<truncstorei16, s32ImmPred, u6_1ImmPred, ToImmHalf,
1200 def: Storexm_add_pat<store, s32ImmPred, u6_2ImmPred, ToImmWord,
1204 def: Storexm_simple_pat<truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
1205 def: Storexm_simple_pat<truncstorei16, s32ImmPred, ToImmHalf, S4_storeirh_io>;
1206 def: Storexm_simple_pat<store, s32ImmPred, ToImmWord, S4_storeiri_io>;
1208 // memb(Rx++#s4:0:circ(Mu))=Rt
1209 // memb(Rx++I:circ(Mu))=Rt
1211 // memb(Rx++Mu:brev)=Rt
1212 // memb(gp+#u16:0)=Rt
1215 // TODO: needs to be implemented
1216 // memh(Re=#U6)=Rt.H
1217 // memh(Rs+#s11:1)=Rt.H
1218 // memh(Rs+Ru<<#u2)=Rt.H
1219 // TODO: needs to be implemented.
1221 // memh(Ru<<#u2+#U6)=Rt.H
1222 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1223 // memh(Rx++#s4:1:circ(Mu))=Rt
1224 // memh(Rx++I:circ(Mu))=Rt.H
1225 // memh(Rx++I:circ(Mu))=Rt
1226 // memh(Rx++Mu)=Rt.H
1228 // memh(Rx++Mu:brev)=Rt.H
1229 // memh(Rx++Mu:brev)=Rt
1230 // memh(gp+#u16:1)=Rt
1231 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1232 // if ([!]Pv[.new]) memh(#u6)=Rt
1234 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1235 // TODO: needs to be implemented.
1237 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1238 // TODO: Needs to be implemented.
1242 // TODO: Needs to be implemented.
1243 // memw(Rx++#s4:2)=Rt
1244 // memw(Rx++#s4:2:circ(Mu))=Rt
1245 // memw(Rx++I:circ(Mu))=Rt
1247 // memw(Rx++Mu:brev)=Rt
1249 //===----------------------------------------------------------------------===
1251 //===----------------------------------------------------------------------===
1254 //===----------------------------------------------------------------------===//
1256 //===----------------------------------------------------------------------===//
1258 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1259 class T_store_io_nv <string mnemonic, RegisterClass RC,
1260 Operand ImmOp, bits<2>MajOp>
1261 : NVInst_V4 <(outs),
1262 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1263 mnemonic#"($src1+#$src2) = $src3.new",
1264 [],"",ST_tc_st_SLOT0> {
1266 bits<13> src2; // Actual address offset
1268 bits<11> offsetBits; // Represents offset encoding
1270 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1271 !if (!eq(mnemonic, "memh"), 12,
1272 !if (!eq(mnemonic, "memw"), 13, 0)));
1274 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1275 !if (!eq(mnemonic, "memh"), 1,
1276 !if (!eq(mnemonic, "memw"), 2, 0)));
1278 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1279 !if (!eq(mnemonic, "memh"), src2{11-1},
1280 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1282 let IClass = 0b1010;
1285 let Inst{26-25} = offsetBits{10-9};
1286 let Inst{24-21} = 0b1101;
1287 let Inst{20-16} = src1;
1288 let Inst{13} = offsetBits{8};
1289 let Inst{12-11} = MajOp;
1290 let Inst{10-8} = src3;
1291 let Inst{7-0} = offsetBits{7-0};
1294 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1295 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1296 bits<2>MajOp, bit PredNot, bit isPredNew>
1297 : NVInst_V4 <(outs),
1298 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1299 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1300 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1301 [],"",V2LDST_tc_st_SLOT0> {
1306 bits<6> offsetBits; // Represents offset encoding
1308 let isPredicatedNew = isPredNew;
1309 let isPredicatedFalse = PredNot;
1310 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1311 !if (!eq(mnemonic, "memh"), 7,
1312 !if (!eq(mnemonic, "memw"), 8, 0)));
1314 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1315 !if (!eq(mnemonic, "memh"), 1,
1316 !if (!eq(mnemonic, "memw"), 2, 0)));
1318 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1319 !if (!eq(mnemonic, "memh"), src3{6-1},
1320 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1322 let IClass = 0b0100;
1325 let Inst{26} = PredNot;
1326 let Inst{25} = isPredNew;
1327 let Inst{24-21} = 0b0101;
1328 let Inst{20-16} = src2;
1329 let Inst{13} = offsetBits{5};
1330 let Inst{12-11} = MajOp;
1331 let Inst{10-8} = src4;
1332 let Inst{7-3} = offsetBits{4-0};
1334 let Inst{1-0} = src1;
1337 // multiclass for new-value store instructions with base + immediate offset.
1339 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1341 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1342 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1344 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1345 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1347 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1348 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1350 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1352 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1357 let addrMode = BaseImmOffset, InputType = "imm" in {
1358 let accessSize = ByteAccess in
1359 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1360 u6_0Ext, 0b00>, AddrModeRel;
1362 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1363 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1364 u6_1Ext, 0b01>, AddrModeRel;
1366 let accessSize = WordAccess, opExtentAlign = 2 in
1367 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1368 u6_2Ext, 0b10>, AddrModeRel;
1371 //===----------------------------------------------------------------------===//
1372 // Post increment loads with register offset.
1373 //===----------------------------------------------------------------------===//
1375 let hasNewValue = 1 in
1376 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1378 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1380 let hasSideEffects = 0, addrMode = PostInc in
1381 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1382 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1383 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1384 "$dst = "#mnemonic#"($src2++$src3)", [],
1385 "$src1 = $dst, $src2 = $_dst_"> {
1390 let accessSize = AccessSz;
1391 let IClass = 0b1001;
1393 let Inst{27-25} = 0b110;
1394 let Inst{24-21} = MajOp;
1395 let Inst{20-16} = src2;
1396 let Inst{13} = src3;
1399 let Inst{4-0} = dst;
1402 def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
1403 def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
1405 //===----------------------------------------------------------------------===//
1406 // Template class for non-predicated post increment .new stores
1407 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1408 //===----------------------------------------------------------------------===//
1409 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1410 isNewValue = 1, opNewValue = 3 in
1411 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1412 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1413 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1414 mnemonic#"($src1++#$offset) = $src2.new",
1415 [], "$src1 = $_dst_">,
1422 string ImmOpStr = !cast<string>(ImmOp);
1423 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1424 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1425 /* s4_0Imm */ offset{3-0}));
1426 let IClass = 0b1010;
1428 let Inst{27-21} = 0b1011101;
1429 let Inst{20-16} = src1;
1431 let Inst{12-11} = MajOp;
1432 let Inst{10-8} = src2;
1434 let Inst{6-3} = offsetBits;
1438 //===----------------------------------------------------------------------===//
1439 // Template class for predicated post increment .new stores
1440 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1441 //===----------------------------------------------------------------------===//
1442 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1443 isNewValue = 1, opNewValue = 4 in
1444 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1445 bits<2> MajOp, bit isPredNot, bit isPredNew >
1446 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1447 (ins PredRegs:$src1, IntRegs:$src2,
1448 ImmOp:$offset, IntRegs:$src3),
1449 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1450 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1451 [], "$src2 = $_dst_">,
1459 string ImmOpStr = !cast<string>(ImmOp);
1460 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1461 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1462 /* s4_0Imm */ offset{3-0}));
1463 let isPredicatedNew = isPredNew;
1464 let isPredicatedFalse = isPredNot;
1466 let IClass = 0b1010;
1468 let Inst{27-21} = 0b1011101;
1469 let Inst{20-16} = src2;
1471 let Inst{12-11} = MajOp;
1472 let Inst{10-8} = src3;
1473 let Inst{7} = isPredNew;
1474 let Inst{6-3} = offsetBits;
1475 let Inst{2} = isPredNot;
1476 let Inst{1-0} = src1;
1479 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1480 bits<2> MajOp, bit PredNot> {
1481 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1484 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1487 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1489 let BaseOpcode = "POST_"#BaseOp in {
1490 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1493 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1494 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1498 let accessSize = ByteAccess in
1499 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1501 let accessSize = HalfWordAccess in
1502 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1504 let accessSize = WordAccess in
1505 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1507 //===----------------------------------------------------------------------===//
1508 // Template class for post increment .new stores with register offset
1509 //===----------------------------------------------------------------------===//
1510 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1511 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1512 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1513 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1514 #mnemonic#"($src1++$src2) = $src3.new",
1515 [], "$src1 = $_dst_"> {
1519 let accessSize = AccessSz;
1521 let IClass = 0b1010;
1523 let Inst{27-21} = 0b1101101;
1524 let Inst{20-16} = src1;
1525 let Inst{13} = src2;
1526 let Inst{12-11} = MajOp;
1527 let Inst{10-8} = src3;
1531 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1532 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1533 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1535 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1536 // memb(Rx++I:circ(Mu))=Nt.new
1537 // memb(Rx++Mu:brev)=Nt.new
1538 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1539 // memh(Rx++I:circ(Mu))=Nt.new
1540 // memh(Rx++Mu)=Nt.new
1541 // memh(Rx++Mu:brev)=Nt.new
1543 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1544 // memw(Rx++I:circ(Mu))=Nt.new
1545 // memw(Rx++Mu)=Nt.new
1546 // memw(Rx++Mu:brev)=Nt.new
1548 //===----------------------------------------------------------------------===//
1550 //===----------------------------------------------------------------------===//
1552 //===----------------------------------------------------------------------===//
1554 //===----------------------------------------------------------------------===//
1556 //===----------------------------------------------------------------------===//
1557 // multiclass/template class for the new-value compare jumps with the register
1559 //===----------------------------------------------------------------------===//
1561 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1562 opExtentAlign = 2 in
1563 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1564 bit isNegCond, bit isTak>
1566 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1567 "if ("#!if(isNegCond, "!","")#mnemonic#
1568 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1569 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1570 #!if(isTak, "t","nt")#" $offset", []> {
1574 bits<3> Ns; // New-Value Operand
1575 bits<5> RegOp; // Non-New-Value Operand
1578 let isTaken = isTak;
1579 let isPredicatedFalse = isNegCond;
1580 let opNewValue{0} = NvOpNum;
1582 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1583 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1585 let IClass = 0b0010;
1586 let Inst{27-26} = 0b00;
1587 let Inst{25-23} = majOp;
1588 let Inst{22} = isNegCond;
1589 let Inst{18-16} = Ns;
1590 let Inst{13} = isTak;
1591 let Inst{12-8} = RegOp;
1592 let Inst{21-20} = offset{10-9};
1593 let Inst{7-1} = offset{8-2};
1597 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1599 // Branch not taken:
1600 def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1602 def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1605 // NvOpNum = 0 -> First Operand is a new-value Register
1606 // NvOpNum = 1 -> Second Operand is a new-value Register
1608 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1610 let BaseOpcode = BaseOp#_NVJ in {
1611 defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1612 defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1616 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1617 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1618 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1619 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1620 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1622 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1623 Defs = [PC], hasSideEffects = 0 in {
1624 defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1625 defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1626 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1627 defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1628 defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1631 //===----------------------------------------------------------------------===//
1632 // multiclass/template class for the new-value compare jumps instruction
1633 // with a register and an unsigned immediate (U5) operand.
1634 //===----------------------------------------------------------------------===//
1636 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1637 opExtentAlign = 2 in
1638 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1641 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1642 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1643 #!if(isTak, "t","nt")#" $offset", []> {
1645 let isTaken = isTak;
1646 let isPredicatedFalse = isNegCond;
1647 let isTaken = isTak;
1653 let IClass = 0b0010;
1655 let Inst{25-23} = majOp;
1656 let Inst{22} = isNegCond;
1657 let Inst{18-16} = src1;
1658 let Inst{13} = isTak;
1659 let Inst{12-8} = src2;
1660 let Inst{21-20} = offset{10-9};
1661 let Inst{7-1} = offset{8-2};
1664 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1665 // Branch not taken:
1666 def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1668 def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
1671 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1672 let BaseOpcode = BaseOp#_NVJri in {
1673 defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1674 defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1678 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1679 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1680 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1682 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1683 Defs = [PC], hasSideEffects = 0 in {
1684 defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1685 defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1686 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1689 //===----------------------------------------------------------------------===//
1690 // multiclass/template class for the new-value compare jumps instruction
1691 // with a register and an hardcoded 0/-1 immediate value.
1692 //===----------------------------------------------------------------------===//
1694 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1695 opExtentAlign = 2 in
1696 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1697 bit isNegCond, bit isTak>
1699 (ins IntRegs:$src1, brtarget:$offset),
1700 "if ("#!if(isNegCond, "!","")#mnemonic
1701 #"($src1.new, #"#ImmVal#")) jump:"
1702 #!if(isTak, "t","nt")#" $offset", []> {
1704 let isTaken = isTak;
1705 let isPredicatedFalse = isNegCond;
1706 let isTaken = isTak;
1710 let IClass = 0b0010;
1712 let Inst{25-23} = majOp;
1713 let Inst{22} = isNegCond;
1714 let Inst{18-16} = src1;
1715 let Inst{13} = isTak;
1716 let Inst{21-20} = offset{10-9};
1717 let Inst{7-1} = offset{8-2};
1720 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1722 // Branch not taken:
1723 def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1725 def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1728 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1730 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1731 defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1732 defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1736 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1737 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1738 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1740 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1741 Defs = [PC], hasSideEffects = 0 in {
1742 defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1743 defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1744 defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1747 // J4_hintjumpr: Hint indirect conditional jump.
1748 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
1749 def J4_hintjumpr: JRInst <
1754 let IClass = 0b0101;
1755 let Inst{27-21} = 0b0010101;
1756 let Inst{20-16} = Rs;
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1763 //===----------------------------------------------------------------------===//
1765 //===----------------------------------------------------------------------===//
1768 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1769 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
1770 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1771 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1775 let IClass = 0b0110;
1776 let Inst{27-16} = 0b101001001001;
1777 let Inst{12-7} = u6;
1783 let hasSideEffects = 0 in
1784 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1785 : CRInst<(outs PredRegs:$Pd),
1786 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1787 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1788 !if (IsNeg,"!","") # "$Pu))",
1789 [], "", CR_tc_2early_SLOT23> {
1795 let IClass = 0b0110;
1796 let Inst{27-24} = 0b1011;
1797 let Inst{23} = IsNeg;
1798 let Inst{22-21} = OpBits;
1800 let Inst{17-16} = Ps;
1807 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1808 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1809 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1810 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1811 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1812 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1813 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1814 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1816 // op(Ps, op(Pt, Pu))
1817 class LogLog_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1818 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, I1:$Pu))),
1819 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1821 // op(Ps, op(Pt, ~Pu))
1822 class LogLogNot_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1823 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, (not I1:$Pu)))),
1824 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1826 def: LogLog_pat<and, and, C4_and_and>;
1827 def: LogLog_pat<and, or, C4_and_or>;
1828 def: LogLog_pat<or, and, C4_or_and>;
1829 def: LogLog_pat<or, or, C4_or_or>;
1831 def: LogLogNot_pat<and, and, C4_and_andn>;
1832 def: LogLogNot_pat<and, or, C4_and_orn>;
1833 def: LogLogNot_pat<or, and, C4_or_andn>;
1834 def: LogLogNot_pat<or, or, C4_or_orn>;
1836 //===----------------------------------------------------------------------===//
1837 // PIC: Support for PIC compilations. The patterns and SD nodes defined
1838 // below are needed to support code generation for PIC
1839 //===----------------------------------------------------------------------===//
1841 def SDT_HexagonPICAdd
1842 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1843 def SDT_HexagonGOTAdd
1844 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1846 def SDT_HexagonGOTAddInternal : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1847 def SDT_HexagonGOTAddInternalJT : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1848 def SDT_HexagonGOTAddInternalBA : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1850 def Hexagonpic_add : SDNode<"HexagonISD::PIC_ADD", SDT_HexagonPICAdd>;
1851 def Hexagonat_got : SDNode<"HexagonISD::AT_GOT", SDT_HexagonGOTAdd>;
1852 def Hexagongat_pcrel : SDNode<"HexagonISD::AT_PCREL",
1853 SDT_HexagonGOTAddInternal>;
1854 def Hexagongat_pcrel_jt : SDNode<"HexagonISD::AT_PCREL",
1855 SDT_HexagonGOTAddInternalJT>;
1856 def Hexagongat_pcrel_ba : SDNode<"HexagonISD::AT_PCREL",
1857 SDT_HexagonGOTAddInternalBA>;
1859 // PIC: Map from a block address computation to a PC-relative add
1860 def: Pat<(Hexagongat_pcrel_ba tblockaddress:$src1),
1861 (C4_addipc u32ImmPred:$src1)>;
1863 // PIC: Map from the computation to generate a GOT pointer to a PC-relative add
1864 def: Pat<(Hexagonpic_add texternalsym:$src1),
1865 (C4_addipc u32ImmPred:$src1)>;
1867 // PIC: Map from a jump table address computation to a PC-relative add
1868 def: Pat<(Hexagongat_pcrel_jt tjumptable:$src1),
1869 (C4_addipc u32ImmPred:$src1)>;
1871 // PIC: Map from a GOT-relative symbol reference to a load
1872 def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
1873 (L2_loadri_io IntRegs:$src1, s30_2ImmPred:$src2)>;
1875 // PIC: Map from a static symbol reference to a PC-relative add
1876 def: Pat<(Hexagongat_pcrel tglobaladdr:$src1),
1877 (C4_addipc u32ImmPred:$src1)>;
1879 //===----------------------------------------------------------------------===//
1881 //===----------------------------------------------------------------------===//
1883 //===----------------------------------------------------------------------===//
1885 //===----------------------------------------------------------------------===//
1887 // Logical with-not instructions.
1888 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1889 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1891 def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1892 (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1893 def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1894 (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1896 let hasNewValue = 1, hasSideEffects = 0 in
1897 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1898 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1903 let IClass = 0b1101;
1904 let Inst{27-21} = 0b0101111;
1905 let Inst{20-16} = Rs;
1906 let Inst{12-8} = Rt;
1910 // Add and accumulate.
1911 // Rd=add(Rs,add(Ru,#s6))
1912 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1914 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1915 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1916 "$Rd = add($Rs, add($Ru, #$s6))" ,
1917 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1918 (add (i32 IntRegs:$Ru), s32ImmPred:$s6)))],
1919 "", ALU64_tc_2_SLOT23> {
1925 let IClass = 0b1101;
1927 let Inst{27-23} = 0b10110;
1928 let Inst{22-21} = s6{5-4};
1929 let Inst{20-16} = Rs;
1930 let Inst{13} = s6{3};
1931 let Inst{12-8} = Rd;
1932 let Inst{7-5} = s6{2-0};
1936 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1937 opExtentBits = 6, opExtendable = 2 in
1938 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1939 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1940 "$Rd = add($Rs, sub(#$s6, $Ru))",
1941 [], "", ALU64_tc_2_SLOT23> {
1947 let IClass = 0b1101;
1949 let Inst{27-23} = 0b10111;
1950 let Inst{22-21} = s6{5-4};
1951 let Inst{20-16} = Rs;
1952 let Inst{13} = s6{3};
1953 let Inst{12-8} = Rd;
1954 let Inst{7-5} = s6{2-0};
1958 // Rd=add(Rs,sub(#s6,Ru))
1959 def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
1960 (i32 IntRegs:$src3))),
1961 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1963 // Rd=sub(add(Rs,#s6),Ru)
1964 def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
1965 (i32 IntRegs:$src3)),
1966 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1968 // Rd=add(sub(Rs,Ru),#s6)
1969 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1970 (s32ImmPred:$src2)),
1971 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1974 // Add or subtract doublewords with carry.
1976 // Rdd=add(Rss,Rtt,Px):carry
1978 // Rdd=sub(Rss,Rtt,Px):carry
1981 // Rdd=extract(Rss,#u6,#U6)
1982 // Rdd=extract(Rss,Rtt)
1983 // Rd=extract(Rs,Rtt)
1984 // Rd=extract(Rs,#u5,#U5)
1986 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1987 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1989 let hasNewValue = 1 in {
1990 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1991 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1994 // Complex add/sub halfwords/words
1995 let Defs = [USR_OVF] in {
1996 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1997 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1998 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1999 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
2002 let Defs = [USR_OVF] in {
2003 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
2004 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
2007 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in {
2008 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
2009 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
2012 // Logical xor with xor accumulation.
2013 // Rxx^=xor(Rss,Rtt)
2014 let hasSideEffects = 0 in
2016 : SInst <(outs DoubleRegs:$Rxx),
2017 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2018 "$Rxx ^= xor($Rss, $Rtt)",
2019 [(set (i64 DoubleRegs:$Rxx),
2020 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
2021 (i64 DoubleRegs:$Rtt))))],
2022 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
2027 let IClass = 0b1100;
2029 let Inst{27-22} = 0b101010;
2030 let Inst{20-16} = Rss;
2031 let Inst{12-8} = Rtt;
2032 let Inst{7-5} = 0b000;
2033 let Inst{4-0} = Rxx;
2036 // Rotate and reduce bytes
2037 // Rdd=vrcrotate(Rss,Rt,#u2)
2038 let hasSideEffects = 0 in
2040 : SInst <(outs DoubleRegs:$Rdd),
2041 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2042 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
2043 [], "", S_3op_tc_3x_SLOT23> {
2049 let IClass = 0b1100;
2051 let Inst{27-22} = 0b001111;
2052 let Inst{20-16} = Rss;
2053 let Inst{13} = u2{1};
2054 let Inst{12-8} = Rt;
2055 let Inst{7-6} = 0b11;
2056 let Inst{5} = u2{0};
2057 let Inst{4-0} = Rdd;
2060 // Rotate and reduce bytes with accumulation
2061 // Rxx+=vrcrotate(Rss,Rt,#u2)
2062 let hasSideEffects = 0 in
2063 def S4_vrcrotate_acc
2064 : SInst <(outs DoubleRegs:$Rxx),
2065 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2066 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
2067 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2073 let IClass = 0b1100;
2075 let Inst{27-21} = 0b1011101;
2076 let Inst{20-16} = Rss;
2077 let Inst{13} = u2{1};
2078 let Inst{12-8} = Rt;
2079 let Inst{5} = u2{0};
2080 let Inst{4-0} = Rxx;
2083 // Vector reduce conditional negate halfwords
2084 let hasSideEffects = 0 in
2086 : SInst <(outs DoubleRegs:$Rxx),
2087 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2088 "$Rxx += vrcnegh($Rss, $Rt)", [],
2089 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2094 let IClass = 0b1100;
2096 let Inst{27-21} = 0b1011001;
2097 let Inst{20-16} = Rss;
2099 let Inst{12-8} = Rt;
2100 let Inst{7-5} = 0b111;
2101 let Inst{4-0} = Rxx;
2105 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
2107 // Arithmetic/Convergent round
2108 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
2110 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
2112 let Defs = [USR_OVF] in
2113 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
2115 // Logical-logical words.
2116 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
2117 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
2120 ALU64Inst<(outs IntRegs:$Rx),
2121 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2122 "$Rx = or($Ru, and($_src_, #$s10))" ,
2123 [(set (i32 IntRegs:$Rx),
2124 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
2125 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
2130 let IClass = 0b1101;
2132 let Inst{27-22} = 0b101001;
2133 let Inst{20-16} = Rx;
2134 let Inst{21} = s10{9};
2135 let Inst{13-5} = s10{8-0};
2139 // Miscellaneous ALU64 instructions.
2141 let hasNewValue = 1, hasSideEffects = 0 in
2142 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2143 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2148 let IClass = 0b1101;
2149 let Inst{27-21} = 0b0011111;
2150 let Inst{20-16} = Rs;
2151 let Inst{12-8} = Rt;
2152 let Inst{7-5} = 0b111;
2156 let hasSideEffects = 0 in
2157 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2158 (ins IntRegs:$Rs, IntRegs:$Rt),
2159 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2164 let IClass = 0b1101;
2165 let Inst{27-24} = 0b0100;
2167 let Inst{20-16} = Rs;
2168 let Inst{12-8} = Rt;
2172 let hasSideEffects = 0 in
2173 def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
2174 (ins IntRegs:$Rs, IntRegs:$Rt),
2175 "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
2180 let IClass = 0b1101;
2181 let Inst{27-24} = 0b0100;
2183 let Inst{20-16} = Rs;
2184 let Inst{12-8} = Rt;
2188 let hasNewValue = 1, hasSideEffects = 0 in
2189 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2190 (ins IntRegs:$Rs, IntRegs:$Rt),
2191 "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2196 let IClass = 0b1101;
2197 let Inst{27-21} = 0b0101100;
2198 let Inst{20-16} = Rs;
2199 let Inst{12-8} = Rt;
2204 let hasNewValue = 1, hasSideEffects = 0 in
2205 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2206 (ins IntRegs:$Rs, IntRegs:$Rt),
2207 "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2212 let IClass = 0b1101;
2213 let Inst{27-21} = 0b0101100;
2214 let Inst{20-16} = Rt;
2215 let Inst{12-8} = Rs;
2220 // Rx[&|]=xor(Rs,Rt)
2221 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
2222 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
2224 // Rx[&|^]=or(Rs,Rt)
2225 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
2227 let CextOpcode = "ORr_ORr" in
2228 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
2229 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
2231 // Rx[&|^]=and(Rs,Rt)
2232 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
2234 let CextOpcode = "ORr_ANDr" in
2235 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
2236 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
2238 // Rx[&|^]=and(Rs,~Rt)
2239 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
2240 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
2241 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
2243 def: T_MType_acc_pat2 <M4_or_xor, xor, or>;
2244 def: T_MType_acc_pat2 <M4_and_xor, xor, and>;
2245 def: T_MType_acc_pat2 <M4_or_and, and, or>;
2246 def: T_MType_acc_pat2 <M4_and_and, and, and>;
2247 def: T_MType_acc_pat2 <M4_xor_and, and, xor>;
2248 def: T_MType_acc_pat2 <M4_or_or, or, or>;
2249 def: T_MType_acc_pat2 <M4_and_or, or, and>;
2250 def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
2252 class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2253 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
2254 (not IntRegs:$src3)))),
2255 (i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
2257 def: T_MType_acc_pat3 <M4_or_andn, and, or>;
2258 def: T_MType_acc_pat3 <M4_and_andn, and, and>;
2259 def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
2261 // Compound or-or and or-and
2262 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
2263 opExtentBits = 10, opExtendable = 3 in
2264 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2265 : MInst_acc <(outs IntRegs:$Rx),
2266 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2267 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2268 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2269 (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
2270 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
2275 let IClass = 0b1101;
2277 let Inst{27-24} = 0b1010;
2278 let Inst{23-22} = MajOp;
2279 let Inst{20-16} = Rs;
2280 let Inst{21} = s10{9};
2281 let Inst{13-5} = s10{8-0};
2285 let CextOpcode = "ORr_ANDr" in
2286 def S4_or_andi : T_CompOR <"and", 0b00, and>;
2288 let CextOpcode = "ORr_ORr" in
2289 def S4_or_ori : T_CompOR <"or", 0b10, or>;
2292 // Rd=modwrap(Rs,Rt)
2294 // Rd=cround(Rs,#u5)
2296 // Rd=round(Rs,#u5)[:sat]
2297 // Rd=round(Rs,Rt)[:sat]
2298 // Vector reduce add unsigned halfwords
2299 // Rd=vraddh(Rss,Rtt)
2301 // Rdd=vaddb(Rss,Rtt)
2302 // Vector conditional negate
2303 // Rdd=vcnegh(Rss,Rt)
2304 // Rxx+=vrcnegh(Rss,Rt)
2305 // Vector maximum bytes
2306 // Rdd=vmaxb(Rtt,Rss)
2307 // Vector reduce maximum halfwords
2308 // Rxx=vrmaxh(Rss,Ru)
2309 // Rxx=vrmaxuh(Rss,Ru)
2310 // Vector reduce maximum words
2311 // Rxx=vrmaxuw(Rss,Ru)
2312 // Rxx=vrmaxw(Rss,Ru)
2313 // Vector minimum bytes
2314 // Rdd=vminb(Rtt,Rss)
2315 // Vector reduce minimum halfwords
2316 // Rxx=vrminh(Rss,Ru)
2317 // Rxx=vrminuh(Rss,Ru)
2318 // Vector reduce minimum words
2319 // Rxx=vrminuw(Rss,Ru)
2320 // Rxx=vrminw(Rss,Ru)
2321 // Vector subtract bytes
2322 // Rdd=vsubb(Rss,Rtt)
2324 //===----------------------------------------------------------------------===//
2326 //===----------------------------------------------------------------------===//
2328 //===----------------------------------------------------------------------===//
2330 //===----------------------------------------------------------------------===//
2333 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2336 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2337 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2338 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2340 // Count trailing zeros: 64-bit.
2341 def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>;
2342 def: Pat<(i32 (trunc (cttz_zero_undef I64:$Rss))), (S2_ct0p I64:$Rss)>;
2344 // Count trailing ones: 64-bit.
2345 def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
2346 def: Pat<(i32 (trunc (cttz_zero_undef (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
2348 // Define leading/trailing patterns that require zero-extensions to 64 bits.
2349 def: Pat<(i64 (ctlz I64:$Rss)), (Zext64 (S2_cl0p I64:$Rss))>;
2350 def: Pat<(i64 (ctlz_zero_undef I64:$Rss)), (Zext64 (S2_cl0p I64:$Rss))>;
2351 def: Pat<(i64 (cttz I64:$Rss)), (Zext64 (S2_ct0p I64:$Rss))>;
2352 def: Pat<(i64 (cttz_zero_undef I64:$Rss)), (Zext64 (S2_ct0p I64:$Rss))>;
2353 def: Pat<(i64 (ctlz (not I64:$Rss))), (Zext64 (S2_cl1p I64:$Rss))>;
2354 def: Pat<(i64 (ctlz_zero_undef (not I64:$Rss))), (Zext64 (S2_cl1p I64:$Rss))>;
2355 def: Pat<(i64 (cttz (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>;
2356 def: Pat<(i64 (cttz_zero_undef (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>;
2359 let hasSideEffects = 0, hasNewValue = 1 in
2360 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2361 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2365 let IClass = 0b1000;
2366 let Inst{27-24} = 0b1100;
2367 let Inst{23-21} = 0b001;
2368 let Inst{20-16} = Rs;
2369 let Inst{13-8} = s6;
2370 let Inst{7-5} = 0b000;
2374 let hasSideEffects = 0, hasNewValue = 1 in
2375 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2376 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2380 let IClass = 0b1000;
2381 let Inst{27-24} = 0b1000;
2382 let Inst{23-21} = 0b011;
2383 let Inst{20-16} = Rs;
2384 let Inst{13-8} = s6;
2385 let Inst{7-5} = 0b010;
2390 // Bit test/set/clear
2391 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2392 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2394 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2395 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2396 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2397 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2398 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2401 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2402 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2403 // if ([!]tstbit(...)) jump ...
2404 let AddedComplexity = 100 in
2405 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2406 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2408 let AddedComplexity = 100 in
2409 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2410 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2412 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2413 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2414 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2416 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2417 // represented as a compare against "value & 0xFF", which is an exact match
2418 // for cmpb (same for cmph). The patterns below do not contain any additional
2419 // complexity that would make them preferable, and if they were actually used
2420 // instead of cmpb/cmph, they would result in a compare against register that
2421 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2422 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2423 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2424 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2425 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2426 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2427 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2429 //===----------------------------------------------------------------------===//
2431 //===----------------------------------------------------------------------===//
2433 //===----------------------------------------------------------------------===//
2435 //===----------------------------------------------------------------------===//
2437 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2439 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2440 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2441 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2442 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2443 [(set (i32 IntRegs:$Rd),
2444 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2445 u32ImmPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2451 let IClass = 0b1101;
2453 let Inst{27-24} = 0b1000;
2454 let Inst{23} = U6{5};
2455 let Inst{22-21} = u6{5-4};
2456 let Inst{20-16} = Rs;
2457 let Inst{13} = u6{3};
2458 let Inst{12-8} = Rd;
2459 let Inst{7-5} = u6{2-0};
2460 let Inst{4-0} = U6{4-0};
2463 // Rd=add(#u6,mpyi(Rs,Rt))
2464 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2465 isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2466 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2467 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2468 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2469 [(set (i32 IntRegs:$Rd),
2470 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
2471 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2477 let IClass = 0b1101;
2479 let Inst{27-23} = 0b01110;
2480 let Inst{22-21} = u6{5-4};
2481 let Inst{20-16} = Rs;
2482 let Inst{13} = u6{3};
2483 let Inst{12-8} = Rt;
2484 let Inst{7-5} = u6{2-0};
2488 let hasNewValue = 1 in
2489 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2490 : ALU64Inst <(outs IntRegs:$dst), ins,
2491 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2493 [(set (i32 IntRegs:$dst),
2494 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2495 "", ALU64_tc_3x_SLOT23> {
2501 let IClass = 0b1101;
2503 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2505 let Inst{27-24} = 0b1111;
2506 let Inst{23} = MajOp;
2507 let Inst{22-21} = ImmValue{5-4};
2508 let Inst{20-16} = src3;
2509 let Inst{13} = ImmValue{3};
2510 let Inst{12-8} = dst;
2511 let Inst{7-5} = ImmValue{2-0};
2512 let Inst{4-0} = src1;
2515 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2516 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2518 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2519 CextOpcode = "ADD_MPY", InputType = "imm" in
2520 def M4_mpyri_addr : T_AddMpy<0b1, u32ImmPred,
2521 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2523 // Rx=add(Ru,mpyi(Rx,Rs))
2524 let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
2525 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2526 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2527 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2528 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2529 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2530 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2535 let IClass = 0b1110;
2537 let Inst{27-21} = 0b0011000;
2538 let Inst{12-8} = Rx;
2540 let Inst{20-16} = Rs;
2544 // Vector reduce multiply word by signed half (32x16)
2545 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2546 def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
2547 def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
2549 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2550 def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
2551 def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
2553 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
2554 def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
2555 def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
2557 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2558 def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
2559 def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
2561 // Vector multiply halfwords, signed by unsigned
2562 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2563 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
2564 def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
2566 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2567 def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
2568 def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
2570 // Vector polynomial multiply halfwords
2571 // Rdd=vpmpyh(Rs,Rt)
2572 def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
2574 // Rxx^=vpmpyh(Rs,Rt)
2575 def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
2577 // Polynomial multiply words
2579 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2581 // Rxx^=pmpyw(Rs,Rt)
2582 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2584 //===----------------------------------------------------------------------===//
2586 //===----------------------------------------------------------------------===//
2588 //===----------------------------------------------------------------------===//
2589 // ALU64/Vector compare
2590 //===----------------------------------------------------------------------===//
2591 //===----------------------------------------------------------------------===//
2592 // Template class for vector compare
2593 //===----------------------------------------------------------------------===//
2595 let hasSideEffects = 0 in
2596 class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
2597 : ALU64_rr <(outs PredRegs:$Pd),
2598 (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
2599 "$Pd = "#Str#"($Rss, #$Imm)",
2600 [], "", ALU64_tc_2early_SLOT23> {
2605 let ImmBits{6-0} = Imm{6-0};
2606 let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
2608 let IClass = 0b1101;
2610 let Inst{27-24} = 0b1100;
2611 let Inst{22-21} = cmpOp;
2612 let Inst{20-16} = Rss;
2613 let Inst{12-5} = ImmBits;
2614 let Inst{4-3} = minOp;
2618 // Vector compare bytes
2619 def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
2620 def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
2622 let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
2623 def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
2625 def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
2626 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2627 def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
2629 // Vector compare halfwords
2630 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2631 def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
2632 def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
2634 // Vector compare words
2635 def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
2636 def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
2637 def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
2639 //===----------------------------------------------------------------------===//
2641 //===----------------------------------------------------------------------===//
2642 // Shift by immediate and accumulate/logical.
2643 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2644 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2645 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2646 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2647 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2648 hasNewValue = 1, opNewValue = 0 in
2649 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2650 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2651 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2652 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2653 [(set (i32 IntRegs:$Rd),
2654 (Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))],
2655 "$Rd = $Rx", Itin> {
2662 let IClass = 0b1101;
2663 let Inst{27-24} = 0b1110;
2664 let Inst{23-21} = u8{7-5};
2665 let Inst{20-16} = Rd;
2666 let Inst{13} = u8{4};
2667 let Inst{12-8} = U5;
2668 let Inst{7-5} = u8{3-1};
2669 let Inst{4} = asl_lsr;
2670 let Inst{3} = u8{0};
2671 let Inst{2-1} = MajOp;
2674 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2675 InstrItinClass Itin> {
2676 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2677 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2680 let AddedComplexity = 200 in {
2681 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2682 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2685 let AddedComplexity = 30 in
2686 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2688 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2690 let AddedComplexity = 200 in {
2691 def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2692 (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2693 def: Pat<(add addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2694 (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2695 def: Pat<(sub addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2696 (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2697 def: Pat<(sub addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2698 (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2701 // Vector conditional negate
2702 // Rdd=vcnegh(Rss,Rt)
2703 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2704 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2706 // Rd=[cround|round](Rs,Rt)
2707 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in {
2708 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2709 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2712 // Rd=round(Rs,Rt):sat
2713 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2714 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2716 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2717 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
2718 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2719 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2722 // Rdd=[add|sub](Rss,Rtt,Px):carry
2723 let isPredicateLate = 1, hasSideEffects = 0 in
2724 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2725 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2726 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2727 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2728 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2734 let IClass = 0b1100;
2736 let Inst{27-24} = 0b0010;
2737 let Inst{23-21} = MajOp;
2738 let Inst{20-16} = Rss;
2739 let Inst{12-8} = Rtt;
2741 let Inst{4-0} = Rdd;
2744 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2745 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2747 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2748 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2749 : SInst <(outs DoubleRegs:$Rxx),
2750 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2751 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2752 [] , "$dst2 = $Rxx"> {
2757 let IClass = 0b1100;
2759 let Inst{27-21} = 0b1011001;
2760 let Inst{20-16} = Rss;
2761 let Inst{13} = isUnsigned;
2762 let Inst{12-8} = Rxx;
2763 let Inst{7-5} = MinOp;
2767 // Vector reduce maximum halfwords
2768 // Rxx=vrmax[u]h(Rss,Ru)
2769 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2770 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2772 // Vector reduce maximum words
2773 // Rxx=vrmax[u]w(Rss,Ru)
2774 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2775 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2777 // Vector reduce minimum halfwords
2778 // Rxx=vrmin[u]h(Rss,Ru)
2779 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2780 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2782 // Vector reduce minimum words
2783 // Rxx=vrmin[u]w(Rss,Ru)
2784 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2785 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2787 // Shift an immediate left by register amount.
2788 let hasNewValue = 1, hasSideEffects = 0 in
2789 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2790 "$Rd = lsl(#$s6, $Rt)" ,
2791 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2792 (i32 IntRegs:$Rt)))],
2793 "", S_3op_tc_1_SLOT23> {
2798 let IClass = 0b1100;
2800 let Inst{27-22} = 0b011010;
2801 let Inst{20-16} = s6{5-1};
2802 let Inst{12-8} = Rt;
2803 let Inst{7-6} = 0b11;
2805 let Inst{5} = s6{0};
2808 //===----------------------------------------------------------------------===//
2810 //===----------------------------------------------------------------------===//
2812 //===----------------------------------------------------------------------===//
2813 // MEMOP: Word, Half, Byte
2814 //===----------------------------------------------------------------------===//
2816 def MEMOPIMM : SDNodeXForm<imm, [{
2817 // Call the transformation function XformM5ToU5Imm to get the negative
2818 // immediate's positive counterpart.
2819 int32_t imm = N->getSExtValue();
2820 return XformM5ToU5Imm(imm, SDLoc(N));
2823 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2824 // -1 .. -31 represented as 65535..65515
2825 // assigning to a short restores our desired signed value.
2826 // Call the transformation function XformM5ToU5Imm to get the negative
2827 // immediate's positive counterpart.
2828 int16_t imm = N->getSExtValue();
2829 return XformM5ToU5Imm(imm, SDLoc(N));
2832 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2833 // -1 .. -31 represented as 255..235
2834 // assigning to a char restores our desired signed value.
2835 // Call the transformation function XformM5ToU5Imm to get the negative
2836 // immediate's positive counterpart.
2837 int8_t imm = N->getSExtValue();
2838 return XformM5ToU5Imm(imm, SDLoc(N));
2841 def SETMEMIMM : SDNodeXForm<imm, [{
2842 // Return the bit position we will set [0-31].
2844 int32_t imm = N->getSExtValue();
2845 return XformMskToBitPosU5Imm(imm, SDLoc(N));
2848 def CLRMEMIMM : SDNodeXForm<imm, [{
2849 // Return the bit position we will clear [0-31].
2851 // we bit negate the value first
2852 int32_t imm = ~(N->getSExtValue());
2853 return XformMskToBitPosU5Imm(imm, SDLoc(N));
2856 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2857 // Return the bit position we will set [0-15].
2859 int16_t imm = N->getSExtValue();
2860 return XformMskToBitPosU4Imm(imm, SDLoc(N));
2863 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2864 // Return the bit position we will clear [0-15].
2866 // we bit negate the value first
2867 int16_t imm = ~(N->getSExtValue());
2868 return XformMskToBitPosU4Imm(imm, SDLoc(N));
2871 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2872 // Return the bit position we will set [0-7].
2874 int8_t imm = N->getSExtValue();
2875 return XformMskToBitPosU3Imm(imm, SDLoc(N));
2878 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2879 // Return the bit position we will clear [0-7].
2881 // we bit negate the value first
2882 int8_t imm = ~(N->getSExtValue());
2883 return XformMskToBitPosU3Imm(imm, SDLoc(N));
2886 //===----------------------------------------------------------------------===//
2887 // Template class for MemOp instructions with the register value.
2888 //===----------------------------------------------------------------------===//
2889 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2890 string memOp, bits<2> memOpBits> :
2892 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2893 opc#"($base+#$offset)"#memOp#"$delta",
2895 Requires<[UseMEMOP]> {
2900 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2902 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2903 !if (!eq(opcBits, 0b01), offset{6-1},
2904 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2906 let opExtentAlign = opcBits;
2907 let IClass = 0b0011;
2908 let Inst{27-24} = 0b1110;
2909 let Inst{22-21} = opcBits;
2910 let Inst{20-16} = base;
2912 let Inst{12-7} = offsetBits;
2913 let Inst{6-5} = memOpBits;
2914 let Inst{4-0} = delta;
2917 //===----------------------------------------------------------------------===//
2918 // Template class for MemOp instructions with the immediate value.
2919 //===----------------------------------------------------------------------===//
2920 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2921 string memOp, bits<2> memOpBits> :
2923 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2924 opc#"($base+#$offset)"#memOp#"#$delta"
2925 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2927 Requires<[UseMEMOP]> {
2932 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2934 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2935 !if (!eq(opcBits, 0b01), offset{6-1},
2936 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2938 let opExtentAlign = opcBits;
2939 let IClass = 0b0011;
2940 let Inst{27-24} = 0b1111;
2941 let Inst{22-21} = opcBits;
2942 let Inst{20-16} = base;
2944 let Inst{12-7} = offsetBits;
2945 let Inst{6-5} = memOpBits;
2946 let Inst{4-0} = delta;
2949 // multiclass to define MemOp instructions with register operand.
2950 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2951 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2952 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2953 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2954 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2957 // multiclass to define MemOp instructions with immediate Operand.
2958 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2959 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2960 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2961 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2962 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2965 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2966 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2967 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2970 // Define MemOp instructions.
2971 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
2972 let opExtentBits = 6, accessSize = ByteAccess in
2973 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2975 let opExtentBits = 7, accessSize = HalfWordAccess in
2976 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2978 let opExtentBits = 8, accessSize = WordAccess in
2979 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2982 //===----------------------------------------------------------------------===//
2983 // Multiclass to define 'Def Pats' for ALU operations on the memory
2984 // Here value used for the ALU operation is an immediate value.
2985 // mem[bh](Rs+#0) += #U5
2986 // mem[bh](Rs+#u6) += #U5
2987 //===----------------------------------------------------------------------===//
2989 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
2990 InstHexagon MI, SDNode OpNode> {
2991 let AddedComplexity = 180 in
2992 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2994 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
2996 let AddedComplexity = 190 in
2997 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
2999 (add IntRegs:$base, ImmPred:$offset)),
3000 (MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
3003 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
3004 InstHexagon addMI, InstHexagon subMI> {
3005 defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, addMI, add>;
3006 defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, subMI, sub>;
3009 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3011 defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
3012 L4_iadd_memoph_io, L4_isub_memoph_io>;
3014 defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u32ImmPred,
3015 L4_iadd_memopb_io, L4_isub_memopb_io>;
3018 let Predicates = [UseMEMOP] in {
3019 defm: MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
3020 defm: MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
3021 defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
3024 defm: MemOpi_u5ALUOp <load, store, u30_2ImmPred, L4_iadd_memopw_io,
3028 //===----------------------------------------------------------------------===//
3029 // multiclass to define 'Def Pats' for ALU operations on the memory.
3030 // Here value used for the ALU operation is a negative value.
3031 // mem[bh](Rs+#0) += #m5
3032 // mem[bh](Rs+#u6) += #m5
3033 //===----------------------------------------------------------------------===//
3035 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
3036 PatLeaf immPred, SDNodeXForm xformFunc,
3038 let AddedComplexity = 190 in
3039 def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
3040 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
3042 let AddedComplexity = 195 in
3043 def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
3045 (add IntRegs:$base, ImmPred:$offset)),
3046 (MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
3049 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3051 defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u31_1ImmPred, m5HImmPred,
3052 MEMOPIMM_HALF, L4_isub_memoph_io>;
3054 defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u32ImmPred, m5BImmPred,
3055 MEMOPIMM_BYTE, L4_isub_memopb_io>;
3058 let Predicates = [UseMEMOP] in {
3059 defm: MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
3060 defm: MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
3061 defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
3064 defm: MemOpi_m5Pats <load, store, u30_2ImmPred, m5ImmPred,
3065 MEMOPIMM, L4_isub_memopw_io>;
3068 //===----------------------------------------------------------------------===//
3069 // Multiclass to define 'def Pats' for bit operations on the memory.
3070 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3071 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
3072 //===----------------------------------------------------------------------===//
3074 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
3075 PatLeaf extPred, SDNodeXForm xformFunc, InstHexagon MI,
3078 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
3079 let AddedComplexity = 250 in
3080 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3082 (add IntRegs:$base, extPred:$offset)),
3083 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
3085 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3086 let AddedComplexity = 225 in
3087 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
3088 (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
3091 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
3093 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u32ImmPred,
3094 CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
3096 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u32ImmPred,
3097 SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
3098 // Half Word - clrbit
3099 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u31_1ImmPred,
3100 CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
3101 // Half Word - setbit
3102 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u31_1ImmPred,
3103 SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
3106 let Predicates = [UseMEMOP] in {
3107 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
3108 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
3109 defm: MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
3110 defm: MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
3111 defm: MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
3113 // memw(Rs+#0) = [clrbit|setbit](#U5)
3114 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
3115 defm: MemOpi_bitPats<load, store, Clr5ImmPred, u30_2ImmPred, CLRMEMIMM,
3116 L4_iand_memopw_io, and>;
3117 defm: MemOpi_bitPats<load, store, Set5ImmPred, u30_2ImmPred, SETMEMIMM,
3118 L4_ior_memopw_io, or>;
3121 //===----------------------------------------------------------------------===//
3122 // Multiclass to define 'def Pats' for ALU operations on the memory
3123 // where addend is a register.
3124 // mem[bhw](Rs+#0) [+-&|]= Rt
3125 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3126 //===----------------------------------------------------------------------===//
3128 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3129 InstHexagon MI, SDNode OpNode> {
3130 let AddedComplexity = 141 in
3131 // mem[bhw](Rs+#0) [+-&|]= Rt
3132 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
3134 (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
3136 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3137 let AddedComplexity = 150 in
3138 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3139 (i32 IntRegs:$orend)),
3140 (add IntRegs:$base, extPred:$offset)),
3141 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
3144 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3145 InstHexagon addMI, InstHexagon subMI,
3146 InstHexagon andMI, InstHexagon orMI> {
3147 defm: MemOpr_Pats <ldOp, stOp, extPred, addMI, add>;
3148 defm: MemOpr_Pats <ldOp, stOp, extPred, subMI, sub>;
3149 defm: MemOpr_Pats <ldOp, stOp, extPred, andMI, and>;
3150 defm: MemOpr_Pats <ldOp, stOp, extPred, orMI, or>;
3153 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3155 defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
3156 L4_add_memoph_io, L4_sub_memoph_io,
3157 L4_and_memoph_io, L4_or_memoph_io>;
3159 defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u32ImmPred,
3160 L4_add_memopb_io, L4_sub_memopb_io,
3161 L4_and_memopb_io, L4_or_memopb_io>;
3164 // Define 'def Pats' for MemOps with register addend.
3165 let Predicates = [UseMEMOP] in {
3167 defm: MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
3168 defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
3169 defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
3171 defm: MemOPr_ALUOp <load, store, u30_2ImmPred, L4_add_memopw_io,
3172 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
3175 //===----------------------------------------------------------------------===//
3177 //===----------------------------------------------------------------------===//
3179 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3180 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3181 // hardware. However, compiler can still implement these patterns through
3182 // appropriate patterns combinations based on current implemented patterns.
3183 // The implemented patterns are: EQ/GT/GTU.
3184 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3186 // Following instruction is not being extended as it results into the
3187 // incorrect code for negative numbers.
3188 // Pd=cmpb.eq(Rs,#u8)
3190 // p=!cmp.eq(r1,#s10)
3191 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
3192 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
3193 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
3195 def : T_CMP_pat <C4_cmpneqi, setne, s32ImmPred>;
3196 def : T_CMP_pat <C4_cmpltei, setle, s32ImmPred>;
3197 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
3199 // rs <= rt -> !(rs > rt).
3201 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
3202 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
3203 // (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
3205 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3206 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
3207 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
3209 // rs != rt -> !(rs == rt).
3210 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
3211 (C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
3213 // SDNode for converting immediate C to C-1.
3214 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
3215 // Return the byte immediate const-1 as an SDNode.
3216 int32_t imm = N->getSExtValue();
3217 return XformU7ToU7M1Imm(imm, SDLoc(N));
3221 // zext( setult ( and(Rs, 255), u8))
3222 // Use the isdigit transformation below
3224 // Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
3225 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3226 // The isdigit transformation relies on two 'clever' aspects:
3227 // 1) The data type is unsigned which allows us to eliminate a zero test after
3228 // biasing the expression by 48. We are depending on the representation of
3229 // the unsigned types, and semantics.
3230 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3233 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3234 // The code is transformed upstream of llvm into
3235 // retval = (c-48) < 10 ? 1 : 0;
3236 let AddedComplexity = 139 in
3237 def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3238 u7StrictPosImmPred:$src2)))),
3239 (C2_muxii (A4_cmpbgtui IntRegs:$src1,
3240 (DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
3243 //===----------------------------------------------------------------------===//
3245 //===----------------------------------------------------------------------===//
3247 //===----------------------------------------------------------------------===//
3248 // Multiclass for DeallocReturn
3249 //===----------------------------------------------------------------------===//
3250 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3251 : LD0Inst<(outs), (ins PredRegs:$src),
3252 !if(isNot, "if (!$src", "if ($src")#
3253 !if(isPredNew, ".new) ", ") ")#mnemonic#
3254 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3255 [], "", LD_tc_3or4stall_SLOT0> {
3258 let BaseOpcode = "L4_RETURN";
3259 let isPredicatedFalse = isNot;
3260 let isPredicatedNew = isPredNew;
3261 let isTaken = isTak;
3262 let IClass = 0b1001;
3264 let Inst{27-16} = 0b011000011110;
3266 let Inst{13} = isNot;
3267 let Inst{12} = isTak;
3268 let Inst{11} = isPredNew;
3270 let Inst{9-8} = src;
3271 let Inst{4-0} = 0b11110;
3274 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3275 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3276 let isPredicated = 1 in {
3277 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3278 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3279 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3283 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3284 let isBarrier = 1, isPredicable = 1 in
3285 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3286 LD_tc_3or4stall_SLOT0> {
3287 let BaseOpcode = "L4_RETURN";
3288 let IClass = 0b1001;
3289 let Inst{27-16} = 0b011000011110;
3290 let Inst{13-10} = 0b0000;
3291 let Inst{4-0} = 0b11110;
3293 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3294 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3297 let isReturn = 1, isTerminator = 1,
3298 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
3299 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3301 // Restore registers and dealloc return function call.
3302 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3303 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3304 def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
3305 let isExtended = 1, opExtendable = 0 in
3306 def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
3309 // Restore registers and dealloc frame before a tail call.
3310 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
3311 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
3312 let isExtended = 1, opExtendable = 0 in
3313 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
3316 // Save registers function call.
3317 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
3318 def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
3319 let isExtended = 1, opExtendable = 0 in
3320 def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
3323 //===----------------------------------------------------------------------===//
3324 // Template class for non predicated store instructions with
3325 // GP-Relative or absolute addressing.
3326 //===----------------------------------------------------------------------===//
3327 let hasSideEffects = 0, isPredicable = 1 in
3328 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3329 bits<2>MajOp, bit isAbs, bit isHalf>
3330 : STInst<(outs), (ins ImmOp:$addr, RC:$src),
3331 mnemonic # "(#$addr) = $src"#!if(isHalf, ".h",""),
3332 [], "", V2LDST_tc_st_SLOT01> {
3335 bits<16> offsetBits;
3337 string ImmOpStr = !cast<string>(ImmOp);
3338 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3339 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3340 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3341 /* u16_0Imm */ addr{15-0})));
3342 // Store upper-half and store doubleword cannot be NV.
3343 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
3345 let IClass = 0b0100;
3347 let Inst{26-25} = offsetBits{15-14};
3349 let Inst{23-22} = MajOp;
3350 let Inst{21} = isHalf;
3351 let Inst{20-16} = offsetBits{13-9};
3352 let Inst{13} = offsetBits{8};
3353 let Inst{12-8} = src;
3354 let Inst{7-0} = offsetBits{7-0};
3357 //===----------------------------------------------------------------------===//
3358 // Template class for predicated store instructions with
3359 // GP-Relative or absolute addressing.
3360 //===----------------------------------------------------------------------===//
3361 let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in
3362 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3363 bit isHalf, bit isNot, bit isNew>
3364 : STInst<(outs), (ins PredRegs:$src1, u32MustExt:$absaddr, RC: $src2),
3365 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3366 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3367 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3372 let isPredicatedNew = isNew;
3373 let isPredicatedFalse = isNot;
3374 // Store upper-half and store doubleword cannot be NV.
3375 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
3377 let IClass = 0b1010;
3379 let Inst{27-24} = 0b1111;
3380 let Inst{23-22} = MajOp;
3381 let Inst{21} = isHalf;
3382 let Inst{17-16} = absaddr{5-4};
3383 let Inst{13} = isNew;
3384 let Inst{12-8} = src2;
3386 let Inst{6-3} = absaddr{3-0};
3387 let Inst{2} = isNot;
3388 let Inst{1-0} = src1;
3391 //===----------------------------------------------------------------------===//
3392 // Template class for predicated store instructions with absolute addressing.
3393 //===----------------------------------------------------------------------===//
3394 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3395 bits<2> MajOp, bit isHalf>
3396 : T_StoreAbsGP <mnemonic, RC, u32MustExt, MajOp, 1, isHalf>,
3398 string ImmOpStr = !cast<string>(ImmOp);
3399 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3400 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3401 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3402 /* u16_0Imm */ 16)));
3404 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3405 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3406 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3407 /* u16_0Imm */ 0)));
3410 //===----------------------------------------------------------------------===//
3411 // Multiclass for store instructions with absolute addressing.
3412 //===----------------------------------------------------------------------===//
3413 let addrMode = Absolute, isExtended = 1 in
3414 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3415 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3416 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3417 let opExtendable = 0, isPredicable = 1 in
3418 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3421 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3422 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3425 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3426 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3430 //===----------------------------------------------------------------------===//
3431 // Template class for non predicated new-value store instructions with
3432 // GP-Relative or absolute addressing.
3433 //===----------------------------------------------------------------------===//
3434 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3435 isNewValue = 1, opNewValue = 1 in
3436 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3437 : NVInst_V4<(outs), (ins u32Imm:$addr, IntRegs:$src),
3438 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3439 [], "", V2LDST_tc_st_SLOT0> {
3442 bits<16> offsetBits;
3444 string ImmOpStr = !cast<string>(ImmOp);
3445 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3446 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3447 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3448 /* u16_0Imm */ addr{15-0})));
3449 let IClass = 0b0100;
3452 let Inst{26-25} = offsetBits{15-14};
3453 let Inst{24-21} = 0b0101;
3454 let Inst{20-16} = offsetBits{13-9};
3455 let Inst{13} = offsetBits{8};
3456 let Inst{12-11} = MajOp;
3457 let Inst{10-8} = src;
3458 let Inst{7-0} = offsetBits{7-0};
3461 //===----------------------------------------------------------------------===//
3462 // Template class for predicated new-value store instructions with
3463 // absolute addressing.
3464 //===----------------------------------------------------------------------===//
3465 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3466 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3467 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3468 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3469 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3470 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3471 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3476 let isPredicatedNew = isNew;
3477 let isPredicatedFalse = isNot;
3479 let IClass = 0b1010;
3481 let Inst{27-24} = 0b1111;
3482 let Inst{23-21} = 0b101;
3483 let Inst{17-16} = absaddr{5-4};
3484 let Inst{13} = isNew;
3485 let Inst{12-11} = MajOp;
3486 let Inst{10-8} = src2;
3488 let Inst{6-3} = absaddr{3-0};
3489 let Inst{2} = isNot;
3490 let Inst{1-0} = src1;
3493 //===----------------------------------------------------------------------===//
3494 // Template class for non-predicated new-value store instructions with
3495 // absolute addressing.
3496 //===----------------------------------------------------------------------===//
3497 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3498 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3500 string ImmOpStr = !cast<string>(ImmOp);
3501 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3502 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3503 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3504 /* u16_0Imm */ 16)));
3506 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3507 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3508 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3509 /* u16_0Imm */ 0)));
3512 //===----------------------------------------------------------------------===//
3513 // Multiclass for new-value store instructions with absolute addressing.
3514 //===----------------------------------------------------------------------===//
3515 let addrMode = Absolute, isExtended = 1 in
3516 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3518 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3519 let opExtendable = 0, isPredicable = 1 in
3520 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3523 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3524 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3527 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3528 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3532 //===----------------------------------------------------------------------===//
3533 // Stores with absolute addressing
3534 //===----------------------------------------------------------------------===//
3535 let accessSize = ByteAccess in
3536 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3537 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3539 let accessSize = HalfWordAccess in
3540 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3541 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3543 let accessSize = WordAccess in
3544 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3545 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3547 let isNVStorable = 0, accessSize = DoubleWordAccess in
3548 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3550 let isNVStorable = 0, accessSize = HalfWordAccess in
3551 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3553 //===----------------------------------------------------------------------===//
3554 // GP-relative stores.
3555 // mem[bhwd](#global)=Rt
3556 // Once predicated, these instructions map to absolute addressing mode.
3557 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3558 //===----------------------------------------------------------------------===//
3560 let isAsmParserOnly = 1 in
3561 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3562 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3563 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> {
3564 // Set BaseOpcode same as absolute addressing instructions so that
3565 // non-predicated GP-Rel instructions can have relate with predicated
3566 // Absolute instruction.
3567 let BaseOpcode = BaseOp#_abs;
3570 let isAsmParserOnly = 1 in
3571 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3572 bits<2> MajOp, bit isHalf = 0> {
3573 // Set BaseOpcode same as absolute addressing instructions so that
3574 // non-predicated GP-Rel instructions can have relate with predicated
3575 // Absolute instruction.
3576 let BaseOpcode = BaseOp#_abs in {
3577 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3580 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3584 let accessSize = ByteAccess in
3585 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3587 let accessSize = HalfWordAccess in
3588 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3590 let accessSize = WordAccess in
3591 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3593 let isNVStorable = 0, accessSize = DoubleWordAccess in
3594 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3595 u16_3Imm, 0b11>, PredNewRel;
3597 let isNVStorable = 0, accessSize = HalfWordAccess in
3598 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3599 u16_1Imm, 0b01, 1>, PredNewRel;
3601 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
3602 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
3604 class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
3606 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
3608 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
3609 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
3611 class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
3613 : Pat<(Store Value:$val, Addr:$addr),
3614 (MI Addr:$addr, (ValueMod Value:$val))>;
3616 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
3617 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
3618 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
3619 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdgp>;
3621 let AddedComplexity = 100 in {
3622 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>;
3623 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>;
3624 def: Storea_pat<store, I32, addrgp, S2_storerigp>;
3625 def: Storea_pat<store, I64, addrgp, S2_storerdgp>;
3627 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3628 // to "r0 = 1; memw(#foo) = r0"
3629 let AddedComplexity = 100 in
3630 def: Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3631 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3634 //===----------------------------------------------------------------------===//
3635 // Template class for non predicated load instructions with
3636 // absolute addressing mode.
3637 //===----------------------------------------------------------------------===//
3638 let isPredicable = 1, hasSideEffects = 0 in
3639 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3641 : LDInst <(outs RC:$dst), (ins ImmOp:$addr),
3642 "$dst = "#mnemonic# "(#$addr)",
3643 [], "", V2LDST_tc_ld_SLOT01> {
3646 bits<16> offsetBits;
3648 string ImmOpStr = !cast<string>(ImmOp);
3649 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3650 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3651 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3652 /* u16_0Imm */ addr{15-0})));
3654 let IClass = 0b0100;
3657 let Inst{26-25} = offsetBits{15-14};
3659 let Inst{23-21} = MajOp;
3660 let Inst{20-16} = offsetBits{13-9};
3661 let Inst{13-5} = offsetBits{8-0};
3662 let Inst{4-0} = dst;
3665 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3667 : T_LoadAbsGP <mnemonic, RC, u32MustExt, MajOp>, AddrModeRel {
3669 string ImmOpStr = !cast<string>(ImmOp);
3670 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3671 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3672 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3673 /* u16_0Imm */ 16)));
3675 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3676 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3677 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3678 /* u16_0Imm */ 0)));
3681 //===----------------------------------------------------------------------===//
3682 // Template class for predicated load instructions with
3683 // absolute addressing mode.
3684 //===----------------------------------------------------------------------===//
3685 let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6,
3687 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3688 bit isPredNot, bit isPredNew>
3689 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32MustExt:$absaddr),
3690 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3691 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3696 let isPredicatedNew = isPredNew;
3697 let isPredicatedFalse = isPredNot;
3698 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
3700 let IClass = 0b1001;
3702 let Inst{27-24} = 0b1111;
3703 let Inst{23-21} = MajOp;
3704 let Inst{20-16} = absaddr{5-1};
3706 let Inst{12} = isPredNew;
3707 let Inst{11} = isPredNot;
3708 let Inst{10-9} = src1;
3709 let Inst{8} = absaddr{0};
3711 let Inst{4-0} = dst;
3714 //===----------------------------------------------------------------------===//
3715 // Multiclass for the load instructions with absolute addressing mode.
3716 //===----------------------------------------------------------------------===//
3717 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3719 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3721 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3724 let addrMode = Absolute, isExtended = 1 in
3725 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3726 Operand ImmOp, bits<3> MajOp> {
3727 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3728 let opExtendable = 1, isPredicable = 1 in
3729 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3732 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3733 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3737 let accessSize = ByteAccess, hasNewValue = 1 in {
3738 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3739 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3742 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3743 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3744 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3747 let accessSize = WordAccess, hasNewValue = 1 in
3748 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3750 let accessSize = DoubleWordAccess in
3751 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3753 //===----------------------------------------------------------------------===//
3754 // multiclass for load instructions with GP-relative addressing mode.
3755 // Rx=mem[bhwd](##global)
3756 // Once predicated, these instructions map to absolute addressing mode.
3757 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3758 //===----------------------------------------------------------------------===//
3760 let isAsmParserOnly = 1 in
3761 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3763 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel {
3764 let BaseOpcode = BaseOp#_abs;
3767 let accessSize = ByteAccess, hasNewValue = 1 in {
3768 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3769 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3772 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3773 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3774 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3777 let accessSize = WordAccess, hasNewValue = 1 in
3778 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3780 let accessSize = DoubleWordAccess in
3781 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3783 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
3784 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
3785 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
3786 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
3788 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3789 def: Loadam_pat<load, i1, addrga, I32toI1, L4_loadrub_abs>;
3790 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
3792 def: Stoream_pat<store, I1, addrga, I1toI32, S2_storerbabs>;
3793 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
3795 // Map from load(globaladdress) -> mem[u][bhwd](#foo)
3796 class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
3797 : Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
3798 (VT (MI tglobaladdr:$global))>;
3800 let AddedComplexity = 100 in {
3801 def: LoadGP_pats <extloadi8, L2_loadrbgp>;
3802 def: LoadGP_pats <sextloadi8, L2_loadrbgp>;
3803 def: LoadGP_pats <zextloadi8, L2_loadrubgp>;
3804 def: LoadGP_pats <extloadi16, L2_loadrhgp>;
3805 def: LoadGP_pats <sextloadi16, L2_loadrhgp>;
3806 def: LoadGP_pats <zextloadi16, L2_loadruhgp>;
3807 def: LoadGP_pats <load, L2_loadrigp>;
3808 def: LoadGP_pats <load, L2_loadrdgp, i64>;
3811 // When the Interprocedural Global Variable optimizer realizes that a certain
3812 // global variable takes only two constant values, it shrinks the global to
3813 // a boolean. Catch those loads here in the following 3 patterns.
3814 let AddedComplexity = 100 in {
3815 def: LoadGP_pats <extloadi1, L2_loadrubgp>;
3816 def: LoadGP_pats <zextloadi1, L2_loadrubgp>;
3819 // Transfer global address into a register
3820 def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3821 def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3822 def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3824 let AddedComplexity = 30 in {
3825 def: Storea_pat<truncstorei8, I32, u32ImmPred, S2_storerbabs>;
3826 def: Storea_pat<truncstorei16, I32, u32ImmPred, S2_storerhabs>;
3827 def: Storea_pat<store, I32, u32ImmPred, S2_storeriabs>;
3830 let AddedComplexity = 30 in {
3831 def: Loada_pat<load, i32, u32ImmPred, L4_loadri_abs>;
3832 def: Loada_pat<sextloadi8, i32, u32ImmPred, L4_loadrb_abs>;
3833 def: Loada_pat<zextloadi8, i32, u32ImmPred, L4_loadrub_abs>;
3834 def: Loada_pat<sextloadi16, i32, u32ImmPred, L4_loadrh_abs>;
3835 def: Loada_pat<zextloadi16, i32, u32ImmPred, L4_loadruh_abs>;
3838 // Indexed store word - global address.
3839 // memw(Rs+#u6:2)=#S8
3840 let AddedComplexity = 100 in
3841 def: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
3843 // Load from a global address that has only one use in the current basic block.
3844 let AddedComplexity = 100 in {
3845 def: Loada_pat<extloadi8, i32, addrga, L4_loadrub_abs>;
3846 def: Loada_pat<sextloadi8, i32, addrga, L4_loadrb_abs>;
3847 def: Loada_pat<zextloadi8, i32, addrga, L4_loadrub_abs>;
3849 def: Loada_pat<extloadi16, i32, addrga, L4_loadruh_abs>;
3850 def: Loada_pat<sextloadi16, i32, addrga, L4_loadrh_abs>;
3851 def: Loada_pat<zextloadi16, i32, addrga, L4_loadruh_abs>;
3853 def: Loada_pat<load, i32, addrga, L4_loadri_abs>;
3854 def: Loada_pat<load, i64, addrga, L4_loadrd_abs>;
3857 // Store to a global address that has only one use in the current basic block.
3858 let AddedComplexity = 100 in {
3859 def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
3860 def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
3861 def: Storea_pat<store, I32, addrga, S2_storeriabs>;
3862 def: Storea_pat<store, I64, addrga, S2_storerdabs>;
3864 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
3867 // i8/i16/i32 -> i64 loads
3868 // We need a complexity of 120 here to override preceding handling of
3870 let AddedComplexity = 120 in {
3871 def: Loadam_pat<extloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3872 def: Loadam_pat<sextloadi8, i64, addrga, Sext64, L4_loadrb_abs>;
3873 def: Loadam_pat<zextloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3875 def: Loadam_pat<extloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3876 def: Loadam_pat<sextloadi16, i64, addrga, Sext64, L4_loadrh_abs>;
3877 def: Loadam_pat<zextloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3879 def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3880 def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
3881 def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3884 let AddedComplexity = 100 in {
3885 def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
3886 def: Loada_pat<sextloadi8, i32, addrgp, L4_loadrb_abs>;
3887 def: Loada_pat<zextloadi8, i32, addrgp, L4_loadrub_abs>;
3889 def: Loada_pat<extloadi16, i32, addrgp, L4_loadruh_abs>;
3890 def: Loada_pat<sextloadi16, i32, addrgp, L4_loadrh_abs>;
3891 def: Loada_pat<zextloadi16, i32, addrgp, L4_loadruh_abs>;
3893 def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
3894 def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
3897 let AddedComplexity = 100 in {
3898 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
3899 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
3900 def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
3901 def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
3904 def: Loada_pat<atomic_load_8, i32, addrgp, L4_loadrub_abs>;
3905 def: Loada_pat<atomic_load_16, i32, addrgp, L4_loadruh_abs>;
3906 def: Loada_pat<atomic_load_32, i32, addrgp, L4_loadri_abs>;
3907 def: Loada_pat<atomic_load_64, i64, addrgp, L4_loadrd_abs>;
3909 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbabs>;
3910 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
3911 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
3912 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
3914 let Constraints = "@earlyclobber $dst" in
3915 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3916 IntRegs:$c, IntRegs:$d),
3917 ".error \"Should never try to emit Insert4\"",
3918 [(set (i64 DoubleRegs:$dst),
3919 (or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))),
3921 (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))),
3922 (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))),
3924 (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))))]>;
3926 //===----------------------------------------------------------------------===//
3927 // :raw for of boundscheck:hi:lo insns
3928 //===----------------------------------------------------------------------===//
3930 // A4_boundscheck_lo: Detect if a register is within bounds.
3931 let hasSideEffects = 0 in
3932 def A4_boundscheck_lo: ALU64Inst <
3933 (outs PredRegs:$Pd),
3934 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3935 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
3940 let IClass = 0b1101;
3942 let Inst{27-23} = 0b00100;
3944 let Inst{7-5} = 0b100;
3946 let Inst{20-16} = Rss;
3947 let Inst{12-8} = Rtt;
3950 // A4_boundscheck_hi: Detect if a register is within bounds.
3951 let hasSideEffects = 0 in
3952 def A4_boundscheck_hi: ALU64Inst <
3953 (outs PredRegs:$Pd),
3954 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3955 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
3960 let IClass = 0b1101;
3962 let Inst{27-23} = 0b00100;
3964 let Inst{7-5} = 0b101;
3966 let Inst{20-16} = Rss;
3967 let Inst{12-8} = Rtt;
3970 let hasSideEffects = 0, isAsmParserOnly = 1 in
3971 def A4_boundscheck : MInst <
3972 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3973 "$Pd=boundscheck($Rs,$Rtt)">;
3975 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
3976 let isPredicateLate = 1, hasSideEffects = 0 in
3977 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
3978 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3979 "$Pd = tlbmatch($Rs, $Rt)",
3980 [], "", ALU64_tc_2early_SLOT23> {
3985 let IClass = 0b1101;
3986 let Inst{27-23} = 0b00100;
3987 let Inst{20-16} = Rs;
3989 let Inst{12-8} = Rt;
3990 let Inst{7-5} = 0b011;
3994 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
3995 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
3996 // We don't really want either one here.
3997 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
3998 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
4001 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
4002 // really do a load.
4003 let hasSideEffects = 1, mayLoad = 0 in
4004 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
4005 "dcfetch($Rs + #$u11_3)",
4006 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
4007 "", LD_tc_ld_SLOT0> {
4011 let IClass = 0b1001;
4012 let Inst{27-21} = 0b0100000;
4013 let Inst{20-16} = Rs;
4015 let Inst{10-0} = u11_3{13-3};
4018 //===----------------------------------------------------------------------===//
4019 // Compound instructions
4020 //===----------------------------------------------------------------------===//
4022 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4023 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4024 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4026 class CJInst_tstbit_R0<string px, bit np, string tnt>
4027 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4028 ""#px#" = tstbit($Rs, #0); if ("
4029 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4030 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4035 let isPredicatedFalse = np;
4036 // tnt: Taken/Not Taken
4037 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4038 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4040 let IClass = 0b0001;
4041 let Inst{27-26} = 0b00;
4042 let Inst{25} = !if (!eq(px, "!p1"), 1,
4043 !if (!eq(px, "p1"), 1, 0));
4044 let Inst{24-23} = 0b11;
4046 let Inst{21-20} = r9_2{10-9};
4047 let Inst{19-16} = Rs;
4048 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4049 let Inst{9-8} = 0b11;
4050 let Inst{7-1} = r9_2{8-2};
4053 let Defs = [PC, P0], Uses = [P0] in {
4054 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4055 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4056 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4057 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4060 let Defs = [PC, P1], Uses = [P1] in {
4061 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4062 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4063 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4064 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4068 let isBranch = 1, hasSideEffects = 0,
4069 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4070 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4071 opExtendable = 2, isTerminator = 1 in
4072 class CJInst_RR<string px, string op, bit np, string tnt>
4073 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4074 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4075 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4076 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4082 let isPredicatedFalse = np;
4083 // tnt: Taken/Not Taken
4084 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4085 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4087 let IClass = 0b0001;
4088 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4089 !if (!eq(op, "gt"), 0b01001,
4090 !if (!eq(op, "gtu"), 0b01010, 0)));
4092 let Inst{21-20} = r9_2{10-9};
4093 let Inst{19-16} = Rs;
4094 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4095 // px: Predicate reg 0/1
4096 let Inst{12} = !if (!eq(px, "!p1"), 1,
4097 !if (!eq(px, "p1"), 1, 0));
4098 let Inst{11-8} = Rt;
4099 let Inst{7-1} = r9_2{8-2};
4102 // P[10] taken/not taken.
4103 multiclass T_tnt_CJInst_RR<string op, bit np> {
4104 let Defs = [PC, P0], Uses = [P0] in {
4105 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4106 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4108 let Defs = [PC, P1], Uses = [P1] in {
4109 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4110 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4113 // Predicate / !Predicate
4114 multiclass T_pnp_CJInst_RR<string op>{
4115 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4116 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4118 // TypeCJ Instructions compare RR and jump
4119 defm eq : T_pnp_CJInst_RR<"eq">;
4120 defm gt : T_pnp_CJInst_RR<"gt">;
4121 defm gtu : T_pnp_CJInst_RR<"gtu">;
4123 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4124 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4125 opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
4126 class CJInst_RU5<string px, string op, bit np, string tnt>
4127 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4128 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4129 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4130 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4136 let isPredicatedFalse = np;
4137 // tnt: Taken/Not Taken
4138 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4139 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4141 let IClass = 0b0001;
4142 let Inst{27-26} = 0b00;
4143 // px: Predicate reg 0/1
4144 let Inst{25} = !if (!eq(px, "!p1"), 1,
4145 !if (!eq(px, "p1"), 1, 0));
4146 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4147 !if (!eq(op, "gt"), 0b01,
4148 !if (!eq(op, "gtu"), 0b10, 0)));
4150 let Inst{21-20} = r9_2{10-9};
4151 let Inst{19-16} = Rs;
4152 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4153 let Inst{12-8} = U5;
4154 let Inst{7-1} = r9_2{8-2};
4156 // P[10] taken/not taken.
4157 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4158 let Defs = [PC, P0], Uses = [P0] in {
4159 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4160 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4162 let Defs = [PC, P1], Uses = [P1] in {
4163 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4164 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4167 // Predicate / !Predicate
4168 multiclass T_pnp_CJInst_RU5<string op>{
4169 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4170 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4172 // TypeCJ Instructions compare RI and jump
4173 defm eq : T_pnp_CJInst_RU5<"eq">;
4174 defm gt : T_pnp_CJInst_RU5<"gt">;
4175 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4177 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4178 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4179 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4181 class CJInst_Rn1<string px, string op, bit np, string tnt>
4182 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4183 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4184 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4185 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4190 let isPredicatedFalse = np;
4191 // tnt: Taken/Not Taken
4192 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4193 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4195 let IClass = 0b0001;
4196 let Inst{27-26} = 0b00;
4197 let Inst{25} = !if (!eq(px, "!p1"), 1,
4198 !if (!eq(px, "p1"), 1, 0));
4200 let Inst{24-23} = 0b11;
4202 let Inst{21-20} = r9_2{10-9};
4203 let Inst{19-16} = Rs;
4204 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4205 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4206 !if (!eq(op, "gt"), 0b01, 0));
4207 let Inst{7-1} = r9_2{8-2};
4210 // P[10] taken/not taken.
4211 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4212 let Defs = [PC, P0], Uses = [P0] in {
4213 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4214 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4216 let Defs = [PC, P1], Uses = [P1] in {
4217 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4218 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4221 // Predicate / !Predicate
4222 multiclass T_pnp_CJInst_Rn1<string op>{
4223 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4224 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4226 // TypeCJ Instructions compare -1 and jump
4227 defm eq : T_pnp_CJInst_Rn1<"eq">;
4228 defm gt : T_pnp_CJInst_Rn1<"gt">;
4230 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4231 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4232 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4233 opExtentAlign = 2, opExtendable = 2 in
4234 def J4_jumpseti: CJInst <
4236 (ins u6Imm:$U6, brtarget:$r9_2),
4237 "$Rd = #$U6 ; jump $r9_2"> {
4242 let IClass = 0b0001;
4243 let Inst{27-24} = 0b0110;
4244 let Inst{21-20} = r9_2{10-9};
4245 let Inst{19-16} = Rd;
4246 let Inst{13-8} = U6;
4247 let Inst{7-1} = r9_2{8-2};
4250 // J4_jumpsetr: Direct unconditional jump and transfer register.
4251 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4252 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4253 opExtentAlign = 2, opExtendable = 2 in
4254 def J4_jumpsetr: CJInst <
4256 (ins IntRegs:$Rs, brtarget:$r9_2),
4257 "$Rd = $Rs ; jump $r9_2"> {
4262 let IClass = 0b0001;
4263 let Inst{27-24} = 0b0111;
4264 let Inst{21-20} = r9_2{10-9};
4265 let Inst{11-8} = Rd;
4266 let Inst{19-16} = Rs;
4267 let Inst{7-1} = r9_2{8-2};
4270 // Duplex instructions
4271 //===----------------------------------------------------------------------===//
4272 include "HexagonIsetDx.td"