1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Hexagon V4 Architecture spec defines 8 instruction classes:
15 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
19 // ========================================
20 // Loads (8/16/32/64 bit)
24 // ========================================
25 // Stores (8/16/32/64 bit)
28 // ALU32 Instructions:
29 // ========================================
30 // Arithmetic / Logical (32 bit)
33 // XTYPE Instructions (32/64 bit):
34 // ========================================
35 // Arithmetic, Logical, Bit Manipulation
36 // Multiply (Integer, Fractional, Complex)
37 // Permute / Vector Permute Operations
38 // Predicate Operations
39 // Shift / Shift with Add/Sub/Logical
41 // Vector Halfword (ALU, Shift, Multiply)
42 // Vector Word (ALU, Shift)
45 // ========================================
46 // Jump/Call PC-relative
49 // ========================================
52 // MEMOP Instructions:
53 // ========================================
54 // Operation on memory (8/16/32 bit)
57 // ========================================
62 // ========================================
63 // Control-Register Transfers
64 // Hardware Loop Setup
65 // Predicate Logicals & Reductions
67 // SYSTEM Instructions (not implemented in the compiler):
68 // ========================================
74 //===----------------------------------------------------------------------===//
76 //===----------------------------------------------------------------------===//
80 let isPredicated = 1 in
81 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
82 (ins PredRegs:$src1, IntRegs:$src2),
83 "if ($src1) $dst = aslh($src2)",
87 let isPredicated = 1 in
88 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
89 (ins PredRegs:$src1, IntRegs:$src2),
90 "if (!$src1) $dst = aslh($src2)",
94 let isPredicated = 1 in
95 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
96 (ins PredRegs:$src1, IntRegs:$src2),
97 "if ($src1.new) $dst = aslh($src2)",
101 let isPredicated = 1 in
102 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2),
104 "if (!$src1.new) $dst = aslh($src2)",
108 let isPredicated = 1 in
109 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
110 (ins PredRegs:$src1, IntRegs:$src2),
111 "if ($src1) $dst = asrh($src2)",
115 let isPredicated = 1 in
116 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
117 (ins PredRegs:$src1, IntRegs:$src2),
118 "if (!$src1) $dst = asrh($src2)",
122 let isPredicated = 1 in
123 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
124 (ins PredRegs:$src1, IntRegs:$src2),
125 "if ($src1.new) $dst = asrh($src2)",
129 let isPredicated = 1 in
130 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
131 (ins PredRegs:$src1, IntRegs:$src2),
132 "if (!$src1.new) $dst = asrh($src2)",
138 let isPredicated = 1 in
139 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
140 (ins PredRegs:$src1, IntRegs:$src2),
141 "if ($src1) $dst = sxtb($src2)",
145 let isPredicated = 1 in
146 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
147 (ins PredRegs:$src1, IntRegs:$src2),
148 "if (!$src1) $dst = sxtb($src2)",
152 let isPredicated = 1 in
153 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
154 (ins PredRegs:$src1, IntRegs:$src2),
155 "if ($src1.new) $dst = sxtb($src2)",
159 let isPredicated = 1 in
160 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
161 (ins PredRegs:$src1, IntRegs:$src2),
162 "if (!$src1.new) $dst = sxtb($src2)",
167 let isPredicated = 1 in
168 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
169 (ins PredRegs:$src1, IntRegs:$src2),
170 "if ($src1) $dst = sxth($src2)",
174 let isPredicated = 1 in
175 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
176 (ins PredRegs:$src1, IntRegs:$src2),
177 "if (!$src1) $dst = sxth($src2)",
181 let isPredicated = 1 in
182 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
183 (ins PredRegs:$src1, IntRegs:$src2),
184 "if ($src1.new) $dst = sxth($src2)",
188 let isPredicated = 1 in
189 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
190 (ins PredRegs:$src1, IntRegs:$src2),
191 "if (!$src1.new) $dst = sxth($src2)",
197 let neverHasSideEffects = 1, isPredicated = 1 in
198 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
199 (ins PredRegs:$src1, IntRegs:$src2),
200 "if ($src1) $dst = zxtb($src2)",
204 let neverHasSideEffects = 1, isPredicated = 1 in
205 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
206 (ins PredRegs:$src1, IntRegs:$src2),
207 "if (!$src1) $dst = zxtb($src2)",
211 let neverHasSideEffects = 1, isPredicated = 1 in
212 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
213 (ins PredRegs:$src1, IntRegs:$src2),
214 "if ($src1.new) $dst = zxtb($src2)",
218 let neverHasSideEffects = 1, isPredicated = 1 in
219 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
220 (ins PredRegs:$src1, IntRegs:$src2),
221 "if (!$src1.new) $dst = zxtb($src2)",
225 let neverHasSideEffects = 1, isPredicated = 1 in
226 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
227 (ins PredRegs:$src1, IntRegs:$src2),
228 "if ($src1) $dst = zxth($src2)",
232 let neverHasSideEffects = 1, isPredicated = 1 in
233 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
234 (ins PredRegs:$src1, IntRegs:$src2),
235 "if (!$src1) $dst = zxth($src2)",
239 let neverHasSideEffects = 1, isPredicated = 1 in
240 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
241 (ins PredRegs:$src1, IntRegs:$src2),
242 "if ($src1.new) $dst = zxth($src2)",
246 let neverHasSideEffects = 1, isPredicated = 1 in
247 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
248 (ins PredRegs:$src1, IntRegs:$src2),
249 "if (!$src1.new) $dst = zxth($src2)",
254 //===----------------------------------------------------------------------===//
256 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 //===----------------------------------------------------------------------===//
264 /// Make sure that in post increment load, the first operand is always the post
265 /// increment operand.
267 //// Load doubleword.
270 // Rdd=memd(Rs+Rt<<#u2)
271 // Special case pattern for indexed load without offset which is easier to
272 // match. AddedComplexity of this pattern should be lower than base+offset load
273 // and lower yet than the more generic version with offset/shift below
274 // Similar approach is taken for all other base+index loads.
275 let AddedComplexity = 10, isPredicable = 1 in
276 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
277 (ins IntRegs:$src1, IntRegs:$src2),
278 "$dst=memd($src1+$src2<<#0)",
279 [(set DoubleRegs:$dst, (load (add IntRegs:$src1,
283 let AddedComplexity = 40, isPredicable = 1 in
284 def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst),
285 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
286 "$dst=memd($src1+$src2<<#$offset)",
287 [(set DoubleRegs:$dst, (load (add IntRegs:$src1,
289 u2ImmPred:$offset))))]>,
292 //// Load doubleword conditionally.
293 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
294 // if (Pv) Rd=memd(Rs+Rt<<#u2)
295 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
296 def LDrid_indexed_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
297 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
298 "if ($src1) $dst=memd($src2+$src3<<#0)",
302 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
303 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
304 def LDrid_indexed_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
305 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
306 "if ($src1.new) $dst=memd($src2+$src3<<#0)",
310 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
311 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
312 def LDrid_indexed_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
313 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
314 "if (!$src1) $dst=memd($src2+$src3<<#0)",
318 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
319 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
320 def LDrid_indexed_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
321 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
322 "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
326 // if (Pv) Rd=memd(Rs+Rt<<#u2)
327 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
328 def LDrid_indexed_shl_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
329 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
331 "if ($src1) $dst=memd($src2+$src3<<#$offset)",
335 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
336 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
337 def LDrid_indexed_shl_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
338 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
340 "if ($src1.new) $dst=memd($src2+$src3<<#$offset)",
344 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
345 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
346 def LDrid_indexed_shl_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
347 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
349 "if (!$src1) $dst=memd($src2+$src3<<#$offset)",
353 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
354 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
355 def LDrid_indexed_shl_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
356 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
358 "if (!$src1.new) $dst=memd($src2+$src3<<#$offset)",
362 // Rdd=memd(Rt<<#u2+#U6)
367 // Rd=memb(Rs+Rt<<#u2)
368 let AddedComplexity = 10, isPredicable = 1 in
369 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
370 (ins IntRegs:$src1, IntRegs:$src2),
371 "$dst=memb($src1+$src2<<#0)",
372 [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,
376 let AddedComplexity = 10, isPredicable = 1 in
377 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
378 (ins IntRegs:$src1, IntRegs:$src2),
379 "$dst=memub($src1+$src2<<#0)",
380 [(set IntRegs:$dst, (zextloadi8 (add IntRegs:$src1,
384 let AddedComplexity = 10, isPredicable = 1 in
385 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
386 (ins IntRegs:$src1, IntRegs:$src2),
387 "$dst=memub($src1+$src2<<#0)",
388 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
392 let AddedComplexity = 40, isPredicable = 1 in
393 def LDrib_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
394 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
395 "$dst=memb($src1+$src2<<#$offset)",
397 (sextloadi8 (add IntRegs:$src1,
399 u2ImmPred:$offset))))]>,
402 let AddedComplexity = 40, isPredicable = 1 in
403 def LDriub_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
404 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
405 "$dst=memub($src1+$src2<<#$offset)",
407 (zextloadi8 (add IntRegs:$src1,
409 u2ImmPred:$offset))))]>,
412 let AddedComplexity = 40, isPredicable = 1 in
413 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
414 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
415 "$dst=memub($src1+$src2<<#$offset)",
416 [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,
418 u2ImmPred:$offset))))]>,
421 //// Load byte conditionally.
422 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
423 // if (Pv) Rd=memb(Rs+Rt<<#u2)
424 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
425 def LDrib_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
426 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
427 "if ($src1) $dst=memb($src2+$src3<<#0)",
431 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
432 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
433 def LDrib_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
434 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
435 "if ($src1.new) $dst=memb($src2+$src3<<#0)",
439 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
440 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
441 def LDrib_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
442 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
443 "if (!$src1) $dst=memb($src2+$src3<<#0)",
447 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
448 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
449 def LDrib_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
450 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
451 "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
455 // if (Pv) Rd=memb(Rs+Rt<<#u2)
456 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
457 def LDrib_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
458 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
460 "if ($src1) $dst=memb($src2+$src3<<#$offset)",
464 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
465 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
466 def LDrib_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
469 "if ($src1.new) $dst=memb($src2+$src3<<#$offset)",
473 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
474 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
475 def LDrib_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
476 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
478 "if (!$src1) $dst=memb($src2+$src3<<#$offset)",
482 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
483 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
484 def LDrib_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
485 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
487 "if (!$src1.new) $dst=memb($src2+$src3<<#$offset)",
491 //// Load unsigned byte conditionally.
492 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
493 // if (Pv) Rd=memub(Rs+Rt<<#u2)
494 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
495 def LDriub_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
496 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
497 "if ($src1) $dst=memub($src2+$src3<<#0)",
501 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
502 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
503 def LDriub_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
504 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
505 "if ($src1.new) $dst=memub($src2+$src3<<#0)",
509 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
510 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
511 def LDriub_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
512 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
513 "if (!$src1) $dst=memub($src2+$src3<<#0)",
517 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
518 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
519 def LDriub_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
520 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
521 "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
525 // if (Pv) Rd=memub(Rs+Rt<<#u2)
526 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
527 def LDriub_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
528 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
530 "if ($src1) $dst=memub($src2+$src3<<#$offset)",
534 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
535 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
536 def LDriub_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
537 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
539 "if ($src1.new) $dst=memub($src2+$src3<<#$offset)",
543 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
544 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
545 def LDriub_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
546 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
548 "if (!$src1) $dst=memub($src2+$src3<<#$offset)",
552 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
553 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
554 def LDriub_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
555 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
557 "if (!$src1.new) $dst=memub($src2+$src3<<#$offset)",
561 // Rd=memb(Rt<<#u2+#U6)
566 // Rd=memh(Rs+Rt<<#u2)
567 let AddedComplexity = 10, isPredicable = 1 in
568 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
569 (ins IntRegs:$src1, IntRegs:$src2),
570 "$dst=memh($src1+$src2<<#0)",
571 [(set IntRegs:$dst, (sextloadi16 (add IntRegs:$src1,
575 let AddedComplexity = 10, isPredicable = 1 in
576 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
577 (ins IntRegs:$src1, IntRegs:$src2),
578 "$dst=memuh($src1+$src2<<#0)",
579 [(set IntRegs:$dst, (zextloadi16 (add IntRegs:$src1,
583 let AddedComplexity = 10, isPredicable = 1 in
584 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
585 (ins IntRegs:$src1, IntRegs:$src2),
586 "$dst=memuh($src1+$src2<<#0)",
587 [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,
591 // Rd=memh(Rs+Rt<<#u2)
592 let AddedComplexity = 40, isPredicable = 1 in
593 def LDrih_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
594 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
595 "$dst=memh($src1+$src2<<#$offset)",
597 (sextloadi16 (add IntRegs:$src1,
599 u2ImmPred:$offset))))]>,
602 let AddedComplexity = 40, isPredicable = 1 in
603 def LDriuh_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
604 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
605 "$dst=memuh($src1+$src2<<#$offset)",
607 (zextloadi16 (add IntRegs:$src1,
609 u2ImmPred:$offset))))]>,
612 let AddedComplexity = 40, isPredicable = 1 in
613 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
614 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
615 "$dst=memuh($src1+$src2<<#$offset)",
617 (extloadi16 (add IntRegs:$src1,
619 u2ImmPred:$offset))))]>,
622 //// Load halfword conditionally.
623 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
624 // if (Pv) Rd=memh(Rs+Rt<<#u2)
625 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
626 def LDrih_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
627 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
628 "if ($src1) $dst=memh($src2+$src3<<#0)",
632 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
633 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
634 def LDrih_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
635 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
636 "if ($src1.new) $dst=memh($src2+$src3<<#0)",
640 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
641 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
642 def LDrih_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
643 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
644 "if (!$src1) $dst=memh($src2+$src3<<#0)",
648 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
649 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
650 def LDrih_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
651 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
652 "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
656 // if (Pv) Rd=memh(Rs+Rt<<#u2)
657 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
658 def LDrih_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
659 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
661 "if ($src1) $dst=memh($src2+$src3<<#$offset)",
665 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
666 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
667 def LDrih_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
668 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
670 "if ($src1.new) $dst=memh($src2+$src3<<#$offset)",
674 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
675 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
676 def LDrih_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
677 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
679 "if (!$src1) $dst=memh($src2+$src3<<#$offset)",
683 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
684 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
685 def LDrih_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
686 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
688 "if (!$src1.new) $dst=memh($src2+$src3<<#$offset)",
692 //// Load unsigned halfword conditionally.
693 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
694 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
695 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
696 def LDriuh_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
697 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
698 "if ($src1) $dst=memuh($src2+$src3<<#0)",
702 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
703 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
704 def LDriuh_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
705 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
706 "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
710 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
711 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
712 def LDriuh_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
713 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
714 "if (!$src1) $dst=memuh($src2+$src3<<#0)",
718 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
719 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
720 def LDriuh_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
721 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
722 "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
726 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
727 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
728 def LDriuh_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
729 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
731 "if ($src1) $dst=memuh($src2+$src3<<#$offset)",
735 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
736 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
737 def LDriuh_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
738 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
740 "if ($src1.new) $dst=memuh($src2+$src3<<#$offset)",
744 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
745 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
746 def LDriuh_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
747 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
749 "if (!$src1) $dst=memuh($src2+$src3<<#$offset)",
753 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
754 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
755 def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
756 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
758 "if (!$src1.new) $dst=memuh($src2+$src3<<#$offset)",
762 // Rd=memh(Rt<<#u2+#U6)
767 // Rd=memw(Rs+Rt<<#u2)
768 let AddedComplexity = 10, isPredicable = 1 in
769 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
770 (ins IntRegs:$src1, IntRegs:$src2),
771 "$dst=memw($src1+$src2<<#0)",
772 [(set IntRegs:$dst, (load (add IntRegs:$src1,
776 // Rd=memw(Rs+Rt<<#u2)
777 let AddedComplexity = 40, isPredicable = 1 in
778 def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
779 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
780 "$dst=memw($src1+$src2<<#$offset)",
781 [(set IntRegs:$dst, (load (add IntRegs:$src1,
783 u2ImmPred:$offset))))]>,
786 //// Load word conditionally.
787 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
788 // if (Pv) Rd=memw(Rs+Rt<<#u2)
789 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
790 def LDriw_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
791 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
792 "if ($src1) $dst=memw($src2+$src3<<#0)",
796 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
797 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
798 def LDriw_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
799 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
800 "if ($src1.new) $dst=memw($src2+$src3<<#0)",
804 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
805 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
806 def LDriw_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
807 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
808 "if (!$src1) $dst=memw($src2+$src3<<#0)",
812 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
813 let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
814 def LDriw_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
815 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
816 "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
820 // if (Pv) Rd=memh(Rs+Rt<<#u2)
821 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
822 def LDriw_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
823 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
825 "if ($src1) $dst=memw($src2+$src3<<#$offset)",
829 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
830 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
831 def LDriw_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
832 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
834 "if ($src1.new) $dst=memw($src2+$src3<<#$offset)",
838 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
839 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
840 def LDriw_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
841 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
843 "if (!$src1) $dst=memw($src2+$src3<<#$offset)",
847 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
848 let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
849 def LDriw_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
850 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
852 "if (!$src1.new) $dst=memw($src2+$src3<<#$offset)",
856 // Rd=memw(Rt<<#u2+#U6)
859 // Post-inc Load, Predicated, Dot new
862 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
863 def POST_LDrid_cdnPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
864 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
865 "if ($src1.new) $dst1 = memd($src2++#$src3)",
870 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
871 def POST_LDrid_cdnNotPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
872 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
873 "if (!$src1.new) $dst1 = memd($src2++#$src3)",
878 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
879 def POST_LDrib_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
880 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
881 "if ($src1.new) $dst1 = memb($src2++#$src3)",
886 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
887 def POST_LDrib_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
888 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
889 "if (!$src1.new) $dst1 = memb($src2++#$src3)",
894 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
895 def POST_LDrih_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
896 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
897 "if ($src1.new) $dst1 = memh($src2++#$src3)",
902 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
903 def POST_LDrih_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
904 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
905 "if (!$src1.new) $dst1 = memh($src2++#$src3)",
910 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
911 def POST_LDriub_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
912 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
913 "if ($src1.new) $dst1 = memub($src2++#$src3)",
918 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
919 def POST_LDriub_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
920 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
921 "if (!$src1.new) $dst1 = memub($src2++#$src3)",
926 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
927 def POST_LDriuh_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
928 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
929 "if ($src1.new) $dst1 = memuh($src2++#$src3)",
934 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
935 def POST_LDriuh_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
936 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
937 "if (!$src1.new) $dst1 = memuh($src2++#$src3)",
942 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
943 def POST_LDriw_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
944 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
945 "if ($src1.new) $dst1 = memw($src2++#$src3)",
950 let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
951 def POST_LDriw_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
952 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
953 "if (!$src1.new) $dst1 = memw($src2++#$src3)",
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
963 //===----------------------------------------------------------------------===//
965 //===----------------------------------------------------------------------===//
967 /// Assumptions::: ****** DO NOT IGNORE ********
968 /// 1. Make sure that in post increment store, the zero'th operand is always the
969 /// post increment operand.
970 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
976 // TODO: needs to be implemented
978 // memd(Rs+#s11:3)=Rtt
979 // memd(Rs+Ru<<#u2)=Rtt
980 let AddedComplexity = 10, isPredicable = 1 in
981 def STrid_indexed_shl_V4 : STInst<(outs),
982 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),
983 "memd($src1+$src2<<#$src3) = $src4",
984 [(store DoubleRegs:$src4, (add IntRegs:$src1,
985 (shl IntRegs:$src2, u2ImmPred:$src3)))]>,
988 // memd(Ru<<#u2+#U6)=Rtt
989 let AddedComplexity = 10 in
990 def STrid_shl_V4 : STInst<(outs),
991 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
992 "memd($src1<<#$src2+#$src3) = $src4",
993 [(store DoubleRegs:$src4, (shl IntRegs:$src1,
994 (add u2ImmPred:$src2,
995 u6ImmPred:$src3)))]>,
998 // memd(Rx++#s4:3)=Rtt
999 // memd(Rx++#s4:3:circ(Mu))=Rtt
1000 // memd(Rx++I:circ(Mu))=Rtt
1002 // memd(Rx++Mu:brev)=Rtt
1003 // memd(gp+#u16:3)=Rtt
1005 // Store doubleword conditionally.
1006 // if ([!]Pv[.new]) memd(#u6)=Rtt
1007 // TODO: needs to be implemented.
1009 // if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt
1010 // if (Pv) memd(Rs+#u6:3)=Rtt
1011 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1012 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1013 def STrid_cdnPt_V4 : STInst<(outs),
1014 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1015 "if ($src1.new) memd($addr) = $src2",
1019 // if (!Pv) memd(Rs+#u6:3)=Rtt
1020 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1021 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1022 def STrid_cdnNotPt_V4 : STInst<(outs),
1023 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1024 "if (!$src1.new) memd($addr) = $src2",
1028 // if (Pv) memd(Rs+#u6:3)=Rtt
1029 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1030 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1031 def STrid_indexed_cdnPt_V4 : STInst<(outs),
1032 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1034 "if ($src1.new) memd($src2+#$src3) = $src4",
1038 // if (!Pv) memd(Rs+#u6:3)=Rtt
1039 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1040 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1041 def STrid_indexed_cdnNotPt_V4 : STInst<(outs),
1042 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1044 "if (!$src1.new) memd($src2+#$src3) = $src4",
1048 // if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt
1049 // if (Pv) memd(Rs+Ru<<#u2)=Rtt
1050 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1051 def STrid_indexed_shl_cPt_V4 : STInst<(outs),
1052 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1054 "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1058 // if (Pv.new) memd(Rs+Ru<<#u2)=Rtt
1059 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1060 def STrid_indexed_shl_cdnPt_V4 : STInst<(outs),
1061 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1063 "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1066 // if (!Pv) memd(Rs+Ru<<#u2)=Rtt
1067 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1068 def STrid_indexed_shl_cNotPt_V4 : STInst<(outs),
1069 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1071 "if (!$src1) memd($src2+$src3<<#$src4) = $src5",
1074 // if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt
1075 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1076 def STrid_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1077 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1079 "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",
1083 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1084 // if (Pv) memd(Rx++#s4:3)=Rtt
1085 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1086 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1087 def POST_STdri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1088 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1090 "if ($src1.new) memd($src3++#$offset) = $src2",
1095 // if (!Pv) memd(Rx++#s4:3)=Rtt
1096 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1097 let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
1098 def POST_STdri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1099 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1101 "if (!$src1.new) memd($src3++#$offset) = $src2",
1109 // TODO: needs to be implemented.
1110 // memb(Rs+#s11:0)=Rt
1111 // memb(Rs+#u6:0)=#S8
1112 let AddedComplexity = 10, isPredicable = 1 in
1113 def STrib_imm_V4 : STInst<(outs),
1114 (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
1115 "memb($src1+#$src2) = #$src3",
1116 [(truncstorei8 s8ImmPred:$src3, (add IntRegs:$src1,
1117 u6_0ImmPred:$src2))]>,
1120 // memb(Rs+Ru<<#u2)=Rt
1121 let AddedComplexity = 10, isPredicable = 1 in
1122 def STrib_indexed_shl_V4 : STInst<(outs),
1123 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1124 "memb($src1+$src2<<#$src3) = $src4",
1125 [(truncstorei8 IntRegs:$src4, (add IntRegs:$src1,
1127 u2ImmPred:$src3)))]>,
1130 // memb(Ru<<#u2+#U6)=Rt
1131 let AddedComplexity = 10 in
1132 def STrib_shl_V4 : STInst<(outs),
1133 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1134 "memb($src1<<#$src2+#$src3) = $src4",
1135 [(truncstorei8 IntRegs:$src4, (shl IntRegs:$src1,
1136 (add u2ImmPred:$src2,
1137 u6ImmPred:$src3)))]>,
1140 // memb(Rx++#s4:0:circ(Mu))=Rt
1141 // memb(Rx++I:circ(Mu))=Rt
1143 // memb(Rx++Mu:brev)=Rt
1144 // memb(gp+#u16:0)=Rt
1147 // Store byte conditionally.
1148 // if ([!]Pv[.new]) memb(#u6)=Rt
1149 // if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6
1150 // if (Pv) memb(Rs+#u6:0)=#S6
1151 let mayStore = 1, neverHasSideEffects = 1 in
1152 def STrib_imm_cPt_V4 : STInst<(outs),
1153 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1154 "if ($src1) memb($src2+#$src3) = #$src4",
1158 // if (Pv.new) memb(Rs+#u6:0)=#S6
1159 let mayStore = 1, neverHasSideEffects = 1 in
1160 def STrib_imm_cdnPt_V4 : STInst<(outs),
1161 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1162 "if ($src1.new) memb($src2+#$src3) = #$src4",
1166 // if (!Pv) memb(Rs+#u6:0)=#S6
1167 let mayStore = 1, neverHasSideEffects = 1 in
1168 def STrib_imm_cNotPt_V4 : STInst<(outs),
1169 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1170 "if (!$src1) memb($src2+#$src3) = #$src4",
1174 // if (!Pv.new) memb(Rs+#u6:0)=#S6
1175 let mayStore = 1, neverHasSideEffects = 1 in
1176 def STrib_imm_cdnNotPt_V4 : STInst<(outs),
1177 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1178 "if (!$src1.new) memb($src2+#$src3) = #$src4",
1182 // if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt
1183 // if (Pv) memb(Rs+#u6:0)=Rt
1184 // if (Pv.new) memb(Rs+#u6:0)=Rt
1185 let mayStore = 1, neverHasSideEffects = 1 in
1186 def STrib_cdnPt_V4 : STInst<(outs),
1187 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1188 "if ($src1.new) memb($addr) = $src2",
1192 // if (!Pv) memb(Rs+#u6:0)=Rt
1193 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1194 let mayStore = 1, neverHasSideEffects = 1 in
1195 def STrib_cdnNotPt_V4 : STInst<(outs),
1196 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1197 "if (!$src1.new) memb($addr) = $src2",
1201 // if (Pv) memb(Rs+#u6:0)=Rt
1202 // if (!Pv) memb(Rs+#u6:0)=Rt
1203 // if (Pv.new) memb(Rs+#u6:0)=Rt
1204 let mayStore = 1, neverHasSideEffects = 1 in
1205 def STrib_indexed_cdnPt_V4 : STInst<(outs),
1206 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1207 "if ($src1.new) memb($src2+#$src3) = $src4",
1211 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1212 let mayStore = 1, neverHasSideEffects = 1 in
1213 def STrib_indexed_cdnNotPt_V4 : STInst<(outs),
1214 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1215 "if (!$src1.new) memb($src2+#$src3) = $src4",
1219 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt
1220 // if (Pv) memb(Rs+Ru<<#u2)=Rt
1221 let mayStore = 1, AddedComplexity = 10 in
1222 def STrib_indexed_shl_cPt_V4 : STInst<(outs),
1223 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1225 "if ($src1) memb($src2+$src3<<#$src4) = $src5",
1229 // if (Pv.new) memb(Rs+Ru<<#u2)=Rt
1230 let mayStore = 1, AddedComplexity = 10 in
1231 def STrib_indexed_shl_cdnPt_V4 : STInst<(outs),
1232 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1234 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5",
1238 // if (!Pv) memb(Rs+Ru<<#u2)=Rt
1239 let mayStore = 1, AddedComplexity = 10 in
1240 def STrib_indexed_shl_cNotPt_V4 : STInst<(outs),
1241 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1243 "if (!$src1) memb($src2+$src3<<#$src4) = $src5",
1247 // if (!Pv.new) memb(Rs+Ru<<#u2)=Rt
1248 let mayStore = 1, AddedComplexity = 10 in
1249 def STrib_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1250 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1252 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5",
1256 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1257 // if (Pv) memb(Rx++#s4:0)=Rt
1258 // if (Pv.new) memb(Rx++#s4:0)=Rt
1259 let mayStore = 1, hasCtrlDep = 1 in
1260 def POST_STbri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1261 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1262 "if ($src1.new) memb($src3++#$offset) = $src2",
1266 // if (!Pv) memb(Rx++#s4:0)=Rt
1267 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1268 let mayStore = 1, hasCtrlDep = 1 in
1269 def POST_STbri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1270 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1271 "if (!$src1.new) memb($src3++#$offset) = $src2",
1277 // memh(Re=#U6)=Rt.H
1278 // TODO: needs to be implemented
1281 // TODO: needs to be implemented
1283 // memh(Rs+#s11:1)=Rt.H
1284 // memh(Rs+#s11:1)=Rt
1285 // memh(Rs+#u6:1)=#S8
1286 let AddedComplexity = 10, isPredicable = 1 in
1287 def STrih_imm_V4 : STInst<(outs),
1288 (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
1289 "memh($src1+#$src2) = #$src3",
1290 [(truncstorei16 s8ImmPred:$src3, (add IntRegs:$src1,
1291 u6_1ImmPred:$src2))]>,
1294 // memh(Rs+Ru<<#u2)=Rt.H
1295 // TODO: needs to be implemented.
1297 // memh(Rs+Ru<<#u2)=Rt
1298 let AddedComplexity = 10, isPredicable = 1 in
1299 def STrih_indexed_shl_V4 : STInst<(outs),
1300 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1301 "memh($src1+$src2<<#$src3) = $src4",
1302 [(truncstorei16 IntRegs:$src4, (add IntRegs:$src1,
1304 u2ImmPred:$src3)))]>,
1307 // memh(Ru<<#u2+#U6)=Rt.H
1308 // memh(Ru<<#u2+#U6)=Rt
1309 let AddedComplexity = 10 in
1310 def STrih_shl_V4 : STInst<(outs),
1311 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1312 "memh($src1<<#$src2+#$src3) = $src4",
1313 [(truncstorei16 IntRegs:$src4, (shl IntRegs:$src1,
1314 (add u2ImmPred:$src2,
1315 u6ImmPred:$src3)))]>,
1318 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1319 // memh(Rx++#s4:1:circ(Mu))=Rt
1320 // memh(Rx++I:circ(Mu))=Rt.H
1321 // memh(Rx++I:circ(Mu))=Rt
1322 // memh(Rx++Mu)=Rt.H
1324 // memh(Rx++Mu:brev)=Rt.H
1325 // memh(Rx++Mu:brev)=Rt
1326 // memh(gp+#u16:1)=Rt.H
1327 // memh(gp+#u16:1)=Rt
1330 // Store halfword conditionally.
1331 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1332 // if ([!]Pv[.new]) memh(#u6)=Rt
1334 // if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6
1335 // if (Pv) memh(Rs+#u6:1)=#S6
1336 let mayStore = 1, neverHasSideEffects = 1 in
1337 def STrih_imm_cPt_V4 : STInst<(outs),
1338 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1339 "if ($src1) memh($src2+#$src3) = #$src4",
1343 // if (Pv.new) memh(Rs+#u6:1)=#S6
1344 let mayStore = 1, neverHasSideEffects = 1 in
1345 def STrih_imm_cdnPt_V4 : STInst<(outs),
1346 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1347 "if ($src1.new) memh($src2+#$src3) = #$src4",
1351 // if (!Pv) memh(Rs+#u6:1)=#S6
1352 let mayStore = 1, neverHasSideEffects = 1 in
1353 def STrih_imm_cNotPt_V4 : STInst<(outs),
1354 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1355 "if (!$src1) memh($src2+#$src3) = #$src4",
1359 // if (!Pv.new) memh(Rs+#u6:1)=#S6
1360 let mayStore = 1, neverHasSideEffects = 1 in
1361 def STrih_imm_cdnNotPt_V4 : STInst<(outs),
1362 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1363 "if (!$src1.new) memh($src2+#$src3) = #$src4",
1367 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1368 // TODO: needs to be implemented.
1370 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt
1371 // if (Pv) memh(Rs+#u6:1)=Rt
1372 // if (Pv.new) memh(Rs+#u6:1)=Rt
1373 let mayStore = 1, neverHasSideEffects = 1 in
1374 def STrih_cdnPt_V4 : STInst<(outs),
1375 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1376 "if ($src1.new) memh($addr) = $src2",
1380 // if (!Pv) memh(Rs+#u6:1)=Rt
1381 // if (!Pv.new) memh(Rs+#u6:1)=Rt
1382 let mayStore = 1, neverHasSideEffects = 1 in
1383 def STrih_cdnNotPt_V4 : STInst<(outs),
1384 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1385 "if (!$src1.new) memh($addr) = $src2",
1389 // if (Pv.new) memh(Rs+#u6:1)=Rt
1390 let mayStore = 1, neverHasSideEffects = 1 in
1391 def STrih_indexed_cdnPt_V4 : STInst<(outs),
1392 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1393 "if ($src1.new) memh($src2+#$src3) = $src4",
1397 // if (!Pv.new) memh(Rs+#u6:1)=Rt
1398 let mayStore = 1, neverHasSideEffects = 1 in
1399 def STrih_indexed_cdnNotPt_V4 : STInst<(outs),
1400 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1401 "if (!$src1.new) memh($src2+#$src3) = $src4",
1405 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H
1406 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt
1407 // if (Pv) memh(Rs+Ru<<#u2)=Rt
1408 let mayStore = 1, AddedComplexity = 10 in
1409 def STrih_indexed_shl_cPt_V4 : STInst<(outs),
1410 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1412 "if ($src1) memh($src2+$src3<<#$src4) = $src5",
1416 // if (Pv.new) memh(Rs+Ru<<#u2)=Rt
1417 def STrih_indexed_shl_cdnPt_V4 : STInst<(outs),
1418 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1420 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5",
1424 // if (!Pv) memh(Rs+Ru<<#u2)=Rt
1425 let mayStore = 1, AddedComplexity = 10 in
1426 def STrih_indexed_shl_cNotPt_V4 : STInst<(outs),
1427 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1429 "if (!$src1) memh($src2+$src3<<#$src4) = $src5",
1433 // if (!Pv.new) memh(Rs+Ru<<#u2)=Rt
1434 let mayStore = 1, AddedComplexity = 10 in
1435 def STrih_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1436 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1438 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5",
1442 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1443 // TODO: Needs to be implemented.
1445 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1446 // if (Pv) memh(Rx++#s4:1)=Rt
1447 // if (Pv.new) memh(Rx++#s4:1)=Rt
1448 let mayStore = 1, hasCtrlDep = 1 in
1449 def POST_SThri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1450 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1451 "if ($src1.new) memh($src3++#$offset) = $src2",
1455 // if (!Pv) memh(Rx++#s4:1)=Rt
1456 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1457 let mayStore = 1, hasCtrlDep = 1 in
1458 def POST_SThri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1459 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1460 "if (!$src1.new) memh($src3++#$offset) = $src2",
1467 // TODO: Needs to be implemented.
1469 // memw(Rs+#s11:2)=Rt
1470 // memw(Rs+#u6:2)=#S8
1471 let AddedComplexity = 10, isPredicable = 1 in
1472 def STriw_imm_V4 : STInst<(outs),
1473 (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
1474 "memw($src1+#$src2) = #$src3",
1475 [(store s8ImmPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
1478 // memw(Rs+Ru<<#u2)=Rt
1479 let AddedComplexity = 10, isPredicable = 1 in
1480 def STriw_indexed_shl_V4 : STInst<(outs),
1481 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1482 "memw($src1+$src2<<#$src3) = $src4",
1483 [(store IntRegs:$src4, (add IntRegs:$src1,
1484 (shl IntRegs:$src2, u2ImmPred:$src3)))]>,
1487 // memw(Ru<<#u2+#U6)=Rt
1488 let AddedComplexity = 10 in
1489 def STriw_shl_V4 : STInst<(outs),
1490 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1491 "memw($src1<<#$src2+#$src3) = $src4",
1492 [(store IntRegs:$src4, (shl IntRegs:$src1,
1493 (add u2ImmPred:$src2, u6ImmPred:$src3)))]>,
1496 // memw(Rx++#s4:2)=Rt
1497 // memw(Rx++#s4:2:circ(Mu))=Rt
1498 // memw(Rx++I:circ(Mu))=Rt
1500 // memw(Rx++Mu:brev)=Rt
1501 // memw(gp+#u16:2)=Rt
1504 // Store word conditionally.
1505 // if ([!]Pv[.new]) memw(#u6)=Rt
1506 // TODO: Needs to be implemented.
1508 // if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6
1509 // if (Pv) memw(Rs+#u6:2)=#S6
1510 let mayStore = 1, neverHasSideEffects = 1 in
1511 def STriw_imm_cPt_V4 : STInst<(outs),
1512 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1513 "if ($src1) memw($src2+#$src3) = #$src4",
1517 // if (Pv.new) memw(Rs+#u6:2)=#S6
1518 let mayStore = 1, neverHasSideEffects = 1 in
1519 def STriw_imm_cdnPt_V4 : STInst<(outs),
1520 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1521 "if ($src1.new) memw($src2+#$src3) = #$src4",
1525 // if (!Pv) memw(Rs+#u6:2)=#S6
1526 let mayStore = 1, neverHasSideEffects = 1 in
1527 def STriw_imm_cNotPt_V4 : STInst<(outs),
1528 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1529 "if (!$src1) memw($src2+#$src3) = #$src4",
1533 // if (!Pv.new) memw(Rs+#u6:2)=#S6
1534 let mayStore = 1, neverHasSideEffects = 1 in
1535 def STriw_imm_cdnNotPt_V4 : STInst<(outs),
1536 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1537 "if (!$src1.new) memw($src2+#$src3) = #$src4",
1541 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt
1542 // if (Pv) memw(Rs+#u6:2)=Rt
1543 // if (Pv.new) memw(Rs+#u6:2)=Rt
1544 let mayStore = 1, neverHasSideEffects = 1 in
1545 def STriw_cdnPt_V4 : STInst<(outs),
1546 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1547 "if ($src1.new) memw($addr) = $src2",
1551 // if (!Pv) memw(Rs+#u6:2)=Rt
1552 // if (!Pv.new) memw(Rs+#u6:2)=Rt
1553 let mayStore = 1, neverHasSideEffects = 1 in
1554 def STriw_cdnNotPt_V4 : STInst<(outs),
1555 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1556 "if (!$src1.new) memw($addr) = $src2",
1560 // if (Pv) memw(Rs+#u6:2)=Rt
1561 // if (!Pv) memw(Rs+#u6:2)=Rt
1562 // if (Pv.new) memw(Rs+#u6:2)=Rt
1563 let mayStore = 1, neverHasSideEffects = 1 in
1564 def STriw_indexed_cdnPt_V4 : STInst<(outs),
1565 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
1566 "if ($src1.new) memw($src2+#$src3) = $src4",
1570 // if (!Pv.new) memw(Rs+#u6:2)=Rt
1571 let mayStore = 1, neverHasSideEffects = 1 in
1572 def STriw_indexed_cdnNotPt_V4 : STInst<(outs),
1573 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
1574 "if (!$src1.new) memw($src2+#$src3) = $src4",
1578 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt
1579 // if (Pv) memw(Rs+Ru<<#u2)=Rt
1580 let mayStore = 1, AddedComplexity = 10 in
1581 def STriw_indexed_shl_cPt_V4 : STInst<(outs),
1582 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1584 "if ($src1) memw($src2+$src3<<#$src4) = $src5",
1588 // if (Pv.new) memw(Rs+Ru<<#u2)=Rt
1589 let mayStore = 1, AddedComplexity = 10 in
1590 def STriw_indexed_shl_cdnPt_V4 : STInst<(outs),
1591 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1593 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5",
1597 // if (!Pv) memw(Rs+Ru<<#u2)=Rt
1598 let mayStore = 1, AddedComplexity = 10 in
1599 def STriw_indexed_shl_cNotPt_V4 : STInst<(outs),
1600 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1602 "if (!$src1) memw($src2+$src3<<#$src4) = $src5",
1606 // if (!Pv.new) memw(Rs+Ru<<#u2)=Rt
1607 let mayStore = 1, AddedComplexity = 10 in
1608 def STriw_indexed_shl_cdnNotPt_V4 : STInst<(outs),
1609 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1611 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5",
1615 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
1616 // if (Pv) memw(Rx++#s4:2)=Rt
1617 // if (Pv.new) memw(Rx++#s4:2)=Rt
1618 let mayStore = 1, hasCtrlDep = 1 in
1619 def POST_STwri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),
1620 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1621 "if ($src1.new) memw($src3++#$offset) = $src2",
1625 // if (!Pv) memw(Rx++#s4:2)=Rt
1626 // if (!Pv.new) memw(Rx++#s4:2)=Rt
1627 let mayStore = 1, hasCtrlDep = 1 in
1628 def POST_STwri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),
1629 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1630 "if (!$src1.new) memw($src3++#$offset) = $src2",
1635 //===----------------------------------------------------------------------===
1637 //===----------------------------------------------------------------------===
1640 //===----------------------------------------------------------------------===//
1642 //===----------------------------------------------------------------------===//
1644 // Store new-value byte.
1646 // memb(Re=#U6)=Nt.new
1647 // memb(Rs+#s11:0)=Nt.new
1648 let mayStore = 1, isPredicable = 1 in
1649 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
1650 "memb($addr) = $src1.new",
1654 let mayStore = 1, isPredicable = 1 in
1655 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
1656 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
1657 "memb($src1+#$src2) = $src3.new",
1661 // memb(Rs+Ru<<#u2)=Nt.new
1662 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
1663 def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs),
1664 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1665 "memb($src1+$src2<<#$src3) = $src4.new",
1669 // memb(Ru<<#u2+#U6)=Nt.new
1670 let mayStore = 1, AddedComplexity = 10 in
1671 def STrib_shl_nv_V4 : NVInst_V4<(outs),
1672 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1673 "memb($src1<<#$src2+#$src3) = $src4.new",
1677 // memb(Rx++#s4:0)=Nt.new
1678 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
1679 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1680 (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
1681 "memb($src2++#$offset) = $src1.new",
1686 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1687 // memb(Rx++I:circ(Mu))=Nt.new
1688 // memb(Rx++Mu)=Nt.new
1689 // memb(Rx++Mu:brev)=Nt.new
1691 // memb(gp+#u16:0)=Nt.new
1692 let mayStore = 1, neverHasSideEffects = 1 in
1693 def STrib_GP_nv_V4 : NVInst_V4<(outs),
1694 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1695 "memb(#$global+$offset) = $src.new",
1700 // Store new-value byte conditionally.
1701 // if ([!]Pv[.new]) memb(#u6)=Nt.new
1702 // if (Pv) memb(Rs+#u6:0)=Nt.new
1703 let mayStore = 1, neverHasSideEffects = 1 in
1704 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
1705 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1706 "if ($src1) memb($addr) = $src2.new",
1710 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
1711 let mayStore = 1, neverHasSideEffects = 1 in
1712 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
1713 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1714 "if ($src1.new) memb($addr) = $src2.new",
1718 // if (!Pv) memb(Rs+#u6:0)=Nt.new
1719 let mayStore = 1, neverHasSideEffects = 1 in
1720 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
1721 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1722 "if (!$src1) memb($addr) = $src2.new",
1726 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
1727 let mayStore = 1, neverHasSideEffects = 1 in
1728 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1729 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1730 "if (!$src1.new) memb($addr) = $src2.new",
1734 // if (Pv) memb(Rs+#u6:0)=Nt.new
1735 let mayStore = 1, neverHasSideEffects = 1 in
1736 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
1737 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1738 "if ($src1) memb($src2+#$src3) = $src4.new",
1742 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
1743 let mayStore = 1, neverHasSideEffects = 1 in
1744 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
1745 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1746 "if ($src1.new) memb($src2+#$src3) = $src4.new",
1750 // if (!Pv) memb(Rs+#u6:0)=Nt.new
1751 let mayStore = 1, neverHasSideEffects = 1 in
1752 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
1753 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1754 "if (!$src1) memb($src2+#$src3) = $src4.new",
1758 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
1759 let mayStore = 1, neverHasSideEffects = 1 in
1760 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1761 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1762 "if (!$src1.new) memb($src2+#$src3) = $src4.new",
1767 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new
1768 // if (Pv) memb(Rs+Ru<<#u2)=Nt.new
1769 let mayStore = 1, AddedComplexity = 10 in
1770 def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
1771 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1773 "if ($src1) memb($src2+$src3<<#$src4) = $src5.new",
1777 // if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new
1778 let mayStore = 1, AddedComplexity = 10 in
1779 def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
1780 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1782 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5.new",
1786 // if (!Pv) memb(Rs+Ru<<#u2)=Nt.new
1787 let mayStore = 1, AddedComplexity = 10 in
1788 def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
1789 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1791 "if (!$src1) memb($src2+$src3<<#$src4) = $src5.new",
1795 // if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new
1796 let mayStore = 1, AddedComplexity = 10 in
1797 def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1798 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1800 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5.new",
1804 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
1805 // if (Pv) memb(Rx++#s4:0)=Nt.new
1806 let mayStore = 1, hasCtrlDep = 1 in
1807 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1808 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1809 "if ($src1) memb($src3++#$offset) = $src2.new",
1813 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
1814 let mayStore = 1, hasCtrlDep = 1 in
1815 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1816 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1817 "if ($src1.new) memb($src3++#$offset) = $src2.new",
1821 // if (!Pv) memb(Rx++#s4:0)=Nt.new
1822 let mayStore = 1, hasCtrlDep = 1 in
1823 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1824 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1825 "if (!$src1) memb($src3++#$offset) = $src2.new",
1829 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
1830 let mayStore = 1, hasCtrlDep = 1 in
1831 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1832 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1833 "if (!$src1.new) memb($src3++#$offset) = $src2.new",
1838 // Store new-value halfword.
1839 // memh(Re=#U6)=Nt.new
1840 // memh(Rs+#s11:1)=Nt.new
1841 let mayStore = 1, isPredicable = 1 in
1842 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
1843 "memh($addr) = $src1.new",
1847 let mayStore = 1, isPredicable = 1 in
1848 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
1849 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
1850 "memh($src1+#$src2) = $src3.new",
1854 // memh(Rs+Ru<<#u2)=Nt.new
1855 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
1856 def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs),
1857 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1858 "memh($src1+$src2<<#$src3) = $src4.new",
1862 // memh(Ru<<#u2+#U6)=Nt.new
1863 let mayStore = 1, AddedComplexity = 10 in
1864 def STrih_shl_nv_V4 : NVInst_V4<(outs),
1865 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1866 "memh($src1<<#$src2+#$src3) = $src4.new",
1870 // memh(Rx++#s4:1)=Nt.new
1871 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
1872 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1873 (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
1874 "memh($src2++#$offset) = $src1.new",
1879 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1880 // memh(Rx++I:circ(Mu))=Nt.new
1881 // memh(Rx++Mu)=Nt.new
1882 // memh(Rx++Mu:brev)=Nt.new
1884 // memh(gp+#u16:1)=Nt.new
1885 let mayStore = 1, neverHasSideEffects = 1 in
1886 def STrih_GP_nv_V4 : NVInst_V4<(outs),
1887 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1888 "memh(#$global+$offset) = $src.new",
1893 // Store new-value halfword conditionally.
1895 // if ([!]Pv[.new]) memh(#u6)=Nt.new
1897 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
1898 // if (Pv) memh(Rs+#u6:1)=Nt.new
1899 let mayStore = 1, neverHasSideEffects = 1 in
1900 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
1901 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1902 "if ($src1) memh($addr) = $src2.new",
1906 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
1907 let mayStore = 1, neverHasSideEffects = 1 in
1908 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
1909 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1910 "if ($src1.new) memh($addr) = $src2.new",
1914 // if (!Pv) memh(Rs+#u6:1)=Nt.new
1915 let mayStore = 1, neverHasSideEffects = 1 in
1916 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
1917 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1918 "if (!$src1) memh($addr) = $src2.new",
1922 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
1923 let mayStore = 1, neverHasSideEffects = 1 in
1924 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1925 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1926 "if (!$src1.new) memh($addr) = $src2.new",
1930 // if (Pv) memh(Rs+#u6:1)=Nt.new
1931 let mayStore = 1, neverHasSideEffects = 1 in
1932 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
1933 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1934 "if ($src1) memh($src2+#$src3) = $src4.new",
1938 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
1939 let mayStore = 1, neverHasSideEffects = 1 in
1940 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
1941 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1942 "if ($src1.new) memh($src2+#$src3) = $src4.new",
1946 // if (!Pv) memh(Rs+#u6:1)=Nt.new
1947 let mayStore = 1, neverHasSideEffects = 1 in
1948 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
1949 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1950 "if (!$src1) memh($src2+#$src3) = $src4.new",
1954 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
1955 let mayStore = 1, neverHasSideEffects = 1 in
1956 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1957 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1958 "if (!$src1.new) memh($src2+#$src3) = $src4.new",
1962 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new
1963 // if (Pv) memh(Rs+Ru<<#u2)=Nt.new
1964 let mayStore = 1, AddedComplexity = 10 in
1965 def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
1966 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1968 "if ($src1) memh($src2+$src3<<#$src4) = $src5.new",
1972 // if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new
1973 let mayStore = 1, AddedComplexity = 10 in
1974 def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
1975 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1977 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5.new",
1981 // if (!Pv) memh(Rs+Ru<<#u2)=Nt.new
1982 let mayStore = 1, AddedComplexity = 10 in
1983 def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
1984 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1986 "if (!$src1) memh($src2+$src3<<#$src4) = $src5.new",
1990 // if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new
1991 let mayStore = 1, AddedComplexity = 10 in
1992 def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1993 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1995 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5.new",
1999 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2000 // if (Pv) memh(Rx++#s4:1)=Nt.new
2001 let mayStore = 1, hasCtrlDep = 1 in
2002 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2003 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2004 "if ($src1) memh($src3++#$offset) = $src2.new",
2008 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2009 let mayStore = 1, hasCtrlDep = 1 in
2010 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2011 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2012 "if ($src1.new) memh($src3++#$offset) = $src2.new",
2016 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2017 let mayStore = 1, hasCtrlDep = 1 in
2018 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2019 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2020 "if (!$src1) memh($src3++#$offset) = $src2.new",
2024 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2025 let mayStore = 1, hasCtrlDep = 1 in
2026 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2027 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2028 "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2033 // Store new-value word.
2035 // memw(Re=#U6)=Nt.new
2036 // memw(Rs+#s11:2)=Nt.new
2037 let mayStore = 1, isPredicable = 1 in
2038 def STriw_nv_V4 : NVInst_V4<(outs),
2039 (ins MEMri:$addr, IntRegs:$src1),
2040 "memw($addr) = $src1.new",
2044 let mayStore = 1, isPredicable = 1 in
2045 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
2046 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2047 "memw($src1+#$src2) = $src3.new",
2051 // memw(Rs+Ru<<#u2)=Nt.new
2052 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2053 def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs),
2054 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2055 "memw($src1+$src2<<#$src3) = $src4.new",
2059 // memw(Ru<<#u2+#U6)=Nt.new
2060 let mayStore = 1, AddedComplexity = 10 in
2061 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2062 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2063 "memw($src1<<#$src2+#$src3) = $src4.new",
2067 // memw(Rx++#s4:2)=Nt.new
2068 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
2069 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2070 (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
2071 "memw($src2++#$offset) = $src1.new",
2076 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2077 // memw(Rx++I:circ(Mu))=Nt.new
2078 // memw(Rx++Mu)=Nt.new
2079 // memw(Rx++Mu:brev)=Nt.new
2080 // memw(gp+#u16:2)=Nt.new
2081 let mayStore = 1, neverHasSideEffects = 1 in
2082 def STriw_GP_nv_V4 : NVInst_V4<(outs),
2083 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2084 "memw(#$global+$offset) = $src.new",
2089 // Store new-value word conditionally.
2091 // if ([!]Pv[.new]) memw(#u6)=Nt.new
2093 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
2094 // if (Pv) memw(Rs+#u6:2)=Nt.new
2095 let mayStore = 1, neverHasSideEffects = 1 in
2096 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
2097 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2098 "if ($src1) memw($addr) = $src2.new",
2102 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
2103 let mayStore = 1, neverHasSideEffects = 1 in
2104 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
2105 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2106 "if ($src1.new) memw($addr) = $src2.new",
2110 // if (!Pv) memw(Rs+#u6:2)=Nt.new
2111 let mayStore = 1, neverHasSideEffects = 1 in
2112 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
2113 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2114 "if (!$src1) memw($addr) = $src2.new",
2118 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
2119 let mayStore = 1, neverHasSideEffects = 1 in
2120 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2121 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2122 "if (!$src1.new) memw($addr) = $src2.new",
2126 // if (Pv) memw(Rs+#u6:2)=Nt.new
2127 let mayStore = 1, neverHasSideEffects = 1 in
2128 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2129 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2130 "if ($src1) memw($src2+#$src3) = $src4.new",
2134 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
2135 let mayStore = 1, neverHasSideEffects = 1 in
2136 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2137 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2138 "if ($src1.new) memw($src2+#$src3) = $src4.new",
2142 // if (!Pv) memw(Rs+#u6:2)=Nt.new
2143 let mayStore = 1, neverHasSideEffects = 1 in
2144 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2145 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2146 "if (!$src1) memw($src2+#$src3) = $src4.new",
2150 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
2151 let mayStore = 1, neverHasSideEffects = 1 in
2152 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2153 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2154 "if (!$src1.new) memw($src2+#$src3) = $src4.new",
2159 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new
2160 // if (Pv) memw(Rs+Ru<<#u2)=Nt.new
2161 let mayStore = 1, AddedComplexity = 10 in
2162 def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
2163 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2165 "if ($src1) memw($src2+$src3<<#$src4) = $src5.new",
2169 // if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new
2170 let mayStore = 1, AddedComplexity = 10 in
2171 def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
2172 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2174 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5.new",
2178 // if (!Pv) memw(Rs+Ru<<#u2)=Nt.new
2179 let mayStore = 1, AddedComplexity = 10 in
2180 def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
2181 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2183 "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",
2187 // if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new
2188 let mayStore = 1, AddedComplexity = 10 in
2189 def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2190 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2192 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",
2196 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
2197 // if (Pv) memw(Rx++#s4:2)=Nt.new
2198 let mayStore = 1, hasCtrlDep = 1 in
2199 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2200 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2201 "if ($src1) memw($src3++#$offset) = $src2.new",
2205 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
2206 let mayStore = 1, hasCtrlDep = 1 in
2207 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2208 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2209 "if ($src1.new) memw($src3++#$offset) = $src2.new",
2213 // if (!Pv) memw(Rx++#s4:2)=Nt.new
2214 let mayStore = 1, hasCtrlDep = 1 in
2215 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2216 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2217 "if (!$src1) memw($src3++#$offset) = $src2.new",
2221 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
2222 let mayStore = 1, hasCtrlDep = 1 in
2223 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2224 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2225 "if (!$src1.new) memw($src3++#$offset) = $src2.new",
2230 //===----------------------------------------------------------------------===//
2232 //===----------------------------------------------------------------------===//
2234 //===----------------------------------------------------------------------===//
2236 //===----------------------------------------------------------------------===//
2238 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
2239 def _ie_nv_V4 : NVInst_V4<(outs),
2240 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2241 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2242 !strconcat("($src1.new, $src2)) jump:",
2243 !strconcat(TakenStr, " $offset"))))),
2247 def _nv_V4 : NVInst_V4<(outs),
2248 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2249 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2250 !strconcat("($src1.new, $src2)) jump:",
2251 !strconcat(TakenStr, " $offset"))))),
2256 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr, string TakenStr> {
2257 def _ie_nv_V4 : NVInst_V4<(outs),
2258 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2259 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2260 !strconcat("($src1, $src2.new)) jump:",
2261 !strconcat(TakenStr, " $offset"))))),
2265 def _nv_V4 : NVInst_V4<(outs),
2266 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2267 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2268 !strconcat("($src1, $src2.new)) jump:",
2269 !strconcat(TakenStr, " $offset"))))),
2274 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
2275 def _ie_nv_V4 : NVInst_V4<(outs),
2276 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2277 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2278 !strconcat("($src1.new, #$src2)) jump:",
2279 !strconcat(TakenStr, " $offset"))))),
2283 def _nv_V4 : NVInst_V4<(outs),
2284 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2285 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2286 !strconcat("($src1.new, #$src2)) jump:",
2287 !strconcat(TakenStr, " $offset"))))),
2292 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
2293 def _ie_nv_V4 : NVInst_V4<(outs),
2294 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2295 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2296 !strconcat("($src1.new, #$src2)) jump:",
2297 !strconcat(TakenStr, " $offset"))))),
2301 def _nv_V4 : NVInst_V4<(outs),
2302 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2303 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2304 !strconcat("($src1.new, #$src2)) jump:",
2305 !strconcat(TakenStr, " $offset"))))),
2310 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr, string TakenStr> {
2311 def _ie_nv_V4 : NVInst_V4<(outs),
2312 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2313 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2314 !strconcat("($src1.new, #$src2)) jump:",
2315 !strconcat(TakenStr, " $offset"))))),
2319 def _nv_V4 : NVInst_V4<(outs),
2320 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2321 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2322 !strconcat("($src1.new, #$src2)) jump:",
2323 !strconcat(TakenStr, " $offset"))))),
2328 // Multiclass for regular dot new of Ist operand register.
2329 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
2330 defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
2331 defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
2334 // Multiclass for dot new of 2nd operand register.
2335 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
2336 defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
2337 defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
2340 // Multiclass for 2nd operand immediate, including -1.
2341 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
2342 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2343 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
2344 defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
2345 defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
2348 // Multiclass for 2nd operand immediate, excluding -1.
2349 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
2350 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2351 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
2354 // Multiclass for tstbit, where 2nd operand is always #0.
2355 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
2356 defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
2357 defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
2360 // Multiclass for GT.
2361 multiclass NVJ_type_rr_ri<string OpcStr> {
2362 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
2363 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
2364 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
2365 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
2366 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
2367 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
2370 // Multiclass for EQ.
2371 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
2372 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
2373 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
2374 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
2375 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
2378 // Multiclass for GTU.
2379 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
2380 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
2381 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
2382 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
2383 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
2384 defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
2385 defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
2388 // Multiclass for tstbit.
2389 multiclass NVJ_type_r0<string OpcStr> {
2390 defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
2391 defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
2394 // Base Multiclass for New Value Jump.
2395 multiclass NVJ_type {
2396 defm GT : NVJ_type_rr_ri<"cmp.gt">;
2397 defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
2398 defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
2399 defm TSTBIT : NVJ_type_r0<"tstbit">;
2402 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
2403 defm JMP_ : NVJ_type;
2406 //===----------------------------------------------------------------------===//
2408 //===----------------------------------------------------------------------===//
2410 //===----------------------------------------------------------------------===//
2412 //===----------------------------------------------------------------------===//
2414 // Add and accumulate.
2415 // Rd=add(Rs,add(Ru,#s6))
2416 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
2417 (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
2418 "$dst = add($src1, add($src2, #$src3))",
2420 (add IntRegs:$src1, (add IntRegs:$src2, s6ImmPred:$src3)))]>,
2423 // Rd=add(Rs,sub(#s6,Ru))
2424 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
2425 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
2426 "$dst = add($src1, sub(#$src2, $src3))",
2428 (add IntRegs:$src1, (sub s6ImmPred:$src2, IntRegs:$src3)))]>,
2431 // Generates the same instruction as ADDr_SUBri_V4 but matches different
2433 // Rd=add(Rs,sub(#s6,Ru))
2434 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
2435 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
2436 "$dst = add($src1, sub(#$src2, $src3))",
2438 (sub (add IntRegs:$src1, s6ImmPred:$src2), IntRegs:$src3))]>,
2442 // Add or subtract doublewords with carry.
2444 // Rdd=add(Rss,Rtt,Px):carry
2446 // Rdd=sub(Rss,Rtt,Px):carry
2449 // Logical doublewords.
2450 // Rdd=and(Rtt,~Rss)
2451 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2452 (ins DoubleRegs:$src1, DoubleRegs:$src2),
2453 "$dst = and($src1, ~$src2)",
2454 [(set DoubleRegs:$dst, (and DoubleRegs:$src1,
2455 (not DoubleRegs:$src2)))]>,
2459 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2460 (ins DoubleRegs:$src1, DoubleRegs:$src2),
2461 "$dst = or($src1, ~$src2)",
2462 [(set DoubleRegs:$dst,
2463 (or DoubleRegs:$src1, (not DoubleRegs:$src2)))]>,
2467 // Logical-logical doublewords.
2468 // Rxx^=xor(Rss,Rtt)
2469 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
2470 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
2471 "$dst ^= xor($src2, $src3)",
2472 [(set DoubleRegs:$dst,
2473 (xor DoubleRegs:$src1, (xor DoubleRegs:$src2, DoubleRegs:$src3)))],
2478 // Logical-logical words.
2479 // Rx=or(Ru,and(Rx,#s10))
2480 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
2481 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
2482 "$dst = or($src1, and($src2, #$src3))",
2484 (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],
2488 // Rx[&|^]=and(Rs,Rt)
2490 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2491 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2492 "$dst &= and($src2, $src3)",
2494 (and IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],
2499 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2500 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2501 "$dst |= and($src2, $src3)",
2503 (or IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],
2508 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2509 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2510 "$dst ^= and($src2, $src3)",
2512 (xor IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],
2516 // Rx[&|^]=and(Rs,~Rt)
2518 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2519 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2520 "$dst &= and($src2, ~$src3)",
2522 (and IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],
2527 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2528 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2529 "$dst |= and($src2, ~$src3)",
2531 (or IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],
2536 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2537 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2538 "$dst ^= and($src2, ~$src3)",
2540 (xor IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],
2544 // Rx[&|^]=or(Rs,Rt)
2546 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2547 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2548 "$dst &= or($src2, $src3)",
2550 (and IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],
2555 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2556 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2557 "$dst |= or($src2, $src3)",
2559 (or IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],
2564 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2565 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2566 "$dst ^= or($src2, $src3)",
2568 (xor IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],
2572 // Rx[&|^]=xor(Rs,Rt)
2574 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2575 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2576 "$dst &= xor($src2, $src3)",
2578 (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],
2583 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2584 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2585 "$dst |= xor($src2, $src3)",
2587 (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],
2592 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2593 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2594 "$dst ^= xor($src2, $src3)",
2596 (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],
2601 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
2602 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
2603 "$dst |= and($src2, #$src3)",
2605 (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],
2610 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
2611 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
2612 "$dst |= or($src2, #$src3)",
2614 (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],
2620 // Rd=modwrap(Rs,Rt)
2622 // Rd=cround(Rs,#u5)
2624 // Rd=round(Rs,#u5)[:sat]
2625 // Rd=round(Rs,Rt)[:sat]
2626 // Vector reduce add unsigned halfwords
2627 // Rd=vraddh(Rss,Rtt)
2629 // Rdd=vaddb(Rss,Rtt)
2630 // Vector conditional negate
2631 // Rdd=vcnegh(Rss,Rt)
2632 // Rxx+=vrcnegh(Rss,Rt)
2633 // Vector maximum bytes
2634 // Rdd=vmaxb(Rtt,Rss)
2635 // Vector reduce maximum halfwords
2636 // Rxx=vrmaxh(Rss,Ru)
2637 // Rxx=vrmaxuh(Rss,Ru)
2638 // Vector reduce maximum words
2639 // Rxx=vrmaxuw(Rss,Ru)
2640 // Rxx=vrmaxw(Rss,Ru)
2641 // Vector minimum bytes
2642 // Rdd=vminb(Rtt,Rss)
2643 // Vector reduce minimum halfwords
2644 // Rxx=vrminh(Rss,Ru)
2645 // Rxx=vrminuh(Rss,Ru)
2646 // Vector reduce minimum words
2647 // Rxx=vrminuw(Rss,Ru)
2648 // Rxx=vrminw(Rss,Ru)
2649 // Vector subtract bytes
2650 // Rdd=vsubb(Rss,Rtt)
2652 //===----------------------------------------------------------------------===//
2654 //===----------------------------------------------------------------------===//
2657 //===----------------------------------------------------------------------===//
2659 //===----------------------------------------------------------------------===//
2661 // Multiply and user lower result.
2662 // Rd=add(#u6,mpyi(Rs,#U6))
2663 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
2664 (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
2665 "$dst = add(#$src1, mpyi($src2, #$src3))",
2667 (add (mul IntRegs:$src2, u6ImmPred:$src3), u6ImmPred:$src1))]>,
2670 // Rd=add(#u6,mpyi(Rs,Rt))
2672 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
2673 (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
2674 "$dst = add(#$src1, mpyi($src2, $src3))",
2676 (add (mul IntRegs:$src2, IntRegs:$src3), u6ImmPred:$src1))]>,
2679 // Rd=add(Ru,mpyi(#u6:2,Rs))
2680 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
2681 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
2682 "$dst = add($src1, mpyi(#$src2, $src3))",
2684 (add IntRegs:$src1, (mul IntRegs:$src3, u6_2ImmPred:$src2)))]>,
2687 // Rd=add(Ru,mpyi(Rs,#u6))
2688 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
2689 (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
2690 "$dst = add($src1, mpyi($src2, #$src3))",
2692 (add IntRegs:$src1, (mul IntRegs:$src2, u6ImmPred:$src3)))]>,
2695 // Rx=add(Ru,mpyi(Rx,Rs))
2696 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
2697 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2698 "$dst = add($src1, mpyi($src2, $src3))",
2700 (add IntRegs:$src1, (mul IntRegs:$src2, IntRegs:$src3)))],
2705 // Polynomial multiply words
2707 // Rxx^=pmpyw(Rs,Rt)
2709 // Vector reduce multiply word by signed half (32x16)
2710 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2711 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2712 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
2713 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
2715 // Multiply and use upper result
2716 // Rd=mpy(Rs,Rt.H):<<1:sat
2717 // Rd=mpy(Rs,Rt.L):<<1:sat
2718 // Rd=mpy(Rs,Rt):<<1
2719 // Rd=mpy(Rs,Rt):<<1:sat
2721 // Rx+=mpy(Rs,Rt):<<1:sat
2722 // Rx-=mpy(Rs,Rt):<<1:sat
2724 // Vector multiply bytes
2725 // Rdd=vmpybsu(Rs,Rt)
2726 // Rdd=vmpybu(Rs,Rt)
2727 // Rxx+=vmpybsu(Rs,Rt)
2728 // Rxx+=vmpybu(Rs,Rt)
2730 // Vector polynomial multiply halfwords
2731 // Rdd=vpmpyh(Rs,Rt)
2732 // Rxx^=vpmpyh(Rs,Rt)
2734 //===----------------------------------------------------------------------===//
2736 //===----------------------------------------------------------------------===//
2739 //===----------------------------------------------------------------------===//
2741 //===----------------------------------------------------------------------===//
2743 // Shift by immediate and accumulate.
2744 // Rx=add(#u8,asl(Rx,#U5))
2745 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2746 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2747 "$dst = add(#$src1, asl($src2, #$src3))",
2749 (add (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2753 // Rx=add(#u8,lsr(Rx,#U5))
2754 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2755 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2756 "$dst = add(#$src1, lsr($src2, #$src3))",
2758 (add (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2762 // Rx=sub(#u8,asl(Rx,#U5))
2763 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2764 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2765 "$dst = sub(#$src1, asl($src2, #$src3))",
2767 (sub (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2771 // Rx=sub(#u8,lsr(Rx,#U5))
2772 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2773 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2774 "$dst = sub(#$src1, lsr($src2, #$src3))",
2776 (sub (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2781 //Shift by immediate and logical.
2782 //Rx=and(#u8,asl(Rx,#U5))
2783 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2784 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2785 "$dst = and(#$src1, asl($src2, #$src3))",
2787 (and (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2791 //Rx=and(#u8,lsr(Rx,#U5))
2792 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2793 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2794 "$dst = and(#$src1, lsr($src2, #$src3))",
2796 (and (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2800 //Rx=or(#u8,asl(Rx,#U5))
2801 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2802 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2803 "$dst = or(#$src1, asl($src2, #$src3))",
2805 (or (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2809 //Rx=or(#u8,lsr(Rx,#U5))
2810 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2811 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
2812 "$dst = or(#$src1, lsr($src2, #$src3))",
2814 (or (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],
2819 //Shift by register.
2821 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
2822 "$dst = lsl(#$src1, $src2)",
2823 [(set IntRegs:$dst, (shl s6ImmPred:$src1, IntRegs:$src2))]>,
2827 //Shift by register and logical.
2829 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2830 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2831 "$dst ^= asl($src2, $src3)",
2832 [(set DoubleRegs:$dst,
2833 (xor DoubleRegs:$src1, (shl DoubleRegs:$src2, IntRegs:$src3)))],
2838 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2839 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2840 "$dst ^= asr($src2, $src3)",
2841 [(set DoubleRegs:$dst,
2842 (xor DoubleRegs:$src1, (sra DoubleRegs:$src2, IntRegs:$src3)))],
2847 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2848 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2849 "$dst ^= lsl($src2, $src3)",
2850 [(set DoubleRegs:$dst,
2851 (xor DoubleRegs:$src1, (shl DoubleRegs:$src2, IntRegs:$src3)))],
2856 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2857 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2858 "$dst ^= lsr($src2, $src3)",
2859 [(set DoubleRegs:$dst,
2860 (xor DoubleRegs:$src1, (srl DoubleRegs:$src2, IntRegs:$src3)))],
2865 //===----------------------------------------------------------------------===//
2867 //===----------------------------------------------------------------------===//
2869 //===----------------------------------------------------------------------===//
2870 // MEMOP: Word, Half, Byte
2871 //===----------------------------------------------------------------------===//
2873 //===----------------------------------------------------------------------===//
2877 // MEMw_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
2878 // MEMw_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
2879 // MEMw_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
2880 // MEMw_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
2881 // MEMw_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
2882 // MEMw_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
2883 // MEMw_ADDi_V4 : memw(Rs+#u6:2)+=#U5
2884 // MEMw_SUBi_V4 : memw(Rs+#u6:2)-=#U5
2885 // MEMw_ADDr_V4 : memw(Rs+#u6:2)+=Rt
2886 // MEMw_SUBr_V4 : memw(Rs+#u6:2)-=Rt
2887 // MEMw_CLRr_V4 : memw(Rs+#u6:2)&=Rt
2888 // MEMw_SETr_V4 : memw(Rs+#u6:2)|=Rt
2891 // MEMw_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2892 // MEMw_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
2893 // MEMw_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2894 // MEMw_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
2895 //===----------------------------------------------------------------------===//
2898 // MEMw_ADDSUBi_indexed_V4:
2899 // pseudo operation for MEMw_ADDi_indexed_V4 and
2900 // MEMw_SUBi_indexed_V4 a later pass will change it
2901 // to the corresponding pattern.
2902 let AddedComplexity = 30 in
2903 def MEMw_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2904 (ins IntRegs:$base, u6_2Imm:$offset, m6Imm:$addend),
2905 "Error; should not emit",
2906 [(store (add (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2908 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2909 Requires<[HasV4T, UseMEMOP]>;
2911 // memw(Rs+#u6:2) += #U5
2912 let AddedComplexity = 30 in
2913 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
2914 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
2915 "memw($base+#$offset) += $addend",
2917 Requires<[HasV4T, UseMEMOP]>;
2919 // memw(Rs+#u6:2) -= #U5
2920 let AddedComplexity = 30 in
2921 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2922 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
2923 "memw($base+#$offset) -= $subend",
2925 Requires<[HasV4T, UseMEMOP]>;
2927 // memw(Rs+#u6:2) += Rt
2928 let AddedComplexity = 30 in
2929 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2930 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
2931 "memw($base+#$offset) += $addend",
2932 [(store (add (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2934 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2935 Requires<[HasV4T, UseMEMOP]>;
2937 // memw(Rs+#u6:2) -= Rt
2938 let AddedComplexity = 30 in
2939 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
2940 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
2941 "memw($base+#$offset) -= $subend",
2942 [(store (sub (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2944 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2945 Requires<[HasV4T, UseMEMOP]>;
2947 // memw(Rs+#u6:2) &= Rt
2948 let AddedComplexity = 30 in
2949 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2950 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
2951 "memw($base+#$offset) += $andend",
2952 [(store (and (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2954 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2955 Requires<[HasV4T, UseMEMOP]>;
2957 // memw(Rs+#u6:2) |= Rt
2958 let AddedComplexity = 30 in
2959 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
2960 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
2961 "memw($base+#$offset) |= $orend",
2962 [(store (or (load (add IntRegs:$base, u6_2ImmPred:$offset)),
2964 (add IntRegs:$base, u6_2ImmPred:$offset))]>,
2965 Requires<[HasV4T, UseMEMOP]>;
2968 // Pseudo operation for MEMw_ADDi_V4 and MEMw_SUBi_V4
2969 // a later pass will change it to the right pattern.
2970 let AddedComplexity = 30 in
2971 def MEMw_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
2972 (ins MEMri:$addr, m6Imm:$addend),
2973 "Error; should not emit",
2974 [(store (add (load ADDRriU6_2:$addr), m6ImmPred:$addend),
2975 ADDRriU6_2:$addr)]>,
2976 Requires<[HasV4T, UseMEMOP]>;
2978 // memw(Rs+#u6:2) += #U5
2979 let AddedComplexity = 30 in
2980 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
2981 (ins MEMri:$addr, u5Imm:$addend),
2982 "memw($addr) += $addend",
2984 Requires<[HasV4T, UseMEMOP]>;
2986 // memw(Rs+#u6:2) -= #U5
2987 let AddedComplexity = 30 in
2988 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
2989 (ins MEMri:$addr, u5Imm:$subend),
2990 "memw($addr) -= $subend",
2992 Requires<[HasV4T, UseMEMOP]>;
2994 // memw(Rs+#u6:2) += Rt
2995 let AddedComplexity = 30 in
2996 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
2997 (ins MEMri:$addr, IntRegs:$addend),
2998 "memw($addr) += $addend",
2999 [(store (add (load ADDRriU6_2:$addr), IntRegs:$addend),
3000 ADDRriU6_2:$addr)]>,
3001 Requires<[HasV4T, UseMEMOP]>;
3003 // memw(Rs+#u6:2) -= Rt
3004 let AddedComplexity = 30 in
3005 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
3006 (ins MEMri:$addr, IntRegs:$subend),
3007 "memw($addr) -= $subend",
3008 [(store (sub (load ADDRriU6_2:$addr), IntRegs:$subend),
3009 ADDRriU6_2:$addr)]>,
3010 Requires<[HasV4T, UseMEMOP]>;
3012 // memw(Rs+#u6:2) &= Rt
3013 let AddedComplexity = 30 in
3014 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
3015 (ins MEMri:$addr, IntRegs:$andend),
3016 "memw($addr) &= $andend",
3017 [(store (and (load ADDRriU6_2:$addr), IntRegs:$andend),
3018 ADDRriU6_2:$addr)]>,
3019 Requires<[HasV4T, UseMEMOP]>;
3021 // memw(Rs+#u6:2) |= Rt
3022 let AddedComplexity = 30 in
3023 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
3024 (ins MEMri:$addr, IntRegs:$orend),
3025 "memw($addr) |= $orend",
3026 [(store (or (load ADDRriU6_2:$addr), IntRegs:$orend),
3027 ADDRriU6_2:$addr)]>,
3028 Requires<[HasV4T, UseMEMOP]>;
3030 //===----------------------------------------------------------------------===//
3034 // MEMh_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
3035 // MEMh_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
3036 // MEMh_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
3037 // MEMh_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
3038 // MEMh_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
3039 // MEMh_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
3040 // MEMh_ADDi_V4 : memw(Rs+#u6:2)+=#U5
3041 // MEMh_SUBi_V4 : memw(Rs+#u6:2)-=#U5
3042 // MEMh_ADDr_V4 : memw(Rs+#u6:2)+=Rt
3043 // MEMh_SUBr_V4 : memw(Rs+#u6:2)-=Rt
3044 // MEMh_CLRr_V4 : memw(Rs+#u6:2)&=Rt
3045 // MEMh_SETr_V4 : memw(Rs+#u6:2)|=Rt
3048 // MEMh_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
3049 // MEMh_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
3050 // MEMh_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
3051 // MEMh_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
3052 //===----------------------------------------------------------------------===//
3055 // MEMh_ADDSUBi_indexed_V4:
3056 // Pseudo operation for MEMh_ADDi_indexed_V4 and
3057 // MEMh_SUBi_indexed_V4 a later pass will change it
3058 // to the corresponding pattern.
3059 let AddedComplexity = 30 in
3060 def MEMh_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3061 (ins IntRegs:$base, u6_1Imm:$offset, m6Imm:$addend),
3062 "Error; should not emit",
3063 [(truncstorei16 (add (sextloadi16 (add IntRegs:$base,
3064 u6_1ImmPred:$offset)),
3066 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
3067 Requires<[HasV4T, UseMEMOP]>;
3069 // memh(Rs+#u6:1) += #U5
3070 let AddedComplexity = 30 in
3071 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3072 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
3073 "memh($base+#$offset) += $addend",
3075 Requires<[HasV4T, UseMEMOP]>;
3077 // memh(Rs+#u6:1) -= #U5
3078 let AddedComplexity = 30 in
3079 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3080 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
3081 "memh($base+#$offset) -= $subend",
3083 Requires<[HasV4T, UseMEMOP]>;
3085 // memh(Rs+#u6:1) += Rt
3086 let AddedComplexity = 30 in
3087 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3088 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
3089 "memh($base+#$offset) += $addend",
3090 [(truncstorei16 (add (sextloadi16 (add IntRegs:$base,
3091 u6_1ImmPred:$offset)),
3093 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
3094 Requires<[HasV4T, UseMEMOP]>;
3096 // memh(Rs+#u6:1) -= Rt
3097 let AddedComplexity = 30 in
3098 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3099 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
3100 "memh($base+#$offset) -= $subend",
3101 [(truncstorei16 (sub (sextloadi16 (add IntRegs:$base,
3102 u6_1ImmPred:$offset)),
3104 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
3105 Requires<[HasV4T, UseMEMOP]>;
3107 // memh(Rs+#u6:1) &= Rt
3108 let AddedComplexity = 30 in
3109 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3110 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
3111 "memh($base+#$offset) += $andend",
3112 [(truncstorei16 (and (sextloadi16 (add IntRegs:$base,
3113 u6_1ImmPred:$offset)),
3115 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
3116 Requires<[HasV4T, UseMEMOP]>;
3118 // memh(Rs+#u6:1) |= Rt
3119 let AddedComplexity = 30 in
3120 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3121 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
3122 "memh($base+#$offset) |= $orend",
3123 [(truncstorei16 (or (sextloadi16 (add IntRegs:$base,
3124 u6_1ImmPred:$offset)),
3126 (add IntRegs:$base, u6_1ImmPred:$offset))]>,
3127 Requires<[HasV4T, UseMEMOP]>;
3130 // Pseudo operation for MEMh_ADDi_V4 and MEMh_SUBi_V4
3131 // a later pass will change it to the right pattern.
3132 let AddedComplexity = 30 in
3133 def MEMh_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
3134 (ins MEMri:$addr, m6Imm:$addend),
3135 "Error; should not emit",
3136 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
3137 m6ImmPred:$addend), ADDRriU6_1:$addr)]>,
3138 Requires<[HasV4T, UseMEMOP]>;
3140 // memh(Rs+#u6:1) += #U5
3141 let AddedComplexity = 30 in
3142 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
3143 (ins MEMri:$addr, u5Imm:$addend),
3144 "memh($addr) += $addend",
3146 Requires<[HasV4T, UseMEMOP]>;
3148 // memh(Rs+#u6:1) -= #U5
3149 let AddedComplexity = 30 in
3150 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
3151 (ins MEMri:$addr, u5Imm:$subend),
3152 "memh($addr) -= $subend",
3154 Requires<[HasV4T, UseMEMOP]>;
3156 // memh(Rs+#u6:1) += Rt
3157 let AddedComplexity = 30 in
3158 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
3159 (ins MEMri:$addr, IntRegs:$addend),
3160 "memh($addr) += $addend",
3161 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
3162 IntRegs:$addend), ADDRriU6_1:$addr)]>,
3163 Requires<[HasV4T, UseMEMOP]>;
3165 // memh(Rs+#u6:1) -= Rt
3166 let AddedComplexity = 30 in
3167 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
3168 (ins MEMri:$addr, IntRegs:$subend),
3169 "memh($addr) -= $subend",
3170 [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
3171 IntRegs:$subend), ADDRriU6_1:$addr)]>,
3172 Requires<[HasV4T, UseMEMOP]>;
3174 // memh(Rs+#u6:1) &= Rt
3175 let AddedComplexity = 30 in
3176 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
3177 (ins MEMri:$addr, IntRegs:$andend),
3178 "memh($addr) &= $andend",
3179 [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
3180 IntRegs:$andend), ADDRriU6_1:$addr)]>,
3181 Requires<[HasV4T, UseMEMOP]>;
3183 // memh(Rs+#u6:1) |= Rt
3184 let AddedComplexity = 30 in
3185 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
3186 (ins MEMri:$addr, IntRegs:$orend),
3187 "memh($addr) |= $orend",
3188 [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
3189 IntRegs:$orend), ADDRriU6_1:$addr)]>,
3190 Requires<[HasV4T, UseMEMOP]>;
3193 //===----------------------------------------------------------------------===//
3197 // MEMb_ADDi_indexed_V4 : memb(Rs+#u6:0)+=#U5
3198 // MEMb_SUBi_indexed_V4 : memb(Rs+#u6:0)-=#U5
3199 // MEMb_ADDr_indexed_V4 : memb(Rs+#u6:0)+=Rt
3200 // MEMb_SUBr_indexed_V4 : memb(Rs+#u6:0)-=Rt
3201 // MEMb_CLRr_indexed_V4 : memb(Rs+#u6:0)&=Rt
3202 // MEMb_SETr_indexed_V4 : memb(Rs+#u6:0)|=Rt
3203 // MEMb_ADDi_V4 : memb(Rs+#u6:0)+=#U5
3204 // MEMb_SUBi_V4 : memb(Rs+#u6:0)-=#U5
3205 // MEMb_ADDr_V4 : memb(Rs+#u6:0)+=Rt
3206 // MEMb_SUBr_V4 : memb(Rs+#u6:0)-=Rt
3207 // MEMb_CLRr_V4 : memb(Rs+#u6:0)&=Rt
3208 // MEMb_SETr_V4 : memb(Rs+#u6:0)|=Rt
3211 // MEMb_CLRi_indexed_V4 : memb(Rs+#u6:0)=clrbit(#U5)
3212 // MEMb_SETi_indexed_V4 : memb(Rs+#u6:0)=setbit(#U5)
3213 // MEMb_CLRi_V4 : memb(Rs+#u6:0)=clrbit(#U5)
3214 // MEMb_SETi_V4 : memb(Rs+#u6:0)=setbit(#U5)
3215 //===----------------------------------------------------------------------===//
3218 // MEMb_ADDSUBi_indexed_V4:
3219 // Pseudo operation for MEMb_ADDi_indexed_V4 and
3220 // MEMb_SUBi_indexed_V4 a later pass will change it
3221 // to the corresponding pattern.
3222 let AddedComplexity = 30 in
3223 def MEMb_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3224 (ins IntRegs:$base, u6_0Imm:$offset, m6Imm:$addend),
3225 "Error; should not emit",
3226 [(truncstorei8 (add (sextloadi8 (add IntRegs:$base,
3227 u6_0ImmPred:$offset)),
3229 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3230 Requires<[HasV4T, UseMEMOP]>;
3232 // memb(Rs+#u6:0) += #U5
3233 let AddedComplexity = 30 in
3234 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3235 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
3236 "memb($base+#$offset) += $addend",
3238 Requires<[HasV4T, UseMEMOP]>;
3240 // memb(Rs+#u6:0) -= #U5
3241 let AddedComplexity = 30 in
3242 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3243 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
3244 "memb($base+#$offset) -= $subend",
3246 Requires<[HasV4T, UseMEMOP]>;
3248 // memb(Rs+#u6:0) += Rt
3249 let AddedComplexity = 30 in
3250 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3251 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
3252 "memb($base+#$offset) += $addend",
3253 [(truncstorei8 (add (sextloadi8 (add IntRegs:$base,
3254 u6_0ImmPred:$offset)),
3256 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3257 Requires<[HasV4T, UseMEMOP]>;
3259 // memb(Rs+#u6:0) -= Rt
3260 let AddedComplexity = 30 in
3261 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3262 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
3263 "memb($base+#$offset) -= $subend",
3264 [(truncstorei8 (sub (sextloadi8 (add IntRegs:$base,
3265 u6_0ImmPred:$offset)),
3267 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3268 Requires<[HasV4T, UseMEMOP]>;
3270 // memb(Rs+#u6:0) &= Rt
3271 let AddedComplexity = 30 in
3272 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3273 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
3274 "memb($base+#$offset) += $andend",
3275 [(truncstorei8 (and (sextloadi8 (add IntRegs:$base,
3276 u6_0ImmPred:$offset)),
3278 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3279 Requires<[HasV4T, UseMEMOP]>;
3281 // memb(Rs+#u6:0) |= Rt
3282 let AddedComplexity = 30 in
3283 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3284 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
3285 "memb($base+#$offset) |= $orend",
3286 [(truncstorei8 (or (sextloadi8 (add IntRegs:$base,
3287 u6_0ImmPred:$offset)),
3289 (add IntRegs:$base, u6_0ImmPred:$offset))]>,
3290 Requires<[HasV4T, UseMEMOP]>;
3293 // Pseudo operation for MEMb_ADDi_V4 and MEMb_SUBi_V4
3294 // a later pass will change it to the right pattern.
3295 let AddedComplexity = 30 in
3296 def MEMb_ADDSUBi_MEM_V4 : MEMInst_V4<(outs),
3297 (ins MEMri:$addr, m6Imm:$addend),
3298 "Error; should not emit",
3299 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3300 m6ImmPred:$addend), ADDRriU6_0:$addr)]>,
3301 Requires<[HasV4T, UseMEMOP]>;
3303 // memb(Rs+#u6:0) += #U5
3304 let AddedComplexity = 30 in
3305 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
3306 (ins MEMri:$addr, u5Imm:$addend),
3307 "memb($addr) += $addend",
3309 Requires<[HasV4T, UseMEMOP]>;
3311 // memb(Rs+#u6:0) -= #U5
3312 let AddedComplexity = 30 in
3313 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
3314 (ins MEMri:$addr, u5Imm:$subend),
3315 "memb($addr) -= $subend",
3317 Requires<[HasV4T, UseMEMOP]>;
3319 // memb(Rs+#u6:0) += Rt
3320 let AddedComplexity = 30 in
3321 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
3322 (ins MEMri:$addr, IntRegs:$addend),
3323 "memb($addr) += $addend",
3324 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3325 IntRegs:$addend), ADDRriU6_0:$addr)]>,
3326 Requires<[HasV4T, UseMEMOP]>;
3328 // memb(Rs+#u6:0) -= Rt
3329 let AddedComplexity = 30 in
3330 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
3331 (ins MEMri:$addr, IntRegs:$subend),
3332 "memb($addr) -= $subend",
3333 [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
3334 IntRegs:$subend), ADDRriU6_0:$addr)]>,
3335 Requires<[HasV4T, UseMEMOP]>;
3337 // memb(Rs+#u6:0) &= Rt
3338 let AddedComplexity = 30 in
3339 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
3340 (ins MEMri:$addr, IntRegs:$andend),
3341 "memb($addr) &= $andend",
3342 [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
3343 IntRegs:$andend), ADDRriU6_0:$addr)]>,
3344 Requires<[HasV4T, UseMEMOP]>;
3346 // memb(Rs+#u6:0) |= Rt
3347 let AddedComplexity = 30 in
3348 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
3349 (ins MEMri:$addr, IntRegs:$orend),
3350 "memb($addr) |= $orend",
3351 [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
3352 IntRegs:$orend), ADDRriU6_0:$addr)]>,
3353 Requires<[HasV4T, UseMEMOP]>;
3356 //===----------------------------------------------------------------------===//
3358 //===----------------------------------------------------------------------===//
3360 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3361 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3362 // hardware. However, compiler can still implement these patterns through
3363 // appropriate patterns combinations based on current implemented patterns.
3364 // The implemented patterns are: EQ/GT/GTU.
3365 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3367 // Pd=cmpb.eq(Rs,#u8)
3368 let isCompare = 1 in
3369 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
3370 (ins IntRegs:$src1, u8Imm:$src2),
3371 "$dst = cmpb.eq($src1, #$src2)",
3372 [(set PredRegs:$dst, (seteq (and IntRegs:$src1, 255),
3373 u8ImmPred:$src2))]>,
3376 // Pd=cmpb.eq(Rs,Rt)
3377 let isCompare = 1 in
3378 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
3379 (ins IntRegs:$src1, IntRegs:$src2),
3380 "$dst = cmpb.eq($src1, $src2)",
3381 [(set PredRegs:$dst, (seteq (and (xor IntRegs:$src1,
3387 // Pd=cmpb.eq(Rs,Rt)
3388 let isCompare = 1 in
3389 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
3390 (ins IntRegs:$src1, IntRegs:$src2),
3391 "$dst = cmpb.eq($src1, $src2)",
3392 [(set PredRegs:$dst, (seteq (shl IntRegs:$src1, (i32 24)),
3393 (shl IntRegs:$src2, (i32 24))))]>,
3396 // Pd=cmpb.gt(Rs,#s8)
3397 let isCompare = 1 in
3398 def CMPbGTri_V4 : MInst<(outs PredRegs:$dst),
3399 (ins IntRegs:$src1, s32Imm:$src2),
3400 "$dst = cmpb.gt($src1, #$src2)",
3401 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 24)),
3402 s32_24ImmPred:$src2))]>,
3405 // Pd=cmpb.gt(Rs,Rt)
3406 let isCompare = 1 in
3407 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
3408 (ins IntRegs:$src1, IntRegs:$src2),
3409 "$dst = cmpb.gt($src1, $src2)",
3410 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 24)),
3411 (shl IntRegs:$src2, (i32 24))))]>,
3414 // Pd=cmpb.gtu(Rs,#u7)
3415 let isCompare = 1 in
3416 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
3417 (ins IntRegs:$src1, u7Imm:$src2),
3418 "$dst = cmpb.gtu($src1, #$src2)",
3419 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 255),
3420 u7ImmPred:$src2))]>,
3423 // Pd=cmpb.gtu(Rs,Rt)
3424 let isCompare = 1 in
3425 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
3426 (ins IntRegs:$src1, IntRegs:$src2),
3427 "$dst = cmpb.gtu($src1, $src2)",
3428 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 255),
3429 (and IntRegs:$src2, 255)))]>,
3432 // Signed half compare(.eq) ri.
3433 // Pd=cmph.eq(Rs,#s8)
3434 let isCompare = 1 in
3435 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
3436 (ins IntRegs:$src1, u16Imm:$src2),
3437 "$dst = cmph.eq($src1, #$src2)",
3438 [(set PredRegs:$dst, (seteq (and IntRegs:$src1, 65535),
3439 u16_s8ImmPred:$src2))]>,
3442 // Signed half compare(.eq) rr.
3443 // Case 1: xor + and, then compare:
3445 // r0=and(r0,#0xffff)
3447 // Pd=cmph.eq(Rs,Rt)
3448 let isCompare = 1 in
3449 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
3450 (ins IntRegs:$src1, IntRegs:$src2),
3451 "$dst = cmph.eq($src1, $src2)",
3452 [(set PredRegs:$dst, (seteq (and (xor IntRegs:$src1,
3458 // Signed half compare(.eq) rr.
3459 // Case 2: shift left 16 bits then compare:
3463 // Pd=cmph.eq(Rs,Rt)
3464 let isCompare = 1 in
3465 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
3466 (ins IntRegs:$src1, IntRegs:$src2),
3467 "$dst = cmph.eq($src1, $src2)",
3468 [(set PredRegs:$dst, (seteq (shl IntRegs:$src1, (i32 16)),
3469 (shl IntRegs:$src2, (i32 16))))]>,
3472 // Signed half compare(.gt) ri.
3473 // Pd=cmph.gt(Rs,#s8)
3474 let isCompare = 1 in
3475 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
3476 (ins IntRegs:$src1, s32Imm:$src2),
3477 "$dst = cmph.gt($src1, #$src2)",
3478 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 16)),
3479 s32_16s8ImmPred:$src2))]>,
3482 // Signed half compare(.gt) rr.
3483 // Pd=cmph.gt(Rs,Rt)
3484 let isCompare = 1 in
3485 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
3486 (ins IntRegs:$src1, IntRegs:$src2),
3487 "$dst = cmph.gt($src1, $src2)",
3488 [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 16)),
3489 (shl IntRegs:$src2, (i32 16))))]>,
3492 // Unsigned half compare rr (.gtu).
3493 // Pd=cmph.gtu(Rs,Rt)
3494 let isCompare = 1 in
3495 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
3496 (ins IntRegs:$src1, IntRegs:$src2),
3497 "$dst = cmph.gtu($src1, $src2)",
3498 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 65535),
3499 (and IntRegs:$src2, 65535)))]>,
3502 // Unsigned half compare ri (.gtu).
3503 // Pd=cmph.gtu(Rs,#u7)
3504 let isCompare = 1 in
3505 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
3506 (ins IntRegs:$src1, u7Imm:$src2),
3507 "$dst = cmph.gtu($src1, #$src2)",
3508 [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 65535),
3509 u7ImmPred:$src2))]>,
3512 //===----------------------------------------------------------------------===//
3514 //===----------------------------------------------------------------------===//
3516 //Deallocate frame and return.
3518 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
3519 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3520 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
3526 // if (Ps) dealloc_return
3527 let isReturn = 1, isTerminator = 1,
3528 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3529 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, i32imm:$amt1),
3530 "if ($src1) dealloc_return",
3535 // if (!Ps) dealloc_return
3536 let isReturn = 1, isTerminator = 1,
3537 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3538 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3540 "if (!$src1) dealloc_return",
3545 // if (Ps.new) dealloc_return:nt
3546 let isReturn = 1, isTerminator = 1,
3547 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3548 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3550 "if ($src1.new) dealloc_return:nt",
3555 // if (!Ps.new) dealloc_return:nt
3556 let isReturn = 1, isTerminator = 1,
3557 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3558 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3560 "if (!$src1.new) dealloc_return:nt",
3565 // if (Ps.new) dealloc_return:t
3566 let isReturn = 1, isTerminator = 1,
3567 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3568 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3570 "if ($src1.new) dealloc_return:t",
3575 // if (!Ps.new) dealloc_return:nt
3576 let isReturn = 1, isTerminator = 1,
3577 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3578 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3580 "if (!$src1.new) dealloc_return:t",