1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let hasSideEffects = 0 in
15 class T_Immext<Operand ImmType>
16 : EXTENDERInst<(outs), (ins ImmType:$imm),
17 "immext(#$imm)", []> {
21 let Inst{27-16} = imm{31-20};
22 let Inst{13-0} = imm{19-6};
25 def A4_ext : T_Immext<u26_6Imm>;
26 let isCodeGenOnly = 1 in {
28 def A4_ext_b : T_Immext<brtarget>;
30 def A4_ext_c : T_Immext<calltarget>;
31 def A4_ext_g : T_Immext<globaladdress>;
34 def BITPOS32 : SDNodeXForm<imm, [{
35 // Return the bit position we will set [0-31].
37 int32_t imm = N->getSExtValue();
38 return XformMskToBitPosU5Imm(imm);
41 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
42 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
44 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
45 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
47 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
48 (HexagonCONST32 node:$addr), [{
49 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
52 // Hexagon V4 Architecture spec defines 8 instruction classes:
53 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
57 // ========================================
58 // Loads (8/16/32/64 bit)
62 // ========================================
63 // Stores (8/16/32/64 bit)
66 // ALU32 Instructions:
67 // ========================================
68 // Arithmetic / Logical (32 bit)
71 // XTYPE Instructions (32/64 bit):
72 // ========================================
73 // Arithmetic, Logical, Bit Manipulation
74 // Multiply (Integer, Fractional, Complex)
75 // Permute / Vector Permute Operations
76 // Predicate Operations
77 // Shift / Shift with Add/Sub/Logical
79 // Vector Halfword (ALU, Shift, Multiply)
80 // Vector Word (ALU, Shift)
83 // ========================================
84 // Jump/Call PC-relative
87 // ========================================
90 // MEMOP Instructions:
91 // ========================================
92 // Operation on memory (8/16/32 bit)
95 // ========================================
100 // ========================================
101 // Control-Register Transfers
102 // Hardware Loop Setup
103 // Predicate Logicals & Reductions
105 // SYSTEM Instructions (not implemented in the compiler):
106 // ========================================
112 //===----------------------------------------------------------------------===//
114 //===----------------------------------------------------------------------===//
116 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
118 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
119 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
122 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
123 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
124 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
125 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
127 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
128 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
129 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
130 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
132 let isCodeGenOnly = 0 in {
133 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
134 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
135 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
138 // Pats for instruction selection.
140 // A class to embed the usual comparison patfrags within a zext to i32.
141 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
142 // names, or else the frag's "body" won't match the operands.
143 class CmpInReg<PatFrag Op>
144 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
146 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
147 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
149 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
150 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
151 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
153 let validSubTargets = HasV4SubT;
154 let InputType = "reg";
155 let CextOpcode = mnemonic;
157 let isCommutable = IsComm;
158 let hasSideEffects = 0;
165 let Inst{27-21} = 0b0111110;
166 let Inst{20-16} = Rs;
168 let Inst{7-5} = MinOp;
172 let isCodeGenOnly = 0 in {
173 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
174 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
175 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
176 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
177 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
178 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
181 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
182 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
183 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
184 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
186 let validSubTargets = HasV4SubT;
187 let InputType = "imm";
188 let CextOpcode = mnemonic;
190 let isCommutable = IsComm;
191 let hasSideEffects = 0;
192 let isExtendable = IsImmExt;
193 let opExtendable = !if (IsImmExt, 2, 0);
194 let isExtentSigned = IsImmSigned;
195 let opExtentBits = ImmBits;
202 let Inst{27-24} = 0b1101;
203 let Inst{22-21} = MajOp;
204 let Inst{20-16} = Rs;
205 let Inst{12-5} = Imm;
207 let Inst{3} = IsHalf;
211 let isCodeGenOnly = 0 in {
212 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
213 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
214 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
215 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
216 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
217 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
219 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
220 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
221 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
223 let validSubTargets = HasV4SubT;
224 let InputType = "imm";
225 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
226 let isExtendable = 1;
227 let opExtendable = 2;
228 let isExtentSigned = 1;
229 let opExtentBits = 8;
237 let Inst{27-24} = 0b0011;
239 let Inst{21} = IsNeg;
240 let Inst{20-16} = Rs;
246 let isCodeGenOnly = 0 in {
247 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
248 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
251 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
252 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
253 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
254 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
256 // Preserve the S2_tstbit_r generation
257 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
258 (i32 IntRegs:$src1))), 0)))),
259 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
262 //===----------------------------------------------------------------------===//
264 //===----------------------------------------------------------------------===//
267 //===----------------------------------------------------------------------===//
269 //===----------------------------------------------------------------------===//
271 // Combine a word and an immediate into a register pair.
272 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
274 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
275 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
281 let Inst{27-24} = 0b0011;
282 let Inst{22-21} = MajOp;
283 let Inst{20-16} = Rs;
289 let opExtendable = 2, isCodeGenOnly = 0 in
290 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
291 "$Rdd = combine($Rs, #$s8)">;
293 let opExtendable = 1, isCodeGenOnly = 0 in
294 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
295 "$Rdd = combine(#$s8, $Rs)">;
297 def HexagonWrapperCombineRI_V4 :
298 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
299 def HexagonWrapperCombineIR_V4 :
300 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
302 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
303 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
306 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
307 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
310 // A4_combineii: Set two small immediates.
311 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
312 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
313 "$Rdd = combine(#$s8, #$U6)"> {
319 let Inst{27-23} = 0b11001;
320 let Inst{20-16} = U6{5-1};
321 let Inst{13} = U6{0};
326 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
334 // Template class for load instructions with Absolute set addressing mode.
335 //===----------------------------------------------------------------------===//
336 let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
337 validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
338 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
339 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
340 (ins u0AlwaysExt:$addr),
341 "$dst1 = "#mnemonic#"($dst2=##$addr)",
345 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
346 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
347 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
348 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
349 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
350 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
352 //===----------------------------------------------------------------------===//
353 // Template classes for the non-predicated load instructions with
354 // base + register offset addressing mode
355 //===----------------------------------------------------------------------===//
356 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
357 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
358 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
359 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
367 let Inst{27-24} = 0b1010;
368 let Inst{23-21} = MajOp;
369 let Inst{20-16} = src1;
370 let Inst{12-8} = src2;
371 let Inst{13} = u2{1};
376 //===----------------------------------------------------------------------===//
377 // Template classes for the predicated load instructions with
378 // base + register offset addressing mode
379 //===----------------------------------------------------------------------===//
380 let isPredicated = 1 in
381 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
382 bit isNot, bit isPredNew>:
383 LDInst <(outs RC:$dst),
384 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
385 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
386 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
387 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
394 let isPredicatedFalse = isNot;
395 let isPredicatedNew = isPredNew;
399 let Inst{27-26} = 0b00;
400 let Inst{25} = isPredNew;
401 let Inst{24} = isNot;
402 let Inst{23-21} = MajOp;
403 let Inst{20-16} = src2;
404 let Inst{12-8} = src3;
405 let Inst{13} = u2{1};
407 let Inst{6-5} = src1;
411 //===----------------------------------------------------------------------===//
412 // multiclass for load instructions with base + register offset
414 //===----------------------------------------------------------------------===//
415 let hasSideEffects = 0, addrMode = BaseRegOffset in
416 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
418 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
419 InputType = "reg" in {
420 let isPredicable = 1 in
421 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
424 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
425 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
428 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
429 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
433 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
434 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
435 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
438 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
439 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
440 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
443 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
444 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
446 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
447 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
449 // 'def pats' for load instructions with base + register offset and non-zero
450 // immediate value. Immediate value is used to left-shift the second
452 let AddedComplexity = 40 in {
453 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
454 (shl IntRegs:$src2, u2ImmPred:$offset)))),
455 (L4_loadrb_rr IntRegs:$src1,
456 IntRegs:$src2, u2ImmPred:$offset)>,
459 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
460 (shl IntRegs:$src2, u2ImmPred:$offset)))),
461 (L4_loadrub_rr IntRegs:$src1,
462 IntRegs:$src2, u2ImmPred:$offset)>,
465 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
466 (shl IntRegs:$src2, u2ImmPred:$offset)))),
467 (L4_loadrub_rr IntRegs:$src1,
468 IntRegs:$src2, u2ImmPred:$offset)>,
471 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
472 (shl IntRegs:$src2, u2ImmPred:$offset)))),
473 (L4_loadrh_rr IntRegs:$src1,
474 IntRegs:$src2, u2ImmPred:$offset)>,
477 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
478 (shl IntRegs:$src2, u2ImmPred:$offset)))),
479 (L4_loadruh_rr IntRegs:$src1,
480 IntRegs:$src2, u2ImmPred:$offset)>,
483 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
484 (shl IntRegs:$src2, u2ImmPred:$offset)))),
485 (L4_loadruh_rr IntRegs:$src1,
486 IntRegs:$src2, u2ImmPred:$offset)>,
489 def : Pat <(i32 (load (add IntRegs:$src1,
490 (shl IntRegs:$src2, u2ImmPred:$offset)))),
491 (L4_loadri_rr IntRegs:$src1,
492 IntRegs:$src2, u2ImmPred:$offset)>,
495 def : Pat <(i64 (load (add IntRegs:$src1,
496 (shl IntRegs:$src2, u2ImmPred:$offset)))),
497 (L4_loadrd_rr IntRegs:$src1,
498 IntRegs:$src2, u2ImmPred:$offset)>,
503 // 'def pats' for load instruction base + register offset and
504 // zero immediate value.
505 let AddedComplexity = 10 in {
506 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
507 (L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>,
510 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
511 (L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>,
514 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
515 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
518 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
519 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
522 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
523 (L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
526 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
527 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
530 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
531 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
534 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
535 (L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>,
540 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
541 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
545 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
546 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
549 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
550 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
553 let AddedComplexity = 20 in
554 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
555 s11_0ExtPred:$offset))),
556 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
557 s11_0ExtPred:$offset)))>,
561 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
562 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
565 let AddedComplexity = 20 in
566 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
567 s11_0ExtPred:$offset))),
568 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
569 s11_0ExtPred:$offset)))>,
573 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
574 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
577 let AddedComplexity = 20 in
578 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
579 s11_1ExtPred:$offset))),
580 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
581 s11_1ExtPred:$offset)))>,
585 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
586 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
589 let AddedComplexity = 20 in
590 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
591 s11_1ExtPred:$offset))),
592 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
593 s11_1ExtPred:$offset)))>,
597 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
598 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
601 let AddedComplexity = 100 in
602 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
603 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
604 s11_2ExtPred:$offset)))>,
608 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
609 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
612 let AddedComplexity = 100 in
613 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
614 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
615 s11_2ExtPred:$offset)))>,
620 //===----------------------------------------------------------------------===//
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
629 // Template class for store instructions with Absolute set addressing mode.
630 //===----------------------------------------------------------------------===//
631 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
632 addrMode = AbsoluteSet in
633 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
634 STInst2<(outs IntRegs:$dst1),
635 (ins RC:$src1, u0AlwaysExt:$src2),
636 mnemonic#"($dst1=##$src2) = $src1",
640 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
641 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
642 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
643 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
645 //===----------------------------------------------------------------------===//
646 // Template classes for the non-predicated store instructions with
647 // base + register offset addressing mode
648 //===----------------------------------------------------------------------===//
649 let isPredicable = 1 in
650 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
651 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
652 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
653 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
662 let Inst{27-24} = 0b1011;
663 let Inst{23-21} = MajOp;
664 let Inst{20-16} = Rs;
666 let Inst{13} = u2{1};
671 //===----------------------------------------------------------------------===//
672 // Template classes for the predicated store instructions with
673 // base + register offset addressing mode
674 //===----------------------------------------------------------------------===//
675 let isPredicated = 1 in
676 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
677 bit isNot, bit isPredNew, bit isH>
679 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
681 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
682 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
683 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
690 let isPredicatedFalse = isNot;
691 let isPredicatedNew = isPredNew;
695 let Inst{27-26} = 0b01;
696 let Inst{25} = isPredNew;
697 let Inst{24} = isNot;
698 let Inst{23-21} = MajOp;
699 let Inst{20-16} = Rs;
701 let Inst{13} = u2{1};
707 //===----------------------------------------------------------------------===//
708 // Template classes for the new-value store instructions with
709 // base + register offset addressing mode
710 //===----------------------------------------------------------------------===//
711 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
712 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
713 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
714 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
715 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
724 let Inst{27-21} = 0b1011101;
725 let Inst{20-16} = Rs;
727 let Inst{13} = u2{1};
729 let Inst{4-3} = MajOp;
733 //===----------------------------------------------------------------------===//
734 // Template classes for the predicated new-value store instructions with
735 // base + register offset addressing mode
736 //===----------------------------------------------------------------------===//
737 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
738 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
740 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
741 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
742 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
743 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
750 let isPredicatedFalse = isNot;
751 let isPredicatedNew = isPredNew;
754 let Inst{27-26} = 0b01;
755 let Inst{25} = isPredNew;
756 let Inst{24} = isNot;
757 let Inst{23-21} = 0b101;
758 let Inst{20-16} = Rs;
760 let Inst{13} = u2{1};
763 let Inst{4-3} = MajOp;
767 //===----------------------------------------------------------------------===//
768 // multiclass for store instructions with base + register offset addressing
770 //===----------------------------------------------------------------------===//
771 let isNVStorable = 1 in
772 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
773 bits<3> MajOp, bit isH = 0> {
774 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
775 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
778 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
779 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
782 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
783 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
787 //===----------------------------------------------------------------------===//
788 // multiclass for new-value store instructions with base + register offset
790 //===----------------------------------------------------------------------===//
791 let mayStore = 1, isNVStore = 1 in
792 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
794 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
795 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
798 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
799 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
802 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
803 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
807 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
808 isCodeGenOnly = 0 in {
809 let accessSize = ByteAccess in
810 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
811 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
813 let accessSize = HalfWordAccess in
814 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
815 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
817 let accessSize = WordAccess in
818 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
819 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
821 let isNVStorable = 0, accessSize = DoubleWordAccess in
822 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
824 let isNVStorable = 0, accessSize = HalfWordAccess in
825 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
828 let Predicates = [HasV4T], AddedComplexity = 10 in {
829 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
830 (add IntRegs:$src1, (shl IntRegs:$src2,
832 (S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
833 u2ImmPred:$src3, IntRegs:$src4)>;
835 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
836 (add IntRegs:$src1, (shl IntRegs:$src2,
838 (S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
839 u2ImmPred:$src3, IntRegs:$src4)>;
841 def : Pat<(store (i32 IntRegs:$src4),
842 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
843 (S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
844 u2ImmPred:$src3, IntRegs:$src4)>;
846 def : Pat<(store (i64 DoubleRegs:$src4),
847 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
848 (S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
849 u2ImmPred:$src3, DoubleRegs:$src4)>;
852 let isExtended = 1, opExtendable = 2 in
853 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
855 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
856 mnemonic#"($src1<<#$src2+##$src3) = $src4",
857 [(stOp (VT RC:$src4),
858 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
859 u0AlwaysExtPred:$src3))]>,
862 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
863 class T_ST_LongOff_nv <string mnemonic> :
865 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
866 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
870 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
871 let BaseOpcode = BaseOp#"_shl" in {
872 let isNVStorable = 1 in
873 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
875 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
879 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
880 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
881 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
882 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
883 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
886 let AddedComplexity = 40 in
887 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
889 def : Pat<(stOp (VT RC:$src4),
890 (add (shl IntRegs:$src1, u2ImmPred:$src2),
891 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
892 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
894 def : Pat<(stOp (VT RC:$src4),
896 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
897 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
900 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
901 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
902 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
903 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
905 // memd(Rx++#s4:3)=Rtt
906 // memd(Rx++#s4:3:circ(Mu))=Rtt
907 // memd(Rx++I:circ(Mu))=Rtt
909 // memd(Rx++Mu:brev)=Rtt
910 // memd(gp+#u16:3)=Rtt
912 // Store doubleword conditionally.
913 // if ([!]Pv[.new]) memd(#u6)=Rtt
914 // TODO: needs to be implemented.
916 //===----------------------------------------------------------------------===//
918 //===----------------------------------------------------------------------===//
919 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
921 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
922 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
923 mnemonic#"($Rs+#$offset)=#$S8",
924 [], "", V4LDST_tc_st_SLOT01>,
925 ImmRegRel, PredNewRel {
931 string OffsetOpStr = !cast<string>(OffsetOp);
932 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
933 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
934 /* u6_0Imm */ offset{5-0}));
938 let Inst{27-25} = 0b110;
939 let Inst{22-21} = MajOp;
940 let Inst{20-16} = Rs;
941 let Inst{12-7} = offsetBits;
942 let Inst{13} = S8{7};
943 let Inst{6-0} = S8{6-0};
946 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
948 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
949 bit isPredNot, bit isPredNew >
951 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
952 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
953 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
954 [], "", V4LDST_tc_st_SLOT01>,
955 ImmRegRel, PredNewRel {
962 string OffsetOpStr = !cast<string>(OffsetOp);
963 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
964 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
965 /* u6_0Imm */ offset{5-0}));
966 let isPredicatedNew = isPredNew;
967 let isPredicatedFalse = isPredNot;
971 let Inst{27-25} = 0b100;
972 let Inst{24} = isPredNew;
973 let Inst{23} = isPredNot;
974 let Inst{22-21} = MajOp;
975 let Inst{20-16} = Rs;
976 let Inst{13} = S6{5};
977 let Inst{12-7} = offsetBits;
979 let Inst{4-0} = S6{4-0};
983 //===----------------------------------------------------------------------===//
984 // multiclass for store instructions with base + immediate offset
985 // addressing mode and immediate stored value.
986 // mem[bhw](Rx++#s4:3)=#s8
987 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
988 //===----------------------------------------------------------------------===//
990 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
992 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
994 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
997 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
999 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1000 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1002 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1003 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1007 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1008 InputType = "imm", isCodeGenOnly = 0 in {
1009 let accessSize = ByteAccess in
1010 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1012 let accessSize = HalfWordAccess in
1013 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1015 let accessSize = WordAccess in
1016 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1019 let Predicates = [HasV4T], AddedComplexity = 10 in {
1020 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1021 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1023 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1024 u6_1ImmPred:$src2)),
1025 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1027 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1028 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1031 let AddedComplexity = 6 in
1032 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1033 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1036 // memb(Rx++#s4:0:circ(Mu))=Rt
1037 // memb(Rx++I:circ(Mu))=Rt
1039 // memb(Rx++Mu:brev)=Rt
1040 // memb(gp+#u16:0)=Rt
1044 // TODO: needs to be implemented
1045 // memh(Re=#U6)=Rt.H
1046 // memh(Rs+#s11:1)=Rt.H
1047 let AddedComplexity = 6 in
1048 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1049 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1052 // memh(Rs+Ru<<#u2)=Rt.H
1053 // TODO: needs to be implemented.
1055 // memh(Ru<<#u2+#U6)=Rt.H
1056 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1057 // memh(Rx++#s4:1:circ(Mu))=Rt
1058 // memh(Rx++I:circ(Mu))=Rt.H
1059 // memh(Rx++I:circ(Mu))=Rt
1060 // memh(Rx++Mu)=Rt.H
1062 // memh(Rx++Mu:brev)=Rt.H
1063 // memh(Rx++Mu:brev)=Rt
1064 // memh(gp+#u16:1)=Rt
1065 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1066 // if ([!]Pv[.new]) memh(#u6)=Rt
1069 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1070 // TODO: needs to be implemented.
1072 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1073 // TODO: Needs to be implemented.
1077 // TODO: Needs to be implemented.
1080 let hasSideEffects = 0 in
1081 def STriw_pred_V4 : STInst2<(outs),
1082 (ins MEMri:$addr, PredRegs:$src1),
1083 "Error; should not emit",
1087 let AddedComplexity = 6 in
1088 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1089 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1092 // memw(Rx++#s4:2)=Rt
1093 // memw(Rx++#s4:2:circ(Mu))=Rt
1094 // memw(Rx++I:circ(Mu))=Rt
1096 // memw(Rx++Mu:brev)=Rt
1098 //===----------------------------------------------------------------------===
1100 //===----------------------------------------------------------------------===
1103 //===----------------------------------------------------------------------===//
1105 //===----------------------------------------------------------------------===//
1107 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1108 class T_store_io_nv <string mnemonic, RegisterClass RC,
1109 Operand ImmOp, bits<2>MajOp>
1110 : NVInst_V4 <(outs),
1111 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1112 mnemonic#"($src1+#$src2) = $src3.new",
1113 [],"",ST_tc_st_SLOT0> {
1115 bits<13> src2; // Actual address offset
1117 bits<11> offsetBits; // Represents offset encoding
1119 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1120 !if (!eq(mnemonic, "memh"), 12,
1121 !if (!eq(mnemonic, "memw"), 13, 0)));
1123 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1124 !if (!eq(mnemonic, "memh"), 1,
1125 !if (!eq(mnemonic, "memw"), 2, 0)));
1127 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1128 !if (!eq(mnemonic, "memh"), src2{11-1},
1129 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1131 let IClass = 0b1010;
1134 let Inst{26-25} = offsetBits{10-9};
1135 let Inst{24-21} = 0b1101;
1136 let Inst{20-16} = src1;
1137 let Inst{13} = offsetBits{8};
1138 let Inst{12-11} = MajOp;
1139 let Inst{10-8} = src3;
1140 let Inst{7-0} = offsetBits{7-0};
1143 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1144 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1145 bits<2>MajOp, bit PredNot, bit isPredNew>
1146 : NVInst_V4 <(outs),
1147 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1148 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1149 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1150 [],"",V2LDST_tc_st_SLOT0> {
1155 bits<6> offsetBits; // Represents offset encoding
1157 let isPredicatedNew = isPredNew;
1158 let isPredicatedFalse = PredNot;
1159 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1160 !if (!eq(mnemonic, "memh"), 7,
1161 !if (!eq(mnemonic, "memw"), 8, 0)));
1163 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1164 !if (!eq(mnemonic, "memh"), 1,
1165 !if (!eq(mnemonic, "memw"), 2, 0)));
1167 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1168 !if (!eq(mnemonic, "memh"), src3{6-1},
1169 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1171 let IClass = 0b0100;
1174 let Inst{26} = PredNot;
1175 let Inst{25} = isPredNew;
1176 let Inst{24-21} = 0b0101;
1177 let Inst{20-16} = src2;
1178 let Inst{13} = offsetBits{5};
1179 let Inst{12-11} = MajOp;
1180 let Inst{10-8} = src4;
1181 let Inst{7-3} = offsetBits{4-0};
1183 let Inst{1-0} = src1;
1186 // multiclass for new-value store instructions with base + immediate offset.
1188 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1190 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1191 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1193 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1194 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1196 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1197 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1199 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1201 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1206 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1207 let accessSize = ByteAccess in
1208 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1209 u6_0Ext, 0b00>, AddrModeRel;
1211 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1212 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1213 u6_1Ext, 0b01>, AddrModeRel;
1215 let accessSize = WordAccess, opExtentAlign = 2 in
1216 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1217 u6_2Ext, 0b10>, AddrModeRel;
1220 //===----------------------------------------------------------------------===//
1221 // Template class for non-predicated post increment .new stores
1222 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1223 //===----------------------------------------------------------------------===//
1224 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1225 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1226 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1227 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1228 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1229 mnemonic#"($src1++#$offset) = $src2.new",
1230 [], "$src1 = $_dst_">,
1237 string ImmOpStr = !cast<string>(ImmOp);
1238 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1239 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1240 /* s4_0Imm */ offset{3-0}));
1241 let IClass = 0b1010;
1243 let Inst{27-21} = 0b1011101;
1244 let Inst{20-16} = src1;
1246 let Inst{12-11} = MajOp;
1247 let Inst{10-8} = src2;
1249 let Inst{6-3} = offsetBits;
1253 //===----------------------------------------------------------------------===//
1254 // Template class for predicated post increment .new stores
1255 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1256 //===----------------------------------------------------------------------===//
1257 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1258 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1259 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1260 bits<2> MajOp, bit isPredNot, bit isPredNew >
1261 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1262 (ins PredRegs:$src1, IntRegs:$src2,
1263 ImmOp:$offset, IntRegs:$src3),
1264 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1265 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1266 [], "$src2 = $_dst_">,
1274 string ImmOpStr = !cast<string>(ImmOp);
1275 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1276 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1277 /* s4_0Imm */ offset{3-0}));
1278 let isPredicatedNew = isPredNew;
1279 let isPredicatedFalse = isPredNot;
1281 let IClass = 0b1010;
1283 let Inst{27-21} = 0b1011101;
1284 let Inst{20-16} = src2;
1286 let Inst{12-11} = MajOp;
1287 let Inst{10-8} = src3;
1288 let Inst{7} = isPredNew;
1289 let Inst{6-3} = offsetBits;
1290 let Inst{2} = isPredNot;
1291 let Inst{1-0} = src1;
1294 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1295 bits<2> MajOp, bit PredNot> {
1296 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1299 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1302 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1304 let BaseOpcode = "POST_"#BaseOp in {
1305 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1308 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1309 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1313 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1314 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1316 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1317 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1319 let accessSize = WordAccess, isCodeGenOnly = 0 in
1320 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1322 //===----------------------------------------------------------------------===//
1323 // Template class for post increment .new stores with register offset
1324 //===----------------------------------------------------------------------===//
1325 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1326 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1327 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1328 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1329 #mnemonic#"($src1++$src2) = $src3.new",
1330 [], "$src1 = $_dst_"> {
1334 let accessSize = AccessSz;
1336 let IClass = 0b1010;
1338 let Inst{27-21} = 0b1101101;
1339 let Inst{20-16} = src1;
1340 let Inst{13} = src2;
1341 let Inst{12-11} = MajOp;
1342 let Inst{10-8} = src3;
1346 let isCodeGenOnly = 0 in {
1347 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1348 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1349 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1352 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1353 // memb(Rx++I:circ(Mu))=Nt.new
1354 // memb(Rx++Mu)=Nt.new
1355 // memb(Rx++Mu:brev)=Nt.new
1356 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1357 // memh(Rx++I:circ(Mu))=Nt.new
1358 // memh(Rx++Mu)=Nt.new
1359 // memh(Rx++Mu:brev)=Nt.new
1361 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1362 // memw(Rx++I:circ(Mu))=Nt.new
1363 // memw(Rx++Mu)=Nt.new
1364 // memw(Rx++Mu:brev)=Nt.new
1366 //===----------------------------------------------------------------------===//
1368 //===----------------------------------------------------------------------===//
1370 //===----------------------------------------------------------------------===//
1372 //===----------------------------------------------------------------------===//
1374 //===----------------------------------------------------------------------===//
1375 // multiclass/template class for the new-value compare jumps with the register
1377 //===----------------------------------------------------------------------===//
1379 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1380 opExtentAlign = 2 in
1381 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1382 bit isNegCond, bit isTak>
1384 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1385 "if ("#!if(isNegCond, "!","")#mnemonic#
1386 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1387 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1388 #!if(isTak, "t","nt")#" $offset", []> {
1392 bits<3> Ns; // New-Value Operand
1393 bits<5> RegOp; // Non-New-Value Operand
1396 let isTaken = isTak;
1397 let isPredicatedFalse = isNegCond;
1398 let opNewValue{0} = NvOpNum;
1400 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1401 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1403 let IClass = 0b0010;
1405 let Inst{25-23} = majOp;
1406 let Inst{22} = isNegCond;
1407 let Inst{18-16} = Ns;
1408 let Inst{13} = isTak;
1409 let Inst{12-8} = RegOp;
1410 let Inst{21-20} = offset{10-9};
1411 let Inst{7-1} = offset{8-2};
1415 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1417 // Branch not taken:
1418 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1420 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1423 // NvOpNum = 0 -> First Operand is a new-value Register
1424 // NvOpNum = 1 -> Second Operand is a new-value Register
1426 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1428 let BaseOpcode = BaseOp#_NVJ in {
1429 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1430 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1434 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1435 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1436 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1437 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1438 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1440 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1441 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1442 isCodeGenOnly = 0 in {
1443 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1444 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1445 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1446 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1447 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1450 //===----------------------------------------------------------------------===//
1451 // multiclass/template class for the new-value compare jumps instruction
1452 // with a register and an unsigned immediate (U5) operand.
1453 //===----------------------------------------------------------------------===//
1455 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1456 opExtentAlign = 2 in
1457 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1460 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1461 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1462 #!if(isTak, "t","nt")#" $offset", []> {
1464 let isTaken = isTak;
1465 let isPredicatedFalse = isNegCond;
1466 let isTaken = isTak;
1472 let IClass = 0b0010;
1474 let Inst{25-23} = majOp;
1475 let Inst{22} = isNegCond;
1476 let Inst{18-16} = src1;
1477 let Inst{13} = isTak;
1478 let Inst{12-8} = src2;
1479 let Inst{21-20} = offset{10-9};
1480 let Inst{7-1} = offset{8-2};
1483 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1484 // Branch not taken:
1485 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1487 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1490 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1491 let BaseOpcode = BaseOp#_NVJri in {
1492 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1493 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1497 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1498 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1499 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1501 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1502 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1503 isCodeGenOnly = 0 in {
1504 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1505 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1506 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1509 //===----------------------------------------------------------------------===//
1510 // multiclass/template class for the new-value compare jumps instruction
1511 // with a register and an hardcoded 0/-1 immediate value.
1512 //===----------------------------------------------------------------------===//
1514 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1515 opExtentAlign = 2 in
1516 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1517 bit isNegCond, bit isTak>
1519 (ins IntRegs:$src1, brtarget:$offset),
1520 "if ("#!if(isNegCond, "!","")#mnemonic
1521 #"($src1.new, #"#ImmVal#")) jump:"
1522 #!if(isTak, "t","nt")#" $offset", []> {
1524 let isTaken = isTak;
1525 let isPredicatedFalse = isNegCond;
1526 let isTaken = isTak;
1530 let IClass = 0b0010;
1532 let Inst{25-23} = majOp;
1533 let Inst{22} = isNegCond;
1534 let Inst{18-16} = src1;
1535 let Inst{13} = isTak;
1536 let Inst{21-20} = offset{10-9};
1537 let Inst{7-1} = offset{8-2};
1540 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1542 // Branch not taken:
1543 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1545 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1548 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1550 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1551 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1552 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1556 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1557 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1558 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1560 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1561 Defs = [PC], hasSideEffects = 0, isCodeGenOnly = 0 in {
1562 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1563 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1564 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1567 // J4_hintjumpr: Hint indirect conditional jump.
1568 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1569 def J4_hintjumpr: JRInst <
1574 let IClass = 0b0101;
1575 let Inst{27-21} = 0b0010101;
1576 let Inst{20-16} = Rs;
1579 //===----------------------------------------------------------------------===//
1581 //===----------------------------------------------------------------------===//
1583 //===----------------------------------------------------------------------===//
1585 //===----------------------------------------------------------------------===//
1588 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1589 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0,
1590 Uses = [PC], validSubTargets = HasV4SubT in
1591 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1592 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1596 let IClass = 0b0110;
1597 let Inst{27-16} = 0b101001001001;
1598 let Inst{12-7} = u6;
1604 let hasSideEffects = 0 in
1605 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1606 : CRInst<(outs PredRegs:$Pd),
1607 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1608 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1609 !if (IsNeg,"!","") # "$Pu))",
1610 [], "", CR_tc_2early_SLOT23> {
1616 let IClass = 0b0110;
1617 let Inst{27-24} = 0b1011;
1618 let Inst{23} = IsNeg;
1619 let Inst{22-21} = OpBits;
1621 let Inst{17-16} = Ps;
1628 let isCodeGenOnly = 0 in {
1629 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1630 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1631 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1632 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1633 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1634 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1635 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1636 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1639 //===----------------------------------------------------------------------===//
1641 //===----------------------------------------------------------------------===//
1643 //===----------------------------------------------------------------------===//
1645 //===----------------------------------------------------------------------===//
1647 // Logical with-not instructions.
1648 let validSubTargets = HasV4SubT, isCodeGenOnly = 0 in {
1649 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1650 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1653 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1654 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1655 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1660 let IClass = 0b1101;
1661 let Inst{27-21} = 0b0101111;
1662 let Inst{20-16} = Rs;
1663 let Inst{12-8} = Rt;
1666 // Add and accumulate.
1667 // Rd=add(Rs,add(Ru,#s6))
1668 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1669 opExtendable = 3, isCodeGenOnly = 0 in
1670 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1671 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1672 "$Rd = add($Rs, add($Ru, #$s6))" ,
1673 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1674 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1675 "", ALU64_tc_2_SLOT23> {
1681 let IClass = 0b1101;
1683 let Inst{27-23} = 0b10110;
1684 let Inst{22-21} = s6{5-4};
1685 let Inst{20-16} = Rs;
1686 let Inst{13} = s6{3};
1687 let Inst{12-8} = Rd;
1688 let Inst{7-5} = s6{2-0};
1692 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1693 opExtentBits = 6, opExtendable = 2, isCodeGenOnly = 0 in
1694 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1695 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1696 "$Rd = add($Rs, sub(#$s6, $Ru))",
1697 [], "", ALU64_tc_2_SLOT23> {
1703 let IClass = 0b1101;
1705 let Inst{27-23} = 0b10111;
1706 let Inst{22-21} = s6{5-4};
1707 let Inst{20-16} = Rs;
1708 let Inst{13} = s6{3};
1709 let Inst{12-8} = Rd;
1710 let Inst{7-5} = s6{2-0};
1715 // Rdd=extract(Rss,#u6,#U6)
1716 // Rdd=extract(Rss,Rtt)
1717 // Rd=extract(Rs,Rtt)
1718 // Rd=extract(Rs,#u5,#U5)
1720 let isCodeGenOnly = 0 in {
1721 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1722 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1725 let hasNewValue = 1, isCodeGenOnly = 0 in {
1726 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1727 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1730 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1731 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1732 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1735 // Logical xor with xor accumulation.
1736 // Rxx^=xor(Rss,Rtt)
1737 let hasSideEffects = 0, isCodeGenOnly = 0 in
1739 : SInst <(outs DoubleRegs:$Rxx),
1740 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1741 "$Rxx ^= xor($Rss, $Rtt)",
1742 [(set (i64 DoubleRegs:$Rxx),
1743 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
1744 (i64 DoubleRegs:$Rtt))))],
1745 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
1750 let IClass = 0b1100;
1752 let Inst{27-23} = 0b10101;
1753 let Inst{20-16} = Rss;
1754 let Inst{12-8} = Rtt;
1755 let Inst{4-0} = Rxx;
1759 let isCodeGenOnly = 0 in
1760 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
1762 // Arithmetic/Convergent round
1763 let isCodeGenOnly = 0 in
1764 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
1766 let isCodeGenOnly = 0 in
1767 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
1769 let Defs = [USR_OVF], isCodeGenOnly = 0 in
1770 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
1772 // Logical-logical words.
1773 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
1774 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
1775 opExtendable = 3, isCodeGenOnly = 0 in
1777 ALU64Inst<(outs IntRegs:$Rx),
1778 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
1779 "$Rx = or($Ru, and($_src_, #$s10))" ,
1780 [(set (i32 IntRegs:$Rx),
1781 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
1782 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
1787 let IClass = 0b1101;
1789 let Inst{27-22} = 0b101001;
1790 let Inst{20-16} = Rx;
1791 let Inst{21} = s10{9};
1792 let Inst{13-5} = s10{8-0};
1796 // Miscellaneous ALU64 instructions.
1798 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1799 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1800 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1805 let IClass = 0b1101;
1806 let Inst{27-21} = 0b0011111;
1807 let Inst{20-16} = Rs;
1808 let Inst{12-8} = Rt;
1809 let Inst{7-5} = 0b111;
1813 let hasSideEffects = 0, isCodeGenOnly = 0 in
1814 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
1815 (ins IntRegs:$Rs, IntRegs:$Rt),
1816 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1821 let IClass = 0b1101;
1822 let Inst{27-24} = 0b0100;
1824 let Inst{20-16} = Rs;
1825 let Inst{12-8} = Rt;
1829 let isCodeGenOnly = 0 in {
1830 // Rx[&|]=xor(Rs,Rt)
1831 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
1832 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
1834 // Rx[&|^]=or(Rs,Rt)
1835 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
1837 let CextOpcode = "ORr_ORr" in
1838 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
1839 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
1841 // Rx[&|^]=and(Rs,Rt)
1842 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
1844 let CextOpcode = "ORr_ANDr" in
1845 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
1846 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
1848 // Rx[&|^]=and(Rs,~Rt)
1849 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
1850 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
1851 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
1854 // Compound or-or and or-and
1855 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
1856 opExtentBits = 10, opExtendable = 3 in
1857 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
1858 : MInst_acc <(outs IntRegs:$Rx),
1859 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
1860 "$Rx |= "#mnemonic#"($Rs, #$s10)",
1861 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
1862 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
1863 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
1868 let IClass = 0b1101;
1870 let Inst{27-24} = 0b1010;
1871 let Inst{23-22} = MajOp;
1872 let Inst{20-16} = Rs;
1873 let Inst{21} = s10{9};
1874 let Inst{13-5} = s10{8-0};
1878 let CextOpcode = "ORr_ANDr", isCodeGenOnly = 0 in
1879 def S4_or_andi : T_CompOR <"and", 0b00, and>;
1881 let CextOpcode = "ORr_ORr", isCodeGenOnly = 0 in
1882 def S4_or_ori : T_CompOR <"or", 0b10, or>;
1885 // Rd=modwrap(Rs,Rt)
1887 // Rd=cround(Rs,#u5)
1889 // Rd=round(Rs,#u5)[:sat]
1890 // Rd=round(Rs,Rt)[:sat]
1891 // Vector reduce add unsigned halfwords
1892 // Rd=vraddh(Rss,Rtt)
1894 // Rdd=vaddb(Rss,Rtt)
1895 // Vector conditional negate
1896 // Rdd=vcnegh(Rss,Rt)
1897 // Rxx+=vrcnegh(Rss,Rt)
1898 // Vector maximum bytes
1899 // Rdd=vmaxb(Rtt,Rss)
1900 // Vector reduce maximum halfwords
1901 // Rxx=vrmaxh(Rss,Ru)
1902 // Rxx=vrmaxuh(Rss,Ru)
1903 // Vector reduce maximum words
1904 // Rxx=vrmaxuw(Rss,Ru)
1905 // Rxx=vrmaxw(Rss,Ru)
1906 // Vector minimum bytes
1907 // Rdd=vminb(Rtt,Rss)
1908 // Vector reduce minimum halfwords
1909 // Rxx=vrminh(Rss,Ru)
1910 // Rxx=vrminuh(Rss,Ru)
1911 // Vector reduce minimum words
1912 // Rxx=vrminuw(Rss,Ru)
1913 // Rxx=vrminw(Rss,Ru)
1914 // Vector subtract bytes
1915 // Rdd=vsubb(Rss,Rtt)
1917 //===----------------------------------------------------------------------===//
1919 //===----------------------------------------------------------------------===//
1921 //===----------------------------------------------------------------------===//
1923 //===----------------------------------------------------------------------===//
1926 let isCodeGenOnly = 0 in
1927 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
1930 let isCodeGenOnly = 0 in {
1931 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
1932 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
1933 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
1936 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
1937 (S2_ct0p (i64 DoubleRegs:$Rss))>;
1938 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
1939 (S2_ct1p (i64 DoubleRegs:$Rss))>;
1941 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1942 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
1943 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
1947 let IClass = 0b1000;
1948 let Inst{27-24} = 0b1100;
1949 let Inst{23-21} = 0b001;
1950 let Inst{20-16} = Rs;
1951 let Inst{13-8} = s6;
1952 let Inst{7-5} = 0b000;
1956 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1957 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
1958 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
1962 let IClass = 0b1000;
1963 let Inst{27-24} = 0b1000;
1964 let Inst{23-21} = 0b011;
1965 let Inst{20-16} = Rs;
1966 let Inst{13-8} = s6;
1967 let Inst{7-5} = 0b010;
1972 // Bit test/set/clear
1973 let isCodeGenOnly = 0 in {
1974 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
1975 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
1978 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
1979 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
1980 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
1981 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
1982 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
1985 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
1986 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
1987 // if ([!]tstbit(...)) jump ...
1988 let AddedComplexity = 100 in
1989 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
1990 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
1992 let AddedComplexity = 100 in
1993 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
1994 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
1996 let isCodeGenOnly = 0 in {
1997 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
1998 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
1999 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2002 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2003 // represented as a compare against "value & 0xFF", which is an exact match
2004 // for cmpb (same for cmph). The patterns below do not contain any additional
2005 // complexity that would make them preferable, and if they were actually used
2006 // instead of cmpb/cmph, they would result in a compare against register that
2007 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2008 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2009 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2010 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2011 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2012 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2013 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2015 //===----------------------------------------------------------------------===//
2017 //===----------------------------------------------------------------------===//
2019 //===----------------------------------------------------------------------===//
2021 //===----------------------------------------------------------------------===//
2023 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2025 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1,
2026 isCodeGenOnly = 0 in
2027 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2028 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2029 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2030 [(set (i32 IntRegs:$Rd),
2031 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2032 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2038 let IClass = 0b1101;
2040 let Inst{27-24} = 0b1000;
2041 let Inst{23} = U6{5};
2042 let Inst{22-21} = u6{5-4};
2043 let Inst{20-16} = Rs;
2044 let Inst{13} = u6{3};
2045 let Inst{12-8} = Rd;
2046 let Inst{7-5} = u6{2-0};
2047 let Inst{4-0} = U6{4-0};
2050 // Rd=add(#u6,mpyi(Rs,Rt))
2051 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2052 isExtendable = 1, opExtentBits = 6, opExtendable = 1, isCodeGenOnly = 0 in
2053 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2054 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2055 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2056 [(set (i32 IntRegs:$Rd),
2057 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2058 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2064 let IClass = 0b1101;
2066 let Inst{27-23} = 0b01110;
2067 let Inst{22-21} = u6{5-4};
2068 let Inst{20-16} = Rs;
2069 let Inst{13} = u6{3};
2070 let Inst{12-8} = Rt;
2071 let Inst{7-5} = u6{2-0};
2075 let hasNewValue = 1 in
2076 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2077 : ALU64Inst <(outs IntRegs:$dst), ins,
2078 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2080 [(set (i32 IntRegs:$dst),
2081 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2082 "", ALU64_tc_3x_SLOT23> {
2088 let IClass = 0b1101;
2090 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2092 let Inst{27-24} = 0b1111;
2093 let Inst{23} = MajOp;
2094 let Inst{22-21} = ImmValue{5-4};
2095 let Inst{20-16} = src3;
2096 let Inst{13} = ImmValue{3};
2097 let Inst{12-8} = dst;
2098 let Inst{7-5} = ImmValue{2-0};
2099 let Inst{4-0} = src1;
2102 let isCodeGenOnly = 0 in
2103 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2104 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2106 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2107 CextOpcode = "ADD_MPY", InputType = "imm", isCodeGenOnly = 0 in
2108 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2109 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2111 // Rx=add(Ru,mpyi(Rx,Rs))
2112 let validSubTargets = HasV4SubT, CextOpcode = "ADD_MPY", InputType = "reg",
2113 hasNewValue = 1, isCodeGenOnly = 0 in
2114 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2115 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2116 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2117 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2118 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2119 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2124 let IClass = 0b1110;
2126 let Inst{27-21} = 0b0011000;
2127 let Inst{12-8} = Rx;
2129 let Inst{20-16} = Rs;
2132 // Rd=add(##,mpyi(Rs,#U6))
2133 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2134 (HexagonCONST32 tglobaladdr:$src1)),
2135 (i32 (M4_mpyri_addi tglobaladdr:$src1, IntRegs:$src2,
2138 // Rd=add(##,mpyi(Rs,Rt))
2139 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2140 (HexagonCONST32 tglobaladdr:$src1)),
2141 (i32 (M4_mpyrr_addi tglobaladdr:$src1, IntRegs:$src2,
2144 // Polynomial multiply words
2146 // Rxx^=pmpyw(Rs,Rt)
2148 // Vector reduce multiply word by signed half (32x16)
2149 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2150 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2151 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
2152 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
2154 // Multiply and use upper result
2155 // Rd=mpy(Rs,Rt.H):<<1:sat
2156 // Rd=mpy(Rs,Rt.L):<<1:sat
2157 // Rd=mpy(Rs,Rt):<<1
2158 // Rd=mpy(Rs,Rt):<<1:sat
2160 // Rx+=mpy(Rs,Rt):<<1:sat
2161 // Rx-=mpy(Rs,Rt):<<1:sat
2163 // Vector multiply bytes
2164 // Rdd=vmpybsu(Rs,Rt)
2165 // Rdd=vmpybu(Rs,Rt)
2166 // Rxx+=vmpybsu(Rs,Rt)
2167 // Rxx+=vmpybu(Rs,Rt)
2169 // Vector polynomial multiply halfwords
2170 // Rdd=vpmpyh(Rs,Rt)
2171 // Rxx^=vpmpyh(Rs,Rt)
2173 //===----------------------------------------------------------------------===//
2175 //===----------------------------------------------------------------------===//
2178 //===----------------------------------------------------------------------===//
2180 //===----------------------------------------------------------------------===//
2181 // Shift by immediate and accumulate/logical.
2182 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2183 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2184 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2185 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2186 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2187 hasNewValue = 1, opNewValue = 0, validSubTargets = HasV4SubT in
2188 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2189 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2190 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2191 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2192 [(set (i32 IntRegs:$Rd),
2193 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2194 "$Rd = $Rx", Itin> {
2201 let IClass = 0b1101;
2202 let Inst{27-24} = 0b1110;
2203 let Inst{23-21} = u8{7-5};
2204 let Inst{20-16} = Rd;
2205 let Inst{13} = u8{4};
2206 let Inst{12-8} = U5;
2207 let Inst{7-5} = u8{3-1};
2208 let Inst{4} = asl_lsr;
2209 let Inst{3} = u8{0};
2210 let Inst{2-1} = MajOp;
2213 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2214 InstrItinClass Itin> {
2215 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2216 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2219 let AddedComplexity = 200, isCodeGenOnly = 0 in {
2220 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2221 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2224 let AddedComplexity = 30, isCodeGenOnly = 0 in
2225 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2227 let isCodeGenOnly = 0 in
2228 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2231 // Rd=[cround|round](Rs,Rt)
2232 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in {
2233 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2234 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2237 // Rd=round(Rs,Rt):sat
2238 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23,
2239 isCodeGenOnly = 0 in
2240 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2242 // Shift by immediate and accumulate.
2243 // Rx=add(#u8,asl(Rx,#U5))
2244 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2245 validSubTargets = HasV4SubT in
2246 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2247 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2248 "$dst = add(#$src1, asl($src2, #$src3))",
2249 [(set (i32 IntRegs:$dst),
2250 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2255 // Rx=add(#u8,lsr(Rx,#U5))
2256 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2257 validSubTargets = HasV4SubT in
2258 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2259 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2260 "$dst = add(#$src1, lsr($src2, #$src3))",
2261 [(set (i32 IntRegs:$dst),
2262 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2267 // Rx=sub(#u8,asl(Rx,#U5))
2268 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2269 validSubTargets = HasV4SubT in
2270 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2271 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2272 "$dst = sub(#$src1, asl($src2, #$src3))",
2273 [(set (i32 IntRegs:$dst),
2274 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2279 // Rx=sub(#u8,lsr(Rx,#U5))
2280 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2281 validSubTargets = HasV4SubT in
2282 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2283 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2284 "$dst = sub(#$src1, lsr($src2, #$src3))",
2285 [(set (i32 IntRegs:$dst),
2286 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2292 //Shift by immediate and logical.
2293 //Rx=and(#u8,asl(Rx,#U5))
2294 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2295 validSubTargets = HasV4SubT in
2296 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2297 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2298 "$dst = and(#$src1, asl($src2, #$src3))",
2299 [(set (i32 IntRegs:$dst),
2300 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2305 //Rx=and(#u8,lsr(Rx,#U5))
2306 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2307 validSubTargets = HasV4SubT in
2308 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2309 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2310 "$dst = and(#$src1, lsr($src2, #$src3))",
2311 [(set (i32 IntRegs:$dst),
2312 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2317 //Rx=or(#u8,asl(Rx,#U5))
2318 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2319 AddedComplexity = 30, validSubTargets = HasV4SubT in
2320 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2321 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2322 "$dst = or(#$src1, asl($src2, #$src3))",
2323 [(set (i32 IntRegs:$dst),
2324 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2329 //Rx=or(#u8,lsr(Rx,#U5))
2330 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2331 AddedComplexity = 30, validSubTargets = HasV4SubT in
2332 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2333 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2334 "$dst = or(#$src1, lsr($src2, #$src3))",
2335 [(set (i32 IntRegs:$dst),
2336 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2342 //Shift by register.
2344 let validSubTargets = HasV4SubT in {
2345 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
2346 "$dst = lsl(#$src1, $src2)",
2347 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
2348 (i32 IntRegs:$src2)))]>,
2352 //Shift by register and logical.
2354 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2355 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2356 "$dst ^= asl($src2, $src3)",
2357 [(set (i64 DoubleRegs:$dst),
2358 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
2359 (i32 IntRegs:$src3))))],
2364 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2365 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2366 "$dst ^= asr($src2, $src3)",
2367 [(set (i64 DoubleRegs:$dst),
2368 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
2369 (i32 IntRegs:$src3))))],
2374 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2375 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2376 "$dst ^= lsl($src2, $src3)",
2377 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
2378 (shl (i64 DoubleRegs:$src2),
2379 (i32 IntRegs:$src3))))],
2384 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2385 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2386 "$dst ^= lsr($src2, $src3)",
2387 [(set (i64 DoubleRegs:$dst),
2388 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
2389 (i32 IntRegs:$src3))))],
2394 //===----------------------------------------------------------------------===//
2396 //===----------------------------------------------------------------------===//
2398 //===----------------------------------------------------------------------===//
2399 // MEMOP: Word, Half, Byte
2400 //===----------------------------------------------------------------------===//
2402 def MEMOPIMM : SDNodeXForm<imm, [{
2403 // Call the transformation function XformM5ToU5Imm to get the negative
2404 // immediate's positive counterpart.
2405 int32_t imm = N->getSExtValue();
2406 return XformM5ToU5Imm(imm);
2409 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2410 // -1 .. -31 represented as 65535..65515
2411 // assigning to a short restores our desired signed value.
2412 // Call the transformation function XformM5ToU5Imm to get the negative
2413 // immediate's positive counterpart.
2414 int16_t imm = N->getSExtValue();
2415 return XformM5ToU5Imm(imm);
2418 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2419 // -1 .. -31 represented as 255..235
2420 // assigning to a char restores our desired signed value.
2421 // Call the transformation function XformM5ToU5Imm to get the negative
2422 // immediate's positive counterpart.
2423 int8_t imm = N->getSExtValue();
2424 return XformM5ToU5Imm(imm);
2427 def SETMEMIMM : SDNodeXForm<imm, [{
2428 // Return the bit position we will set [0-31].
2430 int32_t imm = N->getSExtValue();
2431 return XformMskToBitPosU5Imm(imm);
2434 def CLRMEMIMM : SDNodeXForm<imm, [{
2435 // Return the bit position we will clear [0-31].
2437 // we bit negate the value first
2438 int32_t imm = ~(N->getSExtValue());
2439 return XformMskToBitPosU5Imm(imm);
2442 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2443 // Return the bit position we will set [0-15].
2445 int16_t imm = N->getSExtValue();
2446 return XformMskToBitPosU4Imm(imm);
2449 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2450 // Return the bit position we will clear [0-15].
2452 // we bit negate the value first
2453 int16_t imm = ~(N->getSExtValue());
2454 return XformMskToBitPosU4Imm(imm);
2457 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2458 // Return the bit position we will set [0-7].
2460 int8_t imm = N->getSExtValue();
2461 return XformMskToBitPosU3Imm(imm);
2464 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2465 // Return the bit position we will clear [0-7].
2467 // we bit negate the value first
2468 int8_t imm = ~(N->getSExtValue());
2469 return XformMskToBitPosU3Imm(imm);
2472 //===----------------------------------------------------------------------===//
2473 // Template class for MemOp instructions with the register value.
2474 //===----------------------------------------------------------------------===//
2475 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2476 string memOp, bits<2> memOpBits> :
2478 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2479 opc#"($base+#$offset)"#memOp#"$delta",
2481 Requires<[HasV4T, UseMEMOP]> {
2486 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2488 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2489 !if (!eq(opcBits, 0b01), offset{6-1},
2490 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2492 let IClass = 0b0011;
2493 let Inst{27-24} = 0b1110;
2494 let Inst{22-21} = opcBits;
2495 let Inst{20-16} = base;
2497 let Inst{12-7} = offsetBits;
2498 let Inst{6-5} = memOpBits;
2499 let Inst{4-0} = delta;
2502 //===----------------------------------------------------------------------===//
2503 // Template class for MemOp instructions with the immediate value.
2504 //===----------------------------------------------------------------------===//
2505 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2506 string memOp, bits<2> memOpBits> :
2508 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2509 opc#"($base+#$offset)"#memOp#"#$delta"
2510 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2512 Requires<[HasV4T, UseMEMOP]> {
2517 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2519 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2520 !if (!eq(opcBits, 0b01), offset{6-1},
2521 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2523 let IClass = 0b0011;
2524 let Inst{27-24} = 0b1111;
2525 let Inst{22-21} = opcBits;
2526 let Inst{20-16} = base;
2528 let Inst{12-7} = offsetBits;
2529 let Inst{6-5} = memOpBits;
2530 let Inst{4-0} = delta;
2533 // multiclass to define MemOp instructions with register operand.
2534 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2535 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2536 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2537 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2538 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2541 // multiclass to define MemOp instructions with immediate Operand.
2542 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2543 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2544 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2545 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
2546 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
2549 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2550 defm r : MemOp_rr <opc, opcBits, ImmOp>;
2551 defm i : MemOp_ri <opc, opcBits, ImmOp>;
2554 // Define MemOp instructions.
2555 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2556 validSubTargets =HasV4SubT in {
2557 let opExtentBits = 6, accessSize = ByteAccess in
2558 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
2560 let opExtentBits = 7, accessSize = HalfWordAccess in
2561 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
2563 let opExtentBits = 8, accessSize = WordAccess in
2564 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
2567 //===----------------------------------------------------------------------===//
2568 // Multiclass to define 'Def Pats' for ALU operations on the memory
2569 // Here value used for the ALU operation is an immediate value.
2570 // mem[bh](Rs+#0) += #U5
2571 // mem[bh](Rs+#u6) += #U5
2572 //===----------------------------------------------------------------------===//
2574 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2575 InstHexagon MI, SDNode OpNode> {
2576 let AddedComplexity = 180 in
2577 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2579 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2581 let AddedComplexity = 190 in
2582 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2584 (add IntRegs:$base, ExtPred:$offset)),
2585 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2588 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2589 InstHexagon addMI, InstHexagon subMI> {
2590 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2591 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2594 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2596 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2597 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
2599 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2600 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
2603 let Predicates = [HasV4T, UseMEMOP] in {
2604 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2605 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2606 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2609 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
2613 //===----------------------------------------------------------------------===//
2614 // multiclass to define 'Def Pats' for ALU operations on the memory.
2615 // Here value used for the ALU operation is a negative value.
2616 // mem[bh](Rs+#0) += #m5
2617 // mem[bh](Rs+#u6) += #m5
2618 //===----------------------------------------------------------------------===//
2620 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2621 PatLeaf immPred, ComplexPattern addrPred,
2622 SDNodeXForm xformFunc, InstHexagon MI> {
2623 let AddedComplexity = 190 in
2624 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2626 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2628 let AddedComplexity = 195 in
2629 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2631 (add IntRegs:$base, extPred:$offset)),
2632 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2635 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2637 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2638 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
2640 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2641 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
2644 let Predicates = [HasV4T, UseMEMOP] in {
2645 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2646 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2647 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2650 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2651 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
2654 //===----------------------------------------------------------------------===//
2655 // Multiclass to define 'def Pats' for bit operations on the memory.
2656 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2657 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2658 //===----------------------------------------------------------------------===//
2660 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2661 PatLeaf extPred, ComplexPattern addrPred,
2662 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2664 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2665 let AddedComplexity = 250 in
2666 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2668 (add IntRegs:$base, extPred:$offset)),
2669 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2671 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2672 let AddedComplexity = 225 in
2673 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2675 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2676 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2679 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2681 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2682 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
2684 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2685 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
2686 // Half Word - clrbit
2687 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2688 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
2689 // Half Word - setbit
2690 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2691 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
2694 let Predicates = [HasV4T, UseMEMOP] in {
2695 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2696 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2697 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2698 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2699 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2701 // memw(Rs+#0) = [clrbit|setbit](#U5)
2702 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2703 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2704 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2705 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2706 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2709 //===----------------------------------------------------------------------===//
2710 // Multiclass to define 'def Pats' for ALU operations on the memory
2711 // where addend is a register.
2712 // mem[bhw](Rs+#0) [+-&|]= Rt
2713 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2714 //===----------------------------------------------------------------------===//
2716 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2717 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2718 let AddedComplexity = 141 in
2719 // mem[bhw](Rs+#0) [+-&|]= Rt
2720 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2721 (i32 IntRegs:$addend)),
2722 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2723 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2725 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2726 let AddedComplexity = 150 in
2727 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2728 (i32 IntRegs:$orend)),
2729 (add IntRegs:$base, extPred:$offset)),
2730 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2733 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2734 ComplexPattern addrPred, PatLeaf extPred,
2735 InstHexagon addMI, InstHexagon subMI,
2736 InstHexagon andMI, InstHexagon orMI > {
2738 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2739 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2740 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2741 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2744 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2746 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2747 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2748 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2750 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2751 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2752 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2755 // Define 'def Pats' for MemOps with register addend.
2756 let Predicates = [HasV4T, UseMEMOP] in {
2758 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2759 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2760 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2762 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2763 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2766 //===----------------------------------------------------------------------===//
2768 //===----------------------------------------------------------------------===//
2770 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2771 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2772 // hardware. However, compiler can still implement these patterns through
2773 // appropriate patterns combinations based on current implemented patterns.
2774 // The implemented patterns are: EQ/GT/GTU.
2775 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2777 // Following instruction is not being extended as it results into the
2778 // incorrect code for negative numbers.
2779 // Pd=cmpb.eq(Rs,#u8)
2781 let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0,
2782 validSubTargets = HasV4SubT in
2783 class CMP_NOT_REG_IMM<string OpName, bits<2> op, Operand ImmOp,
2785 : ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2),
2786 "$dst = !cmp."#OpName#"($src1, #$src2)",
2788 "", ALU32_2op_tc_2early_SLOT0123> {
2793 let IClass = 0b0111;
2794 let Inst{27-24} = 0b0101;
2795 let Inst{23-22} = op;
2796 let Inst{20-16} = src1;
2797 let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9});
2798 let Inst{13-5} = src2{8-0};
2799 let Inst{4-2} = 0b100;
2800 let Inst{1-0} = dst;
2803 let opExtentBits = 10, isExtentSigned = 1 in {
2804 def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst),
2805 (setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>;
2807 def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst),
2808 (not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>;
2811 let opExtentBits = 9 in
2812 def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
2813 (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
2818 let isCompare = 1, validSubTargets = HasV4SubT in
2819 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2820 (ins IntRegs:$src1, IntRegs:$src2),
2821 "$dst = !cmp.eq($src1, $src2)",
2822 [(set (i1 PredRegs:$dst),
2823 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2827 let isCompare = 1, validSubTargets = HasV4SubT in
2828 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2829 (ins IntRegs:$src1, IntRegs:$src2),
2830 "$dst = !cmp.gt($src1, $src2)",
2831 [(set (i1 PredRegs:$dst),
2832 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2836 // p=!cmp.gtu(r1,r2)
2837 let isCompare = 1, validSubTargets = HasV4SubT in
2838 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2839 (ins IntRegs:$src1, IntRegs:$src2),
2840 "$dst = !cmp.gtu($src1, $src2)",
2841 [(set (i1 PredRegs:$dst),
2842 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2845 let isCompare = 1, validSubTargets = HasV4SubT in
2846 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2847 (ins IntRegs:$src1, u8Imm:$src2),
2848 "$dst = cmpb.eq($src1, #$src2)",
2849 [(set (i1 PredRegs:$dst),
2850 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2853 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2855 (J2_jumpf (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2859 // Pd=cmpb.eq(Rs,Rt)
2860 let isCompare = 1, validSubTargets = HasV4SubT in
2861 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2862 (ins IntRegs:$src1, IntRegs:$src2),
2863 "$dst = cmpb.eq($src1, $src2)",
2864 [(set (i1 PredRegs:$dst),
2865 (seteq (and (xor (i32 IntRegs:$src1),
2866 (i32 IntRegs:$src2)), 255), 0))]>,
2869 // Pd=cmpb.eq(Rs,Rt)
2870 let isCompare = 1, validSubTargets = HasV4SubT in
2871 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2872 (ins IntRegs:$src1, IntRegs:$src2),
2873 "$dst = cmpb.eq($src1, $src2)",
2874 [(set (i1 PredRegs:$dst),
2875 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2876 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2879 // Pd=cmpb.gt(Rs,Rt)
2880 let isCompare = 1, validSubTargets = HasV4SubT in
2881 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2882 (ins IntRegs:$src1, IntRegs:$src2),
2883 "$dst = cmpb.gt($src1, $src2)",
2884 [(set (i1 PredRegs:$dst),
2885 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2886 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2889 // Pd=cmpb.gtu(Rs,#u7)
2890 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2891 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2892 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2893 (ins IntRegs:$src1, u7Ext:$src2),
2894 "$dst = cmpb.gtu($src1, #$src2)",
2895 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2896 u7ExtPred:$src2))]>,
2897 Requires<[HasV4T]>, ImmRegRel;
2899 // SDNode for converting immediate C to C-1.
2900 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2901 // Return the byte immediate const-1 as an SDNode.
2902 int32_t imm = N->getSExtValue();
2903 return XformU7ToU7M1Imm(imm);
2907 // zext( seteq ( and(Rs, 255), u8))
2909 // Pd=cmpb.eq(Rs, #u8)
2910 // if (Pd.new) Rd=#1
2911 // if (!Pd.new) Rd=#0
2912 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2914 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2920 // zext( setne ( and(Rs, 255), u8))
2922 // Pd=cmpb.eq(Rs, #u8)
2923 // if (Pd.new) Rd=#0
2924 // if (!Pd.new) Rd=#1
2925 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2927 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2933 // zext( seteq (Rs, and(Rt, 255)))
2935 // Pd=cmpb.eq(Rs, Rt)
2936 // if (Pd.new) Rd=#1
2937 // if (!Pd.new) Rd=#0
2938 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2939 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2940 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2941 (i32 IntRegs:$Rt))),
2946 // zext( setne (Rs, and(Rt, 255)))
2948 // Pd=cmpb.eq(Rs, Rt)
2949 // if (Pd.new) Rd=#0
2950 // if (!Pd.new) Rd=#1
2951 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2952 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2953 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2954 (i32 IntRegs:$Rt))),
2959 // zext( setugt ( and(Rs, 255), u8))
2961 // Pd=cmpb.gtu(Rs, #u8)
2962 // if (Pd.new) Rd=#1
2963 // if (!Pd.new) Rd=#0
2964 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2966 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2972 // zext( setugt ( and(Rs, 254), u8))
2974 // Pd=cmpb.gtu(Rs, #u8)
2975 // if (Pd.new) Rd=#1
2976 // if (!Pd.new) Rd=#0
2977 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2979 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2985 // zext( setult ( Rs, Rt))
2987 // Pd=cmp.ltu(Rs, Rt)
2988 // if (Pd.new) Rd=#1
2989 // if (!Pd.new) Rd=#0
2990 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2991 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2992 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2993 (i32 IntRegs:$Rs))),
2998 // zext( setlt ( Rs, Rt))
3000 // Pd=cmp.lt(Rs, Rt)
3001 // if (Pd.new) Rd=#1
3002 // if (!Pd.new) Rd=#0
3003 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3004 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3005 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
3006 (i32 IntRegs:$Rs))),
3011 // zext( setugt ( Rs, Rt))
3013 // Pd=cmp.gtu(Rs, Rt)
3014 // if (Pd.new) Rd=#1
3015 // if (!Pd.new) Rd=#0
3016 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3017 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
3018 (i32 IntRegs:$Rt))),
3022 // This pattern interefers with coremark performance, not implementing at this
3025 // zext( setgt ( Rs, Rt))
3027 // Pd=cmp.gt(Rs, Rt)
3028 // if (Pd.new) Rd=#1
3029 // if (!Pd.new) Rd=#0
3032 // zext( setuge ( Rs, Rt))
3034 // Pd=cmp.ltu(Rs, Rt)
3035 // if (Pd.new) Rd=#0
3036 // if (!Pd.new) Rd=#1
3037 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
3038 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3039 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
3040 (i32 IntRegs:$Rs))),
3045 // zext( setge ( Rs, Rt))
3047 // Pd=cmp.lt(Rs, Rt)
3048 // if (Pd.new) Rd=#0
3049 // if (!Pd.new) Rd=#1
3050 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3051 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3052 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
3053 (i32 IntRegs:$Rs))),
3058 // zext( setule ( Rs, Rt))
3060 // Pd=cmp.gtu(Rs, Rt)
3061 // if (Pd.new) Rd=#0
3062 // if (!Pd.new) Rd=#1
3063 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3064 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
3065 (i32 IntRegs:$Rt))),
3070 // zext( setle ( Rs, Rt))
3072 // Pd=cmp.gt(Rs, Rt)
3073 // if (Pd.new) Rd=#0
3074 // if (!Pd.new) Rd=#1
3075 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3076 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
3077 (i32 IntRegs:$Rt))),
3082 // zext( setult ( and(Rs, 255), u8))
3083 // Use the isdigit transformation below
3085 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
3086 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3087 // The isdigit transformation relies on two 'clever' aspects:
3088 // 1) The data type is unsigned which allows us to eliminate a zero test after
3089 // biasing the expression by 48. We are depending on the representation of
3090 // the unsigned types, and semantics.
3091 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3094 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3095 // The code is transformed upstream of llvm into
3096 // retval = (c-48) < 10 ? 1 : 0;
3097 let AddedComplexity = 139 in
3098 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3099 u7StrictPosImmPred:$src2)))),
3100 (i32 (C2_muxii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
3101 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
3105 // Pd=cmpb.gtu(Rs,Rt)
3106 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
3107 InputType = "reg" in
3108 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
3109 (ins IntRegs:$src1, IntRegs:$src2),
3110 "$dst = cmpb.gtu($src1, $src2)",
3111 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
3112 (and (i32 IntRegs:$src2), 255)))]>,
3113 Requires<[HasV4T]>, ImmRegRel;
3115 // Following instruction is not being extended as it results into the incorrect
3116 // code for negative numbers.
3118 // Signed half compare(.eq) ri.
3119 // Pd=cmph.eq(Rs,#s8)
3120 let isCompare = 1, validSubTargets = HasV4SubT in
3121 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
3122 (ins IntRegs:$src1, s8Imm:$src2),
3123 "$dst = cmph.eq($src1, #$src2)",
3124 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
3125 s8ImmPred:$src2))]>,
3128 // Signed half compare(.eq) rr.
3129 // Case 1: xor + and, then compare:
3131 // r0=and(r0,#0xffff)
3133 // Pd=cmph.eq(Rs,Rt)
3134 let isCompare = 1, validSubTargets = HasV4SubT in
3135 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
3136 (ins IntRegs:$src1, IntRegs:$src2),
3137 "$dst = cmph.eq($src1, $src2)",
3138 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
3139 (i32 IntRegs:$src2)),
3143 // Signed half compare(.eq) rr.
3144 // Case 2: shift left 16 bits then compare:
3148 // Pd=cmph.eq(Rs,Rt)
3149 let isCompare = 1, validSubTargets = HasV4SubT in
3150 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
3151 (ins IntRegs:$src1, IntRegs:$src2),
3152 "$dst = cmph.eq($src1, $src2)",
3153 [(set (i1 PredRegs:$dst),
3154 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
3155 (shl (i32 IntRegs:$src2), (i32 16))))]>,
3158 /* Incorrect Pattern -- immediate should be right shifted before being
3159 used in the cmph.gt instruction.
3160 // Signed half compare(.gt) ri.
3161 // Pd=cmph.gt(Rs,#s8)
3163 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
3164 isCompare = 1, validSubTargets = HasV4SubT in
3165 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
3166 (ins IntRegs:$src1, s8Ext:$src2),
3167 "$dst = cmph.gt($src1, #$src2)",
3168 [(set (i1 PredRegs:$dst),
3169 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3170 s8ExtPred:$src2))]>,
3174 // Signed half compare(.gt) rr.
3175 // Pd=cmph.gt(Rs,Rt)
3176 let isCompare = 1, validSubTargets = HasV4SubT in
3177 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
3178 (ins IntRegs:$src1, IntRegs:$src2),
3179 "$dst = cmph.gt($src1, $src2)",
3180 [(set (i1 PredRegs:$dst),
3181 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3182 (shl (i32 IntRegs:$src2), (i32 16))))]>,
3185 // Unsigned half compare rr (.gtu).
3186 // Pd=cmph.gtu(Rs,Rt)
3187 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
3188 InputType = "reg" in
3189 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
3190 (ins IntRegs:$src1, IntRegs:$src2),
3191 "$dst = cmph.gtu($src1, $src2)",
3192 [(set (i1 PredRegs:$dst),
3193 (setugt (and (i32 IntRegs:$src1), 65535),
3194 (and (i32 IntRegs:$src2), 65535)))]>,
3195 Requires<[HasV4T]>, ImmRegRel;
3197 // Unsigned half compare ri (.gtu).
3198 // Pd=cmph.gtu(Rs,#u7)
3199 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
3200 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
3201 InputType = "imm" in
3202 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
3203 (ins IntRegs:$src1, u7Ext:$src2),
3204 "$dst = cmph.gtu($src1, #$src2)",
3205 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
3206 u7ExtPred:$src2))]>,
3207 Requires<[HasV4T]>, ImmRegRel;
3209 let validSubTargets = HasV4SubT in
3210 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3211 "$dst = !tstbit($src1, $src2)",
3212 [(set (i1 PredRegs:$dst),
3213 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
3216 let validSubTargets = HasV4SubT in
3217 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
3218 "$dst = !tstbit($src1, $src2)",
3219 [(set (i1 PredRegs:$dst),
3220 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
3223 //===----------------------------------------------------------------------===//
3225 //===----------------------------------------------------------------------===//
3227 //Deallocate frame and return.
3229 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
3230 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in {
3231 let validSubTargets = HasV4SubT in
3232 def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
3238 // Restore registers and dealloc return function call.
3239 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3240 Defs = [R29, R30, R31, PC] in {
3241 let validSubTargets = HasV4SubT in
3242 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
3243 (ins calltarget:$dst),
3249 // Restore registers and dealloc frame before a tail call.
3250 let isCall = 1, isBarrier = 1,
3251 Defs = [R29, R30, R31, PC] in {
3252 let validSubTargets = HasV4SubT in
3253 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3254 (ins calltarget:$dst),
3260 // Save registers function call.
3261 let isCall = 1, isBarrier = 1,
3262 Uses = [R29, R31] in {
3263 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3264 (ins calltarget:$dst),
3265 "call $dst // Save_calle_saved_registers",
3270 // if (Ps) dealloc_return
3271 let isReturn = 1, isTerminator = 1,
3272 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3273 isPredicated = 1 in {
3274 let validSubTargets = HasV4SubT in
3275 def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
3276 (ins PredRegs:$src1),
3277 "if ($src1) dealloc_return",
3282 // if (!Ps) dealloc_return
3283 let isReturn = 1, isTerminator = 1,
3284 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3285 isPredicated = 1, isPredicatedFalse = 1 in {
3286 let validSubTargets = HasV4SubT in
3287 def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3288 "if (!$src1) dealloc_return",
3293 // if (Ps.new) dealloc_return:nt
3294 let isReturn = 1, isTerminator = 1,
3295 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3296 isPredicated = 1 in {
3297 let validSubTargets = HasV4SubT in
3298 def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3299 "if ($src1.new) dealloc_return:nt",
3304 // if (!Ps.new) dealloc_return:nt
3305 let isReturn = 1, isTerminator = 1,
3306 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3307 isPredicated = 1, isPredicatedFalse = 1 in {
3308 let validSubTargets = HasV4SubT in
3309 def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3310 "if (!$src1.new) dealloc_return:nt",
3315 // if (Ps.new) dealloc_return:t
3316 let isReturn = 1, isTerminator = 1,
3317 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3318 isPredicated = 1 in {
3319 let validSubTargets = HasV4SubT in
3320 def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3321 "if ($src1.new) dealloc_return:t",
3326 // if (!Ps.new) dealloc_return:nt
3327 let isReturn = 1, isTerminator = 1,
3328 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3329 isPredicated = 1, isPredicatedFalse = 1 in {
3330 let validSubTargets = HasV4SubT in
3331 def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3332 "if (!$src1.new) dealloc_return:t",
3337 // Load/Store with absolute addressing mode
3340 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3342 let isPredicatedNew = isPredNew in
3343 def NAME#_V4 : STInst2<(outs),
3344 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3345 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3346 ") ")#mnemonic#"(##$absaddr) = $src2",
3351 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3352 let isPredicatedFalse = PredNot in {
3353 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3355 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3359 let isNVStorable = 1, isExtended = 1, hasSideEffects = 0 in
3360 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3361 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3362 let opExtendable = 0, isPredicable = 1 in
3363 def NAME#_V4 : STInst2<(outs),
3364 (ins u0AlwaysExt:$absaddr, RC:$src),
3365 mnemonic#"(##$absaddr) = $src",
3369 let opExtendable = 1, isPredicated = 1 in {
3370 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
3371 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
3376 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
3378 let isPredicatedNew = isPredNew in
3379 def NAME#_nv_V4 : NVInst_V4<(outs),
3380 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3381 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3382 ") ")#mnemonic#"(##$absaddr) = $src2.new",
3387 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
3388 let isPredicatedFalse = PredNot in {
3389 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
3391 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
3395 let mayStore = 1, isNVStore = 1, isExtended = 1, hasSideEffects = 0 in
3396 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
3397 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3398 let opExtendable = 0, isPredicable = 1 in
3399 def NAME#_nv_V4 : NVInst_V4<(outs),
3400 (ins u0AlwaysExt:$absaddr, RC:$src),
3401 mnemonic#"(##$absaddr) = $src.new",
3405 let opExtendable = 1, isPredicated = 1 in {
3406 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3407 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3412 let addrMode = Absolute in {
3413 let accessSize = ByteAccess in
3414 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
3415 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
3417 let accessSize = HalfWordAccess in
3418 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
3419 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
3421 let accessSize = WordAccess in
3422 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
3423 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
3425 let accessSize = DoubleWordAccess, isNVStorable = 0 in
3426 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
3429 let Predicates = [HasV4T], AddedComplexity = 30 in {
3430 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3431 (HexagonCONST32 tglobaladdr:$absaddr)),
3432 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3434 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3435 (HexagonCONST32 tglobaladdr:$absaddr)),
3436 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3438 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3439 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3441 def : Pat<(store (i64 DoubleRegs:$src1),
3442 (HexagonCONST32 tglobaladdr:$absaddr)),
3443 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3446 //===----------------------------------------------------------------------===//
3447 // multiclass for store instructions with GP-relative addressing mode.
3448 // mem[bhwd](#global)=Rt
3449 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
3450 //===----------------------------------------------------------------------===//
3451 let mayStore = 1, isNVStorable = 1 in
3452 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3453 let BaseOpcode = BaseOp, isPredicable = 1 in
3454 def NAME#_V4 : STInst2<(outs),
3455 (ins globaladdress:$global, RC:$src),
3456 mnemonic#"(#$global) = $src",
3459 // When GP-relative instructions are predicated, their addressing mode is
3460 // changed to absolute and they are always constant extended.
3461 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3462 isPredicated = 1 in {
3463 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
3464 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
3468 let mayStore = 1, isNVStore = 1 in
3469 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
3470 let BaseOpcode = BaseOp, isPredicable = 1 in
3471 def NAME#_nv_V4 : NVInst_V4<(outs),
3472 (ins u0AlwaysExt:$global, RC:$src),
3473 mnemonic#"(#$global) = $src.new",
3477 // When GP-relative instructions are predicated, their addressing mode is
3478 // changed to absolute and they are always constant extended.
3479 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3480 isPredicated = 1 in {
3481 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3482 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3486 let validSubTargets = HasV4SubT, hasSideEffects = 0 in {
3487 let isNVStorable = 0 in
3488 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
3490 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
3491 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel;
3492 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
3493 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel;
3494 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
3495 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel;
3498 // 64 bit atomic store
3499 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3500 (i64 DoubleRegs:$src1)),
3501 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3504 // Map from store(globaladdress) -> memd(#foo)
3505 let AddedComplexity = 100 in
3506 def : Pat <(store (i64 DoubleRegs:$src1),
3507 (HexagonCONST32_GP tglobaladdr:$global)),
3508 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3510 // 8 bit atomic store
3511 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3512 (i32 IntRegs:$src1)),
3513 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3515 // Map from store(globaladdress) -> memb(#foo)
3516 let AddedComplexity = 100 in
3517 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3518 (HexagonCONST32_GP tglobaladdr:$global)),
3519 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3521 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3522 // to "r0 = 1; memw(#foo) = r0"
3523 let AddedComplexity = 100 in
3524 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3525 (STb_GP_V4 tglobaladdr:$global, (A2_tfrsi 1))>;
3527 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3528 (i32 IntRegs:$src1)),
3529 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3531 // Map from store(globaladdress) -> memh(#foo)
3532 let AddedComplexity = 100 in
3533 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3534 (HexagonCONST32_GP tglobaladdr:$global)),
3535 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3537 // 32 bit atomic store
3538 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3539 (i32 IntRegs:$src1)),
3540 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3542 // Map from store(globaladdress) -> memw(#foo)
3543 let AddedComplexity = 100 in
3544 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3545 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3547 //===----------------------------------------------------------------------===//
3548 // Multiclass for the load instructions with absolute addressing mode.
3549 //===----------------------------------------------------------------------===//
3550 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3552 let isPredicatedNew = isPredNew in
3553 def NAME : LDInst2<(outs RC:$dst),
3554 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
3555 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3556 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
3561 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3562 let isPredicatedFalse = PredNot in {
3563 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3565 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3569 let isExtended = 1, hasSideEffects = 0 in
3570 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3571 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3572 let opExtendable = 1, isPredicable = 1 in
3573 def NAME#_V4 : LDInst2<(outs RC:$dst),
3574 (ins u0AlwaysExt:$absaddr),
3575 "$dst = "#mnemonic#"(##$absaddr)",
3579 let opExtendable = 2, isPredicated = 1 in {
3580 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3581 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3586 let addrMode = Absolute in {
3587 let accessSize = ByteAccess in {
3588 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
3589 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
3591 let accessSize = HalfWordAccess in {
3592 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
3593 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
3595 let accessSize = WordAccess in
3596 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
3598 let accessSize = DoubleWordAccess in
3599 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
3602 let Predicates = [HasV4T], AddedComplexity = 30 in {
3603 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3604 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
3606 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3607 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
3609 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3610 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
3612 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3613 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
3615 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3616 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
3619 //===----------------------------------------------------------------------===//
3620 // multiclass for load instructions with GP-relative addressing mode.
3621 // Rx=mem[bhwd](##global)
3622 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3623 //===----------------------------------------------------------------------===//
3624 let hasSideEffects = 0, validSubTargets = HasV4SubT in
3625 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3626 let BaseOpcode = BaseOp in {
3627 let isPredicable = 1 in
3628 def NAME#_V4 : LDInst2<(outs RC:$dst),
3629 (ins globaladdress:$global),
3630 "$dst = "#mnemonic#"(#$global)",
3633 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
3634 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3635 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3640 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel;
3641 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel;
3642 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel;
3643 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel;
3644 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel;
3645 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel;
3647 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3648 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3650 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3651 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3653 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3654 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3656 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3657 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3659 // Map from load(globaladdress) -> memw(#foo + 0)
3660 let AddedComplexity = 100 in
3661 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3662 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3664 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3665 let AddedComplexity = 100 in
3666 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3667 (i1 (C2_tfrrp (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
3669 // When the Interprocedural Global Variable optimizer realizes that a certain
3670 // global variable takes only two constant values, it shrinks the global to
3671 // a boolean. Catch those loads here in the following 3 patterns.
3672 let AddedComplexity = 100 in
3673 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3674 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3676 let AddedComplexity = 100 in
3677 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3678 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3680 // Map from load(globaladdress) -> memb(#foo)
3681 let AddedComplexity = 100 in
3682 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3683 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3685 // Map from load(globaladdress) -> memb(#foo)
3686 let AddedComplexity = 100 in
3687 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3688 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3690 let AddedComplexity = 100 in
3691 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3692 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3694 // Map from load(globaladdress) -> memub(#foo)
3695 let AddedComplexity = 100 in
3696 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3697 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3699 // Map from load(globaladdress) -> memh(#foo)
3700 let AddedComplexity = 100 in
3701 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3702 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3704 // Map from load(globaladdress) -> memh(#foo)
3705 let AddedComplexity = 100 in
3706 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3707 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3709 // Map from load(globaladdress) -> memuh(#foo)
3710 let AddedComplexity = 100 in
3711 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3712 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3714 // Map from load(globaladdress) -> memw(#foo)
3715 let AddedComplexity = 100 in
3716 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3717 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3720 // Transfer global address into a register
3721 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3722 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3723 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3725 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3728 // Transfer a block address into a register
3729 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3730 (TFRI_V4 tblockaddress:$src1)>,
3733 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3734 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3735 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3736 (ins PredRegs:$src1, s16Ext:$src2),
3737 "if($src1) $dst = #$src2",
3741 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3742 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3743 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3744 (ins PredRegs:$src1, s16Ext:$src2),
3745 "if(!$src1) $dst = #$src2",
3749 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3750 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3751 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3752 (ins PredRegs:$src1, s16Ext:$src2),
3753 "if($src1.new) $dst = #$src2",
3757 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3758 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3759 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3760 (ins PredRegs:$src1, s16Ext:$src2),
3761 "if(!$src1.new) $dst = #$src2",
3765 let AddedComplexity = 50, Predicates = [HasV4T] in
3766 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3767 (TFRI_V4 tglobaladdr:$src1)>,
3771 // Load - Indirect with long offset: These instructions take global address
3773 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3774 validSubTargets = HasV4SubT in
3775 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3776 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3777 "$dst=memd($src1<<#$src2+##$offset)",
3778 [(set (i64 DoubleRegs:$dst),
3779 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3780 (HexagonCONST32 tglobaladdr:$offset))))]>,
3783 let AddedComplexity = 40 in
3784 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3785 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3786 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3787 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3788 !strconcat("$dst = ",
3789 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3791 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3792 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3796 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3797 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3798 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3799 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3800 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3801 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3802 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3804 let AddedComplexity = 40 in
3805 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3806 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3807 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3810 let AddedComplexity = 40 in
3811 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3812 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3813 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3816 let Predicates = [HasV4T], AddedComplexity = 30 in {
3817 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3818 (STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3820 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3821 (STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3823 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3824 (STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3827 let Predicates = [HasV4T], AddedComplexity = 30 in {
3828 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3829 (LDriw_abs_V4 u0AlwaysExtPred:$src)>;
3831 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3832 (LDrib_abs_V4 u0AlwaysExtPred:$src)>;
3834 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3835 (LDriub_abs_V4 u0AlwaysExtPred:$src)>;
3837 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3838 (LDrih_abs_V4 u0AlwaysExtPred:$src)>;
3840 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3841 (LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
3844 // Indexed store word - global address.
3845 // memw(Rs+#u6:2)=#S8
3846 let AddedComplexity = 10 in
3847 def STriw_offset_ext_V4 : STInst<(outs),
3848 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3849 "memw($src1+#$src2) = ##$src3",
3850 [(store (HexagonCONST32 tglobaladdr:$src3),
3851 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3854 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3855 (i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
3858 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3859 (i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
3864 // We need a complexity of 120 here to override preceding handling of
3866 let Predicates = [HasV4T], AddedComplexity = 120 in {
3867 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3868 (i64 (A4_combineir 0, (LDrib_abs_V4 tglobaladdr:$addr)))>;
3870 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3871 (i64 (A4_combineir 0, (LDriub_abs_V4 tglobaladdr:$addr)))>;
3873 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3874 (i64 (A2_sxtw (LDrib_abs_V4 tglobaladdr:$addr)))>;
3876 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3877 (i64 (A4_combineir 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3879 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3880 (i64 (A4_combineir 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>;
3882 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3883 (i64 (A2_sxtw (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3886 // We need a complexity of 120 here to override preceding handling of
3888 let AddedComplexity = 120 in {
3889 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3890 (i64 (A4_combineir 0, (LDrih_abs_V4 tglobaladdr:$addr)))>,
3893 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3894 (i64 (A4_combineir 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>,
3897 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3898 (i64 (A2_sxtw (LDrih_abs_V4 tglobaladdr:$addr)))>,
3901 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3902 (i64 (A4_combineir 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3905 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3906 (i64 (A4_combineir 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>,
3909 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3910 (i64 (A2_sxtw (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3914 // We need a complexity of 120 here to override preceding handling of
3916 let AddedComplexity = 120 in {
3917 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3918 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3921 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3922 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3925 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3926 (i64 (A2_sxtw (LDriw_abs_V4 tglobaladdr:$addr)))>,
3929 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3930 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3933 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3934 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3937 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3938 (i64 (A2_sxtw (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3942 // Indexed store double word - global address.
3943 // memw(Rs+#u6:2)=#S8
3944 let AddedComplexity = 10 in
3945 def STrih_offset_ext_V4 : STInst<(outs),
3946 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3947 "memh($src1+#$src2) = ##$src3",
3948 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3949 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3951 // Map from store(globaladdress + x) -> memd(#foo + x)
3952 let AddedComplexity = 100 in
3953 def : Pat<(store (i64 DoubleRegs:$src1),
3954 FoldGlobalAddrGP:$addr),
3955 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3958 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3959 (i64 DoubleRegs:$src1)),
3960 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3963 // Map from store(globaladdress + x) -> memb(#foo + x)
3964 let AddedComplexity = 100 in
3965 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3966 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3969 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3970 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3973 // Map from store(globaladdress + x) -> memh(#foo + x)
3974 let AddedComplexity = 100 in
3975 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3976 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3979 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3980 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3983 // Map from store(globaladdress + x) -> memw(#foo + x)
3984 let AddedComplexity = 100 in
3985 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3986 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3989 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3990 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3993 // Map from load(globaladdress + x) -> memd(#foo + x)
3994 let AddedComplexity = 100 in
3995 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3996 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3999 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
4000 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
4003 // Map from load(globaladdress + x) -> memb(#foo + x)
4004 let AddedComplexity = 100 in
4005 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
4006 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
4009 // Map from load(globaladdress + x) -> memb(#foo + x)
4010 let AddedComplexity = 100 in
4011 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
4012 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
4015 //let AddedComplexity = 100 in
4016 let AddedComplexity = 100 in
4017 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
4018 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
4021 // Map from load(globaladdress + x) -> memh(#foo + x)
4022 let AddedComplexity = 100 in
4023 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
4024 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
4027 // Map from load(globaladdress + x) -> memuh(#foo + x)
4028 let AddedComplexity = 100 in
4029 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
4030 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
4033 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
4034 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
4037 // Map from load(globaladdress + x) -> memub(#foo + x)
4038 let AddedComplexity = 100 in
4039 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
4040 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
4043 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
4044 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
4047 // Map from load(globaladdress + x) -> memw(#foo + x)
4048 let AddedComplexity = 100 in
4049 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
4050 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
4053 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
4054 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,