1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in
15 class T_Immext<dag ins> :
16 EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
20 def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
21 def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
22 def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
24 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
25 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
27 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
28 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
30 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
31 (HexagonCONST32 node:$addr), [{
32 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
35 // Hexagon V4 Architecture spec defines 8 instruction classes:
36 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
40 // ========================================
41 // Loads (8/16/32/64 bit)
45 // ========================================
46 // Stores (8/16/32/64 bit)
49 // ALU32 Instructions:
50 // ========================================
51 // Arithmetic / Logical (32 bit)
54 // XTYPE Instructions (32/64 bit):
55 // ========================================
56 // Arithmetic, Logical, Bit Manipulation
57 // Multiply (Integer, Fractional, Complex)
58 // Permute / Vector Permute Operations
59 // Predicate Operations
60 // Shift / Shift with Add/Sub/Logical
62 // Vector Halfword (ALU, Shift, Multiply)
63 // Vector Word (ALU, Shift)
66 // ========================================
67 // Jump/Call PC-relative
70 // ========================================
73 // MEMOP Instructions:
74 // ========================================
75 // Operation on memory (8/16/32 bit)
78 // ========================================
83 // ========================================
84 // Control-Register Transfers
85 // Hardware Loop Setup
86 // Predicate Logicals & Reductions
88 // SYSTEM Instructions (not implemented in the compiler):
89 // ========================================
95 //===----------------------------------------------------------------------===//
97 //===----------------------------------------------------------------------===//
98 // Generate frame index addresses.
99 let neverHasSideEffects = 1, isReMaterializable = 1,
100 isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
101 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
102 (ins IntRegs:$src1, s32Imm:$offset),
103 "$dst = add($src1, ##$offset)",
108 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
109 isExtentSigned = 1, opExtentBits = 8 in
110 def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
111 (ins IntRegs:$Rs, s8Ext:$s8),
112 "$Rd = cmp.eq($Rs, #$s8)",
113 [(set (i32 IntRegs:$Rd),
114 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
115 s8ExtPred:$s8)))))]>,
118 // Preserve the TSTBIT generation
119 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
120 (i32 IntRegs:$src1))), 0)))),
121 (i32 (MUX_ii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
124 // Interfered with tstbit generation, above pattern preserves, see : tstbit.ll
126 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
127 isExtentSigned = 1, opExtentBits = 8 in
128 def V4_A4_rcmpneqi : ALU32_ri<(outs IntRegs:$Rd),
129 (ins IntRegs:$Rs, s8Ext:$s8),
130 "$Rd = !cmp.eq($Rs, #$s8)",
131 [(set (i32 IntRegs:$Rd),
132 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
133 s8ExtPred:$s8)))))]>,
137 let validSubTargets = HasV4SubT in
138 def V4_A4_rcmpeq : ALU32_ri<(outs IntRegs:$Rd),
139 (ins IntRegs:$Rs, IntRegs:$Rt),
140 "$Rd = cmp.eq($Rs, $Rt)",
141 [(set (i32 IntRegs:$Rd),
142 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
147 let validSubTargets = HasV4SubT in
148 def V4_A4_rcmpneq : ALU32_ri<(outs IntRegs:$Rd),
149 (ins IntRegs:$Rs, IntRegs:$Rt),
150 "$Rd = !cmp.eq($Rs, $Rt)",
151 [(set (i32 IntRegs:$Rd),
152 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
156 //===----------------------------------------------------------------------===//
158 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
163 //===----------------------------------------------------------------------===//
166 // Rdd=combine(Rs, #s8)
167 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
168 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
169 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
170 (ins IntRegs:$src1, s8Ext:$src2),
171 "$dst = combine($src1, #$src2)",
175 // Rdd=combine(#s8, Rs)
176 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
177 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
178 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
179 (ins s8Ext:$src1, IntRegs:$src2),
180 "$dst = combine(#$src1, $src2)",
184 def HexagonWrapperCombineRI_V4 :
185 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
186 def HexagonWrapperCombineIR_V4 :
187 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
189 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
190 (COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>,
193 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
194 (COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>,
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
198 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
199 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
200 (ins s8Imm:$src1, u6Ext:$src2),
201 "$dst = combine(#$src1, #$src2)",
205 //===----------------------------------------------------------------------===//
207 //===----------------------------------------------------------------------===//
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
213 // These absolute set addressing mode instructions accept immediate as
214 // an operand. We have duplicated these patterns to take global address.
216 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
217 validSubTargets = HasV4SubT in {
218 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
219 (ins u0AlwaysExt:$addr),
220 "$dst1 = memd($dst2=##$addr)",
225 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
226 (ins u0AlwaysExt:$addr),
227 "$dst1 = memb($dst2=##$addr)",
232 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
233 (ins u0AlwaysExt:$addr),
234 "$dst1 = memh($dst2=##$addr)",
239 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
240 (ins u0AlwaysExt:$addr),
241 "$dst1 = memub($dst2=##$addr)",
246 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
247 (ins u0AlwaysExt:$addr),
248 "$dst1 = memuh($dst2=##$addr)",
253 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
254 (ins u0AlwaysExt:$addr),
255 "$dst1 = memw($dst2=##$addr)",
260 // Following patterns are defined for absolute set addressing mode
261 // instruction which take global address as operand.
262 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
263 validSubTargets = HasV4SubT in {
264 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
265 (ins globaladdressExt:$addr),
266 "$dst1 = memd($dst2=##$addr)",
271 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
272 (ins globaladdressExt:$addr),
273 "$dst1 = memb($dst2=##$addr)",
278 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
279 (ins globaladdressExt:$addr),
280 "$dst1 = memh($dst2=##$addr)",
285 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
286 (ins globaladdressExt:$addr),
287 "$dst1 = memub($dst2=##$addr)",
292 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
293 (ins globaladdressExt:$addr),
294 "$dst1 = memuh($dst2=##$addr)",
299 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
300 (ins globaladdressExt:$addr),
301 "$dst1 = memw($dst2=##$addr)",
306 // multiclass for load instructions with base + register offset
308 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
310 let isPredicatedNew = isPredNew in
311 def NAME : LDInst2<(outs RC:$dst),
312 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
313 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
314 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
315 []>, Requires<[HasV4T]>;
318 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
319 let isPredicatedFalse = PredNot in {
320 defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
322 defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
326 let neverHasSideEffects = 1 in
327 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
328 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
329 let isPredicable = 1 in
330 def NAME#_V4 : LDInst2<(outs RC:$dst),
331 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
332 "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
333 []>, Requires<[HasV4T]>;
335 let isPredicated = 1 in {
336 defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
337 defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
342 let addrMode = BaseRegOffset in {
343 defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
344 defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
345 defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
346 defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
347 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
348 defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
351 // 'def pats' for load instructions with base + register offset and non-zero
352 // immediate value. Immediate value is used to left-shift the second
354 let AddedComplexity = 40 in {
355 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
356 (shl IntRegs:$src2, u2ImmPred:$offset)))),
357 (LDrib_indexed_shl_V4 IntRegs:$src1,
358 IntRegs:$src2, u2ImmPred:$offset)>,
361 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
362 (shl IntRegs:$src2, u2ImmPred:$offset)))),
363 (LDriub_indexed_shl_V4 IntRegs:$src1,
364 IntRegs:$src2, u2ImmPred:$offset)>,
367 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
368 (shl IntRegs:$src2, u2ImmPred:$offset)))),
369 (LDriub_indexed_shl_V4 IntRegs:$src1,
370 IntRegs:$src2, u2ImmPred:$offset)>,
373 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
374 (shl IntRegs:$src2, u2ImmPred:$offset)))),
375 (LDrih_indexed_shl_V4 IntRegs:$src1,
376 IntRegs:$src2, u2ImmPred:$offset)>,
379 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
380 (shl IntRegs:$src2, u2ImmPred:$offset)))),
381 (LDriuh_indexed_shl_V4 IntRegs:$src1,
382 IntRegs:$src2, u2ImmPred:$offset)>,
385 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
386 (shl IntRegs:$src2, u2ImmPred:$offset)))),
387 (LDriuh_indexed_shl_V4 IntRegs:$src1,
388 IntRegs:$src2, u2ImmPred:$offset)>,
391 def : Pat <(i32 (load (add IntRegs:$src1,
392 (shl IntRegs:$src2, u2ImmPred:$offset)))),
393 (LDriw_indexed_shl_V4 IntRegs:$src1,
394 IntRegs:$src2, u2ImmPred:$offset)>,
397 def : Pat <(i64 (load (add IntRegs:$src1,
398 (shl IntRegs:$src2, u2ImmPred:$offset)))),
399 (LDrid_indexed_shl_V4 IntRegs:$src1,
400 IntRegs:$src2, u2ImmPred:$offset)>,
405 // 'def pats' for load instruction base + register offset and
406 // zero immediate value.
407 let AddedComplexity = 10 in {
408 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
409 (LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
412 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
413 (LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
416 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
417 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
420 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
421 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
424 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
425 (LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
428 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
429 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
432 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
433 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
436 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
437 (LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
442 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
443 (i64 (COMBINE_Ir_V4 0, (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
447 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
448 (i64 (COMBINE_Ir_V4 0, (i32 IntRegs:$src1)))>,
451 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
452 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
455 let AddedComplexity = 20 in
456 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
457 s11_0ExtPred:$offset))),
458 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
459 s11_0ExtPred:$offset)))>,
463 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
464 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
467 let AddedComplexity = 20 in
468 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
469 s11_0ExtPred:$offset))),
470 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
471 s11_0ExtPred:$offset)))>,
475 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
476 (i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>,
479 let AddedComplexity = 20 in
480 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
481 s11_1ExtPred:$offset))),
482 (i64 (COMBINE_Ir_V4 0, (LDriuh_indexed IntRegs:$src1,
483 s11_1ExtPred:$offset)))>,
487 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
488 (i64 (COMBINE_Ir_V4 0, (LDrih ADDRriS11_2:$src1)))>,
491 let AddedComplexity = 20 in
492 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
493 s11_1ExtPred:$offset))),
494 (i64 (COMBINE_Ir_V4 0, (LDrih_indexed IntRegs:$src1,
495 s11_1ExtPred:$offset)))>,
499 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
500 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
503 let AddedComplexity = 100 in
504 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
505 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
506 s11_2ExtPred:$offset)))>,
510 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
511 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
514 let AddedComplexity = 100 in
515 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
516 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
517 s11_2ExtPred:$offset)))>,
522 //===----------------------------------------------------------------------===//
524 //===----------------------------------------------------------------------===//
526 //===----------------------------------------------------------------------===//
528 //===----------------------------------------------------------------------===//
530 /// Assumptions::: ****** DO NOT IGNORE ********
531 /// 1. Make sure that in post increment store, the zero'th operand is always the
532 /// post increment operand.
533 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
538 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
539 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
540 (ins DoubleRegs:$src1, u0AlwaysExt:$src2),
541 "memd($dst1=##$src2) = $src1",
546 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
547 (ins IntRegs:$src1, u0AlwaysExt:$src2),
548 "memb($dst1=##$src2) = $src1",
553 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
554 (ins IntRegs:$src1, u0AlwaysExt:$src2),
555 "memh($dst1=##$src2) = $src1",
560 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
561 (ins IntRegs:$src1, u0AlwaysExt:$src2),
562 "memw($dst1=##$src2) = $src1",
568 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
569 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
570 (ins DoubleRegs:$src1, globaladdressExt:$src2),
571 "memd($dst1=##$src2) = $src1",
576 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
577 (ins IntRegs:$src1, globaladdressExt:$src2),
578 "memb($dst1=##$src2) = $src1",
583 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
584 (ins IntRegs:$src1, globaladdressExt:$src2),
585 "memh($dst1=##$src2) = $src1",
590 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
591 (ins IntRegs:$src1, globaladdressExt:$src2),
592 "memw($dst1=##$src2) = $src1",
597 // multiclass for store instructions with base + register offset addressing
599 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
601 let isPredicatedNew = isPredNew in
602 def NAME : STInst2<(outs),
603 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
605 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
606 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
611 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
612 let isPredicatedFalse = PredNot in {
613 defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
615 defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
619 let isNVStorable = 1 in
620 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
621 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
622 let isPredicable = 1 in
623 def NAME#_V4 : STInst2<(outs),
624 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
625 mnemonic#"($src1+$src2<<#$src3) = $src4",
629 let isPredicated = 1 in {
630 defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
631 defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
636 // multiclass for new-value store instructions with base + register offset
638 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
640 let isPredicatedNew = isPredNew in
641 def NAME#_nv_V4 : NVInst_V4<(outs),
642 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
644 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
645 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
650 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
651 let isPredicatedFalse = PredNot in {
652 defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
654 defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
658 let mayStore = 1, isNVStore = 1 in
659 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
660 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
661 let isPredicable = 1 in
662 def NAME#_nv_V4 : NVInst_V4<(outs),
663 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
664 mnemonic#"($src1+$src2<<#$src3) = $src4.new",
668 let isPredicated = 1 in {
669 defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
670 defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
675 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
676 validSubTargets = HasV4SubT in {
677 defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
678 ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
680 defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
681 ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
683 defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
684 ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
686 let isNVStorable = 0 in
687 defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
690 let Predicates = [HasV4T], AddedComplexity = 10 in {
691 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
692 (add IntRegs:$src1, (shl IntRegs:$src2,
694 (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
695 u2ImmPred:$src3, IntRegs:$src4)>;
697 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
698 (add IntRegs:$src1, (shl IntRegs:$src2,
700 (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
701 u2ImmPred:$src3, IntRegs:$src4)>;
703 def : Pat<(store (i32 IntRegs:$src4),
704 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
705 (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
706 u2ImmPred:$src3, IntRegs:$src4)>;
708 def : Pat<(store (i64 DoubleRegs:$src4),
709 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
710 (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
711 u2ImmPred:$src3, DoubleRegs:$src4)>;
714 // memd(Ru<<#u2+#U6)=Rtt
715 let isExtended = 1, opExtendable = 2, AddedComplexity = 10,
716 validSubTargets = HasV4SubT in
717 def STrid_shl_V4 : STInst<(outs),
718 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, DoubleRegs:$src4),
719 "memd($src1<<#$src2+#$src3) = $src4",
720 [(store (i64 DoubleRegs:$src4),
721 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
722 u0AlwaysExtPred:$src3))]>,
725 // memd(Rx++#s4:3)=Rtt
726 // memd(Rx++#s4:3:circ(Mu))=Rtt
727 // memd(Rx++I:circ(Mu))=Rtt
729 // memd(Rx++Mu:brev)=Rtt
730 // memd(gp+#u16:3)=Rtt
732 // Store doubleword conditionally.
733 // if ([!]Pv[.new]) memd(#u6)=Rtt
734 // TODO: needs to be implemented.
736 //===----------------------------------------------------------------------===//
737 // multiclass for store instructions with base + immediate offset
738 // addressing mode and immediate stored value.
739 // mem[bhw](Rx++#s4:3)=#s8
740 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
741 //===----------------------------------------------------------------------===//
742 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
744 let isPredicatedNew = isPredNew in
745 def NAME : STInst2<(outs),
746 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
747 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
748 ") ")#mnemonic#"($src2+#$src3) = #$src4",
753 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
754 let isPredicatedFalse = PredNot in {
755 defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
757 defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
761 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
762 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
763 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
764 let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
765 def NAME#_V4 : STInst2<(outs),
766 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
767 mnemonic#"($src1+#$src2) = #$src3",
771 let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
772 defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
773 defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
778 let addrMode = BaseImmOffset, InputType = "imm",
779 validSubTargets = HasV4SubT in {
780 defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
781 defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
782 defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
785 let Predicates = [HasV4T], AddedComplexity = 10 in {
786 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
787 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
789 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
791 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
793 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
794 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
797 let AddedComplexity = 6 in
798 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
799 (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
802 // memb(Ru<<#u2+#U6)=Rt
803 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
804 validSubTargets = HasV4SubT in
805 def STrib_shl_V4 : STInst<(outs),
806 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
807 "memb($src1<<#$src2+#$src3) = $src4",
808 [(truncstorei8 (i32 IntRegs:$src4),
809 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
810 u0AlwaysExtPred:$src3))]>,
813 // memb(Rx++#s4:0:circ(Mu))=Rt
814 // memb(Rx++I:circ(Mu))=Rt
816 // memb(Rx++Mu:brev)=Rt
817 // memb(gp+#u16:0)=Rt
821 // TODO: needs to be implemented
823 // memh(Rs+#s11:1)=Rt.H
824 let AddedComplexity = 6 in
825 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
826 (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
829 // memh(Rs+Ru<<#u2)=Rt.H
830 // TODO: needs to be implemented.
832 // memh(Ru<<#u2+#U6)=Rt.H
833 // memh(Ru<<#u2+#U6)=Rt
834 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
835 validSubTargets = HasV4SubT in
836 def STrih_shl_V4 : STInst<(outs),
837 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
838 "memh($src1<<#$src2+#$src3) = $src4",
839 [(truncstorei16 (i32 IntRegs:$src4),
840 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
841 u0AlwaysExtPred:$src3))]>,
844 // memh(Rx++#s4:1:circ(Mu))=Rt.H
845 // memh(Rx++#s4:1:circ(Mu))=Rt
846 // memh(Rx++I:circ(Mu))=Rt.H
847 // memh(Rx++I:circ(Mu))=Rt
850 // memh(Rx++Mu:brev)=Rt.H
851 // memh(Rx++Mu:brev)=Rt
852 // memh(gp+#u16:1)=Rt
853 // if ([!]Pv[.new]) memh(#u6)=Rt.H
854 // if ([!]Pv[.new]) memh(#u6)=Rt
857 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
858 // TODO: needs to be implemented.
860 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
861 // TODO: Needs to be implemented.
865 // TODO: Needs to be implemented.
868 let neverHasSideEffects = 1 in
869 def STriw_pred_V4 : STInst2<(outs),
870 (ins MEMri:$addr, PredRegs:$src1),
871 "Error; should not emit",
875 let AddedComplexity = 6 in
876 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
877 (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
880 // memw(Ru<<#u2+#U6)=Rt
881 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
882 validSubTargets = HasV4SubT in
883 def STriw_shl_V4 : STInst<(outs),
884 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
885 "memw($src1<<#$src2+#$src3) = $src4",
886 [(store (i32 IntRegs:$src4),
887 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
888 u0AlwaysExtPred:$src3))]>,
891 // memw(Rx++#s4:2)=Rt
892 // memw(Rx++#s4:2:circ(Mu))=Rt
893 // memw(Rx++I:circ(Mu))=Rt
895 // memw(Rx++Mu:brev)=Rt
897 //===----------------------------------------------------------------------===
899 //===----------------------------------------------------------------------===
902 //===----------------------------------------------------------------------===//
904 //===----------------------------------------------------------------------===//
906 // multiclass for new-value store instructions with base + immediate offset.
908 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
909 Operand predImmOp, bit isNot, bit isPredNew> {
910 let isPredicatedNew = isPredNew in
911 def NAME#_nv_V4 : NVInst_V4<(outs),
912 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
913 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
914 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
919 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
921 let isPredicatedFalse = PredNot in {
922 defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
924 defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
928 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
929 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
930 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
931 bits<5> PredImmBits> {
933 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
934 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
936 def NAME#_nv_V4 : NVInst_V4<(outs),
937 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
938 mnemonic#"($src1+#$src2) = $src3.new",
942 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
943 isPredicated = 1 in {
944 defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
945 defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
950 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
951 defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
952 u6_0Ext, 11, 6>, AddrModeRel;
953 defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
954 u6_1Ext, 12, 7>, AddrModeRel;
955 defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
956 u6_2Ext, 13, 8>, AddrModeRel;
959 // multiclass for new-value store instructions with base + immediate offset.
960 // and MEMri operand.
961 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
963 let isPredicatedNew = isPredNew in
964 def NAME#_nv_V4 : NVInst_V4<(outs),
965 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
966 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
967 ") ")#mnemonic#"($addr) = $src2.new",
972 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
973 let isPredicatedFalse = PredNot in {
974 defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
977 defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
981 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
982 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
983 bits<5> ImmBits, bits<5> PredImmBits> {
985 let CextOpcode = CextOp, BaseOpcode = CextOp in {
986 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
988 def NAME#_nv_V4 : NVInst_V4<(outs),
989 (ins MEMri:$addr, RC:$src),
990 mnemonic#"($addr) = $src.new",
994 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
995 neverHasSideEffects = 1, isPredicated = 1 in {
996 defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
997 defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
1002 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
1004 defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1005 defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1006 defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1009 // memb(Ru<<#u2+#U6)=Nt.new
1010 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
1011 isNVStore = 1, validSubTargets = HasV4SubT in
1012 def STrib_shl_nv_V4 : NVInst_V4<(outs),
1013 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1014 "memb($src1<<#$src2+#$src3) = $src4.new",
1018 //===----------------------------------------------------------------------===//
1019 // Post increment store
1020 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1021 //===----------------------------------------------------------------------===//
1023 multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
1024 bit isNot, bit isPredNew> {
1025 let isPredicatedNew = isPredNew in
1026 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1027 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1028 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1029 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1035 multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
1036 Operand ImmOp, bit PredNot> {
1037 let isPredicatedFalse = PredNot in {
1038 defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
1040 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1041 defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
1045 let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
1046 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
1049 let BaseOpcode = "POST_"#BaseOp in {
1050 let isPredicable = 1 in
1051 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1052 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1053 mnemonic#"($src1++#$offset) = $src2.new",
1058 let isPredicated = 1 in {
1059 defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
1060 defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
1065 let validSubTargets = HasV4SubT in {
1066 defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1067 defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1068 defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1071 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1072 // memb(Rx++I:circ(Mu))=Nt.new
1073 // memb(Rx++Mu)=Nt.new
1074 // memb(Rx++Mu:brev)=Nt.new
1075 // memh(Ru<<#u2+#U6)=Nt.new
1076 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
1077 isNVStore = 1, validSubTargets = HasV4SubT in
1078 def STrih_shl_nv_V4 : NVInst_V4<(outs),
1079 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1080 "memh($src1<<#$src2+#$src3) = $src4.new",
1084 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1085 // memh(Rx++I:circ(Mu))=Nt.new
1086 // memh(Rx++Mu)=Nt.new
1087 // memh(Rx++Mu:brev)=Nt.new
1089 // memw(Ru<<#u2+#U6)=Nt.new
1090 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
1091 isNVStore = 1, validSubTargets = HasV4SubT in
1092 def STriw_shl_nv_V4 : NVInst_V4<(outs),
1093 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1094 "memw($src1<<#$src2+#$src3) = $src4.new",
1098 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1099 // memw(Rx++I:circ(Mu))=Nt.new
1100 // memw(Rx++Mu)=Nt.new
1101 // memw(Rx++Mu:brev)=Nt.new
1103 //===----------------------------------------------------------------------===//
1105 //===----------------------------------------------------------------------===//
1107 //===----------------------------------------------------------------------===//
1109 //===----------------------------------------------------------------------===//
1111 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
1112 def _ie_nv_V4 : NVInst_V4<(outs),
1113 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1114 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1115 !strconcat("($src1.new, $src2)) jump:",
1116 !strconcat(TakenStr, " $offset"))))),
1120 def _nv_V4 : NVInst_V4<(outs),
1121 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1122 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1123 !strconcat("($src1.new, $src2)) jump:",
1124 !strconcat(TakenStr, " $offset"))))),
1129 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
1131 def _ie_nv_V4 : NVInst_V4<(outs),
1132 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1133 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1134 !strconcat("($src1, $src2.new)) jump:",
1135 !strconcat(TakenStr, " $offset"))))),
1139 def _nv_V4 : NVInst_V4<(outs),
1140 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1141 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1142 !strconcat("($src1, $src2.new)) jump:",
1143 !strconcat(TakenStr, " $offset"))))),
1148 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
1149 def _ie_nv_V4 : NVInst_V4<(outs),
1150 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1151 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1152 !strconcat("($src1.new, #$src2)) jump:",
1153 !strconcat(TakenStr, " $offset"))))),
1157 def _nv_V4 : NVInst_V4<(outs),
1158 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1159 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1160 !strconcat("($src1.new, #$src2)) jump:",
1161 !strconcat(TakenStr, " $offset"))))),
1166 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
1167 def _ie_nv_V4 : NVInst_V4<(outs),
1168 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
1169 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1170 !strconcat("($src1.new, #$src2)) jump:",
1171 !strconcat(TakenStr, " $offset"))))),
1175 def _nv_V4 : NVInst_V4<(outs),
1176 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
1177 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1178 !strconcat("($src1.new, #$src2)) jump:",
1179 !strconcat(TakenStr, " $offset"))))),
1184 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
1186 def _ie_nv_V4 : NVInst_V4<(outs),
1187 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
1188 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1189 !strconcat("($src1.new, #$src2)) jump:",
1190 !strconcat(TakenStr, " $offset"))))),
1194 def _nv_V4 : NVInst_V4<(outs),
1195 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
1196 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1197 !strconcat("($src1.new, #$src2)) jump:",
1198 !strconcat(TakenStr, " $offset"))))),
1203 // Multiclass for regular dot new of Ist operand register.
1204 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
1205 defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
1206 defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
1209 // Multiclass for dot new of 2nd operand register.
1210 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
1211 defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
1212 defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
1215 // Multiclass for 2nd operand immediate, including -1.
1216 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
1217 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
1218 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
1219 defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
1220 defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
1223 // Multiclass for 2nd operand immediate, excluding -1.
1224 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
1225 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
1226 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
1229 // Multiclass for tstbit, where 2nd operand is always #0.
1230 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
1231 defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
1232 defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
1235 // Multiclass for GT.
1236 multiclass NVJ_type_rr_ri<string OpcStr> {
1237 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
1238 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
1239 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
1240 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
1241 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
1242 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
1245 // Multiclass for EQ.
1246 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
1247 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
1248 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
1249 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
1250 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
1253 // Multiclass for GTU.
1254 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
1255 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
1256 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
1257 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
1258 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
1259 defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
1260 defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
1263 // Multiclass for tstbit.
1264 multiclass NVJ_type_r0<string OpcStr> {
1265 defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
1266 defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
1269 // Base Multiclass for New Value Jump.
1270 multiclass NVJ_type {
1271 defm GT : NVJ_type_rr_ri<"cmp.gt">;
1272 defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
1273 defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
1274 defm TSTBIT : NVJ_type_r0<"tstbit">;
1277 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
1278 defm JMP_ : NVJ_type;
1281 //===----------------------------------------------------------------------===//
1283 //===----------------------------------------------------------------------===//
1285 //===----------------------------------------------------------------------===//
1287 //===----------------------------------------------------------------------===//
1289 // Add and accumulate.
1290 // Rd=add(Rs,add(Ru,#s6))
1291 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
1292 validSubTargets = HasV4SubT in
1293 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
1294 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1295 "$dst = add($src1, add($src2, #$src3))",
1296 [(set (i32 IntRegs:$dst),
1297 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1298 s6_16ExtPred:$src3)))]>,
1301 // Rd=add(Rs,sub(#s6,Ru))
1302 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1303 validSubTargets = HasV4SubT in
1304 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
1305 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1306 "$dst = add($src1, sub(#$src2, $src3))",
1307 [(set (i32 IntRegs:$dst),
1308 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1309 (i32 IntRegs:$src3))))]>,
1312 // Generates the same instruction as ADDr_SUBri_V4 but matches different
1314 // Rd=add(Rs,sub(#s6,Ru))
1315 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1316 validSubTargets = HasV4SubT in
1317 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
1318 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1319 "$dst = add($src1, sub(#$src2, $src3))",
1320 [(set (i32 IntRegs:$dst),
1321 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1322 (i32 IntRegs:$src3)))]>,
1326 // Add or subtract doublewords with carry.
1328 // Rdd=add(Rss,Rtt,Px):carry
1330 // Rdd=sub(Rss,Rtt,Px):carry
1333 // Logical doublewords.
1334 // Rdd=and(Rtt,~Rss)
1335 let validSubTargets = HasV4SubT in
1336 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1337 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1338 "$dst = and($src1, ~$src2)",
1339 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1340 (not (i64 DoubleRegs:$src2))))]>,
1344 let validSubTargets = HasV4SubT in
1345 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1346 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1347 "$dst = or($src1, ~$src2)",
1348 [(set (i64 DoubleRegs:$dst),
1349 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
1353 // Logical-logical doublewords.
1354 // Rxx^=xor(Rss,Rtt)
1355 let validSubTargets = HasV4SubT in
1356 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
1357 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1358 "$dst ^= xor($src2, $src3)",
1359 [(set (i64 DoubleRegs:$dst),
1360 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
1361 (i64 DoubleRegs:$src3))))],
1366 // Logical-logical words.
1367 // Rx=or(Ru,and(Rx,#s10))
1368 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1369 validSubTargets = HasV4SubT in
1370 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
1371 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1372 "$dst = or($src1, and($src2, #$src3))",
1373 [(set (i32 IntRegs:$dst),
1374 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1375 s10ExtPred:$src3)))],
1379 // Rx[&|^]=and(Rs,Rt)
1381 let validSubTargets = HasV4SubT in
1382 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1383 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1384 "$dst &= and($src2, $src3)",
1385 [(set (i32 IntRegs:$dst),
1386 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1387 (i32 IntRegs:$src3))))],
1392 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
1393 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1394 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1395 "$dst |= and($src2, $src3)",
1396 [(set (i32 IntRegs:$dst),
1397 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1398 (i32 IntRegs:$src3))))],
1400 Requires<[HasV4T]>, ImmRegRel;
1403 let validSubTargets = HasV4SubT in
1404 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1405 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1406 "$dst ^= and($src2, $src3)",
1407 [(set (i32 IntRegs:$dst),
1408 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1409 (i32 IntRegs:$src3))))],
1413 // Rx[&|^]=and(Rs,~Rt)
1415 let validSubTargets = HasV4SubT in
1416 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1417 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1418 "$dst &= and($src2, ~$src3)",
1419 [(set (i32 IntRegs:$dst),
1420 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1421 (not (i32 IntRegs:$src3)))))],
1426 let validSubTargets = HasV4SubT in
1427 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1428 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1429 "$dst |= and($src2, ~$src3)",
1430 [(set (i32 IntRegs:$dst),
1431 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1432 (not (i32 IntRegs:$src3)))))],
1437 let validSubTargets = HasV4SubT in
1438 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1439 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1440 "$dst ^= and($src2, ~$src3)",
1441 [(set (i32 IntRegs:$dst),
1442 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1443 (not (i32 IntRegs:$src3)))))],
1447 // Rx[&|^]=or(Rs,Rt)
1449 let validSubTargets = HasV4SubT in
1450 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1451 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1452 "$dst &= or($src2, $src3)",
1453 [(set (i32 IntRegs:$dst),
1454 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1455 (i32 IntRegs:$src3))))],
1460 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
1461 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1462 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1463 "$dst |= or($src2, $src3)",
1464 [(set (i32 IntRegs:$dst),
1465 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1466 (i32 IntRegs:$src3))))],
1468 Requires<[HasV4T]>, ImmRegRel;
1471 let validSubTargets = HasV4SubT in
1472 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1473 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1474 "$dst ^= or($src2, $src3)",
1475 [(set (i32 IntRegs:$dst),
1476 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1477 (i32 IntRegs:$src3))))],
1481 // Rx[&|^]=xor(Rs,Rt)
1483 let validSubTargets = HasV4SubT in
1484 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1485 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1486 "$dst &= xor($src2, $src3)",
1487 [(set (i32 IntRegs:$dst),
1488 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1489 (i32 IntRegs:$src3))))],
1494 let validSubTargets = HasV4SubT in
1495 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1496 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1497 "$dst |= xor($src2, $src3)",
1498 [(set (i32 IntRegs:$dst),
1499 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1500 (i32 IntRegs:$src3))))],
1505 let validSubTargets = HasV4SubT in
1506 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1507 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1508 "$dst ^= xor($src2, $src3)",
1509 [(set (i32 IntRegs:$dst),
1510 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1511 (i32 IntRegs:$src3))))],
1516 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1517 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
1518 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
1519 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1520 "$dst |= and($src2, #$src3)",
1521 [(set (i32 IntRegs:$dst),
1522 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1523 s10ExtPred:$src3)))],
1525 Requires<[HasV4T]>, ImmRegRel;
1528 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1529 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
1530 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
1531 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1532 "$dst |= or($src2, #$src3)",
1533 [(set (i32 IntRegs:$dst),
1534 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1535 s10ExtPred:$src3)))],
1537 Requires<[HasV4T]>, ImmRegRel;
1541 // Rd=modwrap(Rs,Rt)
1543 // Rd=cround(Rs,#u5)
1545 // Rd=round(Rs,#u5)[:sat]
1546 // Rd=round(Rs,Rt)[:sat]
1547 // Vector reduce add unsigned halfwords
1548 // Rd=vraddh(Rss,Rtt)
1550 // Rdd=vaddb(Rss,Rtt)
1551 // Vector conditional negate
1552 // Rdd=vcnegh(Rss,Rt)
1553 // Rxx+=vrcnegh(Rss,Rt)
1554 // Vector maximum bytes
1555 // Rdd=vmaxb(Rtt,Rss)
1556 // Vector reduce maximum halfwords
1557 // Rxx=vrmaxh(Rss,Ru)
1558 // Rxx=vrmaxuh(Rss,Ru)
1559 // Vector reduce maximum words
1560 // Rxx=vrmaxuw(Rss,Ru)
1561 // Rxx=vrmaxw(Rss,Ru)
1562 // Vector minimum bytes
1563 // Rdd=vminb(Rtt,Rss)
1564 // Vector reduce minimum halfwords
1565 // Rxx=vrminh(Rss,Ru)
1566 // Rxx=vrminuh(Rss,Ru)
1567 // Vector reduce minimum words
1568 // Rxx=vrminuw(Rss,Ru)
1569 // Rxx=vrminw(Rss,Ru)
1570 // Vector subtract bytes
1571 // Rdd=vsubb(Rss,Rtt)
1573 //===----------------------------------------------------------------------===//
1575 //===----------------------------------------------------------------------===//
1578 //===----------------------------------------------------------------------===//
1580 //===----------------------------------------------------------------------===//
1582 // Multiply and user lower result.
1583 // Rd=add(#u6,mpyi(Rs,#U6))
1584 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1585 validSubTargets = HasV4SubT in
1586 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
1587 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1588 "$dst = add(#$src1, mpyi($src2, #$src3))",
1589 [(set (i32 IntRegs:$dst),
1590 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1591 u6ExtPred:$src1))]>,
1594 // Rd=add(##,mpyi(Rs,#U6))
1595 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1596 (HexagonCONST32 tglobaladdr:$src1)),
1597 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
1600 // Rd=add(#u6,mpyi(Rs,Rt))
1601 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1602 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1603 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
1604 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1605 "$dst = add(#$src1, mpyi($src2, $src3))",
1606 [(set (i32 IntRegs:$dst),
1607 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1608 u6ExtPred:$src1))]>,
1609 Requires<[HasV4T]>, ImmRegRel;
1611 // Rd=add(##,mpyi(Rs,Rt))
1612 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1613 (HexagonCONST32 tglobaladdr:$src1)),
1614 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
1617 // Rd=add(Ru,mpyi(#u6:2,Rs))
1618 let validSubTargets = HasV4SubT in
1619 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
1620 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1621 "$dst = add($src1, mpyi(#$src2, $src3))",
1622 [(set (i32 IntRegs:$dst),
1623 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1624 u6_2ImmPred:$src2)))]>,
1627 // Rd=add(Ru,mpyi(Rs,#u6))
1628 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
1629 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1630 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
1631 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1632 "$dst = add($src1, mpyi($src2, #$src3))",
1633 [(set (i32 IntRegs:$dst),
1634 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1635 u6ExtPred:$src3)))]>,
1636 Requires<[HasV4T]>, ImmRegRel;
1638 // Rx=add(Ru,mpyi(Rx,Rs))
1639 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
1640 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
1641 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1642 "$dst = add($src1, mpyi($src2, $src3))",
1643 [(set (i32 IntRegs:$dst),
1644 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1645 (i32 IntRegs:$src3))))],
1647 Requires<[HasV4T]>, ImmRegRel;
1650 // Polynomial multiply words
1652 // Rxx^=pmpyw(Rs,Rt)
1654 // Vector reduce multiply word by signed half (32x16)
1655 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
1656 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
1657 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
1658 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
1660 // Multiply and use upper result
1661 // Rd=mpy(Rs,Rt.H):<<1:sat
1662 // Rd=mpy(Rs,Rt.L):<<1:sat
1663 // Rd=mpy(Rs,Rt):<<1
1664 // Rd=mpy(Rs,Rt):<<1:sat
1666 // Rx+=mpy(Rs,Rt):<<1:sat
1667 // Rx-=mpy(Rs,Rt):<<1:sat
1669 // Vector multiply bytes
1670 // Rdd=vmpybsu(Rs,Rt)
1671 // Rdd=vmpybu(Rs,Rt)
1672 // Rxx+=vmpybsu(Rs,Rt)
1673 // Rxx+=vmpybu(Rs,Rt)
1675 // Vector polynomial multiply halfwords
1676 // Rdd=vpmpyh(Rs,Rt)
1677 // Rxx^=vpmpyh(Rs,Rt)
1679 //===----------------------------------------------------------------------===//
1681 //===----------------------------------------------------------------------===//
1684 //===----------------------------------------------------------------------===//
1686 //===----------------------------------------------------------------------===//
1688 // Shift by immediate and accumulate.
1689 // Rx=add(#u8,asl(Rx,#U5))
1690 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1691 validSubTargets = HasV4SubT in
1692 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1693 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1694 "$dst = add(#$src1, asl($src2, #$src3))",
1695 [(set (i32 IntRegs:$dst),
1696 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1701 // Rx=add(#u8,lsr(Rx,#U5))
1702 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1703 validSubTargets = HasV4SubT in
1704 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1705 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1706 "$dst = add(#$src1, lsr($src2, #$src3))",
1707 [(set (i32 IntRegs:$dst),
1708 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1713 // Rx=sub(#u8,asl(Rx,#U5))
1714 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1715 validSubTargets = HasV4SubT in
1716 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1717 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1718 "$dst = sub(#$src1, asl($src2, #$src3))",
1719 [(set (i32 IntRegs:$dst),
1720 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1725 // Rx=sub(#u8,lsr(Rx,#U5))
1726 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1727 validSubTargets = HasV4SubT in
1728 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1729 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1730 "$dst = sub(#$src1, lsr($src2, #$src3))",
1731 [(set (i32 IntRegs:$dst),
1732 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1738 //Shift by immediate and logical.
1739 //Rx=and(#u8,asl(Rx,#U5))
1740 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1741 validSubTargets = HasV4SubT in
1742 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1743 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1744 "$dst = and(#$src1, asl($src2, #$src3))",
1745 [(set (i32 IntRegs:$dst),
1746 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1751 //Rx=and(#u8,lsr(Rx,#U5))
1752 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1753 validSubTargets = HasV4SubT in
1754 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1755 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1756 "$dst = and(#$src1, lsr($src2, #$src3))",
1757 [(set (i32 IntRegs:$dst),
1758 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1763 //Rx=or(#u8,asl(Rx,#U5))
1764 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1765 AddedComplexity = 30, validSubTargets = HasV4SubT in
1766 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1767 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1768 "$dst = or(#$src1, asl($src2, #$src3))",
1769 [(set (i32 IntRegs:$dst),
1770 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1775 //Rx=or(#u8,lsr(Rx,#U5))
1776 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1777 AddedComplexity = 30, validSubTargets = HasV4SubT in
1778 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1779 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1780 "$dst = or(#$src1, lsr($src2, #$src3))",
1781 [(set (i32 IntRegs:$dst),
1782 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1788 //Shift by register.
1790 let validSubTargets = HasV4SubT in {
1791 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
1792 "$dst = lsl(#$src1, $src2)",
1793 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
1794 (i32 IntRegs:$src2)))]>,
1798 //Shift by register and logical.
1800 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1801 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1802 "$dst ^= asl($src2, $src3)",
1803 [(set (i64 DoubleRegs:$dst),
1804 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
1805 (i32 IntRegs:$src3))))],
1810 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1811 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1812 "$dst ^= asr($src2, $src3)",
1813 [(set (i64 DoubleRegs:$dst),
1814 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
1815 (i32 IntRegs:$src3))))],
1820 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1821 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1822 "$dst ^= lsl($src2, $src3)",
1823 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
1824 (shl (i64 DoubleRegs:$src2),
1825 (i32 IntRegs:$src3))))],
1830 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1831 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1832 "$dst ^= lsr($src2, $src3)",
1833 [(set (i64 DoubleRegs:$dst),
1834 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
1835 (i32 IntRegs:$src3))))],
1840 //===----------------------------------------------------------------------===//
1842 //===----------------------------------------------------------------------===//
1844 //===----------------------------------------------------------------------===//
1845 // MEMOP: Word, Half, Byte
1846 //===----------------------------------------------------------------------===//
1848 def MEMOPIMM : SDNodeXForm<imm, [{
1849 // Call the transformation function XformM5ToU5Imm to get the negative
1850 // immediate's positive counterpart.
1851 int32_t imm = N->getSExtValue();
1852 return XformM5ToU5Imm(imm);
1855 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
1856 // -1 .. -31 represented as 65535..65515
1857 // assigning to a short restores our desired signed value.
1858 // Call the transformation function XformM5ToU5Imm to get the negative
1859 // immediate's positive counterpart.
1860 int16_t imm = N->getSExtValue();
1861 return XformM5ToU5Imm(imm);
1864 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
1865 // -1 .. -31 represented as 255..235
1866 // assigning to a char restores our desired signed value.
1867 // Call the transformation function XformM5ToU5Imm to get the negative
1868 // immediate's positive counterpart.
1869 int8_t imm = N->getSExtValue();
1870 return XformM5ToU5Imm(imm);
1873 def SETMEMIMM : SDNodeXForm<imm, [{
1874 // Return the bit position we will set [0-31].
1876 int32_t imm = N->getSExtValue();
1877 return XformMskToBitPosU5Imm(imm);
1880 def CLRMEMIMM : SDNodeXForm<imm, [{
1881 // Return the bit position we will clear [0-31].
1883 // we bit negate the value first
1884 int32_t imm = ~(N->getSExtValue());
1885 return XformMskToBitPosU5Imm(imm);
1888 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
1889 // Return the bit position we will set [0-15].
1891 int16_t imm = N->getSExtValue();
1892 return XformMskToBitPosU4Imm(imm);
1895 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
1896 // Return the bit position we will clear [0-15].
1898 // we bit negate the value first
1899 int16_t imm = ~(N->getSExtValue());
1900 return XformMskToBitPosU4Imm(imm);
1903 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
1904 // Return the bit position we will set [0-7].
1906 int8_t imm = N->getSExtValue();
1907 return XformMskToBitPosU3Imm(imm);
1910 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
1911 // Return the bit position we will clear [0-7].
1913 // we bit negate the value first
1914 int8_t imm = ~(N->getSExtValue());
1915 return XformMskToBitPosU3Imm(imm);
1918 //===----------------------------------------------------------------------===//
1919 // Template class for MemOp instructions with the register value.
1920 //===----------------------------------------------------------------------===//
1921 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
1922 string memOp, bits<2> memOpBits> :
1924 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
1925 opc#"($base+#$offset)"#memOp#"$delta",
1927 Requires<[HasV4T, UseMEMOP]> {
1932 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1934 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1935 !if (!eq(opcBits, 0b01), offset{6-1},
1936 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1938 let IClass = 0b0011;
1939 let Inst{27-24} = 0b1110;
1940 let Inst{22-21} = opcBits;
1941 let Inst{20-16} = base;
1943 let Inst{12-7} = offsetBits;
1944 let Inst{6-5} = memOpBits;
1945 let Inst{4-0} = delta;
1948 //===----------------------------------------------------------------------===//
1949 // Template class for MemOp instructions with the immediate value.
1950 //===----------------------------------------------------------------------===//
1951 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
1952 string memOp, bits<2> memOpBits> :
1954 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
1955 opc#"($base+#$offset)"#memOp#"#$delta"
1956 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
1958 Requires<[HasV4T, UseMEMOP]> {
1963 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1965 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1966 !if (!eq(opcBits, 0b01), offset{6-1},
1967 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1969 let IClass = 0b0011;
1970 let Inst{27-24} = 0b1111;
1971 let Inst{22-21} = opcBits;
1972 let Inst{20-16} = base;
1974 let Inst{12-7} = offsetBits;
1975 let Inst{6-5} = memOpBits;
1976 let Inst{4-0} = delta;
1979 // multiclass to define MemOp instructions with register operand.
1980 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
1981 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
1982 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
1983 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
1984 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
1987 // multiclass to define MemOp instructions with immediate Operand.
1988 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
1989 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
1990 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
1991 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
1992 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
1995 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
1996 defm r : MemOp_rr <opc, opcBits, ImmOp>;
1997 defm i : MemOp_ri <opc, opcBits, ImmOp>;
2000 // Define MemOp instructions.
2001 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2002 validSubTargets =HasV4SubT in {
2003 let opExtentBits = 6, accessSize = ByteAccess in
2004 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
2006 let opExtentBits = 7, accessSize = HalfWordAccess in
2007 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
2009 let opExtentBits = 8, accessSize = WordAccess in
2010 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
2013 //===----------------------------------------------------------------------===//
2014 // Multiclass to define 'Def Pats' for ALU operations on the memory
2015 // Here value used for the ALU operation is an immediate value.
2016 // mem[bh](Rs+#0) += #U5
2017 // mem[bh](Rs+#u6) += #U5
2018 //===----------------------------------------------------------------------===//
2020 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2021 InstHexagon MI, SDNode OpNode> {
2022 let AddedComplexity = 180 in
2023 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2025 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2027 let AddedComplexity = 190 in
2028 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2030 (add IntRegs:$base, ExtPred:$offset)),
2031 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2034 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2035 InstHexagon addMI, InstHexagon subMI> {
2036 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2037 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2040 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2042 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2043 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
2045 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2046 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
2049 let Predicates = [HasV4T, UseMEMOP] in {
2050 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2051 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2052 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2055 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
2059 //===----------------------------------------------------------------------===//
2060 // multiclass to define 'Def Pats' for ALU operations on the memory.
2061 // Here value used for the ALU operation is a negative value.
2062 // mem[bh](Rs+#0) += #m5
2063 // mem[bh](Rs+#u6) += #m5
2064 //===----------------------------------------------------------------------===//
2066 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2067 PatLeaf immPred, ComplexPattern addrPred,
2068 SDNodeXForm xformFunc, InstHexagon MI> {
2069 let AddedComplexity = 190 in
2070 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2072 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2074 let AddedComplexity = 195 in
2075 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2077 (add IntRegs:$base, extPred:$offset)),
2078 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2081 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2083 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2084 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
2086 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2087 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
2090 let Predicates = [HasV4T, UseMEMOP] in {
2091 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2092 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2093 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2096 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2097 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
2100 //===----------------------------------------------------------------------===//
2101 // Multiclass to define 'def Pats' for bit operations on the memory.
2102 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2103 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2104 //===----------------------------------------------------------------------===//
2106 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2107 PatLeaf extPred, ComplexPattern addrPred,
2108 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2110 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2111 let AddedComplexity = 250 in
2112 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2114 (add IntRegs:$base, extPred:$offset)),
2115 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2117 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2118 let AddedComplexity = 225 in
2119 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), immPred:$bitend),
2121 (MI IntRegs:$addr, #0, (xformFunc immPred:$bitend))>;
2124 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2126 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2127 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
2129 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2130 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
2131 // Half Word - clrbit
2132 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2133 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
2134 // Half Word - setbit
2135 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2136 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
2139 let Predicates = [HasV4T, UseMEMOP] in {
2140 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2141 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2142 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2143 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2144 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2146 // memw(Rs+#0) = [clrbit|setbit](#U5)
2147 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2148 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2149 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2150 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2151 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2154 //===----------------------------------------------------------------------===//
2155 // Multiclass to define 'def Pats' for ALU operations on the memory
2156 // where addend is a register.
2157 // mem[bhw](Rs+#0) [+-&|]= Rt
2158 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2159 //===----------------------------------------------------------------------===//
2161 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2162 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2163 let AddedComplexity = 141 in
2164 // mem[bhw](Rs+#0) [+-&|]= Rt
2165 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)),
2167 (MI IntRegs:$addr, #0, (i32 IntRegs:$addend) )>;
2169 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2170 let AddedComplexity = 150 in
2171 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2172 (i32 IntRegs:$orend)),
2173 (add IntRegs:$base, extPred:$offset)),
2174 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2177 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2178 ComplexPattern addrPred, PatLeaf extPred,
2179 InstHexagon addMI, InstHexagon subMI,
2180 InstHexagon andMI, InstHexagon orMI > {
2182 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2183 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2184 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2185 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2188 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2190 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2191 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2192 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2194 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2195 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2196 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2199 // Define 'def Pats' for MemOps with register addend.
2200 let Predicates = [HasV4T, UseMEMOP] in {
2202 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2203 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2204 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2206 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2207 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2210 //===----------------------------------------------------------------------===//
2212 //===----------------------------------------------------------------------===//
2214 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2215 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2216 // hardware. However, compiler can still implement these patterns through
2217 // appropriate patterns combinations based on current implemented patterns.
2218 // The implemented patterns are: EQ/GT/GTU.
2219 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2221 // Following instruction is not being extended as it results into the
2222 // incorrect code for negative numbers.
2223 // Pd=cmpb.eq(Rs,#u8)
2226 let isCompare = 1, validSubTargets = HasV4SubT in
2227 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2228 (ins IntRegs:$src1, IntRegs:$src2),
2229 "$dst = !cmp.eq($src1, $src2)",
2230 [(set (i1 PredRegs:$dst),
2231 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2234 // p=!cmp.eq(r1,#s10)
2235 let isCompare = 1, validSubTargets = HasV4SubT in
2236 def CMPnotEQ_ri : ALU32_ri<(outs PredRegs:$dst),
2237 (ins IntRegs:$src1, s10Ext:$src2),
2238 "$dst = !cmp.eq($src1, #$src2)",
2239 [(set (i1 PredRegs:$dst),
2240 (setne (i32 IntRegs:$src1), s10ImmPred:$src2))]>,
2244 let isCompare = 1, validSubTargets = HasV4SubT in
2245 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2246 (ins IntRegs:$src1, IntRegs:$src2),
2247 "$dst = !cmp.gt($src1, $src2)",
2248 [(set (i1 PredRegs:$dst),
2249 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2252 // p=!cmp.gt(r1,#s10)
2253 let isCompare = 1, validSubTargets = HasV4SubT in
2254 def CMPnotGT_ri : ALU32_ri<(outs PredRegs:$dst),
2255 (ins IntRegs:$src1, s10Ext:$src2),
2256 "$dst = !cmp.gt($src1, #$src2)",
2257 [(set (i1 PredRegs:$dst),
2258 (not (setgt (i32 IntRegs:$src1), s10ImmPred:$src2)))]>,
2261 // p=!cmp.gtu(r1,r2)
2262 let isCompare = 1, validSubTargets = HasV4SubT in
2263 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2264 (ins IntRegs:$src1, IntRegs:$src2),
2265 "$dst = !cmp.gtu($src1, $src2)",
2266 [(set (i1 PredRegs:$dst),
2267 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2270 // p=!cmp.gtu(r1,#u9)
2271 let isCompare = 1, validSubTargets = HasV4SubT in
2272 def CMPnotGTU_ri : ALU32_ri<(outs PredRegs:$dst),
2273 (ins IntRegs:$src1, u9Ext:$src2),
2274 "$dst = !cmp.gtu($src1, #$src2)",
2275 [(set (i1 PredRegs:$dst),
2276 (not (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)))]>,
2279 let isCompare = 1, validSubTargets = HasV4SubT in
2280 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2281 (ins IntRegs:$src1, u8Imm:$src2),
2282 "$dst = cmpb.eq($src1, #$src2)",
2283 [(set (i1 PredRegs:$dst),
2284 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2287 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2289 (JMP_cNot (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2293 // Pd=cmpb.eq(Rs,Rt)
2294 let isCompare = 1, validSubTargets = HasV4SubT in
2295 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2296 (ins IntRegs:$src1, IntRegs:$src2),
2297 "$dst = cmpb.eq($src1, $src2)",
2298 [(set (i1 PredRegs:$dst),
2299 (seteq (and (xor (i32 IntRegs:$src1),
2300 (i32 IntRegs:$src2)), 255), 0))]>,
2303 // Pd=cmpb.eq(Rs,Rt)
2304 let isCompare = 1, validSubTargets = HasV4SubT in
2305 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2306 (ins IntRegs:$src1, IntRegs:$src2),
2307 "$dst = cmpb.eq($src1, $src2)",
2308 [(set (i1 PredRegs:$dst),
2309 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2310 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2313 // Pd=cmpb.gt(Rs,Rt)
2314 let isCompare = 1, validSubTargets = HasV4SubT in
2315 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2316 (ins IntRegs:$src1, IntRegs:$src2),
2317 "$dst = cmpb.gt($src1, $src2)",
2318 [(set (i1 PredRegs:$dst),
2319 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2320 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2323 // Pd=cmpb.gtu(Rs,#u7)
2324 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2325 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2326 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2327 (ins IntRegs:$src1, u7Ext:$src2),
2328 "$dst = cmpb.gtu($src1, #$src2)",
2329 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2330 u7ExtPred:$src2))]>,
2331 Requires<[HasV4T]>, ImmRegRel;
2333 // SDNode for converting immediate C to C-1.
2334 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2335 // Return the byte immediate const-1 as an SDNode.
2336 int32_t imm = N->getSExtValue();
2337 return XformU7ToU7M1Imm(imm);
2341 // zext( seteq ( and(Rs, 255), u8))
2343 // Pd=cmpb.eq(Rs, #u8)
2344 // if (Pd.new) Rd=#1
2345 // if (!Pd.new) Rd=#0
2346 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2348 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2354 // zext( setne ( and(Rs, 255), u8))
2356 // Pd=cmpb.eq(Rs, #u8)
2357 // if (Pd.new) Rd=#0
2358 // if (!Pd.new) Rd=#1
2359 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2361 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2367 // zext( seteq (Rs, and(Rt, 255)))
2369 // Pd=cmpb.eq(Rs, Rt)
2370 // if (Pd.new) Rd=#1
2371 // if (!Pd.new) Rd=#0
2372 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2373 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2374 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2375 (i32 IntRegs:$Rt))),
2380 // zext( setne (Rs, and(Rt, 255)))
2382 // Pd=cmpb.eq(Rs, Rt)
2383 // if (Pd.new) Rd=#0
2384 // if (!Pd.new) Rd=#1
2385 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2386 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2387 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2388 (i32 IntRegs:$Rt))),
2393 // zext( setugt ( and(Rs, 255), u8))
2395 // Pd=cmpb.gtu(Rs, #u8)
2396 // if (Pd.new) Rd=#1
2397 // if (!Pd.new) Rd=#0
2398 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2400 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2406 // zext( setugt ( and(Rs, 254), u8))
2408 // Pd=cmpb.gtu(Rs, #u8)
2409 // if (Pd.new) Rd=#1
2410 // if (!Pd.new) Rd=#0
2411 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2413 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2419 // zext( setult ( Rs, Rt))
2421 // Pd=cmp.ltu(Rs, Rt)
2422 // if (Pd.new) Rd=#1
2423 // if (!Pd.new) Rd=#0
2424 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2425 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2426 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
2427 (i32 IntRegs:$Rs))),
2432 // zext( setlt ( Rs, Rt))
2434 // Pd=cmp.lt(Rs, Rt)
2435 // if (Pd.new) Rd=#1
2436 // if (!Pd.new) Rd=#0
2437 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2438 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2439 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
2440 (i32 IntRegs:$Rs))),
2445 // zext( setugt ( Rs, Rt))
2447 // Pd=cmp.gtu(Rs, Rt)
2448 // if (Pd.new) Rd=#1
2449 // if (!Pd.new) Rd=#0
2450 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2451 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
2452 (i32 IntRegs:$Rt))),
2456 // This pattern interefers with coremark performance, not implementing at this
2459 // zext( setgt ( Rs, Rt))
2461 // Pd=cmp.gt(Rs, Rt)
2462 // if (Pd.new) Rd=#1
2463 // if (!Pd.new) Rd=#0
2466 // zext( setuge ( Rs, Rt))
2468 // Pd=cmp.ltu(Rs, Rt)
2469 // if (Pd.new) Rd=#0
2470 // if (!Pd.new) Rd=#1
2471 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2472 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2473 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
2474 (i32 IntRegs:$Rs))),
2479 // zext( setge ( Rs, Rt))
2481 // Pd=cmp.lt(Rs, Rt)
2482 // if (Pd.new) Rd=#0
2483 // if (!Pd.new) Rd=#1
2484 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2485 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2486 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
2487 (i32 IntRegs:$Rs))),
2492 // zext( setule ( Rs, Rt))
2494 // Pd=cmp.gtu(Rs, Rt)
2495 // if (Pd.new) Rd=#0
2496 // if (!Pd.new) Rd=#1
2497 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2498 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
2499 (i32 IntRegs:$Rt))),
2504 // zext( setle ( Rs, Rt))
2506 // Pd=cmp.gt(Rs, Rt)
2507 // if (Pd.new) Rd=#0
2508 // if (!Pd.new) Rd=#1
2509 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2510 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rs),
2511 (i32 IntRegs:$Rt))),
2516 // zext( setult ( and(Rs, 255), u8))
2517 // Use the isdigit transformation below
2519 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
2520 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
2521 // The isdigit transformation relies on two 'clever' aspects:
2522 // 1) The data type is unsigned which allows us to eliminate a zero test after
2523 // biasing the expression by 48. We are depending on the representation of
2524 // the unsigned types, and semantics.
2525 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
2528 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
2529 // The code is transformed upstream of llvm into
2530 // retval = (c-48) < 10 ? 1 : 0;
2531 let AddedComplexity = 139 in
2532 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
2533 u7StrictPosImmPred:$src2)))),
2534 (i32 (MUX_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
2535 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
2539 // Pd=cmpb.gtu(Rs,Rt)
2540 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
2541 InputType = "reg" in
2542 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
2543 (ins IntRegs:$src1, IntRegs:$src2),
2544 "$dst = cmpb.gtu($src1, $src2)",
2545 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2546 (and (i32 IntRegs:$src2), 255)))]>,
2547 Requires<[HasV4T]>, ImmRegRel;
2549 // Following instruction is not being extended as it results into the incorrect
2550 // code for negative numbers.
2552 // Signed half compare(.eq) ri.
2553 // Pd=cmph.eq(Rs,#s8)
2554 let isCompare = 1, validSubTargets = HasV4SubT in
2555 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
2556 (ins IntRegs:$src1, s8Imm:$src2),
2557 "$dst = cmph.eq($src1, #$src2)",
2558 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
2559 s8ImmPred:$src2))]>,
2562 // Signed half compare(.eq) rr.
2563 // Case 1: xor + and, then compare:
2565 // r0=and(r0,#0xffff)
2567 // Pd=cmph.eq(Rs,Rt)
2568 let isCompare = 1, validSubTargets = HasV4SubT in
2569 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
2570 (ins IntRegs:$src1, IntRegs:$src2),
2571 "$dst = cmph.eq($src1, $src2)",
2572 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
2573 (i32 IntRegs:$src2)),
2577 // Signed half compare(.eq) rr.
2578 // Case 2: shift left 16 bits then compare:
2582 // Pd=cmph.eq(Rs,Rt)
2583 let isCompare = 1, validSubTargets = HasV4SubT in
2584 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
2585 (ins IntRegs:$src1, IntRegs:$src2),
2586 "$dst = cmph.eq($src1, $src2)",
2587 [(set (i1 PredRegs:$dst),
2588 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
2589 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2592 /* Incorrect Pattern -- immediate should be right shifted before being
2593 used in the cmph.gt instruction.
2594 // Signed half compare(.gt) ri.
2595 // Pd=cmph.gt(Rs,#s8)
2597 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
2598 isCompare = 1, validSubTargets = HasV4SubT in
2599 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
2600 (ins IntRegs:$src1, s8Ext:$src2),
2601 "$dst = cmph.gt($src1, #$src2)",
2602 [(set (i1 PredRegs:$dst),
2603 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2604 s8ExtPred:$src2))]>,
2608 // Signed half compare(.gt) rr.
2609 // Pd=cmph.gt(Rs,Rt)
2610 let isCompare = 1, validSubTargets = HasV4SubT in
2611 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
2612 (ins IntRegs:$src1, IntRegs:$src2),
2613 "$dst = cmph.gt($src1, $src2)",
2614 [(set (i1 PredRegs:$dst),
2615 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2616 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2619 // Unsigned half compare rr (.gtu).
2620 // Pd=cmph.gtu(Rs,Rt)
2621 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2622 InputType = "reg" in
2623 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
2624 (ins IntRegs:$src1, IntRegs:$src2),
2625 "$dst = cmph.gtu($src1, $src2)",
2626 [(set (i1 PredRegs:$dst),
2627 (setugt (and (i32 IntRegs:$src1), 65535),
2628 (and (i32 IntRegs:$src2), 65535)))]>,
2629 Requires<[HasV4T]>, ImmRegRel;
2631 // Unsigned half compare ri (.gtu).
2632 // Pd=cmph.gtu(Rs,#u7)
2633 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2634 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2635 InputType = "imm" in
2636 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
2637 (ins IntRegs:$src1, u7Ext:$src2),
2638 "$dst = cmph.gtu($src1, #$src2)",
2639 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
2640 u7ExtPred:$src2))]>,
2641 Requires<[HasV4T]>, ImmRegRel;
2643 let validSubTargets = HasV4SubT in
2644 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2645 "$dst = !tstbit($src1, $src2)",
2646 [(set (i1 PredRegs:$dst),
2647 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
2650 let validSubTargets = HasV4SubT in
2651 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2652 "$dst = !tstbit($src1, $src2)",
2653 [(set (i1 PredRegs:$dst),
2654 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
2657 //===----------------------------------------------------------------------===//
2659 //===----------------------------------------------------------------------===//
2661 //Deallocate frame and return.
2663 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
2664 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
2665 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
2671 // Restore registers and dealloc return function call.
2672 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2673 Defs = [R29, R30, R31, PC] in {
2674 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
2675 (ins calltarget:$dst),
2676 "jump $dst // Restore_and_dealloc_return",
2681 // Restore registers and dealloc frame before a tail call.
2682 let isCall = 1, isBarrier = 1,
2683 Defs = [R29, R30, R31, PC] in {
2684 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
2685 (ins calltarget:$dst),
2686 "call $dst // Restore_and_dealloc_before_tailcall",
2691 // Save registers function call.
2692 let isCall = 1, isBarrier = 1,
2693 Uses = [R29, R31] in {
2694 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
2695 (ins calltarget:$dst),
2696 "call $dst // Save_calle_saved_registers",
2701 // if (Ps) dealloc_return
2702 let isReturn = 1, isTerminator = 1,
2703 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2704 isPredicated = 1 in {
2705 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
2706 (ins PredRegs:$src1, i32imm:$amt1),
2707 "if ($src1) dealloc_return",
2712 // if (!Ps) dealloc_return
2713 let isReturn = 1, isTerminator = 1,
2714 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2715 isPredicated = 1 in {
2716 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2718 "if (!$src1) dealloc_return",
2723 // if (Ps.new) dealloc_return:nt
2724 let isReturn = 1, isTerminator = 1,
2725 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2726 isPredicated = 1 in {
2727 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2729 "if ($src1.new) dealloc_return:nt",
2734 // if (!Ps.new) dealloc_return:nt
2735 let isReturn = 1, isTerminator = 1,
2736 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2737 isPredicated = 1 in {
2738 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2740 "if (!$src1.new) dealloc_return:nt",
2745 // if (Ps.new) dealloc_return:t
2746 let isReturn = 1, isTerminator = 1,
2747 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2748 isPredicated = 1 in {
2749 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2751 "if ($src1.new) dealloc_return:t",
2756 // if (!Ps.new) dealloc_return:nt
2757 let isReturn = 1, isTerminator = 1,
2758 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
2759 isPredicated = 1 in {
2760 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
2762 "if (!$src1.new) dealloc_return:t",
2767 // Load/Store with absolute addressing mode
2770 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2772 let isPredicatedNew = isPredNew in
2773 def NAME#_V4 : STInst2<(outs),
2774 (ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
2775 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2776 ") ")#mnemonic#"(##$absaddr) = $src2",
2781 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2782 let isPredicatedFalse = PredNot in {
2783 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2785 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2789 let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
2790 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2791 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2792 let opExtendable = 0, isPredicable = 1 in
2793 def NAME#_V4 : STInst2<(outs),
2794 (ins globaladdressExt:$absaddr, RC:$src),
2795 mnemonic#"(##$absaddr) = $src",
2799 let opExtendable = 1, isPredicated = 1 in {
2800 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
2801 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
2806 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
2808 let isPredicatedNew = isPredNew in
2809 def NAME#_nv_V4 : NVInst_V4<(outs),
2810 (ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
2811 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2812 ") ")#mnemonic#"(##$absaddr) = $src2.new",
2817 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
2818 let isPredicatedFalse = PredNot in {
2819 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
2821 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
2825 let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
2826 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
2827 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2828 let opExtendable = 0, isPredicable = 1 in
2829 def NAME#_nv_V4 : NVInst_V4<(outs),
2830 (ins globaladdressExt:$absaddr, RC:$src),
2831 mnemonic#"(##$absaddr) = $src.new",
2835 let opExtendable = 1, isPredicated = 1 in {
2836 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2837 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2842 let addrMode = Absolute in {
2843 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
2844 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
2846 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
2847 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
2849 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
2850 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
2852 let isNVStorable = 0 in
2853 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
2856 let Predicates = [HasV4T], AddedComplexity = 30 in {
2857 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2858 (HexagonCONST32 tglobaladdr:$absaddr)),
2859 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2861 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2862 (HexagonCONST32 tglobaladdr:$absaddr)),
2863 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2865 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
2866 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2868 def : Pat<(store (i64 DoubleRegs:$src1),
2869 (HexagonCONST32 tglobaladdr:$absaddr)),
2870 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
2873 //===----------------------------------------------------------------------===//
2874 // multiclass for store instructions with GP-relative addressing mode.
2875 // mem[bhwd](#global)=Rt
2876 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
2877 //===----------------------------------------------------------------------===//
2878 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
2879 let BaseOpcode = BaseOp, isPredicable = 1 in
2880 def NAME#_V4 : STInst2<(outs),
2881 (ins globaladdress:$global, RC:$src),
2882 mnemonic#"(#$global) = $src",
2885 // When GP-relative instructions are predicated, their addressing mode is
2886 // changed to absolute and they are always constant extended.
2887 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2888 isPredicated = 1 in {
2889 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
2890 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
2894 let mayStore = 1, isNVStore = 1 in
2895 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
2896 let BaseOpcode = BaseOp, isPredicable = 1 in
2897 def NAME#_nv_V4 : NVInst_V4<(outs),
2898 (ins u0AlwaysExt:$global, RC:$src),
2899 mnemonic#"(#$global) = $src.new",
2903 // When GP-relative instructions are predicated, their addressing mode is
2904 // changed to absolute and they are always constant extended.
2905 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2906 isPredicated = 1 in {
2907 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2908 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2912 let validSubTargets = HasV4SubT, validSubTargets = HasV4SubT in {
2913 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>,
2914 ST_GP_nv<"memd", "STd_GP", DoubleRegs>, NewValueRel ;
2915 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
2916 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel ;
2917 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
2918 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel ;
2919 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
2920 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel ;
2923 // 64 bit atomic store
2924 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2925 (i64 DoubleRegs:$src1)),
2926 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2929 // Map from store(globaladdress) -> memd(#foo)
2930 let AddedComplexity = 100 in
2931 def : Pat <(store (i64 DoubleRegs:$src1),
2932 (HexagonCONST32_GP tglobaladdr:$global)),
2933 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
2935 // 8 bit atomic store
2936 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2937 (i32 IntRegs:$src1)),
2938 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2940 // Map from store(globaladdress) -> memb(#foo)
2941 let AddedComplexity = 100 in
2942 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2943 (HexagonCONST32_GP tglobaladdr:$global)),
2944 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2946 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2947 // to "r0 = 1; memw(#foo) = r0"
2948 let AddedComplexity = 100 in
2949 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2950 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>;
2952 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2953 (i32 IntRegs:$src1)),
2954 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2956 // Map from store(globaladdress) -> memh(#foo)
2957 let AddedComplexity = 100 in
2958 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2959 (HexagonCONST32_GP tglobaladdr:$global)),
2960 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2962 // 32 bit atomic store
2963 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2964 (i32 IntRegs:$src1)),
2965 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2967 // Map from store(globaladdress) -> memw(#foo)
2968 let AddedComplexity = 100 in
2969 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2970 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2972 //===----------------------------------------------------------------------===//
2973 // Multiclass for the load instructions with absolute addressing mode.
2974 //===----------------------------------------------------------------------===//
2975 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2977 let isPredicatedNew = isPredNew in
2978 def NAME : LDInst2<(outs RC:$dst),
2979 (ins PredRegs:$src1, globaladdressExt:$absaddr),
2980 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2981 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
2986 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2987 let isPredicatedFalse = PredNot in {
2988 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2990 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2994 let isExtended = 1, neverHasSideEffects = 1 in
2995 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2996 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2997 let opExtendable = 1, isPredicable = 1 in
2998 def NAME#_V4 : LDInst2<(outs RC:$dst),
2999 (ins globaladdressExt:$absaddr),
3000 "$dst = "#mnemonic#"(##$absaddr)",
3004 let opExtendable = 2, isPredicated = 1 in {
3005 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3006 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3011 let addrMode = Absolute in {
3012 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
3013 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
3014 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
3015 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
3016 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
3017 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
3020 let Predicates = [HasV4T], AddedComplexity = 30 in
3021 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3022 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
3024 let Predicates = [HasV4T], AddedComplexity=30 in
3025 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3026 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
3028 let Predicates = [HasV4T], AddedComplexity=30 in
3029 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3030 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
3032 let Predicates = [HasV4T], AddedComplexity=30 in
3033 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3034 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
3036 let Predicates = [HasV4T], AddedComplexity=30 in
3037 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3038 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
3040 //===----------------------------------------------------------------------===//
3041 // multiclass for load instructions with GP-relative addressing mode.
3042 // Rx=mem[bhwd](##global)
3043 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3044 //===----------------------------------------------------------------------===//
3045 let neverHasSideEffects = 1, validSubTargets = HasV4SubT in
3046 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3047 let BaseOpcode = BaseOp in {
3048 let isPredicable = 1 in
3049 def NAME#_V4 : LDInst2<(outs RC:$dst),
3050 (ins globaladdress:$global),
3051 "$dst = "#mnemonic#"(#$global)",
3054 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
3055 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3056 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3061 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>;
3062 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>;
3063 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>;
3064 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>;
3065 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>;
3066 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>;
3068 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3069 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3071 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3072 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3074 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3075 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3077 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3078 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3080 // Map from load(globaladdress) -> memw(#foo + 0)
3081 let AddedComplexity = 100 in
3082 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3083 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3085 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3086 let AddedComplexity = 100 in
3087 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3088 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
3090 // When the Interprocedural Global Variable optimizer realizes that a certain
3091 // global variable takes only two constant values, it shrinks the global to
3092 // a boolean. Catch those loads here in the following 3 patterns.
3093 let AddedComplexity = 100 in
3094 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3095 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3097 let AddedComplexity = 100 in
3098 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3099 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3101 // Map from load(globaladdress) -> memb(#foo)
3102 let AddedComplexity = 100 in
3103 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3104 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3106 // Map from load(globaladdress) -> memb(#foo)
3107 let AddedComplexity = 100 in
3108 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3109 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3111 let AddedComplexity = 100 in
3112 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3113 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3115 // Map from load(globaladdress) -> memub(#foo)
3116 let AddedComplexity = 100 in
3117 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3118 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3120 // Map from load(globaladdress) -> memh(#foo)
3121 let AddedComplexity = 100 in
3122 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3123 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3125 // Map from load(globaladdress) -> memh(#foo)
3126 let AddedComplexity = 100 in
3127 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3128 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3130 // Map from load(globaladdress) -> memuh(#foo)
3131 let AddedComplexity = 100 in
3132 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3133 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3135 // Map from load(globaladdress) -> memw(#foo)
3136 let AddedComplexity = 100 in
3137 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3138 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3141 // Transfer global address into a register
3142 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
3143 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
3145 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3148 // Transfer a block address into a register
3149 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3150 (TFRI_V4 tblockaddress:$src1)>,
3153 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3154 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3155 (ins PredRegs:$src1, globaladdress:$src2),
3156 "if($src1) $dst = ##$src2",
3160 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3161 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3162 (ins PredRegs:$src1, globaladdress:$src2),
3163 "if(!$src1) $dst = ##$src2",
3167 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3168 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3169 (ins PredRegs:$src1, globaladdress:$src2),
3170 "if($src1.new) $dst = ##$src2",
3174 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3175 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3176 (ins PredRegs:$src1, globaladdress:$src2),
3177 "if(!$src1.new) $dst = ##$src2",
3181 let AddedComplexity = 50, Predicates = [HasV4T] in
3182 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3183 (TFRI_V4 tglobaladdr:$src1)>;
3186 // Load - Indirect with long offset: These instructions take global address
3188 let AddedComplexity = 10 in
3189 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3190 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
3191 "$dst=memd($src1<<#$src2+##$offset)",
3192 [(set (i64 DoubleRegs:$dst),
3193 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3194 (HexagonCONST32 tglobaladdr:$offset))))]>,
3197 let AddedComplexity = 10 in
3198 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3199 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3200 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
3201 !strconcat("$dst = ",
3202 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3204 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3205 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3209 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3210 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3211 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3212 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3213 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3215 // Store - Indirect with long offset: These instructions take global address
3217 let AddedComplexity = 10 in
3218 def STrid_ind_lo_V4 : STInst<(outs),
3219 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
3221 "memd($src1<<#$src2+#$src3) = $src4",
3222 [(store (i64 DoubleRegs:$src4),
3223 (add (shl IntRegs:$src1, u2ImmPred:$src2),
3224 (HexagonCONST32 tglobaladdr:$src3)))]>,
3227 let AddedComplexity = 10 in
3228 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
3229 def _lo_V4 : STInst<(outs),
3230 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
3232 !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
3233 [(OpNode (i32 IntRegs:$src4),
3234 (add (shl IntRegs:$src1, u2ImmPred:$src2),
3235 (HexagonCONST32 tglobaladdr:$src3)))]>,
3239 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
3240 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
3241 defm STriw_ind : ST_indirect_lo<"memw", store>;
3243 // Store - absolute addressing mode: These instruction take constant
3244 // value as the extended operand.
3245 multiclass ST_absimm<string OpcStr> {
3246 let isExtended = 1, opExtendable = 0, isPredicable = 1,
3247 validSubTargets = HasV4SubT in
3248 def _abs_V4 : STInst2<(outs),
3249 (ins u0AlwaysExt:$src1, IntRegs:$src2),
3250 !strconcat(OpcStr, "(##$src1) = $src2"),
3254 let isExtended = 1, opExtendable = 1, isPredicated = 1,
3255 validSubTargets = HasV4SubT in {
3256 def _abs_cPt_V4 : STInst2<(outs),
3257 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3258 !strconcat("if ($src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
3262 def _abs_cNotPt_V4 : STInst2<(outs),
3263 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3264 !strconcat("if (!$src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
3268 def _abs_cdnPt_V4 : STInst2<(outs),
3269 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3270 !strconcat("if ($src1.new)",
3271 !strconcat(OpcStr, "(##$src2) = $src3")),
3275 def _abs_cdnNotPt_V4 : STInst2<(outs),
3276 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3277 !strconcat("if (!$src1.new)",
3278 !strconcat(OpcStr, "(##$src2) = $src3")),
3283 let isExtended = 1, opExtendable = 0, mayStore = 1, isNVStore = 1,
3284 validSubTargets = HasV4SubT in
3285 def _abs_nv_V4 : NVInst_V4<(outs),
3286 (ins u0AlwaysExt:$src1, IntRegs:$src2),
3287 !strconcat(OpcStr, "(##$src1) = $src2.new"),
3291 let isExtended = 1, opExtendable = 1, mayStore = 1, isPredicated = 1,
3292 isNVStore = 1, validSubTargets = HasV4SubT in {
3293 def _abs_cPt_nv_V4 : NVInst_V4<(outs),
3294 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3295 !strconcat("if ($src1)",
3296 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3300 def _abs_cNotPt_nv_V4 : NVInst_V4<(outs),
3301 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3302 !strconcat("if (!$src1)",
3303 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3307 def _abs_cdnPt_nv_V4 : NVInst_V4<(outs),
3308 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3309 !strconcat("if ($src1.new)",
3310 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3314 def _abs_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3315 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3316 !strconcat("if (!$src1.new)",
3317 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3323 defm STrib_imm : ST_absimm<"memb">;
3324 defm STrih_imm : ST_absimm<"memh">;
3325 defm STriw_imm : ST_absimm<"memw">;
3327 let Predicates = [HasV4T], AddedComplexity = 30 in {
3328 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3329 (STrib_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3331 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3332 (STrih_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3334 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3335 (STriw_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3338 // Load - absolute addressing mode: These instruction take constant
3339 // value as the extended operand
3341 multiclass LD_absimm<string OpcStr> {
3342 let isExtended = 1, opExtendable = 1, isPredicable = 1,
3343 validSubTargets = HasV4SubT in
3344 def _abs_V4 : LDInst2<(outs IntRegs:$dst),
3345 (ins u0AlwaysExt:$src),
3346 !strconcat("$dst = ",
3347 !strconcat(OpcStr, "(##$src)")),
3351 let isExtended = 1, opExtendable = 2, isPredicated = 1,
3352 validSubTargets = HasV4SubT in {
3353 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
3354 (ins PredRegs:$src1, u0AlwaysExt:$src2),
3355 !strconcat("if ($src1) $dst = ",
3356 !strconcat(OpcStr, "(##$src2)")),
3360 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
3361 (ins PredRegs:$src1, u0AlwaysExt:$src2),
3362 !strconcat("if (!$src1) $dst = ",
3363 !strconcat(OpcStr, "(##$src2)")),
3367 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
3368 (ins PredRegs:$src1, u0AlwaysExt:$src2),
3369 !strconcat("if ($src1.new) $dst = ",
3370 !strconcat(OpcStr, "(##$src2)")),
3374 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
3375 (ins PredRegs:$src1, u0AlwaysExt:$src2),
3376 !strconcat("if (!$src1.new) $dst = ",
3377 !strconcat(OpcStr, "(##$src2)")),
3383 defm LDrib_imm : LD_absimm<"memb">;
3384 defm LDriub_imm : LD_absimm<"memub">;
3385 defm LDrih_imm : LD_absimm<"memh">;
3386 defm LDriuh_imm : LD_absimm<"memuh">;
3387 defm LDriw_imm : LD_absimm<"memw">;
3389 let Predicates = [HasV4T], AddedComplexity = 30 in {
3390 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3391 (LDriw_imm_abs_V4 u0AlwaysExtPred:$src)>;
3393 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3394 (LDrib_imm_abs_V4 u0AlwaysExtPred:$src)>;
3396 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3397 (LDriub_imm_abs_V4 u0AlwaysExtPred:$src)>;
3399 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3400 (LDrih_imm_abs_V4 u0AlwaysExtPred:$src)>;
3402 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3403 (LDriuh_imm_abs_V4 u0AlwaysExtPred:$src)>;
3406 // Indexed store double word - global address.
3407 // memw(Rs+#u6:2)=#S8
3408 let AddedComplexity = 10 in
3409 def STriw_offset_ext_V4 : STInst<(outs),
3410 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3411 "memw($src1+#$src2) = ##$src3",
3412 [(store (HexagonCONST32 tglobaladdr:$src3),
3413 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3417 // Indexed store double word - global address.
3418 // memw(Rs+#u6:2)=#S8
3419 let AddedComplexity = 10 in
3420 def STrih_offset_ext_V4 : STInst<(outs),
3421 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3422 "memh($src1+#$src2) = ##$src3",
3423 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3424 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3426 // Map from store(globaladdress + x) -> memd(#foo + x)
3427 let AddedComplexity = 100 in
3428 def : Pat<(store (i64 DoubleRegs:$src1),
3429 FoldGlobalAddrGP:$addr),
3430 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3433 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3434 (i64 DoubleRegs:$src1)),
3435 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3438 // Map from store(globaladdress + x) -> memb(#foo + x)
3439 let AddedComplexity = 100 in
3440 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3441 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3444 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3445 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3448 // Map from store(globaladdress + x) -> memh(#foo + x)
3449 let AddedComplexity = 100 in
3450 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3451 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3454 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3455 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3458 // Map from store(globaladdress + x) -> memw(#foo + x)
3459 let AddedComplexity = 100 in
3460 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3461 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3464 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3465 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3468 // Map from load(globaladdress + x) -> memd(#foo + x)
3469 let AddedComplexity = 100 in
3470 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3471 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3474 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3475 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3478 // Map from load(globaladdress + x) -> memb(#foo + x)
3479 let AddedComplexity = 100 in
3480 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3481 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3484 // Map from load(globaladdress + x) -> memb(#foo + x)
3485 let AddedComplexity = 100 in
3486 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3487 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3490 //let AddedComplexity = 100 in
3491 let AddedComplexity = 100 in
3492 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3493 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3496 // Map from load(globaladdress + x) -> memh(#foo + x)
3497 let AddedComplexity = 100 in
3498 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3499 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3502 // Map from load(globaladdress + x) -> memuh(#foo + x)
3503 let AddedComplexity = 100 in
3504 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3505 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3508 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3509 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3512 // Map from load(globaladdress + x) -> memub(#foo + x)
3513 let AddedComplexity = 100 in
3514 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3515 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3518 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3519 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3522 // Map from load(globaladdress + x) -> memw(#foo + x)
3523 let AddedComplexity = 100 in
3524 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3525 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
3528 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3529 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,