1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in
15 class T_Immext<dag ins> :
16 EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
20 def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
21 def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
22 def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
24 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
25 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
27 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
28 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
30 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
31 (HexagonCONST32 node:$addr), [{
32 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
35 // Hexagon V4 Architecture spec defines 8 instruction classes:
36 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
40 // ========================================
41 // Loads (8/16/32/64 bit)
45 // ========================================
46 // Stores (8/16/32/64 bit)
49 // ALU32 Instructions:
50 // ========================================
51 // Arithmetic / Logical (32 bit)
54 // XTYPE Instructions (32/64 bit):
55 // ========================================
56 // Arithmetic, Logical, Bit Manipulation
57 // Multiply (Integer, Fractional, Complex)
58 // Permute / Vector Permute Operations
59 // Predicate Operations
60 // Shift / Shift with Add/Sub/Logical
62 // Vector Halfword (ALU, Shift, Multiply)
63 // Vector Word (ALU, Shift)
66 // ========================================
67 // Jump/Call PC-relative
70 // ========================================
73 // MEMOP Instructions:
74 // ========================================
75 // Operation on memory (8/16/32 bit)
78 // ========================================
83 // ========================================
84 // Control-Register Transfers
85 // Hardware Loop Setup
86 // Predicate Logicals & Reductions
88 // SYSTEM Instructions (not implemented in the compiler):
89 // ========================================
95 //===----------------------------------------------------------------------===//
97 //===----------------------------------------------------------------------===//
98 // Generate frame index addresses.
99 let neverHasSideEffects = 1, isReMaterializable = 1,
100 isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
101 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
102 (ins IntRegs:$src1, s32Imm:$offset),
103 "$dst = add($src1, ##$offset)",
108 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
109 isExtentSigned = 1, opExtentBits = 8 in
110 def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
111 (ins IntRegs:$Rs, s8Ext:$s8),
112 "$Rd = cmp.eq($Rs, #$s8)",
113 [(set (i32 IntRegs:$Rd),
114 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
115 s8ExtPred:$s8)))))]>,
118 // Preserve the TSTBIT generation
119 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
120 (i32 IntRegs:$src1))), 0)))),
121 (i32 (MUX_ii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
124 // Interfered with tstbit generation, above pattern preserves, see : tstbit.ll
126 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
127 isExtentSigned = 1, opExtentBits = 8 in
128 def V4_A4_rcmpneqi : ALU32_ri<(outs IntRegs:$Rd),
129 (ins IntRegs:$Rs, s8Ext:$s8),
130 "$Rd = !cmp.eq($Rs, #$s8)",
131 [(set (i32 IntRegs:$Rd),
132 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
133 s8ExtPred:$s8)))))]>,
137 let validSubTargets = HasV4SubT in
138 def V4_A4_rcmpeq : ALU32_ri<(outs IntRegs:$Rd),
139 (ins IntRegs:$Rs, IntRegs:$Rt),
140 "$Rd = cmp.eq($Rs, $Rt)",
141 [(set (i32 IntRegs:$Rd),
142 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
147 let validSubTargets = HasV4SubT in
148 def V4_A4_rcmpneq : ALU32_ri<(outs IntRegs:$Rd),
149 (ins IntRegs:$Rs, IntRegs:$Rt),
150 "$Rd = !cmp.eq($Rs, $Rt)",
151 [(set (i32 IntRegs:$Rd),
152 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
156 //===----------------------------------------------------------------------===//
158 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
163 //===----------------------------------------------------------------------===//
166 // Rdd=combine(Rs, #s8)
167 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
168 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
169 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
170 (ins IntRegs:$src1, s8Ext:$src2),
171 "$dst = combine($src1, #$src2)",
175 // Rdd=combine(#s8, Rs)
176 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
177 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
178 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
179 (ins s8Ext:$src1, IntRegs:$src2),
180 "$dst = combine(#$src1, $src2)",
184 def HexagonWrapperCombineRI_V4 :
185 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
186 def HexagonWrapperCombineIR_V4 :
187 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
189 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
190 (COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>,
193 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
194 (COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>,
197 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
198 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
199 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
200 (ins s8Imm:$src1, u6Ext:$src2),
201 "$dst = combine(#$src1, #$src2)",
205 //===----------------------------------------------------------------------===//
207 //===----------------------------------------------------------------------===//
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
213 // Template class for load instructions with Absolute set addressing mode.
214 //===----------------------------------------------------------------------===//
215 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
216 validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
217 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
218 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
219 (ins u0AlwaysExt:$addr),
220 "$dst1 = "#mnemonic#"($dst2=##$addr)",
224 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
225 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
226 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
227 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
228 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
229 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
232 // multiclass for load instructions with base + register offset
234 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
236 let isPredicatedNew = isPredNew in
237 def NAME : LDInst2<(outs RC:$dst),
238 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
239 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
240 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
241 []>, Requires<[HasV4T]>;
244 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
245 let isPredicatedFalse = PredNot in {
246 defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
248 defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
252 let neverHasSideEffects = 1 in
253 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
254 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
255 let isPredicable = 1 in
256 def NAME#_V4 : LDInst2<(outs RC:$dst),
257 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
258 "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
259 []>, Requires<[HasV4T]>;
261 let isPredicated = 1 in {
262 defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
263 defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
268 let addrMode = BaseRegOffset in {
269 let accessSize = ByteAccess in {
270 defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>,
272 defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>,
275 let accessSize = HalfWordAccess in {
276 defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
277 defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>,
280 let accessSize = WordAccess in
281 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
283 let accessSize = DoubleWordAccess in
284 defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>,
288 // 'def pats' for load instructions with base + register offset and non-zero
289 // immediate value. Immediate value is used to left-shift the second
291 let AddedComplexity = 40 in {
292 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
293 (shl IntRegs:$src2, u2ImmPred:$offset)))),
294 (LDrib_indexed_shl_V4 IntRegs:$src1,
295 IntRegs:$src2, u2ImmPred:$offset)>,
298 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
299 (shl IntRegs:$src2, u2ImmPred:$offset)))),
300 (LDriub_indexed_shl_V4 IntRegs:$src1,
301 IntRegs:$src2, u2ImmPred:$offset)>,
304 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
305 (shl IntRegs:$src2, u2ImmPred:$offset)))),
306 (LDriub_indexed_shl_V4 IntRegs:$src1,
307 IntRegs:$src2, u2ImmPred:$offset)>,
310 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
311 (shl IntRegs:$src2, u2ImmPred:$offset)))),
312 (LDrih_indexed_shl_V4 IntRegs:$src1,
313 IntRegs:$src2, u2ImmPred:$offset)>,
316 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
317 (shl IntRegs:$src2, u2ImmPred:$offset)))),
318 (LDriuh_indexed_shl_V4 IntRegs:$src1,
319 IntRegs:$src2, u2ImmPred:$offset)>,
322 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
323 (shl IntRegs:$src2, u2ImmPred:$offset)))),
324 (LDriuh_indexed_shl_V4 IntRegs:$src1,
325 IntRegs:$src2, u2ImmPred:$offset)>,
328 def : Pat <(i32 (load (add IntRegs:$src1,
329 (shl IntRegs:$src2, u2ImmPred:$offset)))),
330 (LDriw_indexed_shl_V4 IntRegs:$src1,
331 IntRegs:$src2, u2ImmPred:$offset)>,
334 def : Pat <(i64 (load (add IntRegs:$src1,
335 (shl IntRegs:$src2, u2ImmPred:$offset)))),
336 (LDrid_indexed_shl_V4 IntRegs:$src1,
337 IntRegs:$src2, u2ImmPred:$offset)>,
342 // 'def pats' for load instruction base + register offset and
343 // zero immediate value.
344 let AddedComplexity = 10 in {
345 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
346 (LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
349 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
350 (LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
353 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
354 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
357 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
358 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
361 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
362 (LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
365 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
366 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
369 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
370 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
373 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
374 (LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
379 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
380 (i64 (COMBINE_Ir_V4 0, (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
384 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
385 (i64 (COMBINE_Ir_V4 0, (i32 IntRegs:$src1)))>,
388 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
389 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
392 let AddedComplexity = 20 in
393 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
394 s11_0ExtPred:$offset))),
395 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
396 s11_0ExtPred:$offset)))>,
400 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
401 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
404 let AddedComplexity = 20 in
405 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
406 s11_0ExtPred:$offset))),
407 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
408 s11_0ExtPred:$offset)))>,
412 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
413 (i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>,
416 let AddedComplexity = 20 in
417 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
418 s11_1ExtPred:$offset))),
419 (i64 (COMBINE_Ir_V4 0, (LDriuh_indexed IntRegs:$src1,
420 s11_1ExtPred:$offset)))>,
424 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
425 (i64 (COMBINE_Ir_V4 0, (LDrih ADDRriS11_2:$src1)))>,
428 let AddedComplexity = 20 in
429 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
430 s11_1ExtPred:$offset))),
431 (i64 (COMBINE_Ir_V4 0, (LDrih_indexed IntRegs:$src1,
432 s11_1ExtPred:$offset)))>,
436 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
437 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
440 let AddedComplexity = 100 in
441 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
442 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
443 s11_2ExtPred:$offset)))>,
447 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
448 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
451 let AddedComplexity = 100 in
452 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
453 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
454 s11_2ExtPred:$offset)))>,
459 //===----------------------------------------------------------------------===//
461 //===----------------------------------------------------------------------===//
463 //===----------------------------------------------------------------------===//
465 //===----------------------------------------------------------------------===//
467 //===----------------------------------------------------------------------===//
468 // Template class for store instructions with Absolute set addressing mode.
469 //===----------------------------------------------------------------------===//
470 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
471 addrMode = AbsoluteSet in
472 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
473 STInst2<(outs IntRegs:$dst1),
474 (ins RC:$src1, u0AlwaysExt:$src2),
475 mnemonic#"($dst1=##$src2) = $src1",
479 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
480 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
481 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
482 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
484 //===----------------------------------------------------------------------===//
485 // multiclass for store instructions with base + register offset addressing
487 //===----------------------------------------------------------------------===//
488 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
490 let isPredicatedNew = isPredNew in
491 def NAME : STInst2<(outs),
492 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
494 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
495 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
500 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
501 let isPredicatedFalse = PredNot in {
502 defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
504 defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
508 let isNVStorable = 1 in
509 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
510 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
511 let isPredicable = 1 in
512 def NAME#_V4 : STInst2<(outs),
513 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
514 mnemonic#"($src1+$src2<<#$src3) = $src4",
518 let isPredicated = 1 in {
519 defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
520 defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
525 // multiclass for new-value store instructions with base + register offset
527 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
529 let isPredicatedNew = isPredNew in
530 def NAME#_nv_V4 : NVInst_V4<(outs),
531 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
533 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
534 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
539 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
540 let isPredicatedFalse = PredNot in {
541 defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
543 defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
547 let mayStore = 1, isNVStore = 1 in
548 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
549 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
550 let isPredicable = 1 in
551 def NAME#_nv_V4 : NVInst_V4<(outs),
552 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
553 mnemonic#"($src1+$src2<<#$src3) = $src4.new",
557 let isPredicated = 1 in {
558 defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
559 defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
564 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
565 validSubTargets = HasV4SubT in {
566 let accessSize = ByteAccess in
567 defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
568 ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
570 let accessSize = HalfWordAccess in
571 defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
572 ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
574 let accessSize = WordAccess in
575 defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
576 ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
578 let isNVStorable = 0, accessSize = DoubleWordAccess in
579 defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
582 let Predicates = [HasV4T], AddedComplexity = 10 in {
583 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
584 (add IntRegs:$src1, (shl IntRegs:$src2,
586 (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
587 u2ImmPred:$src3, IntRegs:$src4)>;
589 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
590 (add IntRegs:$src1, (shl IntRegs:$src2,
592 (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
593 u2ImmPred:$src3, IntRegs:$src4)>;
595 def : Pat<(store (i32 IntRegs:$src4),
596 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
597 (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
598 u2ImmPred:$src3, IntRegs:$src4)>;
600 def : Pat<(store (i64 DoubleRegs:$src4),
601 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
602 (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
603 u2ImmPred:$src3, DoubleRegs:$src4)>;
606 let isExtended = 1, opExtendable = 2 in
607 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
609 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
610 mnemonic#"($src1<<#$src2+##$src3) = $src4",
611 [(stOp (VT RC:$src4),
612 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
613 u0AlwaysExtPred:$src3))]>,
616 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
617 class T_ST_LongOff_nv <string mnemonic> :
619 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
620 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
624 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
625 let BaseOpcode = BaseOp#"_shl" in {
626 let isNVStorable = 1 in
627 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
629 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
633 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
634 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
635 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
636 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
637 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
640 let AddedComplexity = 40 in
641 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
643 def : Pat<(stOp (VT RC:$src4),
644 (add (shl IntRegs:$src1, u2ImmPred:$src2),
645 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
646 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
648 def : Pat<(stOp (VT RC:$src4),
650 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
651 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
654 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
655 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
656 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
657 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
659 // memd(Rx++#s4:3)=Rtt
660 // memd(Rx++#s4:3:circ(Mu))=Rtt
661 // memd(Rx++I:circ(Mu))=Rtt
663 // memd(Rx++Mu:brev)=Rtt
664 // memd(gp+#u16:3)=Rtt
666 // Store doubleword conditionally.
667 // if ([!]Pv[.new]) memd(#u6)=Rtt
668 // TODO: needs to be implemented.
670 //===----------------------------------------------------------------------===//
671 // multiclass for store instructions with base + immediate offset
672 // addressing mode and immediate stored value.
673 // mem[bhw](Rx++#s4:3)=#s8
674 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
675 //===----------------------------------------------------------------------===//
676 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
678 let isPredicatedNew = isPredNew in
679 def NAME : STInst2<(outs),
680 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
681 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
682 ") ")#mnemonic#"($src2+#$src3) = #$src4",
687 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
688 let isPredicatedFalse = PredNot in {
689 defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
691 defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
695 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
696 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
697 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
698 let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
699 def NAME#_V4 : STInst2<(outs),
700 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
701 mnemonic#"($src1+#$src2) = #$src3",
705 let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
706 defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
707 defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
712 let addrMode = BaseImmOffset, InputType = "imm",
713 validSubTargets = HasV4SubT in {
714 let accessSize = ByteAccess in
715 defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
717 let accessSize = HalfWordAccess in
718 defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
720 let accessSize = WordAccess in
721 defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
724 let Predicates = [HasV4T], AddedComplexity = 10 in {
725 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
726 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
728 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
730 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
732 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
733 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
736 let AddedComplexity = 6 in
737 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
738 (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
741 // memb(Rx++#s4:0:circ(Mu))=Rt
742 // memb(Rx++I:circ(Mu))=Rt
744 // memb(Rx++Mu:brev)=Rt
745 // memb(gp+#u16:0)=Rt
749 // TODO: needs to be implemented
751 // memh(Rs+#s11:1)=Rt.H
752 let AddedComplexity = 6 in
753 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
754 (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
757 // memh(Rs+Ru<<#u2)=Rt.H
758 // TODO: needs to be implemented.
760 // memh(Ru<<#u2+#U6)=Rt.H
761 // memh(Rx++#s4:1:circ(Mu))=Rt.H
762 // memh(Rx++#s4:1:circ(Mu))=Rt
763 // memh(Rx++I:circ(Mu))=Rt.H
764 // memh(Rx++I:circ(Mu))=Rt
767 // memh(Rx++Mu:brev)=Rt.H
768 // memh(Rx++Mu:brev)=Rt
769 // memh(gp+#u16:1)=Rt
770 // if ([!]Pv[.new]) memh(#u6)=Rt.H
771 // if ([!]Pv[.new]) memh(#u6)=Rt
774 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
775 // TODO: needs to be implemented.
777 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
778 // TODO: Needs to be implemented.
782 // TODO: Needs to be implemented.
785 let neverHasSideEffects = 1 in
786 def STriw_pred_V4 : STInst2<(outs),
787 (ins MEMri:$addr, PredRegs:$src1),
788 "Error; should not emit",
792 let AddedComplexity = 6 in
793 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
794 (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
797 // memw(Rx++#s4:2)=Rt
798 // memw(Rx++#s4:2:circ(Mu))=Rt
799 // memw(Rx++I:circ(Mu))=Rt
801 // memw(Rx++Mu:brev)=Rt
803 //===----------------------------------------------------------------------===
805 //===----------------------------------------------------------------------===
808 //===----------------------------------------------------------------------===//
810 //===----------------------------------------------------------------------===//
812 // multiclass for new-value store instructions with base + immediate offset.
814 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
815 Operand predImmOp, bit isNot, bit isPredNew> {
816 let isPredicatedNew = isPredNew in
817 def NAME#_nv_V4 : NVInst_V4<(outs),
818 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
819 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
820 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
825 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
827 let isPredicatedFalse = PredNot in {
828 defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
830 defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
834 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
835 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
836 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
837 bits<5> PredImmBits> {
839 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
840 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
842 def NAME#_nv_V4 : NVInst_V4<(outs),
843 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
844 mnemonic#"($src1+#$src2) = $src3.new",
848 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
849 isPredicated = 1 in {
850 defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
851 defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
856 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
857 let accessSize = ByteAccess in
858 defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
859 u6_0Ext, 11, 6>, AddrModeRel;
861 let accessSize = HalfWordAccess in
862 defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
863 u6_1Ext, 12, 7>, AddrModeRel;
865 let accessSize = WordAccess in
866 defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
867 u6_2Ext, 13, 8>, AddrModeRel;
870 // multiclass for new-value store instructions with base + immediate offset.
871 // and MEMri operand.
872 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
874 let isPredicatedNew = isPredNew in
875 def NAME#_nv_V4 : NVInst_V4<(outs),
876 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
877 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
878 ") ")#mnemonic#"($addr) = $src2.new",
883 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
884 let isPredicatedFalse = PredNot in {
885 defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
888 defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
892 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
893 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
894 bits<5> ImmBits, bits<5> PredImmBits> {
896 let CextOpcode = CextOp, BaseOpcode = CextOp in {
897 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
899 def NAME#_nv_V4 : NVInst_V4<(outs),
900 (ins MEMri:$addr, RC:$src),
901 mnemonic#"($addr) = $src.new",
905 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
906 neverHasSideEffects = 1, isPredicated = 1 in {
907 defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
908 defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
913 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
915 let accessSize = ByteAccess in
916 defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
918 let accessSize = HalfWordAccess in
919 defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
921 let accessSize = WordAccess in
922 defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
925 //===----------------------------------------------------------------------===//
926 // Post increment store
927 // mem[bhwd](Rx++#s4:[0123])=Nt.new
928 //===----------------------------------------------------------------------===//
930 multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
931 bit isNot, bit isPredNew> {
932 let isPredicatedNew = isPredNew in
933 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
934 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
935 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
936 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
942 multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
943 Operand ImmOp, bit PredNot> {
944 let isPredicatedFalse = PredNot in {
945 defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
947 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
948 defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
952 let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
953 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
956 let BaseOpcode = "POST_"#BaseOp in {
957 let isPredicable = 1 in
958 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
959 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
960 mnemonic#"($src1++#$offset) = $src2.new",
965 let isPredicated = 1 in {
966 defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
967 defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
972 let addrMode = PostInc, validSubTargets = HasV4SubT in {
973 defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
974 defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
975 defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
978 // memb(Rx++#s4:0:circ(Mu))=Nt.new
979 // memb(Rx++I:circ(Mu))=Nt.new
980 // memb(Rx++Mu)=Nt.new
981 // memb(Rx++Mu:brev)=Nt.new
982 // memh(Rx++#s4:1:circ(Mu))=Nt.new
983 // memh(Rx++I:circ(Mu))=Nt.new
984 // memh(Rx++Mu)=Nt.new
985 // memh(Rx++Mu:brev)=Nt.new
987 // memw(Rx++#s4:2:circ(Mu))=Nt.new
988 // memw(Rx++I:circ(Mu))=Nt.new
989 // memw(Rx++Mu)=Nt.new
990 // memw(Rx++Mu:brev)=Nt.new
992 //===----------------------------------------------------------------------===//
994 //===----------------------------------------------------------------------===//
996 //===----------------------------------------------------------------------===//
998 //===----------------------------------------------------------------------===//
1000 //===----------------------------------------------------------------------===//
1001 // multiclass/template class for the new-value compare jumps with the register
1003 //===----------------------------------------------------------------------===//
1005 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
1006 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1007 bit isNegCond, bit isTak>
1009 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1010 "if ("#!if(isNegCond, "!","")#mnemonic#
1011 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1012 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1013 #!if(isTak, "t","nt")#" $offset",
1014 []>, Requires<[HasV4T]> {
1018 bits<3> Ns; // New-Value Operand
1019 bits<5> RegOp; // Non-New-Value Operand
1022 let isTaken = isTak;
1023 let isBrTaken = !if(isTaken, "true", "false");
1024 let isPredicatedFalse = isNegCond;
1026 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1027 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1029 let IClass = 0b0010;
1031 let Inst{25-23} = majOp;
1032 let Inst{22} = isNegCond;
1033 let Inst{18-16} = Ns;
1034 let Inst{13} = isTak;
1035 let Inst{12-8} = RegOp;
1036 let Inst{21-20} = offset{10-9};
1037 let Inst{7-1} = offset{8-2};
1041 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1043 // Branch not taken:
1044 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1046 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1049 // NvOpNum = 0 -> First Operand is a new-value Register
1050 // NvOpNum = 1 -> Second Operand is a new-value Register
1052 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1054 let BaseOpcode = BaseOp#_NVJ in {
1055 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1056 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1060 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1061 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1062 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1063 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1064 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1066 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1067 Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
1068 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1069 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1070 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1071 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1072 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1075 //===----------------------------------------------------------------------===//
1076 // multiclass/template class for the new-value compare jumps instruction
1077 // with a register and an unsigned immediate (U5) operand.
1078 //===----------------------------------------------------------------------===//
1080 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
1081 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1084 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1085 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1086 #!if(isTak, "t","nt")#" $offset",
1087 []>, Requires<[HasV4T]> {
1089 let isTaken = isTak;
1090 let isPredicatedFalse = isNegCond;
1091 let isBrTaken = !if(isTaken, "true", "false");
1097 let IClass = 0b0010;
1099 let Inst{25-23} = majOp;
1100 let Inst{22} = isNegCond;
1101 let Inst{18-16} = src1;
1102 let Inst{13} = isTak;
1103 let Inst{12-8} = src2;
1104 let Inst{21-20} = offset{10-9};
1105 let Inst{7-1} = offset{8-2};
1108 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1109 // Branch not taken:
1110 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1112 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1115 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1116 let BaseOpcode = BaseOp#_NVJri in {
1117 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1118 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1122 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1123 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1124 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1126 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1127 Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
1128 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1129 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1130 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1133 //===----------------------------------------------------------------------===//
1134 // multiclass/template class for the new-value compare jumps instruction
1135 // with a register and an hardcoded 0/-1 immediate value.
1136 //===----------------------------------------------------------------------===//
1138 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
1139 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1140 bit isNegCond, bit isTak>
1142 (ins IntRegs:$src1, brtarget:$offset),
1143 "if ("#!if(isNegCond, "!","")#mnemonic
1144 #"($src1.new, #"#ImmVal#")) jump:"
1145 #!if(isTak, "t","nt")#" $offset",
1146 []>, Requires<[HasV4T]> {
1148 let isTaken = isTak;
1149 let isPredicatedFalse = isNegCond;
1150 let isBrTaken = !if(isTaken, "true", "false");
1154 let IClass = 0b0010;
1156 let Inst{25-23} = majOp;
1157 let Inst{22} = isNegCond;
1158 let Inst{18-16} = src1;
1159 let Inst{13} = isTak;
1160 let Inst{21-20} = offset{10-9};
1161 let Inst{7-1} = offset{8-2};
1164 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1166 // Branch not taken:
1167 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1169 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1172 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1174 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1175 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True cond
1176 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False Cond
1180 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1181 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1182 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1184 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1185 Defs = [PC], neverHasSideEffects = 1 in {
1186 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1187 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1188 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1191 //===----------------------------------------------------------------------===//
1193 //===----------------------------------------------------------------------===//
1195 // Add and accumulate.
1196 // Rd=add(Rs,add(Ru,#s6))
1197 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
1198 validSubTargets = HasV4SubT in
1199 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
1200 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1201 "$dst = add($src1, add($src2, #$src3))",
1202 [(set (i32 IntRegs:$dst),
1203 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1204 s6_16ExtPred:$src3)))]>,
1207 // Rd=add(Rs,sub(#s6,Ru))
1208 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1209 validSubTargets = HasV4SubT in
1210 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
1211 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1212 "$dst = add($src1, sub(#$src2, $src3))",
1213 [(set (i32 IntRegs:$dst),
1214 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1215 (i32 IntRegs:$src3))))]>,
1218 // Generates the same instruction as ADDr_SUBri_V4 but matches different
1220 // Rd=add(Rs,sub(#s6,Ru))
1221 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1222 validSubTargets = HasV4SubT in
1223 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
1224 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1225 "$dst = add($src1, sub(#$src2, $src3))",
1226 [(set (i32 IntRegs:$dst),
1227 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1228 (i32 IntRegs:$src3)))]>,
1232 // Add or subtract doublewords with carry.
1234 // Rdd=add(Rss,Rtt,Px):carry
1236 // Rdd=sub(Rss,Rtt,Px):carry
1239 // Logical doublewords.
1240 // Rdd=and(Rtt,~Rss)
1241 let validSubTargets = HasV4SubT in
1242 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1243 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1244 "$dst = and($src1, ~$src2)",
1245 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1246 (not (i64 DoubleRegs:$src2))))]>,
1250 let validSubTargets = HasV4SubT in
1251 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1252 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1253 "$dst = or($src1, ~$src2)",
1254 [(set (i64 DoubleRegs:$dst),
1255 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
1259 // Logical-logical doublewords.
1260 // Rxx^=xor(Rss,Rtt)
1261 let validSubTargets = HasV4SubT in
1262 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
1263 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1264 "$dst ^= xor($src2, $src3)",
1265 [(set (i64 DoubleRegs:$dst),
1266 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
1267 (i64 DoubleRegs:$src3))))],
1272 // Logical-logical words.
1273 // Rx=or(Ru,and(Rx,#s10))
1274 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1275 validSubTargets = HasV4SubT in
1276 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
1277 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1278 "$dst = or($src1, and($src2, #$src3))",
1279 [(set (i32 IntRegs:$dst),
1280 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1281 s10ExtPred:$src3)))],
1285 // Rx[&|^]=and(Rs,Rt)
1287 let validSubTargets = HasV4SubT in
1288 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1289 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1290 "$dst &= and($src2, $src3)",
1291 [(set (i32 IntRegs:$dst),
1292 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1293 (i32 IntRegs:$src3))))],
1298 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
1299 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1300 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1301 "$dst |= and($src2, $src3)",
1302 [(set (i32 IntRegs:$dst),
1303 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1304 (i32 IntRegs:$src3))))],
1306 Requires<[HasV4T]>, ImmRegRel;
1309 let validSubTargets = HasV4SubT in
1310 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1311 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1312 "$dst ^= and($src2, $src3)",
1313 [(set (i32 IntRegs:$dst),
1314 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1315 (i32 IntRegs:$src3))))],
1319 // Rx[&|^]=and(Rs,~Rt)
1321 let validSubTargets = HasV4SubT in
1322 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1323 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1324 "$dst &= and($src2, ~$src3)",
1325 [(set (i32 IntRegs:$dst),
1326 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1327 (not (i32 IntRegs:$src3)))))],
1332 let validSubTargets = HasV4SubT in
1333 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1334 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1335 "$dst |= and($src2, ~$src3)",
1336 [(set (i32 IntRegs:$dst),
1337 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1338 (not (i32 IntRegs:$src3)))))],
1343 let validSubTargets = HasV4SubT in
1344 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1345 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1346 "$dst ^= and($src2, ~$src3)",
1347 [(set (i32 IntRegs:$dst),
1348 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1349 (not (i32 IntRegs:$src3)))))],
1353 // Rx[&|^]=or(Rs,Rt)
1355 let validSubTargets = HasV4SubT in
1356 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1357 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1358 "$dst &= or($src2, $src3)",
1359 [(set (i32 IntRegs:$dst),
1360 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1361 (i32 IntRegs:$src3))))],
1366 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
1367 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1368 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1369 "$dst |= or($src2, $src3)",
1370 [(set (i32 IntRegs:$dst),
1371 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1372 (i32 IntRegs:$src3))))],
1374 Requires<[HasV4T]>, ImmRegRel;
1377 let validSubTargets = HasV4SubT in
1378 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1379 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1380 "$dst ^= or($src2, $src3)",
1381 [(set (i32 IntRegs:$dst),
1382 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1383 (i32 IntRegs:$src3))))],
1387 // Rx[&|^]=xor(Rs,Rt)
1389 let validSubTargets = HasV4SubT in
1390 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1391 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1392 "$dst &= xor($src2, $src3)",
1393 [(set (i32 IntRegs:$dst),
1394 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1395 (i32 IntRegs:$src3))))],
1400 let validSubTargets = HasV4SubT in
1401 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1402 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1403 "$dst |= xor($src2, $src3)",
1404 [(set (i32 IntRegs:$dst),
1405 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1406 (i32 IntRegs:$src3))))],
1411 let validSubTargets = HasV4SubT in
1412 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1413 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1414 "$dst ^= xor($src2, $src3)",
1415 [(set (i32 IntRegs:$dst),
1416 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1417 (i32 IntRegs:$src3))))],
1422 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1423 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
1424 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
1425 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1426 "$dst |= and($src2, #$src3)",
1427 [(set (i32 IntRegs:$dst),
1428 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1429 s10ExtPred:$src3)))],
1431 Requires<[HasV4T]>, ImmRegRel;
1434 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1435 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
1436 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
1437 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1438 "$dst |= or($src2, #$src3)",
1439 [(set (i32 IntRegs:$dst),
1440 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1441 s10ExtPred:$src3)))],
1443 Requires<[HasV4T]>, ImmRegRel;
1447 // Rd=modwrap(Rs,Rt)
1449 // Rd=cround(Rs,#u5)
1451 // Rd=round(Rs,#u5)[:sat]
1452 // Rd=round(Rs,Rt)[:sat]
1453 // Vector reduce add unsigned halfwords
1454 // Rd=vraddh(Rss,Rtt)
1456 // Rdd=vaddb(Rss,Rtt)
1457 // Vector conditional negate
1458 // Rdd=vcnegh(Rss,Rt)
1459 // Rxx+=vrcnegh(Rss,Rt)
1460 // Vector maximum bytes
1461 // Rdd=vmaxb(Rtt,Rss)
1462 // Vector reduce maximum halfwords
1463 // Rxx=vrmaxh(Rss,Ru)
1464 // Rxx=vrmaxuh(Rss,Ru)
1465 // Vector reduce maximum words
1466 // Rxx=vrmaxuw(Rss,Ru)
1467 // Rxx=vrmaxw(Rss,Ru)
1468 // Vector minimum bytes
1469 // Rdd=vminb(Rtt,Rss)
1470 // Vector reduce minimum halfwords
1471 // Rxx=vrminh(Rss,Ru)
1472 // Rxx=vrminuh(Rss,Ru)
1473 // Vector reduce minimum words
1474 // Rxx=vrminuw(Rss,Ru)
1475 // Rxx=vrminw(Rss,Ru)
1476 // Vector subtract bytes
1477 // Rdd=vsubb(Rss,Rtt)
1479 //===----------------------------------------------------------------------===//
1481 //===----------------------------------------------------------------------===//
1484 //===----------------------------------------------------------------------===//
1486 //===----------------------------------------------------------------------===//
1488 // Multiply and user lower result.
1489 // Rd=add(#u6,mpyi(Rs,#U6))
1490 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1491 validSubTargets = HasV4SubT in
1492 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
1493 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1494 "$dst = add(#$src1, mpyi($src2, #$src3))",
1495 [(set (i32 IntRegs:$dst),
1496 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1497 u6ExtPred:$src1))]>,
1500 // Rd=add(##,mpyi(Rs,#U6))
1501 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1502 (HexagonCONST32 tglobaladdr:$src1)),
1503 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
1506 // Rd=add(#u6,mpyi(Rs,Rt))
1507 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1508 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1509 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
1510 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1511 "$dst = add(#$src1, mpyi($src2, $src3))",
1512 [(set (i32 IntRegs:$dst),
1513 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1514 u6ExtPred:$src1))]>,
1515 Requires<[HasV4T]>, ImmRegRel;
1517 // Rd=add(##,mpyi(Rs,Rt))
1518 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1519 (HexagonCONST32 tglobaladdr:$src1)),
1520 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
1523 // Rd=add(Ru,mpyi(#u6:2,Rs))
1524 let validSubTargets = HasV4SubT in
1525 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
1526 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1527 "$dst = add($src1, mpyi(#$src2, $src3))",
1528 [(set (i32 IntRegs:$dst),
1529 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1530 u6_2ImmPred:$src2)))]>,
1533 // Rd=add(Ru,mpyi(Rs,#u6))
1534 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
1535 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1536 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
1537 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1538 "$dst = add($src1, mpyi($src2, #$src3))",
1539 [(set (i32 IntRegs:$dst),
1540 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1541 u6ExtPred:$src3)))]>,
1542 Requires<[HasV4T]>, ImmRegRel;
1544 // Rx=add(Ru,mpyi(Rx,Rs))
1545 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
1546 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
1547 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1548 "$dst = add($src1, mpyi($src2, $src3))",
1549 [(set (i32 IntRegs:$dst),
1550 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1551 (i32 IntRegs:$src3))))],
1553 Requires<[HasV4T]>, ImmRegRel;
1556 // Polynomial multiply words
1558 // Rxx^=pmpyw(Rs,Rt)
1560 // Vector reduce multiply word by signed half (32x16)
1561 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
1562 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
1563 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
1564 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
1566 // Multiply and use upper result
1567 // Rd=mpy(Rs,Rt.H):<<1:sat
1568 // Rd=mpy(Rs,Rt.L):<<1:sat
1569 // Rd=mpy(Rs,Rt):<<1
1570 // Rd=mpy(Rs,Rt):<<1:sat
1572 // Rx+=mpy(Rs,Rt):<<1:sat
1573 // Rx-=mpy(Rs,Rt):<<1:sat
1575 // Vector multiply bytes
1576 // Rdd=vmpybsu(Rs,Rt)
1577 // Rdd=vmpybu(Rs,Rt)
1578 // Rxx+=vmpybsu(Rs,Rt)
1579 // Rxx+=vmpybu(Rs,Rt)
1581 // Vector polynomial multiply halfwords
1582 // Rdd=vpmpyh(Rs,Rt)
1583 // Rxx^=vpmpyh(Rs,Rt)
1585 //===----------------------------------------------------------------------===//
1587 //===----------------------------------------------------------------------===//
1590 //===----------------------------------------------------------------------===//
1592 //===----------------------------------------------------------------------===//
1594 // Shift by immediate and accumulate.
1595 // Rx=add(#u8,asl(Rx,#U5))
1596 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1597 validSubTargets = HasV4SubT in
1598 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1599 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1600 "$dst = add(#$src1, asl($src2, #$src3))",
1601 [(set (i32 IntRegs:$dst),
1602 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1607 // Rx=add(#u8,lsr(Rx,#U5))
1608 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1609 validSubTargets = HasV4SubT in
1610 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1611 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1612 "$dst = add(#$src1, lsr($src2, #$src3))",
1613 [(set (i32 IntRegs:$dst),
1614 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1619 // Rx=sub(#u8,asl(Rx,#U5))
1620 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1621 validSubTargets = HasV4SubT in
1622 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1623 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1624 "$dst = sub(#$src1, asl($src2, #$src3))",
1625 [(set (i32 IntRegs:$dst),
1626 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1631 // Rx=sub(#u8,lsr(Rx,#U5))
1632 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1633 validSubTargets = HasV4SubT in
1634 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1635 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1636 "$dst = sub(#$src1, lsr($src2, #$src3))",
1637 [(set (i32 IntRegs:$dst),
1638 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1644 //Shift by immediate and logical.
1645 //Rx=and(#u8,asl(Rx,#U5))
1646 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1647 validSubTargets = HasV4SubT in
1648 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1649 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1650 "$dst = and(#$src1, asl($src2, #$src3))",
1651 [(set (i32 IntRegs:$dst),
1652 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1657 //Rx=and(#u8,lsr(Rx,#U5))
1658 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1659 validSubTargets = HasV4SubT in
1660 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1661 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1662 "$dst = and(#$src1, lsr($src2, #$src3))",
1663 [(set (i32 IntRegs:$dst),
1664 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1669 //Rx=or(#u8,asl(Rx,#U5))
1670 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1671 AddedComplexity = 30, validSubTargets = HasV4SubT in
1672 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1673 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1674 "$dst = or(#$src1, asl($src2, #$src3))",
1675 [(set (i32 IntRegs:$dst),
1676 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1681 //Rx=or(#u8,lsr(Rx,#U5))
1682 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1683 AddedComplexity = 30, validSubTargets = HasV4SubT in
1684 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1685 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1686 "$dst = or(#$src1, lsr($src2, #$src3))",
1687 [(set (i32 IntRegs:$dst),
1688 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1694 //Shift by register.
1696 let validSubTargets = HasV4SubT in {
1697 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
1698 "$dst = lsl(#$src1, $src2)",
1699 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
1700 (i32 IntRegs:$src2)))]>,
1704 //Shift by register and logical.
1706 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1707 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1708 "$dst ^= asl($src2, $src3)",
1709 [(set (i64 DoubleRegs:$dst),
1710 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
1711 (i32 IntRegs:$src3))))],
1716 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1717 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1718 "$dst ^= asr($src2, $src3)",
1719 [(set (i64 DoubleRegs:$dst),
1720 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
1721 (i32 IntRegs:$src3))))],
1726 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1727 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1728 "$dst ^= lsl($src2, $src3)",
1729 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
1730 (shl (i64 DoubleRegs:$src2),
1731 (i32 IntRegs:$src3))))],
1736 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
1737 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
1738 "$dst ^= lsr($src2, $src3)",
1739 [(set (i64 DoubleRegs:$dst),
1740 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
1741 (i32 IntRegs:$src3))))],
1746 //===----------------------------------------------------------------------===//
1748 //===----------------------------------------------------------------------===//
1750 //===----------------------------------------------------------------------===//
1751 // MEMOP: Word, Half, Byte
1752 //===----------------------------------------------------------------------===//
1754 def MEMOPIMM : SDNodeXForm<imm, [{
1755 // Call the transformation function XformM5ToU5Imm to get the negative
1756 // immediate's positive counterpart.
1757 int32_t imm = N->getSExtValue();
1758 return XformM5ToU5Imm(imm);
1761 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
1762 // -1 .. -31 represented as 65535..65515
1763 // assigning to a short restores our desired signed value.
1764 // Call the transformation function XformM5ToU5Imm to get the negative
1765 // immediate's positive counterpart.
1766 int16_t imm = N->getSExtValue();
1767 return XformM5ToU5Imm(imm);
1770 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
1771 // -1 .. -31 represented as 255..235
1772 // assigning to a char restores our desired signed value.
1773 // Call the transformation function XformM5ToU5Imm to get the negative
1774 // immediate's positive counterpart.
1775 int8_t imm = N->getSExtValue();
1776 return XformM5ToU5Imm(imm);
1779 def SETMEMIMM : SDNodeXForm<imm, [{
1780 // Return the bit position we will set [0-31].
1782 int32_t imm = N->getSExtValue();
1783 return XformMskToBitPosU5Imm(imm);
1786 def CLRMEMIMM : SDNodeXForm<imm, [{
1787 // Return the bit position we will clear [0-31].
1789 // we bit negate the value first
1790 int32_t imm = ~(N->getSExtValue());
1791 return XformMskToBitPosU5Imm(imm);
1794 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
1795 // Return the bit position we will set [0-15].
1797 int16_t imm = N->getSExtValue();
1798 return XformMskToBitPosU4Imm(imm);
1801 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
1802 // Return the bit position we will clear [0-15].
1804 // we bit negate the value first
1805 int16_t imm = ~(N->getSExtValue());
1806 return XformMskToBitPosU4Imm(imm);
1809 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
1810 // Return the bit position we will set [0-7].
1812 int8_t imm = N->getSExtValue();
1813 return XformMskToBitPosU3Imm(imm);
1816 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
1817 // Return the bit position we will clear [0-7].
1819 // we bit negate the value first
1820 int8_t imm = ~(N->getSExtValue());
1821 return XformMskToBitPosU3Imm(imm);
1824 //===----------------------------------------------------------------------===//
1825 // Template class for MemOp instructions with the register value.
1826 //===----------------------------------------------------------------------===//
1827 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
1828 string memOp, bits<2> memOpBits> :
1830 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
1831 opc#"($base+#$offset)"#memOp#"$delta",
1833 Requires<[HasV4T, UseMEMOP]> {
1838 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1840 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1841 !if (!eq(opcBits, 0b01), offset{6-1},
1842 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1844 let IClass = 0b0011;
1845 let Inst{27-24} = 0b1110;
1846 let Inst{22-21} = opcBits;
1847 let Inst{20-16} = base;
1849 let Inst{12-7} = offsetBits;
1850 let Inst{6-5} = memOpBits;
1851 let Inst{4-0} = delta;
1854 //===----------------------------------------------------------------------===//
1855 // Template class for MemOp instructions with the immediate value.
1856 //===----------------------------------------------------------------------===//
1857 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
1858 string memOp, bits<2> memOpBits> :
1860 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
1861 opc#"($base+#$offset)"#memOp#"#$delta"
1862 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
1864 Requires<[HasV4T, UseMEMOP]> {
1869 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
1871 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
1872 !if (!eq(opcBits, 0b01), offset{6-1},
1873 !if (!eq(opcBits, 0b10), offset{7-2},0)));
1875 let IClass = 0b0011;
1876 let Inst{27-24} = 0b1111;
1877 let Inst{22-21} = opcBits;
1878 let Inst{20-16} = base;
1880 let Inst{12-7} = offsetBits;
1881 let Inst{6-5} = memOpBits;
1882 let Inst{4-0} = delta;
1885 // multiclass to define MemOp instructions with register operand.
1886 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
1887 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
1888 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
1889 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
1890 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
1893 // multiclass to define MemOp instructions with immediate Operand.
1894 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
1895 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
1896 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
1897 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
1898 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
1901 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
1902 defm r : MemOp_rr <opc, opcBits, ImmOp>;
1903 defm i : MemOp_ri <opc, opcBits, ImmOp>;
1906 // Define MemOp instructions.
1907 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
1908 validSubTargets =HasV4SubT in {
1909 let opExtentBits = 6, accessSize = ByteAccess in
1910 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
1912 let opExtentBits = 7, accessSize = HalfWordAccess in
1913 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
1915 let opExtentBits = 8, accessSize = WordAccess in
1916 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
1919 //===----------------------------------------------------------------------===//
1920 // Multiclass to define 'Def Pats' for ALU operations on the memory
1921 // Here value used for the ALU operation is an immediate value.
1922 // mem[bh](Rs+#0) += #U5
1923 // mem[bh](Rs+#u6) += #U5
1924 //===----------------------------------------------------------------------===//
1926 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
1927 InstHexagon MI, SDNode OpNode> {
1928 let AddedComplexity = 180 in
1929 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
1931 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
1933 let AddedComplexity = 190 in
1934 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
1936 (add IntRegs:$base, ExtPred:$offset)),
1937 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
1940 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
1941 InstHexagon addMI, InstHexagon subMI> {
1942 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
1943 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
1946 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1948 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
1949 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
1951 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
1952 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
1955 let Predicates = [HasV4T, UseMEMOP] in {
1956 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
1957 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
1958 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
1961 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
1965 //===----------------------------------------------------------------------===//
1966 // multiclass to define 'Def Pats' for ALU operations on the memory.
1967 // Here value used for the ALU operation is a negative value.
1968 // mem[bh](Rs+#0) += #m5
1969 // mem[bh](Rs+#u6) += #m5
1970 //===----------------------------------------------------------------------===//
1972 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
1973 PatLeaf immPred, ComplexPattern addrPred,
1974 SDNodeXForm xformFunc, InstHexagon MI> {
1975 let AddedComplexity = 190 in
1976 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
1978 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
1980 let AddedComplexity = 195 in
1981 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
1983 (add IntRegs:$base, extPred:$offset)),
1984 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
1987 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
1989 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
1990 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
1992 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
1993 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
1996 let Predicates = [HasV4T, UseMEMOP] in {
1997 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
1998 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
1999 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2002 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2003 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
2006 //===----------------------------------------------------------------------===//
2007 // Multiclass to define 'def Pats' for bit operations on the memory.
2008 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2009 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2010 //===----------------------------------------------------------------------===//
2012 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2013 PatLeaf extPred, ComplexPattern addrPred,
2014 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2016 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2017 let AddedComplexity = 250 in
2018 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2020 (add IntRegs:$base, extPred:$offset)),
2021 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2023 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2024 let AddedComplexity = 225 in
2025 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2027 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2028 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2031 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2033 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2034 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
2036 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2037 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
2038 // Half Word - clrbit
2039 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2040 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
2041 // Half Word - setbit
2042 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2043 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
2046 let Predicates = [HasV4T, UseMEMOP] in {
2047 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2048 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2049 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2050 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2051 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2053 // memw(Rs+#0) = [clrbit|setbit](#U5)
2054 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2055 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2056 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2057 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2058 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2061 //===----------------------------------------------------------------------===//
2062 // Multiclass to define 'def Pats' for ALU operations on the memory
2063 // where addend is a register.
2064 // mem[bhw](Rs+#0) [+-&|]= Rt
2065 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2066 //===----------------------------------------------------------------------===//
2068 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2069 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2070 let AddedComplexity = 141 in
2071 // mem[bhw](Rs+#0) [+-&|]= Rt
2072 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2073 (i32 IntRegs:$addend)),
2074 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2075 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2077 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2078 let AddedComplexity = 150 in
2079 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2080 (i32 IntRegs:$orend)),
2081 (add IntRegs:$base, extPred:$offset)),
2082 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2085 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2086 ComplexPattern addrPred, PatLeaf extPred,
2087 InstHexagon addMI, InstHexagon subMI,
2088 InstHexagon andMI, InstHexagon orMI > {
2090 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2091 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2092 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2093 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2096 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2098 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2099 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2100 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2102 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2103 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2104 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2107 // Define 'def Pats' for MemOps with register addend.
2108 let Predicates = [HasV4T, UseMEMOP] in {
2110 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2111 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2112 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2114 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2115 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2118 //===----------------------------------------------------------------------===//
2120 //===----------------------------------------------------------------------===//
2122 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2123 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2124 // hardware. However, compiler can still implement these patterns through
2125 // appropriate patterns combinations based on current implemented patterns.
2126 // The implemented patterns are: EQ/GT/GTU.
2127 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2129 // Following instruction is not being extended as it results into the
2130 // incorrect code for negative numbers.
2131 // Pd=cmpb.eq(Rs,#u8)
2133 let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0,
2134 validSubTargets = HasV4SubT in
2135 class CMP_NOT_REG_IMM<string OpName, bits<2> op, Operand ImmOp,
2137 : ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2),
2138 "$dst = !cmp."#OpName#"($src1, #$src2)",
2140 "", ALU32_2op_tc_2early_SLOT0123> {
2145 let IClass = 0b0111;
2146 let Inst{27-24} = 0b0101;
2147 let Inst{23-22} = op;
2148 let Inst{20-16} = src1;
2149 let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9});
2150 let Inst{13-5} = src2{8-0};
2151 let Inst{4-2} = 0b100;
2152 let Inst{1-0} = dst;
2155 let opExtentBits = 10, isExtentSigned = 1 in {
2156 def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst),
2157 (setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>;
2159 def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst),
2160 (not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>;
2163 let opExtentBits = 9 in
2164 def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
2165 (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
2170 let isCompare = 1, validSubTargets = HasV4SubT in
2171 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2172 (ins IntRegs:$src1, IntRegs:$src2),
2173 "$dst = !cmp.eq($src1, $src2)",
2174 [(set (i1 PredRegs:$dst),
2175 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2179 let isCompare = 1, validSubTargets = HasV4SubT in
2180 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2181 (ins IntRegs:$src1, IntRegs:$src2),
2182 "$dst = !cmp.gt($src1, $src2)",
2183 [(set (i1 PredRegs:$dst),
2184 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2188 // p=!cmp.gtu(r1,r2)
2189 let isCompare = 1, validSubTargets = HasV4SubT in
2190 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2191 (ins IntRegs:$src1, IntRegs:$src2),
2192 "$dst = !cmp.gtu($src1, $src2)",
2193 [(set (i1 PredRegs:$dst),
2194 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2197 let isCompare = 1, validSubTargets = HasV4SubT in
2198 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2199 (ins IntRegs:$src1, u8Imm:$src2),
2200 "$dst = cmpb.eq($src1, #$src2)",
2201 [(set (i1 PredRegs:$dst),
2202 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2205 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2207 (JMP_f (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2211 // Pd=cmpb.eq(Rs,Rt)
2212 let isCompare = 1, validSubTargets = HasV4SubT in
2213 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2214 (ins IntRegs:$src1, IntRegs:$src2),
2215 "$dst = cmpb.eq($src1, $src2)",
2216 [(set (i1 PredRegs:$dst),
2217 (seteq (and (xor (i32 IntRegs:$src1),
2218 (i32 IntRegs:$src2)), 255), 0))]>,
2221 // Pd=cmpb.eq(Rs,Rt)
2222 let isCompare = 1, validSubTargets = HasV4SubT in
2223 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2224 (ins IntRegs:$src1, IntRegs:$src2),
2225 "$dst = cmpb.eq($src1, $src2)",
2226 [(set (i1 PredRegs:$dst),
2227 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2228 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2231 // Pd=cmpb.gt(Rs,Rt)
2232 let isCompare = 1, validSubTargets = HasV4SubT in
2233 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2234 (ins IntRegs:$src1, IntRegs:$src2),
2235 "$dst = cmpb.gt($src1, $src2)",
2236 [(set (i1 PredRegs:$dst),
2237 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2238 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2241 // Pd=cmpb.gtu(Rs,#u7)
2242 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2243 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2244 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2245 (ins IntRegs:$src1, u7Ext:$src2),
2246 "$dst = cmpb.gtu($src1, #$src2)",
2247 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2248 u7ExtPred:$src2))]>,
2249 Requires<[HasV4T]>, ImmRegRel;
2251 // SDNode for converting immediate C to C-1.
2252 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2253 // Return the byte immediate const-1 as an SDNode.
2254 int32_t imm = N->getSExtValue();
2255 return XformU7ToU7M1Imm(imm);
2259 // zext( seteq ( and(Rs, 255), u8))
2261 // Pd=cmpb.eq(Rs, #u8)
2262 // if (Pd.new) Rd=#1
2263 // if (!Pd.new) Rd=#0
2264 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2266 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2272 // zext( setne ( and(Rs, 255), u8))
2274 // Pd=cmpb.eq(Rs, #u8)
2275 // if (Pd.new) Rd=#0
2276 // if (!Pd.new) Rd=#1
2277 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2279 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2285 // zext( seteq (Rs, and(Rt, 255)))
2287 // Pd=cmpb.eq(Rs, Rt)
2288 // if (Pd.new) Rd=#1
2289 // if (!Pd.new) Rd=#0
2290 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2291 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2292 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2293 (i32 IntRegs:$Rt))),
2298 // zext( setne (Rs, and(Rt, 255)))
2300 // Pd=cmpb.eq(Rs, Rt)
2301 // if (Pd.new) Rd=#0
2302 // if (!Pd.new) Rd=#1
2303 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2304 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2305 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2306 (i32 IntRegs:$Rt))),
2311 // zext( setugt ( and(Rs, 255), u8))
2313 // Pd=cmpb.gtu(Rs, #u8)
2314 // if (Pd.new) Rd=#1
2315 // if (!Pd.new) Rd=#0
2316 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2318 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2324 // zext( setugt ( and(Rs, 254), u8))
2326 // Pd=cmpb.gtu(Rs, #u8)
2327 // if (Pd.new) Rd=#1
2328 // if (!Pd.new) Rd=#0
2329 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2331 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2337 // zext( setult ( Rs, Rt))
2339 // Pd=cmp.ltu(Rs, Rt)
2340 // if (Pd.new) Rd=#1
2341 // if (!Pd.new) Rd=#0
2342 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2343 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2344 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2345 (i32 IntRegs:$Rs))),
2350 // zext( setlt ( Rs, Rt))
2352 // Pd=cmp.lt(Rs, Rt)
2353 // if (Pd.new) Rd=#1
2354 // if (!Pd.new) Rd=#0
2355 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2356 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2357 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2358 (i32 IntRegs:$Rs))),
2363 // zext( setugt ( Rs, Rt))
2365 // Pd=cmp.gtu(Rs, Rt)
2366 // if (Pd.new) Rd=#1
2367 // if (!Pd.new) Rd=#0
2368 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2369 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2370 (i32 IntRegs:$Rt))),
2374 // This pattern interefers with coremark performance, not implementing at this
2377 // zext( setgt ( Rs, Rt))
2379 // Pd=cmp.gt(Rs, Rt)
2380 // if (Pd.new) Rd=#1
2381 // if (!Pd.new) Rd=#0
2384 // zext( setuge ( Rs, Rt))
2386 // Pd=cmp.ltu(Rs, Rt)
2387 // if (Pd.new) Rd=#0
2388 // if (!Pd.new) Rd=#1
2389 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2390 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2391 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2392 (i32 IntRegs:$Rs))),
2397 // zext( setge ( Rs, Rt))
2399 // Pd=cmp.lt(Rs, Rt)
2400 // if (Pd.new) Rd=#0
2401 // if (!Pd.new) Rd=#1
2402 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2403 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2404 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2405 (i32 IntRegs:$Rs))),
2410 // zext( setule ( Rs, Rt))
2412 // Pd=cmp.gtu(Rs, Rt)
2413 // if (Pd.new) Rd=#0
2414 // if (!Pd.new) Rd=#1
2415 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2416 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2417 (i32 IntRegs:$Rt))),
2422 // zext( setle ( Rs, Rt))
2424 // Pd=cmp.gt(Rs, Rt)
2425 // if (Pd.new) Rd=#0
2426 // if (!Pd.new) Rd=#1
2427 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2428 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
2429 (i32 IntRegs:$Rt))),
2434 // zext( setult ( and(Rs, 255), u8))
2435 // Use the isdigit transformation below
2437 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
2438 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
2439 // The isdigit transformation relies on two 'clever' aspects:
2440 // 1) The data type is unsigned which allows us to eliminate a zero test after
2441 // biasing the expression by 48. We are depending on the representation of
2442 // the unsigned types, and semantics.
2443 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
2446 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
2447 // The code is transformed upstream of llvm into
2448 // retval = (c-48) < 10 ? 1 : 0;
2449 let AddedComplexity = 139 in
2450 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
2451 u7StrictPosImmPred:$src2)))),
2452 (i32 (MUX_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
2453 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
2457 // Pd=cmpb.gtu(Rs,Rt)
2458 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
2459 InputType = "reg" in
2460 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
2461 (ins IntRegs:$src1, IntRegs:$src2),
2462 "$dst = cmpb.gtu($src1, $src2)",
2463 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2464 (and (i32 IntRegs:$src2), 255)))]>,
2465 Requires<[HasV4T]>, ImmRegRel;
2467 // Following instruction is not being extended as it results into the incorrect
2468 // code for negative numbers.
2470 // Signed half compare(.eq) ri.
2471 // Pd=cmph.eq(Rs,#s8)
2472 let isCompare = 1, validSubTargets = HasV4SubT in
2473 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
2474 (ins IntRegs:$src1, s8Imm:$src2),
2475 "$dst = cmph.eq($src1, #$src2)",
2476 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
2477 s8ImmPred:$src2))]>,
2480 // Signed half compare(.eq) rr.
2481 // Case 1: xor + and, then compare:
2483 // r0=and(r0,#0xffff)
2485 // Pd=cmph.eq(Rs,Rt)
2486 let isCompare = 1, validSubTargets = HasV4SubT in
2487 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
2488 (ins IntRegs:$src1, IntRegs:$src2),
2489 "$dst = cmph.eq($src1, $src2)",
2490 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
2491 (i32 IntRegs:$src2)),
2495 // Signed half compare(.eq) rr.
2496 // Case 2: shift left 16 bits then compare:
2500 // Pd=cmph.eq(Rs,Rt)
2501 let isCompare = 1, validSubTargets = HasV4SubT in
2502 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
2503 (ins IntRegs:$src1, IntRegs:$src2),
2504 "$dst = cmph.eq($src1, $src2)",
2505 [(set (i1 PredRegs:$dst),
2506 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
2507 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2510 /* Incorrect Pattern -- immediate should be right shifted before being
2511 used in the cmph.gt instruction.
2512 // Signed half compare(.gt) ri.
2513 // Pd=cmph.gt(Rs,#s8)
2515 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
2516 isCompare = 1, validSubTargets = HasV4SubT in
2517 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
2518 (ins IntRegs:$src1, s8Ext:$src2),
2519 "$dst = cmph.gt($src1, #$src2)",
2520 [(set (i1 PredRegs:$dst),
2521 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2522 s8ExtPred:$src2))]>,
2526 // Signed half compare(.gt) rr.
2527 // Pd=cmph.gt(Rs,Rt)
2528 let isCompare = 1, validSubTargets = HasV4SubT in
2529 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
2530 (ins IntRegs:$src1, IntRegs:$src2),
2531 "$dst = cmph.gt($src1, $src2)",
2532 [(set (i1 PredRegs:$dst),
2533 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2534 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2537 // Unsigned half compare rr (.gtu).
2538 // Pd=cmph.gtu(Rs,Rt)
2539 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2540 InputType = "reg" in
2541 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
2542 (ins IntRegs:$src1, IntRegs:$src2),
2543 "$dst = cmph.gtu($src1, $src2)",
2544 [(set (i1 PredRegs:$dst),
2545 (setugt (and (i32 IntRegs:$src1), 65535),
2546 (and (i32 IntRegs:$src2), 65535)))]>,
2547 Requires<[HasV4T]>, ImmRegRel;
2549 // Unsigned half compare ri (.gtu).
2550 // Pd=cmph.gtu(Rs,#u7)
2551 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2552 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2553 InputType = "imm" in
2554 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
2555 (ins IntRegs:$src1, u7Ext:$src2),
2556 "$dst = cmph.gtu($src1, #$src2)",
2557 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
2558 u7ExtPred:$src2))]>,
2559 Requires<[HasV4T]>, ImmRegRel;
2561 let validSubTargets = HasV4SubT in
2562 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2563 "$dst = !tstbit($src1, $src2)",
2564 [(set (i1 PredRegs:$dst),
2565 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
2568 let validSubTargets = HasV4SubT in
2569 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2570 "$dst = !tstbit($src1, $src2)",
2571 [(set (i1 PredRegs:$dst),
2572 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
2575 //===----------------------------------------------------------------------===//
2577 //===----------------------------------------------------------------------===//
2579 //Deallocate frame and return.
2581 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
2582 Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1 in {
2583 let validSubTargets = HasV4SubT in
2584 def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
2590 // Restore registers and dealloc return function call.
2591 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2592 Defs = [R29, R30, R31, PC] in {
2593 let validSubTargets = HasV4SubT in
2594 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
2595 (ins calltarget:$dst),
2601 // Restore registers and dealloc frame before a tail call.
2602 let isCall = 1, isBarrier = 1,
2603 Defs = [R29, R30, R31, PC] in {
2604 let validSubTargets = HasV4SubT in
2605 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
2606 (ins calltarget:$dst),
2612 // Save registers function call.
2613 let isCall = 1, isBarrier = 1,
2614 Uses = [R29, R31] in {
2615 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
2616 (ins calltarget:$dst),
2617 "call $dst // Save_calle_saved_registers",
2622 // if (Ps) dealloc_return
2623 let isReturn = 1, isTerminator = 1,
2624 Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
2625 isPredicated = 1 in {
2626 let validSubTargets = HasV4SubT in
2627 def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
2628 (ins PredRegs:$src1),
2629 "if ($src1) dealloc_return",
2634 // if (!Ps) dealloc_return
2635 let isReturn = 1, isTerminator = 1,
2636 Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
2637 isPredicated = 1, isPredicatedFalse = 1 in {
2638 let validSubTargets = HasV4SubT in
2639 def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2640 "if (!$src1) dealloc_return",
2645 // if (Ps.new) dealloc_return:nt
2646 let isReturn = 1, isTerminator = 1,
2647 Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
2648 isPredicated = 1 in {
2649 let validSubTargets = HasV4SubT in
2650 def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2651 "if ($src1.new) dealloc_return:nt",
2656 // if (!Ps.new) dealloc_return:nt
2657 let isReturn = 1, isTerminator = 1,
2658 Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
2659 isPredicated = 1, isPredicatedFalse = 1 in {
2660 let validSubTargets = HasV4SubT in
2661 def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2662 "if (!$src1.new) dealloc_return:nt",
2667 // if (Ps.new) dealloc_return:t
2668 let isReturn = 1, isTerminator = 1,
2669 Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
2670 isPredicated = 1 in {
2671 let validSubTargets = HasV4SubT in
2672 def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2673 "if ($src1.new) dealloc_return:t",
2678 // if (!Ps.new) dealloc_return:nt
2679 let isReturn = 1, isTerminator = 1,
2680 Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
2681 isPredicated = 1, isPredicatedFalse = 1 in {
2682 let validSubTargets = HasV4SubT in
2683 def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2684 "if (!$src1.new) dealloc_return:t",
2689 // Load/Store with absolute addressing mode
2692 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2694 let isPredicatedNew = isPredNew in
2695 def NAME#_V4 : STInst2<(outs),
2696 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2697 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2698 ") ")#mnemonic#"(##$absaddr) = $src2",
2703 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2704 let isPredicatedFalse = PredNot in {
2705 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2707 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2711 let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
2712 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2713 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2714 let opExtendable = 0, isPredicable = 1 in
2715 def NAME#_V4 : STInst2<(outs),
2716 (ins u0AlwaysExt:$absaddr, RC:$src),
2717 mnemonic#"(##$absaddr) = $src",
2721 let opExtendable = 1, isPredicated = 1 in {
2722 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
2723 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
2728 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
2730 let isPredicatedNew = isPredNew in
2731 def NAME#_nv_V4 : NVInst_V4<(outs),
2732 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2733 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2734 ") ")#mnemonic#"(##$absaddr) = $src2.new",
2739 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
2740 let isPredicatedFalse = PredNot in {
2741 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
2743 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
2747 let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
2748 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
2749 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2750 let opExtendable = 0, isPredicable = 1 in
2751 def NAME#_nv_V4 : NVInst_V4<(outs),
2752 (ins u0AlwaysExt:$absaddr, RC:$src),
2753 mnemonic#"(##$absaddr) = $src.new",
2757 let opExtendable = 1, isPredicated = 1 in {
2758 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2759 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2764 let addrMode = Absolute in {
2765 let accessSize = ByteAccess in
2766 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
2767 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
2769 let accessSize = HalfWordAccess in
2770 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
2771 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
2773 let accessSize = WordAccess in
2774 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
2775 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
2777 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2778 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
2781 let Predicates = [HasV4T], AddedComplexity = 30 in {
2782 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2783 (HexagonCONST32 tglobaladdr:$absaddr)),
2784 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2786 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2787 (HexagonCONST32 tglobaladdr:$absaddr)),
2788 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2790 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
2791 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2793 def : Pat<(store (i64 DoubleRegs:$src1),
2794 (HexagonCONST32 tglobaladdr:$absaddr)),
2795 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
2798 //===----------------------------------------------------------------------===//
2799 // multiclass for store instructions with GP-relative addressing mode.
2800 // mem[bhwd](#global)=Rt
2801 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
2802 //===----------------------------------------------------------------------===//
2803 let mayStore = 1, isNVStorable = 1 in
2804 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
2805 let BaseOpcode = BaseOp, isPredicable = 1 in
2806 def NAME#_V4 : STInst2<(outs),
2807 (ins globaladdress:$global, RC:$src),
2808 mnemonic#"(#$global) = $src",
2811 // When GP-relative instructions are predicated, their addressing mode is
2812 // changed to absolute and they are always constant extended.
2813 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2814 isPredicated = 1 in {
2815 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
2816 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
2820 let mayStore = 1, isNVStore = 1 in
2821 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
2822 let BaseOpcode = BaseOp, isPredicable = 1 in
2823 def NAME#_nv_V4 : NVInst_V4<(outs),
2824 (ins u0AlwaysExt:$global, RC:$src),
2825 mnemonic#"(#$global) = $src.new",
2829 // When GP-relative instructions are predicated, their addressing mode is
2830 // changed to absolute and they are always constant extended.
2831 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
2832 isPredicated = 1 in {
2833 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
2834 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
2838 let validSubTargets = HasV4SubT, neverHasSideEffects = 1 in {
2839 let isNVStorable = 0 in
2840 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
2842 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
2843 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel;
2844 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
2845 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel;
2846 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
2847 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel;
2850 // 64 bit atomic store
2851 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2852 (i64 DoubleRegs:$src1)),
2853 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2856 // Map from store(globaladdress) -> memd(#foo)
2857 let AddedComplexity = 100 in
2858 def : Pat <(store (i64 DoubleRegs:$src1),
2859 (HexagonCONST32_GP tglobaladdr:$global)),
2860 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
2862 // 8 bit atomic store
2863 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2864 (i32 IntRegs:$src1)),
2865 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2867 // Map from store(globaladdress) -> memb(#foo)
2868 let AddedComplexity = 100 in
2869 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2870 (HexagonCONST32_GP tglobaladdr:$global)),
2871 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2873 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2874 // to "r0 = 1; memw(#foo) = r0"
2875 let AddedComplexity = 100 in
2876 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2877 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>;
2879 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2880 (i32 IntRegs:$src1)),
2881 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2883 // Map from store(globaladdress) -> memh(#foo)
2884 let AddedComplexity = 100 in
2885 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2886 (HexagonCONST32_GP tglobaladdr:$global)),
2887 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2889 // 32 bit atomic store
2890 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2891 (i32 IntRegs:$src1)),
2892 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2894 // Map from store(globaladdress) -> memw(#foo)
2895 let AddedComplexity = 100 in
2896 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2897 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
2899 //===----------------------------------------------------------------------===//
2900 // Multiclass for the load instructions with absolute addressing mode.
2901 //===----------------------------------------------------------------------===//
2902 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
2904 let isPredicatedNew = isPredNew in
2905 def NAME : LDInst2<(outs RC:$dst),
2906 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
2907 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2908 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
2913 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2914 let isPredicatedFalse = PredNot in {
2915 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
2917 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
2921 let isExtended = 1, neverHasSideEffects = 1 in
2922 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
2923 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
2924 let opExtendable = 1, isPredicable = 1 in
2925 def NAME#_V4 : LDInst2<(outs RC:$dst),
2926 (ins u0AlwaysExt:$absaddr),
2927 "$dst = "#mnemonic#"(##$absaddr)",
2931 let opExtendable = 2, isPredicated = 1 in {
2932 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
2933 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
2938 let addrMode = Absolute in {
2939 let accessSize = ByteAccess in {
2940 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
2941 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
2943 let accessSize = HalfWordAccess in {
2944 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
2945 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
2947 let accessSize = WordAccess in
2948 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
2950 let accessSize = DoubleWordAccess in
2951 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
2954 let Predicates = [HasV4T], AddedComplexity = 30 in {
2955 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
2956 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
2958 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2959 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
2961 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2962 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
2964 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2965 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
2967 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2968 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
2971 //===----------------------------------------------------------------------===//
2972 // multiclass for load instructions with GP-relative addressing mode.
2973 // Rx=mem[bhwd](##global)
2974 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
2975 //===----------------------------------------------------------------------===//
2976 let neverHasSideEffects = 1, validSubTargets = HasV4SubT in
2977 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
2978 let BaseOpcode = BaseOp in {
2979 let isPredicable = 1 in
2980 def NAME#_V4 : LDInst2<(outs RC:$dst),
2981 (ins globaladdress:$global),
2982 "$dst = "#mnemonic#"(#$global)",
2985 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
2986 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
2987 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
2992 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel;
2993 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel;
2994 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel;
2995 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel;
2996 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel;
2997 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel;
2999 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3000 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3002 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3003 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3005 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3006 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3008 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3009 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3011 // Map from load(globaladdress) -> memw(#foo + 0)
3012 let AddedComplexity = 100 in
3013 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3014 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3016 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3017 let AddedComplexity = 100 in
3018 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3019 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
3021 // When the Interprocedural Global Variable optimizer realizes that a certain
3022 // global variable takes only two constant values, it shrinks the global to
3023 // a boolean. Catch those loads here in the following 3 patterns.
3024 let AddedComplexity = 100 in
3025 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3026 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3028 let AddedComplexity = 100 in
3029 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3030 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3032 // Map from load(globaladdress) -> memb(#foo)
3033 let AddedComplexity = 100 in
3034 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3035 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3037 // Map from load(globaladdress) -> memb(#foo)
3038 let AddedComplexity = 100 in
3039 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3040 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3042 let AddedComplexity = 100 in
3043 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3044 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3046 // Map from load(globaladdress) -> memub(#foo)
3047 let AddedComplexity = 100 in
3048 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3049 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3051 // Map from load(globaladdress) -> memh(#foo)
3052 let AddedComplexity = 100 in
3053 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3054 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3056 // Map from load(globaladdress) -> memh(#foo)
3057 let AddedComplexity = 100 in
3058 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3059 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3061 // Map from load(globaladdress) -> memuh(#foo)
3062 let AddedComplexity = 100 in
3063 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3064 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3066 // Map from load(globaladdress) -> memw(#foo)
3067 let AddedComplexity = 100 in
3068 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3069 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3072 // Transfer global address into a register
3073 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3074 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3075 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3077 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3080 // Transfer a block address into a register
3081 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3082 (TFRI_V4 tblockaddress:$src1)>,
3085 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3086 neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
3087 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3088 (ins PredRegs:$src1, s16Ext:$src2),
3089 "if($src1) $dst = #$src2",
3093 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3094 neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
3095 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3096 (ins PredRegs:$src1, s16Ext:$src2),
3097 "if(!$src1) $dst = #$src2",
3101 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3102 neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
3103 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3104 (ins PredRegs:$src1, s16Ext:$src2),
3105 "if($src1.new) $dst = #$src2",
3109 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3110 neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
3111 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3112 (ins PredRegs:$src1, s16Ext:$src2),
3113 "if(!$src1.new) $dst = #$src2",
3117 let AddedComplexity = 50, Predicates = [HasV4T] in
3118 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3119 (TFRI_V4 tglobaladdr:$src1)>,
3123 // Load - Indirect with long offset: These instructions take global address
3125 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3126 validSubTargets = HasV4SubT in
3127 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3128 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3129 "$dst=memd($src1<<#$src2+##$offset)",
3130 [(set (i64 DoubleRegs:$dst),
3131 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3132 (HexagonCONST32 tglobaladdr:$offset))))]>,
3135 let AddedComplexity = 40 in
3136 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3137 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3138 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3139 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3140 !strconcat("$dst = ",
3141 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3143 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3144 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3148 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3149 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3150 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3151 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3152 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3153 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3154 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3156 let AddedComplexity = 40 in
3157 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3158 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3159 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3162 let AddedComplexity = 40 in
3163 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3164 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3165 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3168 let Predicates = [HasV4T], AddedComplexity = 30 in {
3169 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3170 (STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3172 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3173 (STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3175 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3176 (STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3179 let Predicates = [HasV4T], AddedComplexity = 30 in {
3180 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3181 (LDriw_abs_V4 u0AlwaysExtPred:$src)>;
3183 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3184 (LDrib_abs_V4 u0AlwaysExtPred:$src)>;
3186 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3187 (LDriub_abs_V4 u0AlwaysExtPred:$src)>;
3189 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3190 (LDrih_abs_V4 u0AlwaysExtPred:$src)>;
3192 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3193 (LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
3196 // Indexed store word - global address.
3197 // memw(Rs+#u6:2)=#S8
3198 let AddedComplexity = 10 in
3199 def STriw_offset_ext_V4 : STInst<(outs),
3200 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3201 "memw($src1+#$src2) = ##$src3",
3202 [(store (HexagonCONST32 tglobaladdr:$src3),
3203 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3206 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3207 (i64 (COMBINE_Ir_V4 (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
3210 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3211 (i64 (COMBINE_Ir_V4 (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
3216 // We need a complexity of 120 here to override preceding handling of
3218 let Predicates = [HasV4T], AddedComplexity = 120 in {
3219 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3220 (i64 (COMBINE_Ir_V4 0, (LDrib_abs_V4 tglobaladdr:$addr)))>;
3222 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3223 (i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 tglobaladdr:$addr)))>;
3225 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3226 (i64 (SXTW (LDrib_abs_V4 tglobaladdr:$addr)))>;
3228 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3229 (i64 (COMBINE_Ir_V4 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3231 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3232 (i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>;
3234 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3235 (i64 (SXTW (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3238 // We need a complexity of 120 here to override preceding handling of
3240 let AddedComplexity = 120 in {
3241 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3242 (i64 (COMBINE_Ir_V4 0, (LDrih_abs_V4 tglobaladdr:$addr)))>,
3245 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3246 (i64 (COMBINE_Ir_V4 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>,
3249 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3250 (i64 (SXTW (LDrih_abs_V4 tglobaladdr:$addr)))>,
3253 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3254 (i64 (COMBINE_Ir_V4 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3257 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3258 (i64 (COMBINE_Ir_V4 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>,
3261 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3262 (i64 (SXTW (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3266 // We need a complexity of 120 here to override preceding handling of
3268 let AddedComplexity = 120 in {
3269 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3270 (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3273 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3274 (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3277 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3278 (i64 (SXTW (LDriw_abs_V4 tglobaladdr:$addr)))>,
3281 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3282 (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3285 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3286 (i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3289 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3290 (i64 (SXTW (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3294 // Indexed store double word - global address.
3295 // memw(Rs+#u6:2)=#S8
3296 let AddedComplexity = 10 in
3297 def STrih_offset_ext_V4 : STInst<(outs),
3298 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3299 "memh($src1+#$src2) = ##$src3",
3300 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3301 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3303 // Map from store(globaladdress + x) -> memd(#foo + x)
3304 let AddedComplexity = 100 in
3305 def : Pat<(store (i64 DoubleRegs:$src1),
3306 FoldGlobalAddrGP:$addr),
3307 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3310 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3311 (i64 DoubleRegs:$src1)),
3312 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3315 // Map from store(globaladdress + x) -> memb(#foo + x)
3316 let AddedComplexity = 100 in
3317 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3318 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3321 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3322 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3325 // Map from store(globaladdress + x) -> memh(#foo + x)
3326 let AddedComplexity = 100 in
3327 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3328 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3331 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3332 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3335 // Map from store(globaladdress + x) -> memw(#foo + x)
3336 let AddedComplexity = 100 in
3337 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3338 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3341 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3342 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3345 // Map from load(globaladdress + x) -> memd(#foo + x)
3346 let AddedComplexity = 100 in
3347 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3348 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3351 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3352 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3355 // Map from load(globaladdress + x) -> memb(#foo + x)
3356 let AddedComplexity = 100 in
3357 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3358 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3361 // Map from load(globaladdress + x) -> memb(#foo + x)
3362 let AddedComplexity = 100 in
3363 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3364 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3367 //let AddedComplexity = 100 in
3368 let AddedComplexity = 100 in
3369 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3370 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3373 // Map from load(globaladdress + x) -> memh(#foo + x)
3374 let AddedComplexity = 100 in
3375 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3376 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3379 // Map from load(globaladdress + x) -> memuh(#foo + x)
3380 let AddedComplexity = 100 in
3381 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3382 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3385 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3386 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3389 // Map from load(globaladdress + x) -> memub(#foo + x)
3390 let AddedComplexity = 100 in
3391 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3392 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3395 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3396 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3399 // Map from load(globaladdress + x) -> memw(#foo + x)
3400 let AddedComplexity = 100 in
3401 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3402 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
3405 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3406 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,