1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
15 def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
17 let hasSideEffects = 0 in
18 class T_Immext<Operand ImmType>
19 : EXTENDERInst<(outs), (ins ImmType:$imm),
20 "immext(#$imm)", []> {
24 let Inst{27-16} = imm{31-20};
25 let Inst{13-0} = imm{19-6};
28 def A4_ext : T_Immext<u26_6Imm>;
29 let isCodeGenOnly = 1 in {
31 def A4_ext_b : T_Immext<brtarget>;
33 def A4_ext_c : T_Immext<calltarget>;
34 def A4_ext_g : T_Immext<globaladdress>;
37 def BITPOS32 : SDNodeXForm<imm, [{
38 // Return the bit position we will set [0-31].
40 int32_t imm = N->getSExtValue();
41 return XformMskToBitPosU5Imm(imm);
44 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
45 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
47 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
48 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
50 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
51 (HexagonCONST32 node:$addr), [{
52 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
55 // Hexagon V4 Architecture spec defines 8 instruction classes:
56 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
60 // ========================================
61 // Loads (8/16/32/64 bit)
65 // ========================================
66 // Stores (8/16/32/64 bit)
69 // ALU32 Instructions:
70 // ========================================
71 // Arithmetic / Logical (32 bit)
74 // XTYPE Instructions (32/64 bit):
75 // ========================================
76 // Arithmetic, Logical, Bit Manipulation
77 // Multiply (Integer, Fractional, Complex)
78 // Permute / Vector Permute Operations
79 // Predicate Operations
80 // Shift / Shift with Add/Sub/Logical
82 // Vector Halfword (ALU, Shift, Multiply)
83 // Vector Word (ALU, Shift)
86 // ========================================
87 // Jump/Call PC-relative
90 // ========================================
93 // MEMOP Instructions:
94 // ========================================
95 // Operation on memory (8/16/32 bit)
98 // ========================================
103 // ========================================
104 // Control-Register Transfers
105 // Hardware Loop Setup
106 // Predicate Logicals & Reductions
108 // SYSTEM Instructions (not implemented in the compiler):
109 // ========================================
115 //===----------------------------------------------------------------------===//
117 //===----------------------------------------------------------------------===//
119 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
121 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
122 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
125 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
126 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
127 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
128 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
130 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
131 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
132 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
133 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
135 let isCodeGenOnly = 0 in {
136 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
137 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
138 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
141 // Pats for instruction selection.
143 // A class to embed the usual comparison patfrags within a zext to i32.
144 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
145 // names, or else the frag's "body" won't match the operands.
146 class CmpInReg<PatFrag Op>
147 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
149 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
150 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
152 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
154 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
155 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
156 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
158 let validSubTargets = HasV4SubT;
159 let InputType = "reg";
160 let CextOpcode = mnemonic;
162 let isCommutable = IsComm;
163 let hasSideEffects = 0;
170 let Inst{27-21} = 0b0111110;
171 let Inst{20-16} = Rs;
173 let Inst{7-5} = MinOp;
177 let isCodeGenOnly = 0 in {
178 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
179 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
180 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
181 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
182 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
183 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
186 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
187 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
188 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
189 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
191 let validSubTargets = HasV4SubT;
192 let InputType = "imm";
193 let CextOpcode = mnemonic;
195 let isCommutable = IsComm;
196 let hasSideEffects = 0;
197 let isExtendable = IsImmExt;
198 let opExtendable = !if (IsImmExt, 2, 0);
199 let isExtentSigned = IsImmSigned;
200 let opExtentBits = ImmBits;
207 let Inst{27-24} = 0b1101;
208 let Inst{22-21} = MajOp;
209 let Inst{20-16} = Rs;
210 let Inst{12-5} = Imm;
212 let Inst{3} = IsHalf;
216 let isCodeGenOnly = 0 in {
217 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
218 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
219 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
220 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
221 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
222 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
224 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
225 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
226 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
228 let validSubTargets = HasV4SubT;
229 let InputType = "imm";
230 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
231 let isExtendable = 1;
232 let opExtendable = 2;
233 let isExtentSigned = 1;
234 let opExtentBits = 8;
242 let Inst{27-24} = 0b0011;
244 let Inst{21} = IsNeg;
245 let Inst{20-16} = Rs;
251 let isCodeGenOnly = 0 in {
252 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
253 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
256 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
257 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
258 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
259 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
261 // Preserve the S2_tstbit_r generation
262 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
263 (i32 IntRegs:$src1))), 0)))),
264 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
267 //===----------------------------------------------------------------------===//
269 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
274 //===----------------------------------------------------------------------===//
276 // Combine a word and an immediate into a register pair.
277 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
279 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
280 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
286 let Inst{27-24} = 0b0011;
287 let Inst{22-21} = MajOp;
288 let Inst{20-16} = Rs;
294 let opExtendable = 2, isCodeGenOnly = 0 in
295 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
296 "$Rdd = combine($Rs, #$s8)">;
298 let opExtendable = 1, isCodeGenOnly = 0 in
299 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
300 "$Rdd = combine(#$s8, $Rs)">;
302 def HexagonWrapperCombineRI_V4 :
303 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
304 def HexagonWrapperCombineIR_V4 :
305 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
307 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
308 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
311 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
312 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
315 // A4_combineii: Set two small immediates.
316 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
317 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
318 "$Rdd = combine(#$s8, #$U6)"> {
324 let Inst{27-23} = 0b11001;
325 let Inst{20-16} = U6{5-1};
326 let Inst{13} = U6{0};
331 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
335 //===----------------------------------------------------------------------===//
337 //===----------------------------------------------------------------------===//
339 def Zext64: OutPatFrag<(ops node:$Rs),
340 (i64 (A4_combineir 0, (i32 $Rs)))>;
341 def Sext64: OutPatFrag<(ops node:$Rs),
342 (i64 (A2_sxtw (i32 $Rs)))>;
344 //===----------------------------------------------------------------------===//
345 // Template class for load instructions with Absolute set addressing mode.
346 //===----------------------------------------------------------------------===//
347 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
348 hasSideEffects = 0 in
349 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
350 LDInst<(outs RC:$dst1, IntRegs:$dst2),
352 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
360 let Inst{27-25} = 0b101;
361 let Inst{24-21} = MajOp;
362 let Inst{13-12} = 0b01;
363 let Inst{4-0} = dst1;
364 let Inst{20-16} = dst2;
365 let Inst{11-8} = addr{5-2};
366 let Inst{6-5} = addr{1-0};
369 let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
370 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
371 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
374 let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
375 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
376 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
379 let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
380 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
382 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
383 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
384 // Load - Indirect with long offset
385 let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
386 opExtentBits = 6, opExtendable = 3 in
387 class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
389 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
390 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
396 let CextOpcode = CextOp;
397 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
400 let Inst{27-25} = 0b110;
401 let Inst{24-21} = MajOp;
402 let Inst{20-16} = src1;
403 let Inst{13} = src2{1};
405 let Inst{11-8} = src3{5-2};
406 let Inst{7} = src2{0};
407 let Inst{6-5} = src3{1-0};
411 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
412 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
413 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
414 def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
418 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
419 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
420 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
421 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
422 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
423 def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
427 let accessSize = WordAccess, isCodeGenOnly = 0 in {
428 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
429 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
430 def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
433 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
434 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
437 multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
438 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
439 (HexagonCONST32 tglobaladdr:$src3)))),
440 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
442 def : Pat <(VT (ldOp (add IntRegs:$src1,
443 (HexagonCONST32 tglobaladdr:$src2)))),
444 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
447 let AddedComplexity = 60 in {
448 defm : T_LoadAbsReg_Pat <sextloadi8, L4_loadrb_ur>;
449 defm : T_LoadAbsReg_Pat <zextloadi8, L4_loadrub_ur>;
450 defm : T_LoadAbsReg_Pat <extloadi8, L4_loadrub_ur>;
452 defm : T_LoadAbsReg_Pat <sextloadi16, L4_loadrh_ur>;
453 defm : T_LoadAbsReg_Pat <zextloadi16, L4_loadruh_ur>;
454 defm : T_LoadAbsReg_Pat <extloadi16, L4_loadruh_ur>;
456 defm : T_LoadAbsReg_Pat <load, L4_loadri_ur>;
457 defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
460 //===----------------------------------------------------------------------===//
461 // Template classes for the non-predicated load instructions with
462 // base + register offset addressing mode
463 //===----------------------------------------------------------------------===//
464 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
465 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
466 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
467 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
475 let Inst{27-24} = 0b1010;
476 let Inst{23-21} = MajOp;
477 let Inst{20-16} = src1;
478 let Inst{12-8} = src2;
479 let Inst{13} = u2{1};
484 //===----------------------------------------------------------------------===//
485 // Template classes for the predicated load instructions with
486 // base + register offset addressing mode
487 //===----------------------------------------------------------------------===//
488 let isPredicated = 1 in
489 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
490 bit isNot, bit isPredNew>:
491 LDInst <(outs RC:$dst),
492 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
493 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
494 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
495 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
502 let isPredicatedFalse = isNot;
503 let isPredicatedNew = isPredNew;
507 let Inst{27-26} = 0b00;
508 let Inst{25} = isPredNew;
509 let Inst{24} = isNot;
510 let Inst{23-21} = MajOp;
511 let Inst{20-16} = src2;
512 let Inst{12-8} = src3;
513 let Inst{13} = u2{1};
515 let Inst{6-5} = src1;
519 //===----------------------------------------------------------------------===//
520 // multiclass for load instructions with base + register offset
522 //===----------------------------------------------------------------------===//
523 let hasSideEffects = 0, addrMode = BaseRegOffset in
524 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
526 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
527 InputType = "reg" in {
528 let isPredicable = 1 in
529 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
532 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
533 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
536 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
537 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
541 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
542 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
543 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
546 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
547 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
548 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
551 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
552 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
554 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
555 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
557 // 'def pats' for load instructions with base + register offset and non-zero
558 // immediate value. Immediate value is used to left-shift the second
560 class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
561 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
562 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
563 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
565 let AddedComplexity = 40 in {
566 def: Loadxs_pat<extloadi8, i32, L4_loadrub_rr>;
567 def: Loadxs_pat<zextloadi8, i32, L4_loadrub_rr>;
568 def: Loadxs_pat<sextloadi8, i32, L4_loadrb_rr>;
569 def: Loadxs_pat<extloadi16, i32, L4_loadruh_rr>;
570 def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
571 def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
572 def: Loadxs_pat<load, i32, L4_loadri_rr>;
573 def: Loadxs_pat<load, i64, L4_loadrd_rr>;
576 // 'def pats' for load instruction base + register offset and
577 // zero immediate value.
578 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
579 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
580 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
582 let AddedComplexity = 20 in {
583 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
584 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
585 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
586 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
587 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
588 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
589 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
590 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
594 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
595 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
599 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
600 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
603 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
604 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
607 let AddedComplexity = 20 in
608 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
609 s11_0ExtPred:$offset))),
610 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
611 s11_0ExtPred:$offset)))>,
615 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
616 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
619 let AddedComplexity = 20 in
620 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
621 s11_0ExtPred:$offset))),
622 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
623 s11_0ExtPred:$offset)))>,
627 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
628 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
631 let AddedComplexity = 20 in
632 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
633 s11_1ExtPred:$offset))),
634 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
635 s11_1ExtPred:$offset)))>,
639 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
640 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
643 let AddedComplexity = 20 in
644 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
645 s11_1ExtPred:$offset))),
646 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
647 s11_1ExtPred:$offset)))>,
651 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
652 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
655 let AddedComplexity = 100 in
656 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
657 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
658 s11_2ExtPred:$offset)))>,
662 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
663 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
666 let AddedComplexity = 100 in
667 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
668 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
669 s11_2ExtPred:$offset)))>,
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
678 //===----------------------------------------------------------------------===//
680 //===----------------------------------------------------------------------===//
682 //===----------------------------------------------------------------------===//
683 // Template class for store instructions with Absolute set addressing mode.
684 //===----------------------------------------------------------------------===//
685 let isExtended = 1, opExtendable = 1, opExtentBits = 6,
686 addrMode = AbsoluteSet, isNVStorable = 1 in
687 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
688 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
689 : STInst<(outs IntRegs:$dst),
690 (ins u6Ext:$addr, RC:$src),
691 mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
695 let accessSize = AccessSz;
696 let BaseOpcode = BaseOp#"_AbsSet";
700 let Inst{27-24} = 0b1011;
701 let Inst{23-21} = MajOp;
702 let Inst{20-16} = dst;
704 let Inst{12-8} = src;
706 let Inst{5-0} = addr;
709 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
710 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
712 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
714 let isNVStorable = 0 in {
715 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
716 0b011, HalfWordAccess, 1>;
717 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
718 0b110, DoubleWordAccess>;
721 let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
722 isExtended = 1, opExtentBits= 6 in
723 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
724 MemAccessSize AccessSz >
725 : NVInst <(outs IntRegs:$dst),
726 (ins u6Ext:$addr, IntRegs:$src),
727 mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
731 let accessSize = AccessSz;
732 let BaseOpcode = BaseOp#"_AbsSet";
736 let Inst{27-21} = 0b1011101;
737 let Inst{20-16} = dst;
738 let Inst{13-11} = 0b000;
739 let Inst{12-11} = MajOp;
740 let Inst{10-8} = src;
742 let Inst{5-0} = addr;
745 let mayStore = 1, addrMode = AbsoluteSet, isCodeGenOnly = 0 in {
746 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
747 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
748 def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
751 let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
752 addrMode = BaseLongOffset, AddedComplexity = 40 in
753 class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
754 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
756 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
757 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
758 []>, ImmRegShl, NewValueRel {
765 let accessSize = AccessSz;
766 let CextOpcode = CextOp;
767 let BaseOpcode = CextOp#"_shl";
770 let Inst{27-24} =0b1101;
771 let Inst{23-21} = MajOp;
772 let Inst{20-16} = src1;
773 let Inst{13} = src2{1};
774 let Inst{12-8} = src4;
776 let Inst{6} = src2{0};
777 let Inst{5-0} = src3;
780 let isCodeGenOnly = 0 in {
781 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
782 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
784 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
786 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
787 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
791 let AddedComplexity = 40 in
792 multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
794 def : Pat<(stOp (VT RC:$src4),
795 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
796 u0AlwaysExtPred:$src3)),
797 (MI IntRegs:$src1, u2ImmPred:$src2, u0AlwaysExtPred:$src3, RC:$src4)>;
799 def : Pat<(stOp (VT RC:$src4),
800 (add (shl IntRegs:$src1, u2ImmPred:$src2),
801 (HexagonCONST32 tglobaladdr:$src3))),
802 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
804 def : Pat<(stOp (VT RC:$src4),
805 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
806 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
809 defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
810 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
811 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
812 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
814 let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
815 opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
816 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
817 MemAccessSize AccessSz>
819 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
820 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
826 let CextOpcode = CextOp;
827 let BaseOpcode = CextOp#"_shl";
830 let Inst{27-21} = 0b1101101;
831 let Inst{12-11} = 0b00;
833 let Inst{20-16} = src1;
834 let Inst{13} = src2{1};
835 let Inst{12-11} = MajOp;
836 let Inst{10-8} = src4;
837 let Inst{6} = src2{0};
838 let Inst{5-0} = src3;
841 let isCodeGenOnly = 0 in {
842 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
843 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
844 def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
847 //===----------------------------------------------------------------------===//
848 // Template classes for the non-predicated store instructions with
849 // base + register offset addressing mode
850 //===----------------------------------------------------------------------===//
851 let isPredicable = 1 in
852 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
853 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
854 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
855 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
864 let Inst{27-24} = 0b1011;
865 let Inst{23-21} = MajOp;
866 let Inst{20-16} = Rs;
868 let Inst{13} = u2{1};
873 //===----------------------------------------------------------------------===//
874 // Template classes for the predicated store instructions with
875 // base + register offset addressing mode
876 //===----------------------------------------------------------------------===//
877 let isPredicated = 1 in
878 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
879 bit isNot, bit isPredNew, bit isH>
881 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
883 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
884 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
885 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
892 let isPredicatedFalse = isNot;
893 let isPredicatedNew = isPredNew;
897 let Inst{27-26} = 0b01;
898 let Inst{25} = isPredNew;
899 let Inst{24} = isNot;
900 let Inst{23-21} = MajOp;
901 let Inst{20-16} = Rs;
903 let Inst{13} = u2{1};
909 //===----------------------------------------------------------------------===//
910 // Template classes for the new-value store instructions with
911 // base + register offset addressing mode
912 //===----------------------------------------------------------------------===//
913 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
914 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
915 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
916 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
917 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
926 let Inst{27-21} = 0b1011101;
927 let Inst{20-16} = Rs;
929 let Inst{13} = u2{1};
931 let Inst{4-3} = MajOp;
935 //===----------------------------------------------------------------------===//
936 // Template classes for the predicated new-value store instructions with
937 // base + register offset addressing mode
938 //===----------------------------------------------------------------------===//
939 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
940 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
942 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
943 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
944 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
945 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
952 let isPredicatedFalse = isNot;
953 let isPredicatedNew = isPredNew;
956 let Inst{27-26} = 0b01;
957 let Inst{25} = isPredNew;
958 let Inst{24} = isNot;
959 let Inst{23-21} = 0b101;
960 let Inst{20-16} = Rs;
962 let Inst{13} = u2{1};
965 let Inst{4-3} = MajOp;
969 //===----------------------------------------------------------------------===//
970 // multiclass for store instructions with base + register offset addressing
972 //===----------------------------------------------------------------------===//
973 let isNVStorable = 1 in
974 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
975 bits<3> MajOp, bit isH = 0> {
976 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
977 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
980 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
981 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
984 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
985 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
989 //===----------------------------------------------------------------------===//
990 // multiclass for new-value store instructions with base + register offset
992 //===----------------------------------------------------------------------===//
993 let mayStore = 1, isNVStore = 1 in
994 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
996 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
997 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
1000 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
1001 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
1004 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
1005 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
1009 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
1010 isCodeGenOnly = 0 in {
1011 let accessSize = ByteAccess in
1012 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1013 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1015 let accessSize = HalfWordAccess in
1016 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1017 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1019 let accessSize = WordAccess in
1020 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1021 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1023 let isNVStorable = 0, accessSize = DoubleWordAccess in
1024 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1026 let isNVStorable = 0, accessSize = HalfWordAccess in
1027 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1030 class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
1031 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1032 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1033 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1035 let AddedComplexity = 40 in {
1036 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1037 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1038 def: Storexs_pat<store, I32, S4_storeri_rr>;
1039 def: Storexs_pat<store, I64, S4_storerd_rr>;
1042 // memd(Rx++#s4:3)=Rtt
1043 // memd(Rx++#s4:3:circ(Mu))=Rtt
1044 // memd(Rx++I:circ(Mu))=Rtt
1046 // memd(Rx++Mu:brev)=Rtt
1047 // memd(gp+#u16:3)=Rtt
1049 // Store doubleword conditionally.
1050 // if ([!]Pv[.new]) memd(#u6)=Rtt
1051 // TODO: needs to be implemented.
1053 //===----------------------------------------------------------------------===//
1055 //===----------------------------------------------------------------------===//
1056 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1058 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1059 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1060 mnemonic#"($Rs+#$offset)=#$S8",
1061 [], "", V4LDST_tc_st_SLOT01>,
1062 ImmRegRel, PredNewRel {
1068 string OffsetOpStr = !cast<string>(OffsetOp);
1069 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1070 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1071 /* u6_0Imm */ offset{5-0}));
1073 let IClass = 0b0011;
1075 let Inst{27-25} = 0b110;
1076 let Inst{22-21} = MajOp;
1077 let Inst{20-16} = Rs;
1078 let Inst{12-7} = offsetBits;
1079 let Inst{13} = S8{7};
1080 let Inst{6-0} = S8{6-0};
1083 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
1085 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1086 bit isPredNot, bit isPredNew >
1088 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1089 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
1090 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1091 [], "", V4LDST_tc_st_SLOT01>,
1092 ImmRegRel, PredNewRel {
1099 string OffsetOpStr = !cast<string>(OffsetOp);
1100 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1101 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1102 /* u6_0Imm */ offset{5-0}));
1103 let isPredicatedNew = isPredNew;
1104 let isPredicatedFalse = isPredNot;
1106 let IClass = 0b0011;
1108 let Inst{27-25} = 0b100;
1109 let Inst{24} = isPredNew;
1110 let Inst{23} = isPredNot;
1111 let Inst{22-21} = MajOp;
1112 let Inst{20-16} = Rs;
1113 let Inst{13} = S6{5};
1114 let Inst{12-7} = offsetBits;
1116 let Inst{4-0} = S6{4-0};
1120 //===----------------------------------------------------------------------===//
1121 // multiclass for store instructions with base + immediate offset
1122 // addressing mode and immediate stored value.
1123 // mem[bhw](Rx++#s4:3)=#s8
1124 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1125 //===----------------------------------------------------------------------===//
1127 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1129 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1131 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1134 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1136 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1137 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1139 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1140 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1144 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1145 InputType = "imm", isCodeGenOnly = 0 in {
1146 let accessSize = ByteAccess in
1147 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1149 let accessSize = HalfWordAccess in
1150 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1152 let accessSize = WordAccess in
1153 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1156 let Predicates = [HasV4T], AddedComplexity = 10 in {
1157 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1158 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1160 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1161 u6_1ImmPred:$src2)),
1162 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1164 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1165 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1168 let AddedComplexity = 6 in
1169 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1170 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1173 // memb(Rx++#s4:0:circ(Mu))=Rt
1174 // memb(Rx++I:circ(Mu))=Rt
1176 // memb(Rx++Mu:brev)=Rt
1177 // memb(gp+#u16:0)=Rt
1181 // TODO: needs to be implemented
1182 // memh(Re=#U6)=Rt.H
1183 // memh(Rs+#s11:1)=Rt.H
1184 let AddedComplexity = 6 in
1185 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1186 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1189 // memh(Rs+Ru<<#u2)=Rt.H
1190 // TODO: needs to be implemented.
1192 // memh(Ru<<#u2+#U6)=Rt.H
1193 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1194 // memh(Rx++#s4:1:circ(Mu))=Rt
1195 // memh(Rx++I:circ(Mu))=Rt.H
1196 // memh(Rx++I:circ(Mu))=Rt
1197 // memh(Rx++Mu)=Rt.H
1199 // memh(Rx++Mu:brev)=Rt.H
1200 // memh(Rx++Mu:brev)=Rt
1201 // memh(gp+#u16:1)=Rt
1202 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1203 // if ([!]Pv[.new]) memh(#u6)=Rt
1206 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1207 // TODO: needs to be implemented.
1209 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1210 // TODO: Needs to be implemented.
1214 // TODO: Needs to be implemented.
1217 let hasSideEffects = 0 in
1218 def STriw_pred_V4 : STInst2<(outs),
1219 (ins MEMri:$addr, PredRegs:$src1),
1220 "Error; should not emit",
1224 let AddedComplexity = 6 in
1225 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1226 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1229 // memw(Rx++#s4:2)=Rt
1230 // memw(Rx++#s4:2:circ(Mu))=Rt
1231 // memw(Rx++I:circ(Mu))=Rt
1233 // memw(Rx++Mu:brev)=Rt
1235 //===----------------------------------------------------------------------===
1237 //===----------------------------------------------------------------------===
1240 //===----------------------------------------------------------------------===//
1242 //===----------------------------------------------------------------------===//
1244 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1245 class T_store_io_nv <string mnemonic, RegisterClass RC,
1246 Operand ImmOp, bits<2>MajOp>
1247 : NVInst_V4 <(outs),
1248 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1249 mnemonic#"($src1+#$src2) = $src3.new",
1250 [],"",ST_tc_st_SLOT0> {
1252 bits<13> src2; // Actual address offset
1254 bits<11> offsetBits; // Represents offset encoding
1256 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1257 !if (!eq(mnemonic, "memh"), 12,
1258 !if (!eq(mnemonic, "memw"), 13, 0)));
1260 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1261 !if (!eq(mnemonic, "memh"), 1,
1262 !if (!eq(mnemonic, "memw"), 2, 0)));
1264 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1265 !if (!eq(mnemonic, "memh"), src2{11-1},
1266 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1268 let IClass = 0b1010;
1271 let Inst{26-25} = offsetBits{10-9};
1272 let Inst{24-21} = 0b1101;
1273 let Inst{20-16} = src1;
1274 let Inst{13} = offsetBits{8};
1275 let Inst{12-11} = MajOp;
1276 let Inst{10-8} = src3;
1277 let Inst{7-0} = offsetBits{7-0};
1280 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1281 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1282 bits<2>MajOp, bit PredNot, bit isPredNew>
1283 : NVInst_V4 <(outs),
1284 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1285 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1286 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1287 [],"",V2LDST_tc_st_SLOT0> {
1292 bits<6> offsetBits; // Represents offset encoding
1294 let isPredicatedNew = isPredNew;
1295 let isPredicatedFalse = PredNot;
1296 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1297 !if (!eq(mnemonic, "memh"), 7,
1298 !if (!eq(mnemonic, "memw"), 8, 0)));
1300 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1301 !if (!eq(mnemonic, "memh"), 1,
1302 !if (!eq(mnemonic, "memw"), 2, 0)));
1304 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1305 !if (!eq(mnemonic, "memh"), src3{6-1},
1306 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1308 let IClass = 0b0100;
1311 let Inst{26} = PredNot;
1312 let Inst{25} = isPredNew;
1313 let Inst{24-21} = 0b0101;
1314 let Inst{20-16} = src2;
1315 let Inst{13} = offsetBits{5};
1316 let Inst{12-11} = MajOp;
1317 let Inst{10-8} = src4;
1318 let Inst{7-3} = offsetBits{4-0};
1320 let Inst{1-0} = src1;
1323 // multiclass for new-value store instructions with base + immediate offset.
1325 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1327 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1328 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1330 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1331 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1333 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1334 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1336 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1338 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1343 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1344 let accessSize = ByteAccess in
1345 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1346 u6_0Ext, 0b00>, AddrModeRel;
1348 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1349 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1350 u6_1Ext, 0b01>, AddrModeRel;
1352 let accessSize = WordAccess, opExtentAlign = 2 in
1353 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1354 u6_2Ext, 0b10>, AddrModeRel;
1357 //===----------------------------------------------------------------------===//
1358 // Post increment loads with register offset.
1359 //===----------------------------------------------------------------------===//
1361 let hasNewValue = 1, isCodeGenOnly = 0 in
1362 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1364 let isCodeGenOnly = 0 in
1365 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1367 //===----------------------------------------------------------------------===//
1368 // Template class for non-predicated post increment .new stores
1369 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1370 //===----------------------------------------------------------------------===//
1371 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1372 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1373 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1374 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1375 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1376 mnemonic#"($src1++#$offset) = $src2.new",
1377 [], "$src1 = $_dst_">,
1384 string ImmOpStr = !cast<string>(ImmOp);
1385 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1386 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1387 /* s4_0Imm */ offset{3-0}));
1388 let IClass = 0b1010;
1390 let Inst{27-21} = 0b1011101;
1391 let Inst{20-16} = src1;
1393 let Inst{12-11} = MajOp;
1394 let Inst{10-8} = src2;
1396 let Inst{6-3} = offsetBits;
1400 //===----------------------------------------------------------------------===//
1401 // Template class for predicated post increment .new stores
1402 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1403 //===----------------------------------------------------------------------===//
1404 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1405 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1406 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1407 bits<2> MajOp, bit isPredNot, bit isPredNew >
1408 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1409 (ins PredRegs:$src1, IntRegs:$src2,
1410 ImmOp:$offset, IntRegs:$src3),
1411 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1412 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1413 [], "$src2 = $_dst_">,
1421 string ImmOpStr = !cast<string>(ImmOp);
1422 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1423 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1424 /* s4_0Imm */ offset{3-0}));
1425 let isPredicatedNew = isPredNew;
1426 let isPredicatedFalse = isPredNot;
1428 let IClass = 0b1010;
1430 let Inst{27-21} = 0b1011101;
1431 let Inst{20-16} = src2;
1433 let Inst{12-11} = MajOp;
1434 let Inst{10-8} = src3;
1435 let Inst{7} = isPredNew;
1436 let Inst{6-3} = offsetBits;
1437 let Inst{2} = isPredNot;
1438 let Inst{1-0} = src1;
1441 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1442 bits<2> MajOp, bit PredNot> {
1443 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1446 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1449 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1451 let BaseOpcode = "POST_"#BaseOp in {
1452 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1455 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1456 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1460 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1461 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1463 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1464 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1466 let accessSize = WordAccess, isCodeGenOnly = 0 in
1467 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1469 //===----------------------------------------------------------------------===//
1470 // Template class for post increment .new stores with register offset
1471 //===----------------------------------------------------------------------===//
1472 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1473 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1474 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1475 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1476 #mnemonic#"($src1++$src2) = $src3.new",
1477 [], "$src1 = $_dst_"> {
1481 let accessSize = AccessSz;
1483 let IClass = 0b1010;
1485 let Inst{27-21} = 0b1101101;
1486 let Inst{20-16} = src1;
1487 let Inst{13} = src2;
1488 let Inst{12-11} = MajOp;
1489 let Inst{10-8} = src3;
1493 let isCodeGenOnly = 0 in {
1494 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1495 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1496 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1499 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1500 // memb(Rx++I:circ(Mu))=Nt.new
1501 // memb(Rx++Mu)=Nt.new
1502 // memb(Rx++Mu:brev)=Nt.new
1503 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1504 // memh(Rx++I:circ(Mu))=Nt.new
1505 // memh(Rx++Mu)=Nt.new
1506 // memh(Rx++Mu:brev)=Nt.new
1508 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1509 // memw(Rx++I:circ(Mu))=Nt.new
1510 // memw(Rx++Mu)=Nt.new
1511 // memw(Rx++Mu:brev)=Nt.new
1513 //===----------------------------------------------------------------------===//
1515 //===----------------------------------------------------------------------===//
1517 //===----------------------------------------------------------------------===//
1519 //===----------------------------------------------------------------------===//
1521 //===----------------------------------------------------------------------===//
1522 // multiclass/template class for the new-value compare jumps with the register
1524 //===----------------------------------------------------------------------===//
1526 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1527 opExtentAlign = 2 in
1528 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1529 bit isNegCond, bit isTak>
1531 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1532 "if ("#!if(isNegCond, "!","")#mnemonic#
1533 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1534 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1535 #!if(isTak, "t","nt")#" $offset", []> {
1539 bits<3> Ns; // New-Value Operand
1540 bits<5> RegOp; // Non-New-Value Operand
1543 let isTaken = isTak;
1544 let isPredicatedFalse = isNegCond;
1545 let opNewValue{0} = NvOpNum;
1547 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1548 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1550 let IClass = 0b0010;
1552 let Inst{25-23} = majOp;
1553 let Inst{22} = isNegCond;
1554 let Inst{18-16} = Ns;
1555 let Inst{13} = isTak;
1556 let Inst{12-8} = RegOp;
1557 let Inst{21-20} = offset{10-9};
1558 let Inst{7-1} = offset{8-2};
1562 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1564 // Branch not taken:
1565 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1567 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1570 // NvOpNum = 0 -> First Operand is a new-value Register
1571 // NvOpNum = 1 -> Second Operand is a new-value Register
1573 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1575 let BaseOpcode = BaseOp#_NVJ in {
1576 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1577 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1581 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1582 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1583 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1584 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1585 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1587 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1588 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1589 isCodeGenOnly = 0 in {
1590 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1591 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1592 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1593 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1594 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1597 //===----------------------------------------------------------------------===//
1598 // multiclass/template class for the new-value compare jumps instruction
1599 // with a register and an unsigned immediate (U5) operand.
1600 //===----------------------------------------------------------------------===//
1602 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1603 opExtentAlign = 2 in
1604 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1607 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1608 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1609 #!if(isTak, "t","nt")#" $offset", []> {
1611 let isTaken = isTak;
1612 let isPredicatedFalse = isNegCond;
1613 let isTaken = isTak;
1619 let IClass = 0b0010;
1621 let Inst{25-23} = majOp;
1622 let Inst{22} = isNegCond;
1623 let Inst{18-16} = src1;
1624 let Inst{13} = isTak;
1625 let Inst{12-8} = src2;
1626 let Inst{21-20} = offset{10-9};
1627 let Inst{7-1} = offset{8-2};
1630 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1631 // Branch not taken:
1632 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1634 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1637 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1638 let BaseOpcode = BaseOp#_NVJri in {
1639 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1640 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1644 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1645 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1646 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1648 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1649 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1650 isCodeGenOnly = 0 in {
1651 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1652 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1653 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1656 //===----------------------------------------------------------------------===//
1657 // multiclass/template class for the new-value compare jumps instruction
1658 // with a register and an hardcoded 0/-1 immediate value.
1659 //===----------------------------------------------------------------------===//
1661 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1662 opExtentAlign = 2 in
1663 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1664 bit isNegCond, bit isTak>
1666 (ins IntRegs:$src1, brtarget:$offset),
1667 "if ("#!if(isNegCond, "!","")#mnemonic
1668 #"($src1.new, #"#ImmVal#")) jump:"
1669 #!if(isTak, "t","nt")#" $offset", []> {
1671 let isTaken = isTak;
1672 let isPredicatedFalse = isNegCond;
1673 let isTaken = isTak;
1677 let IClass = 0b0010;
1679 let Inst{25-23} = majOp;
1680 let Inst{22} = isNegCond;
1681 let Inst{18-16} = src1;
1682 let Inst{13} = isTak;
1683 let Inst{21-20} = offset{10-9};
1684 let Inst{7-1} = offset{8-2};
1687 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1689 // Branch not taken:
1690 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1692 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1695 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1697 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1698 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1699 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1703 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1704 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1705 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1707 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1708 Defs = [PC], hasSideEffects = 0, isCodeGenOnly = 0 in {
1709 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1710 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1711 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1714 // J4_hintjumpr: Hint indirect conditional jump.
1715 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1716 def J4_hintjumpr: JRInst <
1721 let IClass = 0b0101;
1722 let Inst{27-21} = 0b0010101;
1723 let Inst{20-16} = Rs;
1726 //===----------------------------------------------------------------------===//
1728 //===----------------------------------------------------------------------===//
1730 //===----------------------------------------------------------------------===//
1732 //===----------------------------------------------------------------------===//
1735 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1736 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0,
1737 Uses = [PC], validSubTargets = HasV4SubT, isCodeGenOnly = 0 in
1738 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1739 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1743 let IClass = 0b0110;
1744 let Inst{27-16} = 0b101001001001;
1745 let Inst{12-7} = u6;
1751 let hasSideEffects = 0 in
1752 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1753 : CRInst<(outs PredRegs:$Pd),
1754 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1755 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1756 !if (IsNeg,"!","") # "$Pu))",
1757 [], "", CR_tc_2early_SLOT23> {
1763 let IClass = 0b0110;
1764 let Inst{27-24} = 0b1011;
1765 let Inst{23} = IsNeg;
1766 let Inst{22-21} = OpBits;
1768 let Inst{17-16} = Ps;
1775 let isCodeGenOnly = 0 in {
1776 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1777 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1778 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1779 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1780 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1781 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1782 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1783 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1786 //===----------------------------------------------------------------------===//
1788 //===----------------------------------------------------------------------===//
1790 //===----------------------------------------------------------------------===//
1792 //===----------------------------------------------------------------------===//
1794 // Logical with-not instructions.
1795 let validSubTargets = HasV4SubT, isCodeGenOnly = 0 in {
1796 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1797 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1800 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1801 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1802 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1807 let IClass = 0b1101;
1808 let Inst{27-21} = 0b0101111;
1809 let Inst{20-16} = Rs;
1810 let Inst{12-8} = Rt;
1813 // Add and accumulate.
1814 // Rd=add(Rs,add(Ru,#s6))
1815 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1816 opExtendable = 3, isCodeGenOnly = 0 in
1817 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1818 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1819 "$Rd = add($Rs, add($Ru, #$s6))" ,
1820 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1821 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1822 "", ALU64_tc_2_SLOT23> {
1828 let IClass = 0b1101;
1830 let Inst{27-23} = 0b10110;
1831 let Inst{22-21} = s6{5-4};
1832 let Inst{20-16} = Rs;
1833 let Inst{13} = s6{3};
1834 let Inst{12-8} = Rd;
1835 let Inst{7-5} = s6{2-0};
1839 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1840 opExtentBits = 6, opExtendable = 2, isCodeGenOnly = 0 in
1841 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1842 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1843 "$Rd = add($Rs, sub(#$s6, $Ru))",
1844 [], "", ALU64_tc_2_SLOT23> {
1850 let IClass = 0b1101;
1852 let Inst{27-23} = 0b10111;
1853 let Inst{22-21} = s6{5-4};
1854 let Inst{20-16} = Rs;
1855 let Inst{13} = s6{3};
1856 let Inst{12-8} = Rd;
1857 let Inst{7-5} = s6{2-0};
1862 // Rdd=extract(Rss,#u6,#U6)
1863 // Rdd=extract(Rss,Rtt)
1864 // Rd=extract(Rs,Rtt)
1865 // Rd=extract(Rs,#u5,#U5)
1867 let isCodeGenOnly = 0 in {
1868 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1869 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1872 let hasNewValue = 1, isCodeGenOnly = 0 in {
1873 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1874 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1877 // Complex add/sub halfwords/words
1878 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
1879 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1880 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1881 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1882 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1885 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
1886 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1887 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
1890 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1891 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1892 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1895 // Logical xor with xor accumulation.
1896 // Rxx^=xor(Rss,Rtt)
1897 let hasSideEffects = 0, isCodeGenOnly = 0 in
1899 : SInst <(outs DoubleRegs:$Rxx),
1900 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1901 "$Rxx ^= xor($Rss, $Rtt)",
1902 [(set (i64 DoubleRegs:$Rxx),
1903 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
1904 (i64 DoubleRegs:$Rtt))))],
1905 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
1910 let IClass = 0b1100;
1912 let Inst{27-23} = 0b10101;
1913 let Inst{20-16} = Rss;
1914 let Inst{12-8} = Rtt;
1915 let Inst{4-0} = Rxx;
1918 // Rotate and reduce bytes
1919 // Rdd=vrcrotate(Rss,Rt,#u2)
1920 let hasSideEffects = 0, isCodeGenOnly = 0 in
1922 : SInst <(outs DoubleRegs:$Rdd),
1923 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
1924 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
1925 [], "", S_3op_tc_3x_SLOT23> {
1931 let IClass = 0b1100;
1933 let Inst{27-22} = 0b001111;
1934 let Inst{20-16} = Rss;
1935 let Inst{13} = u2{1};
1936 let Inst{12-8} = Rt;
1937 let Inst{7-6} = 0b11;
1938 let Inst{5} = u2{0};
1939 let Inst{4-0} = Rdd;
1942 // Rotate and reduce bytes with accumulation
1943 // Rxx+=vrcrotate(Rss,Rt,#u2)
1944 let hasSideEffects = 0, isCodeGenOnly = 0 in
1945 def S4_vrcrotate_acc
1946 : SInst <(outs DoubleRegs:$Rxx),
1947 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
1948 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
1949 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
1955 let IClass = 0b1100;
1957 let Inst{27-21} = 0b1011101;
1958 let Inst{20-16} = Rss;
1959 let Inst{13} = u2{1};
1960 let Inst{12-8} = Rt;
1961 let Inst{5} = u2{0};
1962 let Inst{4-0} = Rxx;
1966 // Vector reduce conditional negate halfwords
1967 let hasSideEffects = 0, isCodeGenOnly = 0 in
1969 : SInst <(outs DoubleRegs:$Rxx),
1970 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
1971 "$Rxx += vrcnegh($Rss, $Rt)", [],
1972 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
1977 let IClass = 0b1100;
1979 let Inst{27-21} = 0b1011001;
1980 let Inst{20-16} = Rss;
1982 let Inst{12-8} = Rt;
1983 let Inst{7-5} = 0b111;
1984 let Inst{4-0} = Rxx;
1988 let isCodeGenOnly = 0 in
1989 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
1991 // Arithmetic/Convergent round
1992 let isCodeGenOnly = 0 in
1993 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
1995 let isCodeGenOnly = 0 in
1996 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
1998 let Defs = [USR_OVF], isCodeGenOnly = 0 in
1999 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
2001 // Logical-logical words.
2002 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
2003 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
2004 opExtendable = 3, isCodeGenOnly = 0 in
2006 ALU64Inst<(outs IntRegs:$Rx),
2007 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2008 "$Rx = or($Ru, and($_src_, #$s10))" ,
2009 [(set (i32 IntRegs:$Rx),
2010 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
2011 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
2016 let IClass = 0b1101;
2018 let Inst{27-22} = 0b101001;
2019 let Inst{20-16} = Rx;
2020 let Inst{21} = s10{9};
2021 let Inst{13-5} = s10{8-0};
2025 // Miscellaneous ALU64 instructions.
2027 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
2028 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2029 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2034 let IClass = 0b1101;
2035 let Inst{27-21} = 0b0011111;
2036 let Inst{20-16} = Rs;
2037 let Inst{12-8} = Rt;
2038 let Inst{7-5} = 0b111;
2042 let hasSideEffects = 0, isCodeGenOnly = 0 in
2043 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2044 (ins IntRegs:$Rs, IntRegs:$Rt),
2045 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2050 let IClass = 0b1101;
2051 let Inst{27-24} = 0b0100;
2053 let Inst{20-16} = Rs;
2054 let Inst{12-8} = Rt;
2058 let isCodeGenOnly = 0 in {
2059 // Rx[&|]=xor(Rs,Rt)
2060 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
2061 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
2063 // Rx[&|^]=or(Rs,Rt)
2064 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
2066 let CextOpcode = "ORr_ORr" in
2067 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
2068 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
2070 // Rx[&|^]=and(Rs,Rt)
2071 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
2073 let CextOpcode = "ORr_ANDr" in
2074 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
2075 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
2077 // Rx[&|^]=and(Rs,~Rt)
2078 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
2079 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
2080 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
2083 // Compound or-or and or-and
2084 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
2085 opExtentBits = 10, opExtendable = 3 in
2086 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2087 : MInst_acc <(outs IntRegs:$Rx),
2088 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2089 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2090 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2091 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
2092 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
2097 let IClass = 0b1101;
2099 let Inst{27-24} = 0b1010;
2100 let Inst{23-22} = MajOp;
2101 let Inst{20-16} = Rs;
2102 let Inst{21} = s10{9};
2103 let Inst{13-5} = s10{8-0};
2107 let CextOpcode = "ORr_ANDr", isCodeGenOnly = 0 in
2108 def S4_or_andi : T_CompOR <"and", 0b00, and>;
2110 let CextOpcode = "ORr_ORr", isCodeGenOnly = 0 in
2111 def S4_or_ori : T_CompOR <"or", 0b10, or>;
2114 // Rd=modwrap(Rs,Rt)
2116 // Rd=cround(Rs,#u5)
2118 // Rd=round(Rs,#u5)[:sat]
2119 // Rd=round(Rs,Rt)[:sat]
2120 // Vector reduce add unsigned halfwords
2121 // Rd=vraddh(Rss,Rtt)
2123 // Rdd=vaddb(Rss,Rtt)
2124 // Vector conditional negate
2125 // Rdd=vcnegh(Rss,Rt)
2126 // Rxx+=vrcnegh(Rss,Rt)
2127 // Vector maximum bytes
2128 // Rdd=vmaxb(Rtt,Rss)
2129 // Vector reduce maximum halfwords
2130 // Rxx=vrmaxh(Rss,Ru)
2131 // Rxx=vrmaxuh(Rss,Ru)
2132 // Vector reduce maximum words
2133 // Rxx=vrmaxuw(Rss,Ru)
2134 // Rxx=vrmaxw(Rss,Ru)
2135 // Vector minimum bytes
2136 // Rdd=vminb(Rtt,Rss)
2137 // Vector reduce minimum halfwords
2138 // Rxx=vrminh(Rss,Ru)
2139 // Rxx=vrminuh(Rss,Ru)
2140 // Vector reduce minimum words
2141 // Rxx=vrminuw(Rss,Ru)
2142 // Rxx=vrminw(Rss,Ru)
2143 // Vector subtract bytes
2144 // Rdd=vsubb(Rss,Rtt)
2146 //===----------------------------------------------------------------------===//
2148 //===----------------------------------------------------------------------===//
2150 //===----------------------------------------------------------------------===//
2152 //===----------------------------------------------------------------------===//
2155 let isCodeGenOnly = 0 in
2156 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2159 let isCodeGenOnly = 0 in {
2160 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2161 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2162 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2165 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
2166 (S2_ct0p (i64 DoubleRegs:$Rss))>;
2167 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
2168 (S2_ct1p (i64 DoubleRegs:$Rss))>;
2170 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2171 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2172 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2176 let IClass = 0b1000;
2177 let Inst{27-24} = 0b1100;
2178 let Inst{23-21} = 0b001;
2179 let Inst{20-16} = Rs;
2180 let Inst{13-8} = s6;
2181 let Inst{7-5} = 0b000;
2185 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2186 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2187 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2191 let IClass = 0b1000;
2192 let Inst{27-24} = 0b1000;
2193 let Inst{23-21} = 0b011;
2194 let Inst{20-16} = Rs;
2195 let Inst{13-8} = s6;
2196 let Inst{7-5} = 0b010;
2201 // Bit test/set/clear
2202 let isCodeGenOnly = 0 in {
2203 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2204 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2207 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2208 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2209 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2210 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2211 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2214 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2215 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2216 // if ([!]tstbit(...)) jump ...
2217 let AddedComplexity = 100 in
2218 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2219 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2221 let AddedComplexity = 100 in
2222 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2223 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2225 let isCodeGenOnly = 0 in {
2226 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2227 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2228 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2231 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2232 // represented as a compare against "value & 0xFF", which is an exact match
2233 // for cmpb (same for cmph). The patterns below do not contain any additional
2234 // complexity that would make them preferable, and if they were actually used
2235 // instead of cmpb/cmph, they would result in a compare against register that
2236 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2237 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2238 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2239 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2240 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2241 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2242 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2244 //===----------------------------------------------------------------------===//
2246 //===----------------------------------------------------------------------===//
2248 //===----------------------------------------------------------------------===//
2250 //===----------------------------------------------------------------------===//
2252 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2254 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1,
2255 isCodeGenOnly = 0 in
2256 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2257 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2258 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2259 [(set (i32 IntRegs:$Rd),
2260 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2261 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2267 let IClass = 0b1101;
2269 let Inst{27-24} = 0b1000;
2270 let Inst{23} = U6{5};
2271 let Inst{22-21} = u6{5-4};
2272 let Inst{20-16} = Rs;
2273 let Inst{13} = u6{3};
2274 let Inst{12-8} = Rd;
2275 let Inst{7-5} = u6{2-0};
2276 let Inst{4-0} = U6{4-0};
2279 // Rd=add(#u6,mpyi(Rs,Rt))
2280 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2281 isExtendable = 1, opExtentBits = 6, opExtendable = 1, isCodeGenOnly = 0 in
2282 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2283 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2284 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2285 [(set (i32 IntRegs:$Rd),
2286 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2287 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2293 let IClass = 0b1101;
2295 let Inst{27-23} = 0b01110;
2296 let Inst{22-21} = u6{5-4};
2297 let Inst{20-16} = Rs;
2298 let Inst{13} = u6{3};
2299 let Inst{12-8} = Rt;
2300 let Inst{7-5} = u6{2-0};
2304 let hasNewValue = 1 in
2305 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2306 : ALU64Inst <(outs IntRegs:$dst), ins,
2307 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2309 [(set (i32 IntRegs:$dst),
2310 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2311 "", ALU64_tc_3x_SLOT23> {
2317 let IClass = 0b1101;
2319 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2321 let Inst{27-24} = 0b1111;
2322 let Inst{23} = MajOp;
2323 let Inst{22-21} = ImmValue{5-4};
2324 let Inst{20-16} = src3;
2325 let Inst{13} = ImmValue{3};
2326 let Inst{12-8} = dst;
2327 let Inst{7-5} = ImmValue{2-0};
2328 let Inst{4-0} = src1;
2331 let isCodeGenOnly = 0 in
2332 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2333 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2335 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2336 CextOpcode = "ADD_MPY", InputType = "imm", isCodeGenOnly = 0 in
2337 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2338 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2340 // Rx=add(Ru,mpyi(Rx,Rs))
2341 let validSubTargets = HasV4SubT, CextOpcode = "ADD_MPY", InputType = "reg",
2342 hasNewValue = 1, isCodeGenOnly = 0 in
2343 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2344 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2345 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2346 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2347 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2348 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2353 let IClass = 0b1110;
2355 let Inst{27-21} = 0b0011000;
2356 let Inst{12-8} = Rx;
2358 let Inst{20-16} = Rs;
2361 // Rd=add(##,mpyi(Rs,#U6))
2362 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2363 (HexagonCONST32 tglobaladdr:$src1)),
2364 (i32 (M4_mpyri_addi tglobaladdr:$src1, IntRegs:$src2,
2367 // Rd=add(##,mpyi(Rs,Rt))
2368 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2369 (HexagonCONST32 tglobaladdr:$src1)),
2370 (i32 (M4_mpyrr_addi tglobaladdr:$src1, IntRegs:$src2,
2373 // Vector reduce multiply word by signed half (32x16)
2374 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2375 let isCodeGenOnly = 0 in {
2376 def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
2377 def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
2380 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2381 let isCodeGenOnly = 0 in {
2382 def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
2383 def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
2385 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
2386 let isCodeGenOnly = 0 in {
2387 def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
2388 def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
2391 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2392 let isCodeGenOnly = 0 in {
2393 def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
2394 def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
2397 // Vector multiply halfwords, signed by unsigned
2398 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2399 let isCodeGenOnly = 0 in {
2400 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
2401 def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
2404 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2405 let isCodeGenOnly = 0 in {
2406 def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
2407 def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
2410 // Vector polynomial multiply halfwords
2411 // Rdd=vpmpyh(Rs,Rt)
2412 let isCodeGenOnly = 0 in
2413 def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
2415 // Rxx^=vpmpyh(Rs,Rt)
2416 let isCodeGenOnly = 0 in
2417 def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
2419 // Polynomial multiply words
2421 let isCodeGenOnly = 0 in
2422 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2424 // Rxx^=pmpyw(Rs,Rt)
2425 let isCodeGenOnly = 0 in
2426 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2428 //===----------------------------------------------------------------------===//
2430 //===----------------------------------------------------------------------===//
2433 //===----------------------------------------------------------------------===//
2434 // ALU64/Vector compare
2435 //===----------------------------------------------------------------------===//
2436 //===----------------------------------------------------------------------===//
2437 // Template class for vector compare
2438 //===----------------------------------------------------------------------===//
2440 let hasSideEffects = 0 in
2441 class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
2442 : ALU64_rr <(outs PredRegs:$Pd),
2443 (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
2444 "$Pd = "#Str#"($Rss, #$Imm)",
2445 [], "", ALU64_tc_2early_SLOT23> {
2450 let ImmBits{6-0} = Imm{6-0};
2451 let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
2453 let IClass = 0b1101;
2455 let Inst{27-24} = 0b1100;
2456 let Inst{22-21} = cmpOp;
2457 let Inst{20-16} = Rss;
2458 let Inst{12-5} = ImmBits;
2459 let Inst{4-3} = minOp;
2463 // Vector compare bytes
2464 let isCodeGenOnly = 0 in
2465 def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
2466 def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
2468 let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
2469 let isCodeGenOnly = 0 in
2470 def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
2472 let isCodeGenOnly = 0 in {
2473 def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
2474 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2475 def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
2478 // Vector compare halfwords
2479 let isCodeGenOnly = 0 in {
2480 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2481 def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
2482 def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
2485 // Vector compare words
2486 let isCodeGenOnly = 0 in {
2487 def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
2488 def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
2489 def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
2492 //===----------------------------------------------------------------------===//
2494 //===----------------------------------------------------------------------===//
2495 // Shift by immediate and accumulate/logical.
2496 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2497 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2498 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2499 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2500 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2501 hasNewValue = 1, opNewValue = 0, validSubTargets = HasV4SubT in
2502 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2503 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2504 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2505 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2506 [(set (i32 IntRegs:$Rd),
2507 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2508 "$Rd = $Rx", Itin> {
2515 let IClass = 0b1101;
2516 let Inst{27-24} = 0b1110;
2517 let Inst{23-21} = u8{7-5};
2518 let Inst{20-16} = Rd;
2519 let Inst{13} = u8{4};
2520 let Inst{12-8} = U5;
2521 let Inst{7-5} = u8{3-1};
2522 let Inst{4} = asl_lsr;
2523 let Inst{3} = u8{0};
2524 let Inst{2-1} = MajOp;
2527 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2528 InstrItinClass Itin> {
2529 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2530 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2533 let AddedComplexity = 200, isCodeGenOnly = 0 in {
2534 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2535 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2538 let AddedComplexity = 30, isCodeGenOnly = 0 in
2539 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2541 let isCodeGenOnly = 0 in
2542 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2544 // Vector conditional negate
2545 // Rdd=vcnegh(Rss,Rt)
2546 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in
2547 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2549 // Rd=[cround|round](Rs,Rt)
2550 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in {
2551 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2552 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2555 // Rd=round(Rs,Rt):sat
2556 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23,
2557 isCodeGenOnly = 0 in
2558 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2560 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2561 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2562 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2563 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2566 // Rdd=[add|sub](Rss,Rtt,Px):carry
2567 let isPredicateLate = 1, hasSideEffects = 0 in
2568 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2569 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2570 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2571 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2572 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2578 let IClass = 0b1100;
2580 let Inst{27-24} = 0b0010;
2581 let Inst{23-21} = MajOp;
2582 let Inst{20-16} = Rss;
2583 let Inst{12-8} = Rtt;
2585 let Inst{4-0} = Rdd;
2588 let isCodeGenOnly = 0 in {
2589 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2590 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2593 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2594 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2595 : SInst <(outs DoubleRegs:$Rxx),
2596 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2597 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2598 [] , "$dst2 = $Rxx"> {
2603 let IClass = 0b1100;
2605 let Inst{27-21} = 0b1011001;
2606 let Inst{20-16} = Rss;
2607 let Inst{13} = isUnsigned;
2608 let Inst{12-8} = Rxx;
2609 let Inst{7-5} = MinOp;
2613 // Vector reduce maximum halfwords
2614 // Rxx=vrmax[u]h(Rss,Ru)
2615 let isCodeGenOnly = 0 in {
2616 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2617 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2619 // Vector reduce maximum words
2620 // Rxx=vrmax[u]w(Rss,Ru)
2621 let isCodeGenOnly = 0 in {
2622 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2623 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2625 // Vector reduce minimum halfwords
2626 // Rxx=vrmin[u]h(Rss,Ru)
2627 let isCodeGenOnly = 0 in {
2628 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2629 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2632 // Vector reduce minimum words
2633 // Rxx=vrmin[u]w(Rss,Ru)
2634 let isCodeGenOnly = 0 in {
2635 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2636 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2639 // Shift an immediate left by register amount.
2640 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
2641 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2642 "$Rd = lsl(#$s6, $Rt)" ,
2643 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2644 (i32 IntRegs:$Rt)))],
2645 "", S_3op_tc_1_SLOT23> {
2650 let IClass = 0b1100;
2652 let Inst{27-22} = 0b011010;
2653 let Inst{20-16} = s6{5-1};
2654 let Inst{12-8} = Rt;
2655 let Inst{7-6} = 0b11;
2657 let Inst{5} = s6{0};
2660 //===----------------------------------------------------------------------===//
2662 //===----------------------------------------------------------------------===//
2664 //===----------------------------------------------------------------------===//
2665 // MEMOP: Word, Half, Byte
2666 //===----------------------------------------------------------------------===//
2668 def MEMOPIMM : SDNodeXForm<imm, [{
2669 // Call the transformation function XformM5ToU5Imm to get the negative
2670 // immediate's positive counterpart.
2671 int32_t imm = N->getSExtValue();
2672 return XformM5ToU5Imm(imm);
2675 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2676 // -1 .. -31 represented as 65535..65515
2677 // assigning to a short restores our desired signed value.
2678 // Call the transformation function XformM5ToU5Imm to get the negative
2679 // immediate's positive counterpart.
2680 int16_t imm = N->getSExtValue();
2681 return XformM5ToU5Imm(imm);
2684 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2685 // -1 .. -31 represented as 255..235
2686 // assigning to a char restores our desired signed value.
2687 // Call the transformation function XformM5ToU5Imm to get the negative
2688 // immediate's positive counterpart.
2689 int8_t imm = N->getSExtValue();
2690 return XformM5ToU5Imm(imm);
2693 def SETMEMIMM : SDNodeXForm<imm, [{
2694 // Return the bit position we will set [0-31].
2696 int32_t imm = N->getSExtValue();
2697 return XformMskToBitPosU5Imm(imm);
2700 def CLRMEMIMM : SDNodeXForm<imm, [{
2701 // Return the bit position we will clear [0-31].
2703 // we bit negate the value first
2704 int32_t imm = ~(N->getSExtValue());
2705 return XformMskToBitPosU5Imm(imm);
2708 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2709 // Return the bit position we will set [0-15].
2711 int16_t imm = N->getSExtValue();
2712 return XformMskToBitPosU4Imm(imm);
2715 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2716 // Return the bit position we will clear [0-15].
2718 // we bit negate the value first
2719 int16_t imm = ~(N->getSExtValue());
2720 return XformMskToBitPosU4Imm(imm);
2723 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2724 // Return the bit position we will set [0-7].
2726 int8_t imm = N->getSExtValue();
2727 return XformMskToBitPosU3Imm(imm);
2730 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2731 // Return the bit position we will clear [0-7].
2733 // we bit negate the value first
2734 int8_t imm = ~(N->getSExtValue());
2735 return XformMskToBitPosU3Imm(imm);
2738 //===----------------------------------------------------------------------===//
2739 // Template class for MemOp instructions with the register value.
2740 //===----------------------------------------------------------------------===//
2741 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2742 string memOp, bits<2> memOpBits> :
2744 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2745 opc#"($base+#$offset)"#memOp#"$delta",
2747 Requires<[UseMEMOP]> {
2752 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2754 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2755 !if (!eq(opcBits, 0b01), offset{6-1},
2756 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2758 let opExtentAlign = opcBits;
2759 let IClass = 0b0011;
2760 let Inst{27-24} = 0b1110;
2761 let Inst{22-21} = opcBits;
2762 let Inst{20-16} = base;
2764 let Inst{12-7} = offsetBits;
2765 let Inst{6-5} = memOpBits;
2766 let Inst{4-0} = delta;
2769 //===----------------------------------------------------------------------===//
2770 // Template class for MemOp instructions with the immediate value.
2771 //===----------------------------------------------------------------------===//
2772 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2773 string memOp, bits<2> memOpBits> :
2775 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2776 opc#"($base+#$offset)"#memOp#"#$delta"
2777 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2779 Requires<[UseMEMOP]> {
2784 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2786 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2787 !if (!eq(opcBits, 0b01), offset{6-1},
2788 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2790 let opExtentAlign = opcBits;
2791 let IClass = 0b0011;
2792 let Inst{27-24} = 0b1111;
2793 let Inst{22-21} = opcBits;
2794 let Inst{20-16} = base;
2796 let Inst{12-7} = offsetBits;
2797 let Inst{6-5} = memOpBits;
2798 let Inst{4-0} = delta;
2801 // multiclass to define MemOp instructions with register operand.
2802 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2803 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2804 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2805 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2806 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2809 // multiclass to define MemOp instructions with immediate Operand.
2810 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2811 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2812 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2813 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2814 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2817 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2818 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2819 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2822 // Define MemOp instructions.
2823 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2824 validSubTargets =HasV4SubT in {
2825 let opExtentBits = 6, accessSize = ByteAccess, isCodeGenOnly = 0 in
2826 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2828 let opExtentBits = 7, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
2829 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2831 let opExtentBits = 8, accessSize = WordAccess, isCodeGenOnly = 0 in
2832 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2835 //===----------------------------------------------------------------------===//
2836 // Multiclass to define 'Def Pats' for ALU operations on the memory
2837 // Here value used for the ALU operation is an immediate value.
2838 // mem[bh](Rs+#0) += #U5
2839 // mem[bh](Rs+#u6) += #U5
2840 //===----------------------------------------------------------------------===//
2842 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2843 InstHexagon MI, SDNode OpNode> {
2844 let AddedComplexity = 180 in
2845 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2847 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2849 let AddedComplexity = 190 in
2850 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2852 (add IntRegs:$base, ExtPred:$offset)),
2853 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2856 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2857 InstHexagon addMI, InstHexagon subMI> {
2858 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2859 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2862 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2864 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2865 L4_iadd_memoph_io, L4_isub_memoph_io>;
2867 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2868 L4_iadd_memopb_io, L4_isub_memopb_io>;
2871 let Predicates = [HasV4T, UseMEMOP] in {
2872 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2873 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2874 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2877 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
2881 //===----------------------------------------------------------------------===//
2882 // multiclass to define 'Def Pats' for ALU operations on the memory.
2883 // Here value used for the ALU operation is a negative value.
2884 // mem[bh](Rs+#0) += #m5
2885 // mem[bh](Rs+#u6) += #m5
2886 //===----------------------------------------------------------------------===//
2888 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2889 PatLeaf immPred, ComplexPattern addrPred,
2890 SDNodeXForm xformFunc, InstHexagon MI> {
2891 let AddedComplexity = 190 in
2892 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2894 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2896 let AddedComplexity = 195 in
2897 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2899 (add IntRegs:$base, extPred:$offset)),
2900 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2903 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2905 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2906 ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>;
2908 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2909 ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>;
2912 let Predicates = [HasV4T, UseMEMOP] in {
2913 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2914 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2915 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2918 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2919 ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>;
2922 //===----------------------------------------------------------------------===//
2923 // Multiclass to define 'def Pats' for bit operations on the memory.
2924 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2925 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2926 //===----------------------------------------------------------------------===//
2928 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2929 PatLeaf extPred, ComplexPattern addrPred,
2930 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2932 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2933 let AddedComplexity = 250 in
2934 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2936 (add IntRegs:$base, extPred:$offset)),
2937 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2939 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2940 let AddedComplexity = 225 in
2941 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2943 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2944 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2947 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2949 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2950 ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
2952 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2953 ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
2954 // Half Word - clrbit
2955 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2956 ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
2957 // Half Word - setbit
2958 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2959 ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
2962 let Predicates = [HasV4T, UseMEMOP] in {
2963 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2964 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2965 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2966 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2967 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2969 // memw(Rs+#0) = [clrbit|setbit](#U5)
2970 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2971 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2972 CLRMEMIMM, L4_iand_memopw_io, and>;
2973 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2974 SETMEMIMM, L4_ior_memopw_io, or>;
2977 //===----------------------------------------------------------------------===//
2978 // Multiclass to define 'def Pats' for ALU operations on the memory
2979 // where addend is a register.
2980 // mem[bhw](Rs+#0) [+-&|]= Rt
2981 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2982 //===----------------------------------------------------------------------===//
2984 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2985 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2986 let AddedComplexity = 141 in
2987 // mem[bhw](Rs+#0) [+-&|]= Rt
2988 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2989 (i32 IntRegs:$addend)),
2990 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2991 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2993 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2994 let AddedComplexity = 150 in
2995 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2996 (i32 IntRegs:$orend)),
2997 (add IntRegs:$base, extPred:$offset)),
2998 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
3001 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
3002 ComplexPattern addrPred, PatLeaf extPred,
3003 InstHexagon addMI, InstHexagon subMI,
3004 InstHexagon andMI, InstHexagon orMI > {
3006 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
3007 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
3008 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
3009 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
3012 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3014 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
3015 L4_add_memoph_io, L4_sub_memoph_io,
3016 L4_and_memoph_io, L4_or_memoph_io>;
3018 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
3019 L4_add_memopb_io, L4_sub_memopb_io,
3020 L4_and_memopb_io, L4_or_memopb_io>;
3023 // Define 'def Pats' for MemOps with register addend.
3024 let Predicates = [HasV4T, UseMEMOP] in {
3026 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
3027 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
3028 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
3030 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
3031 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io >;
3034 //===----------------------------------------------------------------------===//
3036 //===----------------------------------------------------------------------===//
3038 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3039 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3040 // hardware. However, compiler can still implement these patterns through
3041 // appropriate patterns combinations based on current implemented patterns.
3042 // The implemented patterns are: EQ/GT/GTU.
3043 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3045 // Following instruction is not being extended as it results into the
3046 // incorrect code for negative numbers.
3047 // Pd=cmpb.eq(Rs,#u8)
3049 // p=!cmp.eq(r1,#s10)
3050 let isCodeGenOnly = 0 in {
3051 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
3052 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
3053 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
3056 def : T_CMP_pat <C4_cmpneqi, setne, s10ExtPred>;
3057 def : T_CMP_pat <C4_cmpltei, setle, s10ExtPred>;
3058 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
3060 // rs <= rt -> !(rs > rt).
3062 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
3063 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
3064 // (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
3066 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3067 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
3068 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
3070 // rs != rt -> !(rs == rt).
3071 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
3072 (C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
3074 // SDNode for converting immediate C to C-1.
3075 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
3076 // Return the byte immediate const-1 as an SDNode.
3077 int32_t imm = N->getSExtValue();
3078 return XformU7ToU7M1Imm(imm);
3082 // zext( seteq ( and(Rs, 255), u8))
3084 // Pd=cmpb.eq(Rs, #u8)
3085 // if (Pd.new) Rd=#1
3086 // if (!Pd.new) Rd=#0
3087 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
3089 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
3095 // zext( setne ( and(Rs, 255), u8))
3097 // Pd=cmpb.eq(Rs, #u8)
3098 // if (Pd.new) Rd=#0
3099 // if (!Pd.new) Rd=#1
3100 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
3102 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
3108 // zext( seteq (Rs, and(Rt, 255)))
3110 // Pd=cmpb.eq(Rs, Rt)
3111 // if (Pd.new) Rd=#1
3112 // if (!Pd.new) Rd=#0
3113 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
3114 (i32 (and (i32 IntRegs:$Rs), 255)))))),
3115 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
3116 (i32 IntRegs:$Rt))),
3121 // zext( setne (Rs, and(Rt, 255)))
3123 // Pd=cmpb.eq(Rs, Rt)
3124 // if (Pd.new) Rd=#0
3125 // if (!Pd.new) Rd=#1
3126 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
3127 (i32 (and (i32 IntRegs:$Rs), 255)))))),
3128 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
3129 (i32 IntRegs:$Rt))),
3134 // zext( setugt ( and(Rs, 255), u8))
3136 // Pd=cmpb.gtu(Rs, #u8)
3137 // if (Pd.new) Rd=#1
3138 // if (!Pd.new) Rd=#0
3139 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
3141 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
3147 // zext( setugt ( and(Rs, 254), u8))
3149 // Pd=cmpb.gtu(Rs, #u8)
3150 // if (Pd.new) Rd=#1
3151 // if (!Pd.new) Rd=#0
3152 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
3154 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
3160 // zext( setult ( Rs, Rt))
3162 // Pd=cmp.ltu(Rs, Rt)
3163 // if (Pd.new) Rd=#1
3164 // if (!Pd.new) Rd=#0
3165 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
3166 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3167 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
3168 (i32 IntRegs:$Rs))),
3173 // zext( setlt ( Rs, Rt))
3175 // Pd=cmp.lt(Rs, Rt)
3176 // if (Pd.new) Rd=#1
3177 // if (!Pd.new) Rd=#0
3178 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3179 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3180 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
3181 (i32 IntRegs:$Rs))),
3186 // zext( setugt ( Rs, Rt))
3188 // Pd=cmp.gtu(Rs, Rt)
3189 // if (Pd.new) Rd=#1
3190 // if (!Pd.new) Rd=#0
3191 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3192 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
3193 (i32 IntRegs:$Rt))),
3197 // This pattern interefers with coremark performance, not implementing at this
3200 // zext( setgt ( Rs, Rt))
3202 // Pd=cmp.gt(Rs, Rt)
3203 // if (Pd.new) Rd=#1
3204 // if (!Pd.new) Rd=#0
3207 // zext( setuge ( Rs, Rt))
3209 // Pd=cmp.ltu(Rs, Rt)
3210 // if (Pd.new) Rd=#0
3211 // if (!Pd.new) Rd=#1
3212 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
3213 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3214 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
3215 (i32 IntRegs:$Rs))),
3220 // zext( setge ( Rs, Rt))
3222 // Pd=cmp.lt(Rs, Rt)
3223 // if (Pd.new) Rd=#0
3224 // if (!Pd.new) Rd=#1
3225 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3226 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3227 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
3228 (i32 IntRegs:$Rs))),
3233 // zext( setule ( Rs, Rt))
3235 // Pd=cmp.gtu(Rs, Rt)
3236 // if (Pd.new) Rd=#0
3237 // if (!Pd.new) Rd=#1
3238 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3239 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
3240 (i32 IntRegs:$Rt))),
3245 // zext( setle ( Rs, Rt))
3247 // Pd=cmp.gt(Rs, Rt)
3248 // if (Pd.new) Rd=#0
3249 // if (!Pd.new) Rd=#1
3250 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3251 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
3252 (i32 IntRegs:$Rt))),
3257 // zext( setult ( and(Rs, 255), u8))
3258 // Use the isdigit transformation below
3260 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
3261 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3262 // The isdigit transformation relies on two 'clever' aspects:
3263 // 1) The data type is unsigned which allows us to eliminate a zero test after
3264 // biasing the expression by 48. We are depending on the representation of
3265 // the unsigned types, and semantics.
3266 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3269 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3270 // The code is transformed upstream of llvm into
3271 // retval = (c-48) < 10 ? 1 : 0;
3272 let AddedComplexity = 139 in
3273 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3274 u7StrictPosImmPred:$src2)))),
3275 (i32 (C2_muxii (i1 (A4_cmpbgtui (i32 IntRegs:$src1),
3276 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
3280 //===----------------------------------------------------------------------===//
3282 //===----------------------------------------------------------------------===//
3284 //===----------------------------------------------------------------------===//
3285 // Multiclass for DeallocReturn
3286 //===----------------------------------------------------------------------===//
3287 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3288 : LD0Inst<(outs), (ins PredRegs:$src),
3289 !if(isNot, "if (!$src", "if ($src")#
3290 !if(isPredNew, ".new) ", ") ")#mnemonic#
3291 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3292 [], "", LD_tc_3or4stall_SLOT0> {
3295 let BaseOpcode = "L4_RETURN";
3296 let isPredicatedFalse = isNot;
3297 let isPredicatedNew = isPredNew;
3298 let isTaken = isTak;
3299 let IClass = 0b1001;
3301 let Inst{27-16} = 0b011000011110;
3303 let Inst{13} = isNot;
3304 let Inst{12} = isTak;
3305 let Inst{11} = isPredNew;
3307 let Inst{9-8} = src;
3308 let Inst{4-0} = 0b11110;
3311 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3312 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3313 let isPredicated = 1 in {
3314 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3315 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3316 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3320 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3321 let isBarrier = 1, isPredicable = 1 in
3322 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3323 LD_tc_3or4stall_SLOT0> {
3324 let BaseOpcode = "L4_RETURN";
3325 let IClass = 0b1001;
3326 let Inst{27-16} = 0b011000011110;
3327 let Inst{13-10} = 0b0000;
3328 let Inst{4-0} = 0b11110;
3330 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3331 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3334 let isReturn = 1, isTerminator = 1,
3335 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3336 validSubTargets = HasV4SubT, isCodeGenOnly = 0 in
3337 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3339 // Restore registers and dealloc return function call.
3340 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3341 Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
3342 let validSubTargets = HasV4SubT in
3343 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
3344 (ins calltarget:$dst),
3350 // Restore registers and dealloc frame before a tail call.
3351 let isCall = 1, isBarrier = 1, isAsmParserOnly = 1,
3352 Defs = [R29, R30, R31, PC] in {
3353 let validSubTargets = HasV4SubT in
3354 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3355 (ins calltarget:$dst),
3361 // Save registers function call.
3362 let isCall = 1, isBarrier = 1, isAsmParserOnly = 1,
3363 Uses = [R29, R31] in {
3364 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3365 (ins calltarget:$dst),
3366 "call $dst // Save_calle_saved_registers",
3371 //===----------------------------------------------------------------------===//
3372 // Template class for non predicated store instructions with
3373 // GP-Relative or absolute addressing.
3374 //===----------------------------------------------------------------------===//
3375 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3376 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3377 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3378 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3379 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3380 [], "", V2LDST_tc_st_SLOT01> {
3383 bits<16> offsetBits;
3385 string ImmOpStr = !cast<string>(ImmOp);
3386 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3387 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3388 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3389 /* u16_0Imm */ addr{15-0})));
3390 let IClass = 0b0100;
3392 let Inst{26-25} = offsetBits{15-14};
3394 let Inst{23-22} = MajOp;
3395 let Inst{21} = isHalf;
3396 let Inst{20-16} = offsetBits{13-9};
3397 let Inst{13} = offsetBits{8};
3398 let Inst{12-8} = src;
3399 let Inst{7-0} = offsetBits{7-0};
3402 //===----------------------------------------------------------------------===//
3403 // Template class for predicated store instructions with
3404 // GP-Relative or absolute addressing.
3405 //===----------------------------------------------------------------------===//
3406 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3408 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3409 bit isHalf, bit isNot, bit isNew>
3410 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3411 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3412 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3413 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3418 let isPredicatedNew = isNew;
3419 let isPredicatedFalse = isNot;
3421 let IClass = 0b1010;
3423 let Inst{27-24} = 0b1111;
3424 let Inst{23-22} = MajOp;
3425 let Inst{21} = isHalf;
3426 let Inst{17-16} = absaddr{5-4};
3427 let Inst{13} = isNew;
3428 let Inst{12-8} = src2;
3430 let Inst{6-3} = absaddr{3-0};
3431 let Inst{2} = isNot;
3432 let Inst{1-0} = src1;
3435 //===----------------------------------------------------------------------===//
3436 // Template class for predicated store instructions with absolute addressing.
3437 //===----------------------------------------------------------------------===//
3438 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3439 bits<2> MajOp, bit isHalf>
3440 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1, isHalf>,
3442 string ImmOpStr = !cast<string>(ImmOp);
3443 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3444 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3445 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3446 /* u16_0Imm */ 16)));
3448 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3449 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3450 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3451 /* u16_0Imm */ 0)));
3454 //===----------------------------------------------------------------------===//
3455 // Multiclass for store instructions with absolute addressing.
3456 //===----------------------------------------------------------------------===//
3457 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3458 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3459 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3460 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3461 let opExtendable = 0, isPredicable = 1 in
3462 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3465 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3466 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3469 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3470 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3474 //===----------------------------------------------------------------------===//
3475 // Template class for non predicated new-value store instructions with
3476 // GP-Relative or absolute addressing.
3477 //===----------------------------------------------------------------------===//
3478 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3479 isNewValue = 1, opNewValue = 1 in
3480 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3481 : NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
3482 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3483 [], "", V2LDST_tc_st_SLOT0> {
3486 bits<16> offsetBits;
3488 string ImmOpStr = !cast<string>(ImmOp);
3489 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3490 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3491 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3492 /* u16_0Imm */ addr{15-0})));
3493 let IClass = 0b0100;
3496 let Inst{26-25} = offsetBits{15-14};
3497 let Inst{24-21} = 0b0101;
3498 let Inst{20-16} = offsetBits{13-9};
3499 let Inst{13} = offsetBits{8};
3500 let Inst{12-11} = MajOp;
3501 let Inst{10-8} = src;
3502 let Inst{7-0} = offsetBits{7-0};
3505 //===----------------------------------------------------------------------===//
3506 // Template class for predicated new-value store instructions with
3507 // absolute addressing.
3508 //===----------------------------------------------------------------------===//
3509 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3510 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3511 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3512 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3513 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3514 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3515 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3520 let isPredicatedNew = isNew;
3521 let isPredicatedFalse = isNot;
3523 let IClass = 0b1010;
3525 let Inst{27-24} = 0b1111;
3526 let Inst{23-21} = 0b101;
3527 let Inst{17-16} = absaddr{5-4};
3528 let Inst{13} = isNew;
3529 let Inst{12-11} = MajOp;
3530 let Inst{10-8} = src2;
3532 let Inst{6-3} = absaddr{3-0};
3533 let Inst{2} = isNot;
3534 let Inst{1-0} = src1;
3537 //===----------------------------------------------------------------------===//
3538 // Template class for non-predicated new-value store instructions with
3539 // absolute addressing.
3540 //===----------------------------------------------------------------------===//
3541 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3542 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3544 string ImmOpStr = !cast<string>(ImmOp);
3545 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3546 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3547 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3548 /* u16_0Imm */ 16)));
3550 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3551 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3552 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3553 /* u16_0Imm */ 0)));
3556 //===----------------------------------------------------------------------===//
3557 // Multiclass for new-value store instructions with absolute addressing.
3558 //===----------------------------------------------------------------------===//
3559 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3560 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3562 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3563 let opExtendable = 0, isPredicable = 1 in
3564 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3567 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3568 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3571 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3572 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3576 //===----------------------------------------------------------------------===//
3577 // Stores with absolute addressing
3578 //===----------------------------------------------------------------------===//
3579 let accessSize = ByteAccess, isCodeGenOnly = 0 in
3580 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3581 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3583 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3584 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3585 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3587 let accessSize = WordAccess, isCodeGenOnly = 0 in
3588 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3589 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3591 let isNVStorable = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3592 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3594 let isNVStorable = 0, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3595 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3597 //===----------------------------------------------------------------------===//
3598 // GP-relative stores.
3599 // mem[bhwd](#global)=Rt
3600 // Once predicated, these instructions map to absolute addressing mode.
3601 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3602 //===----------------------------------------------------------------------===//
3604 let validSubTargets = HasV4SubT, isAsmParserOnly = 1 in
3605 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3606 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3607 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3608 // Set BaseOpcode same as absolute addressing instructions so that
3609 // non-predicated GP-Rel instructions can have relate with predicated
3610 // Absolute instruction.
3611 let BaseOpcode = BaseOp#_abs;
3614 let validSubTargets = HasV4SubT, isAsmParserOnly = 1 in
3615 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3616 bits<2> MajOp, bit isHalf = 0> {
3617 // Set BaseOpcode same as absolute addressing instructions so that
3618 // non-predicated GP-Rel instructions can have relate with predicated
3619 // Absolute instruction.
3620 let BaseOpcode = BaseOp#_abs in {
3621 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3622 globaladdress, 0, isHalf>;
3624 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3628 let accessSize = ByteAccess in
3629 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3631 let accessSize = HalfWordAccess in
3632 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3634 let accessSize = WordAccess in
3635 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3637 let isNVStorable = 0, accessSize = DoubleWordAccess in
3638 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3639 u16_3Imm, 0b11>, PredNewRel;
3641 let isNVStorable = 0, accessSize = HalfWordAccess in
3642 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3643 u16_1Imm, 0b01, 1>, PredNewRel;
3645 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
3646 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
3648 class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
3650 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
3652 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
3653 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
3655 let Predicates = [HasV4T], AddedComplexity = 30 in {
3656 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3657 (HexagonCONST32 tglobaladdr:$absaddr)),
3658 (S2_storerbabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3660 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3661 (HexagonCONST32 tglobaladdr:$absaddr)),
3662 (S2_storerhabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3664 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3665 (S2_storeriabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3667 def : Pat<(store (i64 DoubleRegs:$src1),
3668 (HexagonCONST32 tglobaladdr:$absaddr)),
3669 (S2_storerdabs tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3672 // 64 bit atomic store
3673 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3674 (i64 DoubleRegs:$src1)),
3675 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3678 // Map from store(globaladdress) -> memd(#foo)
3679 let AddedComplexity = 100 in
3680 def : Pat <(store (i64 DoubleRegs:$src1),
3681 (HexagonCONST32_GP tglobaladdr:$global)),
3682 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3684 // 8 bit atomic store
3685 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3686 (i32 IntRegs:$src1)),
3687 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3689 // Map from store(globaladdress) -> memb(#foo)
3690 let AddedComplexity = 100 in
3691 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3692 (HexagonCONST32_GP tglobaladdr:$global)),
3693 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3695 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3696 // to "r0 = 1; memw(#foo) = r0"
3697 let AddedComplexity = 100 in
3698 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3699 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3701 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3702 (i32 IntRegs:$src1)),
3703 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3705 // Map from store(globaladdress) -> memh(#foo)
3706 let AddedComplexity = 100 in
3707 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3708 (HexagonCONST32_GP tglobaladdr:$global)),
3709 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3711 // 32 bit atomic store
3712 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3713 (i32 IntRegs:$src1)),
3714 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3716 // Map from store(globaladdress) -> memw(#foo)
3717 let AddedComplexity = 100 in
3718 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3719 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3721 //===----------------------------------------------------------------------===//
3722 // Template class for non predicated load instructions with
3723 // absolute addressing mode.
3724 //===----------------------------------------------------------------------===//
3725 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT in
3726 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3727 bits<3> MajOp, Operand AddrOp, bit isAbs>
3728 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3729 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3730 [], "", V2LDST_tc_ld_SLOT01> {
3733 bits<16> offsetBits;
3735 string ImmOpStr = !cast<string>(ImmOp);
3736 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3737 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3738 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3739 /* u16_0Imm */ addr{15-0})));
3741 let IClass = 0b0100;
3744 let Inst{26-25} = offsetBits{15-14};
3746 let Inst{23-21} = MajOp;
3747 let Inst{20-16} = offsetBits{13-9};
3748 let Inst{13-5} = offsetBits{8-0};
3749 let Inst{4-0} = dst;
3752 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3754 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1>, AddrModeRel {
3756 string ImmOpStr = !cast<string>(ImmOp);
3757 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3758 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3759 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3760 /* u16_0Imm */ 16)));
3762 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3763 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3764 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3765 /* u16_0Imm */ 0)));
3767 //===----------------------------------------------------------------------===//
3768 // Template class for predicated load instructions with
3769 // absolute addressing mode.
3770 //===----------------------------------------------------------------------===//
3771 let isPredicated = 1, hasNewValue = 1, opExtentBits = 6, opExtendable = 2 in
3772 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3773 bit isPredNot, bit isPredNew>
3774 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3775 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3776 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3781 let isPredicatedNew = isPredNew;
3782 let isPredicatedFalse = isPredNot;
3784 let IClass = 0b1001;
3786 let Inst{27-24} = 0b1111;
3787 let Inst{23-21} = MajOp;
3788 let Inst{20-16} = absaddr{5-1};
3790 let Inst{12} = isPredNew;
3791 let Inst{11} = isPredNot;
3792 let Inst{10-9} = src1;
3793 let Inst{8} = absaddr{0};
3795 let Inst{4-0} = dst;
3798 //===----------------------------------------------------------------------===//
3799 // Multiclass for the load instructions with absolute addressing mode.
3800 //===----------------------------------------------------------------------===//
3801 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3803 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3805 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3808 let addrMode = Absolute, isExtended = 1 in
3809 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3810 Operand ImmOp, bits<3> MajOp> {
3811 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3812 let opExtendable = 1, isPredicable = 1 in
3813 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3816 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3817 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3821 let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3822 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3823 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3826 let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3827 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3828 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3831 let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
3832 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3834 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3835 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3837 //===----------------------------------------------------------------------===//
3838 // multiclass for load instructions with GP-relative addressing mode.
3839 // Rx=mem[bhwd](##global)
3840 // Once predicated, these instructions map to absolute addressing mode.
3841 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3842 //===----------------------------------------------------------------------===//
3844 let isAsmParserOnly = 1 in
3845 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3847 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3848 let BaseOpcode = BaseOp#_abs;
3851 let accessSize = ByteAccess, hasNewValue = 1 in {
3852 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3853 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3856 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3857 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3858 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3861 let accessSize = WordAccess, hasNewValue = 1 in
3862 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3864 let accessSize = DoubleWordAccess in
3865 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3867 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
3868 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
3869 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
3870 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
3872 // Map from load(globaladdress) -> mem[u][bhwd](#foo)
3873 class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
3874 : Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
3875 (VT (MI tglobaladdr:$global))>;
3877 let AddedComplexity = 100 in {
3878 def: LoadGP_pats <extloadi8, L2_loadrbgp>;
3879 def: LoadGP_pats <sextloadi8, L2_loadrbgp>;
3880 def: LoadGP_pats <zextloadi8, L2_loadrubgp>;
3881 def: LoadGP_pats <extloadi16, L2_loadrhgp>;
3882 def: LoadGP_pats <sextloadi16, L2_loadrhgp>;
3883 def: LoadGP_pats <zextloadi16, L2_loadruhgp>;
3884 def: LoadGP_pats <load, L2_loadrigp>;
3885 def: LoadGP_pats <load, L2_loadrdgp, i64>;
3888 let AddedComplexity = 30 in {
3889 def: Storea_pat<truncstorei8, I32, u0AlwaysExtPred, S2_storerbabs>;
3890 def: Storea_pat<truncstorei16, I32, u0AlwaysExtPred, S2_storerhabs>;
3891 def: Storea_pat<store, I32, u0AlwaysExtPred, S2_storeriabs>;
3894 let AddedComplexity = 30 in {
3895 def: Loada_pat<load, i32, u0AlwaysExtPred, L4_loadri_abs>;
3896 def: Loada_pat<sextloadi8, i32, u0AlwaysExtPred, L4_loadrb_abs>;
3897 def: Loada_pat<zextloadi8, i32, u0AlwaysExtPred, L4_loadrub_abs>;
3898 def: Loada_pat<sextloadi16, i32, u0AlwaysExtPred, L4_loadrh_abs>;
3899 def: Loada_pat<zextloadi16, i32, u0AlwaysExtPred, L4_loadruh_abs>;
3902 let Predicates = [HasV4T], AddedComplexity = 30 in {
3903 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3904 (L4_loadri_abs tglobaladdr: $absaddr)>;
3906 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3907 (L4_loadrb_abs tglobaladdr:$absaddr)>;
3909 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3910 (L4_loadrub_abs tglobaladdr:$absaddr)>;
3912 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3913 (L4_loadrh_abs tglobaladdr:$absaddr)>;
3915 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3916 (L4_loadruh_abs tglobaladdr:$absaddr)>;
3919 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3920 let AddedComplexity = 100 in
3921 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3922 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3924 // When the Interprocedural Global Variable optimizer realizes that a certain
3925 // global variable takes only two constant values, it shrinks the global to
3926 // a boolean. Catch those loads here in the following 3 patterns.
3927 let AddedComplexity = 100 in
3928 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3929 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3931 let AddedComplexity = 100 in
3932 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3933 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3935 let AddedComplexity = 100 in
3936 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3937 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3940 // Transfer global address into a register
3941 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3942 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3943 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3945 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3948 // Transfer a block address into a register
3949 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3950 (TFRI_V4 tblockaddress:$src1)>,
3953 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3954 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3955 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3956 (ins PredRegs:$src1, s16Ext:$src2),
3957 "if($src1) $dst = #$src2",
3961 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3962 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3963 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3964 (ins PredRegs:$src1, s16Ext:$src2),
3965 "if(!$src1) $dst = #$src2",
3969 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3970 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3971 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3972 (ins PredRegs:$src1, s16Ext:$src2),
3973 "if($src1.new) $dst = #$src2",
3977 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3978 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3979 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3980 (ins PredRegs:$src1, s16Ext:$src2),
3981 "if(!$src1.new) $dst = #$src2",
3985 let AddedComplexity = 50, Predicates = [HasV4T] in
3986 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3987 (TFRI_V4 tglobaladdr:$src1)>,
3990 // Indexed store word - global address.
3991 // memw(Rs+#u6:2)=#S8
3992 let AddedComplexity = 10 in
3993 def STriw_offset_ext_V4 : STInst<(outs),
3994 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3995 "memw($src1+#$src2) = ##$src3",
3996 [(store (HexagonCONST32 tglobaladdr:$src3),
3997 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
4000 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
4001 (i64 (A4_combineir (i32 0), (i32 (S2_cl0p DoubleRegs:$src1))))>,
4004 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
4005 (i64 (A4_combineir (i32 0), (i32 (S2_ct0p DoubleRegs:$src1))))>,
4008 // i8/i16/i32 -> i64 loads
4009 // We need a complexity of 120 here to override preceding handling of
4011 let AddedComplexity = 120 in {
4012 def: Loadam_pat<extloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
4013 def: Loadam_pat<sextloadi8, i64, addrga, Sext64, L4_loadrb_abs>;
4014 def: Loadam_pat<zextloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
4016 def: Loadam_pat<extloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
4017 def: Loadam_pat<sextloadi16, i64, addrga, Sext64, L4_loadrh_abs>;
4018 def: Loadam_pat<zextloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
4020 def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
4021 def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
4022 def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
4024 let AddedComplexity = 100 in {
4025 def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
4026 def: Loada_pat<sextloadi8, i32, addrgp, L4_loadrb_abs>;
4027 def: Loada_pat<zextloadi8, i32, addrgp, L4_loadrub_abs>;
4029 def: Loada_pat<extloadi16, i32, addrgp, L4_loadruh_abs>;
4030 def: Loada_pat<sextloadi16, i32, addrgp, L4_loadrh_abs>;
4031 def: Loada_pat<zextloadi16, i32, addrgp, L4_loadruh_abs>;
4033 def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
4034 def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
4037 let AddedComplexity = 100 in {
4038 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
4039 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
4040 def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
4041 def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
4044 def: Loada_pat<atomic_load_8, i32, addrgp, L4_loadrub_abs>;
4045 def: Loada_pat<atomic_load_16, i32, addrgp, L4_loadruh_abs>;
4046 def: Loada_pat<atomic_load_32, i32, addrgp, L4_loadri_abs>;
4047 def: Loada_pat<atomic_load_64, i64, addrgp, L4_loadrd_abs>;
4049 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbabs>;
4050 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
4051 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
4052 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
4054 // Indexed store double word - global address.
4055 // memw(Rs+#u6:2)=#S8
4056 let AddedComplexity = 10 in
4057 def STrih_offset_ext_V4 : STInst<(outs),
4058 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
4059 "memh($src1+#$src2) = ##$src3",
4060 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
4061 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
4064 //===----------------------------------------------------------------------===//
4065 // :raw for of boundscheck:hi:lo insns
4066 //===----------------------------------------------------------------------===//
4068 // A4_boundscheck_lo: Detect if a register is within bounds.
4069 let hasSideEffects = 0, isCodeGenOnly = 0 in
4070 def A4_boundscheck_lo: ALU64Inst <
4071 (outs PredRegs:$Pd),
4072 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
4073 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
4078 let IClass = 0b1101;
4080 let Inst{27-23} = 0b00100;
4082 let Inst{7-5} = 0b100;
4084 let Inst{20-16} = Rss;
4085 let Inst{12-8} = Rtt;
4088 // A4_boundscheck_hi: Detect if a register is within bounds.
4089 let hasSideEffects = 0, isCodeGenOnly = 0 in
4090 def A4_boundscheck_hi: ALU64Inst <
4091 (outs PredRegs:$Pd),
4092 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
4093 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
4098 let IClass = 0b1101;
4100 let Inst{27-23} = 0b00100;
4102 let Inst{7-5} = 0b101;
4104 let Inst{20-16} = Rss;
4105 let Inst{12-8} = Rtt;
4108 let hasSideEffects = 0, isAsmParserOnly = 1 in
4109 def A4_boundscheck : MInst <
4110 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
4111 "$Pd=boundscheck($Rs,$Rtt)">;
4113 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
4114 let isPredicateLate = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
4115 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
4116 (ins DoubleRegs:$Rs, IntRegs:$Rt),
4117 "$Pd = tlbmatch($Rs, $Rt)",
4118 [], "", ALU64_tc_2early_SLOT23> {
4123 let IClass = 0b1101;
4124 let Inst{27-23} = 0b00100;
4125 let Inst{20-16} = Rs;
4127 let Inst{12-8} = Rt;
4128 let Inst{7-5} = 0b011;
4132 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
4133 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
4134 // We don't really want either one here.
4135 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
4136 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
4139 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
4140 // really do a load.
4141 let hasSideEffects = 1, mayLoad = 0, isCodeGenOnly = 0 in
4142 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
4143 "dcfetch($Rs + #$u11_3)",
4144 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
4145 "", LD_tc_ld_SLOT0> {
4149 let IClass = 0b1001;
4150 let Inst{27-21} = 0b0100000;
4151 let Inst{20-16} = Rs;
4153 let Inst{10-0} = u11_3{13-3};
4156 //===----------------------------------------------------------------------===//
4157 // Compound instructions
4158 //===----------------------------------------------------------------------===//
4160 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4161 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4162 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4163 isTerminator = 1, validSubTargets = HasV4SubT in
4164 class CJInst_tstbit_R0<string px, bit np, string tnt>
4165 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4166 ""#px#" = tstbit($Rs, #0); if ("
4167 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4168 [], "", COMPOUND, TypeCOMPOUND> {
4173 let isPredicatedFalse = np;
4174 // tnt: Taken/Not Taken
4175 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4176 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4178 let IClass = 0b0001;
4179 let Inst{27-26} = 0b00;
4180 let Inst{25} = !if (!eq(px, "!p1"), 1,
4181 !if (!eq(px, "p1"), 1, 0));
4182 let Inst{24-23} = 0b11;
4184 let Inst{21-20} = r9_2{10-9};
4185 let Inst{19-16} = Rs;
4186 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4187 let Inst{9-8} = 0b11;
4188 let Inst{7-1} = r9_2{8-2};
4191 let Defs = [PC, P0], Uses = [P0], isCodeGenOnly = 0 in {
4192 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4193 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4194 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4195 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4198 let Defs = [PC, P1], Uses = [P1], isCodeGenOnly = 0 in {
4199 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4200 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4201 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4202 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4206 let isBranch = 1, hasSideEffects = 0,
4207 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4208 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4209 opExtendable = 2, isTerminator = 1, validSubTargets = HasV4SubT in
4210 class CJInst_RR<string px, string op, bit np, string tnt>
4211 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4212 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4213 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4214 [], "", COMPOUND, TypeCOMPOUND> {
4220 let isPredicatedFalse = np;
4221 // tnt: Taken/Not Taken
4222 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4223 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4225 let IClass = 0b0001;
4226 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4227 !if (!eq(op, "gt"), 0b01001,
4228 !if (!eq(op, "gtu"), 0b01010, 0)));
4230 let Inst{21-20} = r9_2{10-9};
4231 let Inst{19-16} = Rs;
4232 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4233 // px: Predicate reg 0/1
4234 let Inst{12} = !if (!eq(px, "!p1"), 1,
4235 !if (!eq(px, "p1"), 1, 0));
4236 let Inst{11-8} = Rt;
4237 let Inst{7-1} = r9_2{8-2};
4240 // P[10] taken/not taken.
4241 multiclass T_tnt_CJInst_RR<string op, bit np> {
4242 let Defs = [PC, P0], Uses = [P0] in {
4243 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4244 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4246 let Defs = [PC, P1], Uses = [P1] in {
4247 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4248 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4251 // Predicate / !Predicate
4252 multiclass T_pnp_CJInst_RR<string op>{
4253 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4254 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4256 // TypeCJ Instructions compare RR and jump
4257 let isCodeGenOnly = 0 in {
4258 defm eq : T_pnp_CJInst_RR<"eq">;
4259 defm gt : T_pnp_CJInst_RR<"gt">;
4260 defm gtu : T_pnp_CJInst_RR<"gtu">;
4263 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4264 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4265 opExtentAlign = 2, opExtendable = 2, isTerminator = 1,
4266 validSubTargets = HasV4SubT in
4267 class CJInst_RU5<string px, string op, bit np, string tnt>
4268 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4269 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4270 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4271 [], "", COMPOUND, TypeCOMPOUND> {
4277 let isPredicatedFalse = np;
4278 // tnt: Taken/Not Taken
4279 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4280 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4282 let IClass = 0b0001;
4283 let Inst{27-26} = 0b00;
4284 // px: Predicate reg 0/1
4285 let Inst{25} = !if (!eq(px, "!p1"), 1,
4286 !if (!eq(px, "p1"), 1, 0));
4287 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4288 !if (!eq(op, "gt"), 0b01,
4289 !if (!eq(op, "gtu"), 0b10, 0)));
4291 let Inst{21-20} = r9_2{10-9};
4292 let Inst{19-16} = Rs;
4293 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4294 let Inst{12-8} = U5;
4295 let Inst{7-1} = r9_2{8-2};
4297 // P[10] taken/not taken.
4298 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4299 let Defs = [PC, P0], Uses = [P0] in {
4300 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4301 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4303 let Defs = [PC, P1], Uses = [P1] in {
4304 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4305 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4308 // Predicate / !Predicate
4309 multiclass T_pnp_CJInst_RU5<string op>{
4310 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4311 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4313 // TypeCJ Instructions compare RI and jump
4314 let isCodeGenOnly = 0 in {
4315 defm eq : T_pnp_CJInst_RU5<"eq">;
4316 defm gt : T_pnp_CJInst_RU5<"gt">;
4317 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4320 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4321 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4322 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4323 isTerminator = 1, validSubTargets = HasV4SubT in
4324 class CJInst_Rn1<string px, string op, bit np, string tnt>
4325 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4326 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4327 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4328 [], "", COMPOUND, TypeCOMPOUND> {
4333 let isPredicatedFalse = np;
4334 // tnt: Taken/Not Taken
4335 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4336 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4338 let IClass = 0b0001;
4339 let Inst{27-26} = 0b00;
4340 let Inst{25} = !if (!eq(px, "!p1"), 1,
4341 !if (!eq(px, "p1"), 1, 0));
4343 let Inst{24-23} = 0b11;
4345 let Inst{21-20} = r9_2{10-9};
4346 let Inst{19-16} = Rs;
4347 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4348 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4349 !if (!eq(op, "gt"), 0b01, 0));
4350 let Inst{7-1} = r9_2{8-2};
4353 // P[10] taken/not taken.
4354 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4355 let Defs = [PC, P0], Uses = [P0] in {
4356 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4357 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4359 let Defs = [PC, P1], Uses = [P1] in {
4360 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4361 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4364 // Predicate / !Predicate
4365 multiclass T_pnp_CJInst_Rn1<string op>{
4366 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4367 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4369 // TypeCJ Instructions compare -1 and jump
4370 let isCodeGenOnly = 0 in {
4371 defm eq : T_pnp_CJInst_Rn1<"eq">;
4372 defm gt : T_pnp_CJInst_Rn1<"gt">;
4375 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4376 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4377 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4378 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4379 isCodeGenOnly = 0 in
4380 def J4_jumpseti: CJInst <
4382 (ins u6Imm:$U6, brtarget:$r9_2),
4383 "$Rd = #$U6 ; jump $r9_2"> {
4388 let IClass = 0b0001;
4389 let Inst{27-24} = 0b0110;
4390 let Inst{21-20} = r9_2{10-9};
4391 let Inst{19-16} = Rd;
4392 let Inst{13-8} = U6;
4393 let Inst{7-1} = r9_2{8-2};
4396 // J4_jumpsetr: Direct unconditional jump and transfer register.
4397 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4398 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4399 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4400 isCodeGenOnly = 0 in
4401 def J4_jumpsetr: CJInst <
4403 (ins IntRegs:$Rs, brtarget:$r9_2),
4404 "$Rd = $Rs ; jump $r9_2"> {
4409 let IClass = 0b0001;
4410 let Inst{27-24} = 0b0111;
4411 let Inst{21-20} = r9_2{10-9};
4412 let Inst{11-8} = Rd;
4413 let Inst{19-16} = Rs;
4414 let Inst{7-1} = r9_2{8-2};