1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def DuplexIClass0: InstDuplex < 0 >;
15 def DuplexIClass1: InstDuplex < 1 >;
16 def DuplexIClass2: InstDuplex < 2 >;
17 let isExtendable = 1 in {
18 def DuplexIClass3: InstDuplex < 3 >;
19 def DuplexIClass4: InstDuplex < 4 >;
20 def DuplexIClass5: InstDuplex < 5 >;
21 def DuplexIClass6: InstDuplex < 6 >;
22 def DuplexIClass7: InstDuplex < 7 >;
24 def DuplexIClass8: InstDuplex < 8 >;
25 def DuplexIClass9: InstDuplex < 9 >;
26 def DuplexIClassA: InstDuplex < 0xA >;
27 def DuplexIClassB: InstDuplex < 0xB >;
28 def DuplexIClassC: InstDuplex < 0xC >;
29 def DuplexIClassD: InstDuplex < 0xD >;
30 def DuplexIClassE: InstDuplex < 0xE >;
31 def DuplexIClassF: InstDuplex < 0xF >;
33 def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
34 def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
36 let hasSideEffects = 0 in
37 class T_Immext<Operand ImmType>
38 : EXTENDERInst<(outs), (ins ImmType:$imm),
39 "immext(#$imm)", []> {
43 let Inst{27-16} = imm{31-20};
44 let Inst{13-0} = imm{19-6};
47 def A4_ext : T_Immext<u26_6Imm>;
48 let isCodeGenOnly = 1 in {
50 def A4_ext_b : T_Immext<brtarget>;
52 def A4_ext_c : T_Immext<calltarget>;
53 def A4_ext_g : T_Immext<globaladdress>;
56 def BITPOS32 : SDNodeXForm<imm, [{
57 // Return the bit position we will set [0-31].
59 int32_t imm = N->getSExtValue();
60 return XformMskToBitPosU5Imm(imm);
63 // Hexagon V4 Architecture spec defines 8 instruction classes:
64 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
68 // ========================================
69 // Loads (8/16/32/64 bit)
73 // ========================================
74 // Stores (8/16/32/64 bit)
77 // ALU32 Instructions:
78 // ========================================
79 // Arithmetic / Logical (32 bit)
82 // XTYPE Instructions (32/64 bit):
83 // ========================================
84 // Arithmetic, Logical, Bit Manipulation
85 // Multiply (Integer, Fractional, Complex)
86 // Permute / Vector Permute Operations
87 // Predicate Operations
88 // Shift / Shift with Add/Sub/Logical
90 // Vector Halfword (ALU, Shift, Multiply)
91 // Vector Word (ALU, Shift)
94 // ========================================
95 // Jump/Call PC-relative
98 // ========================================
101 // MEMOP Instructions:
102 // ========================================
103 // Operation on memory (8/16/32 bit)
106 // ========================================
111 // ========================================
112 // Control-Register Transfers
113 // Hardware Loop Setup
114 // Predicate Logicals & Reductions
116 // SYSTEM Instructions (not implemented in the compiler):
117 // ========================================
123 //===----------------------------------------------------------------------===//
125 //===----------------------------------------------------------------------===//
127 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
129 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
130 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
133 let BaseOpcode = "andn_rr", CextOpcode = "andn" in
134 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
135 let BaseOpcode = "orn_rr", CextOpcode = "orn" in
136 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
138 let CextOpcode = "rcmp.eq" in
139 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
140 let CextOpcode = "!rcmp.eq" in
141 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
143 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
144 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
145 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
147 // Pats for instruction selection.
149 // A class to embed the usual comparison patfrags within a zext to i32.
150 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
151 // names, or else the frag's "body" won't match the operands.
152 class CmpInReg<PatFrag Op>
153 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
155 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
156 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
158 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
159 def: T_cmp32_rr_pat<C4_cmplteu, setule, i1>;
161 def: T_cmp32_rr_pat<C4_cmplteu, RevCmp<setuge>, i1>;
163 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
164 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
165 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
167 let InputType = "reg";
168 let CextOpcode = mnemonic;
170 let isCommutable = IsComm;
171 let hasSideEffects = 0;
178 let Inst{27-21} = 0b0111110;
179 let Inst{20-16} = Rs;
181 let Inst{7-5} = MinOp;
185 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
186 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
187 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
188 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
189 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
190 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
192 let AddedComplexity = 100 in {
193 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
195 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
196 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
198 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
199 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
201 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
202 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
204 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
207 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
208 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
209 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
210 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
212 let InputType = "imm";
213 let CextOpcode = mnemonic;
215 let isCommutable = IsComm;
216 let hasSideEffects = 0;
217 let isExtendable = IsImmExt;
218 let opExtendable = !if (IsImmExt, 2, 0);
219 let isExtentSigned = IsImmSigned;
220 let opExtentBits = ImmBits;
227 let Inst{27-24} = 0b1101;
228 let Inst{22-21} = MajOp;
229 let Inst{20-16} = Rs;
230 let Inst{12-5} = Imm;
232 let Inst{3} = IsHalf;
236 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
237 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
238 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
239 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
240 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
241 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
243 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
244 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
245 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
247 let InputType = "imm";
248 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
249 let isExtendable = 1;
250 let opExtendable = 2;
251 let isExtentSigned = 1;
252 let opExtentBits = 8;
260 let Inst{27-24} = 0b0011;
262 let Inst{21} = IsNeg;
263 let Inst{20-16} = Rs;
269 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
270 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
272 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
273 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
274 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
275 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
277 // Preserve the S2_tstbit_r generation
278 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
279 (i32 IntRegs:$src1))), 0)))),
280 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
282 //===----------------------------------------------------------------------===//
284 //===----------------------------------------------------------------------===//
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 // Combine a word and an immediate into a register pair.
292 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
294 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
295 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
301 let Inst{27-24} = 0b0011;
302 let Inst{22-21} = MajOp;
303 let Inst{20-16} = Rs;
309 let opExtendable = 2 in
310 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
311 "$Rdd = combine($Rs, #$s8)">;
313 let opExtendable = 1 in
314 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
315 "$Rdd = combine(#$s8, $Rs)">;
317 // The complexity of the combines involving immediates should be greater
318 // than the complexity of the combine with two registers.
319 let AddedComplexity = 50 in {
320 def: Pat<(HexagonCOMBINE IntRegs:$r, s8ExtPred:$i),
321 (A4_combineri IntRegs:$r, s8ExtPred:$i)>;
323 def: Pat<(HexagonCOMBINE s8ExtPred:$i, IntRegs:$r),
324 (A4_combineir s8ExtPred:$i, IntRegs:$r)>;
327 // A4_combineii: Set two small immediates.
328 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
329 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
330 "$Rdd = combine(#$s8, #$U6)"> {
336 let Inst{27-23} = 0b11001;
337 let Inst{20-16} = U6{5-1};
338 let Inst{13} = U6{0};
343 // The complexity of the combine with two immediates should be greater than
344 // the complexity of a combine involving a register.
345 let AddedComplexity = 75 in
346 def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u6ExtPred:$u6),
347 (A4_combineii imm:$s8, imm:$u6)>;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 def Zext64: OutPatFrag<(ops node:$Rs),
358 (i64 (A4_combineir 0, (i32 $Rs)))>;
359 def Sext64: OutPatFrag<(ops node:$Rs),
360 (i64 (A2_sxtw (i32 $Rs)))>;
362 // Patterns to generate indexed loads with different forms of the address:
365 // - base (without offset).
366 multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
367 PatLeaf ImmPred, InstHexagon MI> {
368 def: Pat<(VT (Load AddrFI:$fi)),
369 (VT (ValueMod (MI AddrFI:$fi, 0)))>;
370 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
371 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
372 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
373 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
376 defm: Loadxm_pat<extloadi1, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
377 defm: Loadxm_pat<extloadi8, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
378 defm: Loadxm_pat<extloadi16, i64, Zext64, s11_1ExtPred, L2_loadruh_io>;
379 defm: Loadxm_pat<zextloadi1, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
380 defm: Loadxm_pat<zextloadi8, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
381 defm: Loadxm_pat<zextloadi16, i64, Zext64, s11_1ExtPred, L2_loadruh_io>;
382 defm: Loadxm_pat<sextloadi8, i64, Sext64, s11_0ExtPred, L2_loadrb_io>;
383 defm: Loadxm_pat<sextloadi16, i64, Sext64, s11_1ExtPred, L2_loadrh_io>;
385 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
386 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
388 //===----------------------------------------------------------------------===//
389 // Template class for load instructions with Absolute set addressing mode.
390 //===----------------------------------------------------------------------===//
391 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
392 hasSideEffects = 0 in
393 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
394 LDInst<(outs RC:$dst1, IntRegs:$dst2),
396 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
404 let Inst{27-25} = 0b101;
405 let Inst{24-21} = MajOp;
406 let Inst{13-12} = 0b01;
407 let Inst{4-0} = dst1;
408 let Inst{20-16} = dst2;
409 let Inst{11-8} = addr{5-2};
410 let Inst{6-5} = addr{1-0};
413 let accessSize = ByteAccess, hasNewValue = 1 in {
414 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
415 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
418 let accessSize = HalfWordAccess, hasNewValue = 1 in {
419 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
420 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
421 def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
422 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
425 let accessSize = WordAccess, hasNewValue = 1 in
426 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
428 let accessSize = WordAccess in {
429 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
430 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
433 let accessSize = DoubleWordAccess in
434 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
436 let accessSize = ByteAccess in
437 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
439 let accessSize = HalfWordAccess in
440 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
442 // Load - Indirect with long offset
443 let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
444 opExtentBits = 6, opExtendable = 3 in
445 class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
447 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
448 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
454 let CextOpcode = CextOp;
455 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
458 let Inst{27-25} = 0b110;
459 let Inst{24-21} = MajOp;
460 let Inst{20-16} = src1;
461 let Inst{13} = src2{1};
463 let Inst{11-8} = src3{5-2};
464 let Inst{7} = src2{0};
465 let Inst{6-5} = src3{1-0};
469 let accessSize = ByteAccess in {
470 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
471 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
472 def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
476 let accessSize = HalfWordAccess in {
477 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
478 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
479 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
480 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
481 def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
485 let accessSize = WordAccess in {
486 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
487 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
488 def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
491 let accessSize = DoubleWordAccess in
492 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
495 multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
496 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
497 (HexagonCONST32 tglobaladdr:$src3)))),
498 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
500 def : Pat <(VT (ldOp (add IntRegs:$src1,
501 (HexagonCONST32 tglobaladdr:$src2)))),
502 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
505 let AddedComplexity = 60 in {
506 defm : T_LoadAbsReg_Pat <sextloadi8, L4_loadrb_ur>;
507 defm : T_LoadAbsReg_Pat <zextloadi8, L4_loadrub_ur>;
508 defm : T_LoadAbsReg_Pat <extloadi8, L4_loadrub_ur>;
510 defm : T_LoadAbsReg_Pat <sextloadi16, L4_loadrh_ur>;
511 defm : T_LoadAbsReg_Pat <zextloadi16, L4_loadruh_ur>;
512 defm : T_LoadAbsReg_Pat <extloadi16, L4_loadruh_ur>;
514 defm : T_LoadAbsReg_Pat <load, L4_loadri_ur>;
515 defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
518 //===----------------------------------------------------------------------===//
519 // Template classes for the non-predicated load instructions with
520 // base + register offset addressing mode
521 //===----------------------------------------------------------------------===//
522 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
523 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
524 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
525 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
533 let Inst{27-24} = 0b1010;
534 let Inst{23-21} = MajOp;
535 let Inst{20-16} = src1;
536 let Inst{12-8} = src2;
537 let Inst{13} = u2{1};
542 //===----------------------------------------------------------------------===//
543 // Template classes for the predicated load instructions with
544 // base + register offset addressing mode
545 //===----------------------------------------------------------------------===//
546 let isPredicated = 1 in
547 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
548 bit isNot, bit isPredNew>:
549 LDInst <(outs RC:$dst),
550 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
551 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
552 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
553 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
560 let isPredicatedFalse = isNot;
561 let isPredicatedNew = isPredNew;
565 let Inst{27-26} = 0b00;
566 let Inst{25} = isPredNew;
567 let Inst{24} = isNot;
568 let Inst{23-21} = MajOp;
569 let Inst{20-16} = src2;
570 let Inst{12-8} = src3;
571 let Inst{13} = u2{1};
573 let Inst{6-5} = src1;
577 //===----------------------------------------------------------------------===//
578 // multiclass for load instructions with base + register offset
580 //===----------------------------------------------------------------------===//
581 let hasSideEffects = 0, addrMode = BaseRegOffset in
582 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
584 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
585 InputType = "reg" in {
586 let isPredicable = 1 in
587 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
590 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
591 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
594 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
595 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
599 let hasNewValue = 1, accessSize = ByteAccess in {
600 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
601 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
604 let hasNewValue = 1, accessSize = HalfWordAccess in {
605 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
606 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
609 let hasNewValue = 1, accessSize = WordAccess in
610 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
612 let accessSize = DoubleWordAccess in
613 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
615 // 'def pats' for load instructions with base + register offset and non-zero
616 // immediate value. Immediate value is used to left-shift the second
618 class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
619 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
620 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
621 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
623 let AddedComplexity = 40 in {
624 def: Loadxs_pat<extloadi8, i32, L4_loadrub_rr>;
625 def: Loadxs_pat<zextloadi8, i32, L4_loadrub_rr>;
626 def: Loadxs_pat<sextloadi8, i32, L4_loadrb_rr>;
627 def: Loadxs_pat<extloadi16, i32, L4_loadruh_rr>;
628 def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
629 def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
630 def: Loadxs_pat<load, i32, L4_loadri_rr>;
631 def: Loadxs_pat<load, i64, L4_loadrd_rr>;
634 // 'def pats' for load instruction base + register offset and
635 // zero immediate value.
636 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
637 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
638 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
640 let AddedComplexity = 20 in {
641 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
642 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
643 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
644 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
645 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
646 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
647 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
648 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
652 def: Pat<(i64 (zext (i1 PredRegs:$src1))),
653 (Zext64 (C2_muxii PredRegs:$src1, 1, 0))>;
656 def: Pat<(i64 (zext (i32 IntRegs:$src1))),
657 (Zext64 IntRegs:$src1)>;
660 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
661 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
663 let AddedComplexity = 100 in
664 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
665 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
666 s11_2ExtPred:$offset)))>;
669 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
670 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
672 //===----------------------------------------------------------------------===//
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
678 //===----------------------------------------------------------------------===//
680 //===----------------------------------------------------------------------===//
681 // Template class for store instructions with Absolute set addressing mode.
682 //===----------------------------------------------------------------------===//
683 let isExtended = 1, opExtendable = 1, opExtentBits = 6,
684 addrMode = AbsoluteSet, isNVStorable = 1 in
685 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
686 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
687 : STInst<(outs IntRegs:$dst),
688 (ins u6Ext:$addr, RC:$src),
689 mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
693 let accessSize = AccessSz;
694 let BaseOpcode = BaseOp#"_AbsSet";
698 let Inst{27-24} = 0b1011;
699 let Inst{23-21} = MajOp;
700 let Inst{20-16} = dst;
702 let Inst{12-8} = src;
704 let Inst{5-0} = addr;
707 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
708 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
710 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
712 let isNVStorable = 0 in {
713 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
714 0b011, HalfWordAccess, 1>;
715 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
716 0b110, DoubleWordAccess>;
719 let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
720 isExtended = 1, opExtentBits= 6 in
721 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
722 MemAccessSize AccessSz >
723 : NVInst <(outs IntRegs:$dst),
724 (ins u6Ext:$addr, IntRegs:$src),
725 mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
729 let accessSize = AccessSz;
730 let BaseOpcode = BaseOp#"_AbsSet";
734 let Inst{27-21} = 0b1011101;
735 let Inst{20-16} = dst;
736 let Inst{13-11} = 0b000;
737 let Inst{12-11} = MajOp;
738 let Inst{10-8} = src;
740 let Inst{5-0} = addr;
743 let mayStore = 1, addrMode = AbsoluteSet in {
744 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
745 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
746 def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
749 let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
750 addrMode = BaseLongOffset, AddedComplexity = 40 in
751 class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
752 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
754 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
755 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
756 []>, ImmRegShl, NewValueRel {
763 let accessSize = AccessSz;
764 let CextOpcode = CextOp;
765 let BaseOpcode = CextOp#"_shl";
768 let Inst{27-24} =0b1101;
769 let Inst{23-21} = MajOp;
770 let Inst{20-16} = src1;
771 let Inst{13} = src2{1};
772 let Inst{12-8} = src4;
774 let Inst{6} = src2{0};
775 let Inst{5-0} = src3;
778 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
779 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
781 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
783 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
784 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
787 let AddedComplexity = 40 in
788 multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
790 def : Pat<(stOp (VT RC:$src4),
791 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
792 u0AlwaysExtPred:$src3)),
793 (MI IntRegs:$src1, u2ImmPred:$src2, u0AlwaysExtPred:$src3, RC:$src4)>;
795 def : Pat<(stOp (VT RC:$src4),
796 (add (shl IntRegs:$src1, u2ImmPred:$src2),
797 (HexagonCONST32 tglobaladdr:$src3))),
798 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
800 def : Pat<(stOp (VT RC:$src4),
801 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
802 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
805 defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
806 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
807 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
808 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
810 let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
811 opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
812 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
813 MemAccessSize AccessSz>
815 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
816 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
822 let CextOpcode = CextOp;
823 let BaseOpcode = CextOp#"_shl";
826 let Inst{27-21} = 0b1101101;
827 let Inst{12-11} = 0b00;
829 let Inst{20-16} = src1;
830 let Inst{13} = src2{1};
831 let Inst{12-11} = MajOp;
832 let Inst{10-8} = src4;
833 let Inst{6} = src2{0};
834 let Inst{5-0} = src3;
837 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
838 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
839 def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
841 //===----------------------------------------------------------------------===//
842 // Template classes for the non-predicated store instructions with
843 // base + register offset addressing mode
844 //===----------------------------------------------------------------------===//
845 let isPredicable = 1 in
846 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
847 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
848 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
849 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
858 let Inst{27-24} = 0b1011;
859 let Inst{23-21} = MajOp;
860 let Inst{20-16} = Rs;
862 let Inst{13} = u2{1};
867 //===----------------------------------------------------------------------===//
868 // Template classes for the predicated store instructions with
869 // base + register offset addressing mode
870 //===----------------------------------------------------------------------===//
871 let isPredicated = 1 in
872 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
873 bit isNot, bit isPredNew, bit isH>
875 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
877 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
878 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
879 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
886 let isPredicatedFalse = isNot;
887 let isPredicatedNew = isPredNew;
891 let Inst{27-26} = 0b01;
892 let Inst{25} = isPredNew;
893 let Inst{24} = isNot;
894 let Inst{23-21} = MajOp;
895 let Inst{20-16} = Rs;
897 let Inst{13} = u2{1};
903 //===----------------------------------------------------------------------===//
904 // Template classes for the new-value store instructions with
905 // base + register offset addressing mode
906 //===----------------------------------------------------------------------===//
907 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
908 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
909 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
910 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
911 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
920 let Inst{27-21} = 0b1011101;
921 let Inst{20-16} = Rs;
923 let Inst{13} = u2{1};
925 let Inst{4-3} = MajOp;
929 //===----------------------------------------------------------------------===//
930 // Template classes for the predicated new-value store instructions with
931 // base + register offset addressing mode
932 //===----------------------------------------------------------------------===//
933 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
934 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
936 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
937 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
938 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
939 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
946 let isPredicatedFalse = isNot;
947 let isPredicatedNew = isPredNew;
950 let Inst{27-26} = 0b01;
951 let Inst{25} = isPredNew;
952 let Inst{24} = isNot;
953 let Inst{23-21} = 0b101;
954 let Inst{20-16} = Rs;
956 let Inst{13} = u2{1};
959 let Inst{4-3} = MajOp;
963 //===----------------------------------------------------------------------===//
964 // multiclass for store instructions with base + register offset addressing
966 //===----------------------------------------------------------------------===//
967 let isNVStorable = 1 in
968 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
969 bits<3> MajOp, bit isH = 0> {
970 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
971 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
974 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
975 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
978 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
979 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
983 //===----------------------------------------------------------------------===//
984 // multiclass for new-value store instructions with base + register offset
986 //===----------------------------------------------------------------------===//
987 let mayStore = 1, isNVStore = 1 in
988 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
990 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
991 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
994 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
995 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
998 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
999 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
1003 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
1004 let accessSize = ByteAccess in
1005 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1006 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1008 let accessSize = HalfWordAccess in
1009 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1010 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1012 let accessSize = WordAccess in
1013 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1014 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1016 let isNVStorable = 0, accessSize = DoubleWordAccess in
1017 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1019 let isNVStorable = 0, accessSize = HalfWordAccess in
1020 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1023 class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
1024 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1025 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1026 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1028 let AddedComplexity = 40 in {
1029 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1030 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1031 def: Storexs_pat<store, I32, S4_storeri_rr>;
1032 def: Storexs_pat<store, I64, S4_storerd_rr>;
1035 // memd(Rx++#s4:3)=Rtt
1036 // memd(Rx++#s4:3:circ(Mu))=Rtt
1037 // memd(Rx++I:circ(Mu))=Rtt
1039 // memd(Rx++Mu:brev)=Rtt
1040 // memd(gp+#u16:3)=Rtt
1042 // Store doubleword conditionally.
1043 // if ([!]Pv[.new]) memd(#u6)=Rtt
1044 // TODO: needs to be implemented.
1046 //===----------------------------------------------------------------------===//
1048 //===----------------------------------------------------------------------===//
1049 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1051 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1052 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1053 mnemonic#"($Rs+#$offset)=#$S8",
1054 [], "", V4LDST_tc_st_SLOT01>,
1055 ImmRegRel, PredNewRel {
1061 string OffsetOpStr = !cast<string>(OffsetOp);
1062 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1063 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1064 /* u6_0Imm */ offset{5-0}));
1066 let IClass = 0b0011;
1068 let Inst{27-25} = 0b110;
1069 let Inst{22-21} = MajOp;
1070 let Inst{20-16} = Rs;
1071 let Inst{12-7} = offsetBits;
1072 let Inst{13} = S8{7};
1073 let Inst{6-0} = S8{6-0};
1076 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
1078 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1079 bit isPredNot, bit isPredNew >
1081 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1082 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
1083 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1084 [], "", V4LDST_tc_st_SLOT01>,
1085 ImmRegRel, PredNewRel {
1092 string OffsetOpStr = !cast<string>(OffsetOp);
1093 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1094 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1095 /* u6_0Imm */ offset{5-0}));
1096 let isPredicatedNew = isPredNew;
1097 let isPredicatedFalse = isPredNot;
1099 let IClass = 0b0011;
1101 let Inst{27-25} = 0b100;
1102 let Inst{24} = isPredNew;
1103 let Inst{23} = isPredNot;
1104 let Inst{22-21} = MajOp;
1105 let Inst{20-16} = Rs;
1106 let Inst{13} = S6{5};
1107 let Inst{12-7} = offsetBits;
1109 let Inst{4-0} = S6{4-0};
1113 //===----------------------------------------------------------------------===//
1114 // multiclass for store instructions with base + immediate offset
1115 // addressing mode and immediate stored value.
1116 // mem[bhw](Rx++#s4:3)=#s8
1117 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1118 //===----------------------------------------------------------------------===//
1120 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1122 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1124 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1127 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1129 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1130 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1132 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1133 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1137 let hasSideEffects = 0, addrMode = BaseImmOffset,
1138 InputType = "imm" in {
1139 let accessSize = ByteAccess in
1140 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1142 let accessSize = HalfWordAccess in
1143 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1145 let accessSize = WordAccess in
1146 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1149 def IMM_BYTE : SDNodeXForm<imm, [{
1150 // -1 etc is represented as 255 etc
1151 // assigning to a byte restores our desired signed value.
1152 int8_t imm = N->getSExtValue();
1153 return CurDAG->getTargetConstant(imm, MVT::i32);
1156 def IMM_HALF : SDNodeXForm<imm, [{
1157 // -1 etc is represented as 65535 etc
1158 // assigning to a short restores our desired signed value.
1159 int16_t imm = N->getSExtValue();
1160 return CurDAG->getTargetConstant(imm, MVT::i32);
1163 def IMM_WORD : SDNodeXForm<imm, [{
1164 // -1 etc can be represented as 4294967295 etc
1165 // Currently, it's not doing this. But some optimization
1166 // might convert -1 to a large +ve number.
1167 // assigning to a word restores our desired signed value.
1168 int32_t imm = N->getSExtValue();
1169 return CurDAG->getTargetConstant(imm, MVT::i32);
1172 def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
1173 def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
1174 def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
1176 let AddedComplexity = 40 in {
1177 // Not using frameindex patterns for these stores, because the offset
1178 // is not extendable. This could cause problems during removing the frame
1179 // indices, since the offset with respect to R29/R30 may not fit in the
1181 def: Storexm_add_pat<truncstorei8, s8ExtPred, u6_0ImmPred, ToImmByte,
1183 def: Storexm_add_pat<truncstorei16, s8ExtPred, u6_1ImmPred, ToImmHalf,
1185 def: Storexm_add_pat<store, s8ExtPred, u6_2ImmPred, ToImmWord,
1189 def: Storexm_simple_pat<truncstorei8, s8ExtPred, ToImmByte, S4_storeirb_io>;
1190 def: Storexm_simple_pat<truncstorei16, s8ExtPred, ToImmHalf, S4_storeirh_io>;
1191 def: Storexm_simple_pat<store, s8ExtPred, ToImmWord, S4_storeiri_io>;
1193 // memb(Rx++#s4:0:circ(Mu))=Rt
1194 // memb(Rx++I:circ(Mu))=Rt
1196 // memb(Rx++Mu:brev)=Rt
1197 // memb(gp+#u16:0)=Rt
1200 // TODO: needs to be implemented
1201 // memh(Re=#U6)=Rt.H
1202 // memh(Rs+#s11:1)=Rt.H
1203 // memh(Rs+Ru<<#u2)=Rt.H
1204 // TODO: needs to be implemented.
1206 // memh(Ru<<#u2+#U6)=Rt.H
1207 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1208 // memh(Rx++#s4:1:circ(Mu))=Rt
1209 // memh(Rx++I:circ(Mu))=Rt.H
1210 // memh(Rx++I:circ(Mu))=Rt
1211 // memh(Rx++Mu)=Rt.H
1213 // memh(Rx++Mu:brev)=Rt.H
1214 // memh(Rx++Mu:brev)=Rt
1215 // memh(gp+#u16:1)=Rt
1216 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1217 // if ([!]Pv[.new]) memh(#u6)=Rt
1219 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1220 // TODO: needs to be implemented.
1222 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1223 // TODO: Needs to be implemented.
1227 // TODO: Needs to be implemented.
1228 // memw(Rx++#s4:2)=Rt
1229 // memw(Rx++#s4:2:circ(Mu))=Rt
1230 // memw(Rx++I:circ(Mu))=Rt
1232 // memw(Rx++Mu:brev)=Rt
1234 //===----------------------------------------------------------------------===
1236 //===----------------------------------------------------------------------===
1239 //===----------------------------------------------------------------------===//
1241 //===----------------------------------------------------------------------===//
1243 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1244 class T_store_io_nv <string mnemonic, RegisterClass RC,
1245 Operand ImmOp, bits<2>MajOp>
1246 : NVInst_V4 <(outs),
1247 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1248 mnemonic#"($src1+#$src2) = $src3.new",
1249 [],"",ST_tc_st_SLOT0> {
1251 bits<13> src2; // Actual address offset
1253 bits<11> offsetBits; // Represents offset encoding
1255 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1256 !if (!eq(mnemonic, "memh"), 12,
1257 !if (!eq(mnemonic, "memw"), 13, 0)));
1259 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1260 !if (!eq(mnemonic, "memh"), 1,
1261 !if (!eq(mnemonic, "memw"), 2, 0)));
1263 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1264 !if (!eq(mnemonic, "memh"), src2{11-1},
1265 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1267 let IClass = 0b1010;
1270 let Inst{26-25} = offsetBits{10-9};
1271 let Inst{24-21} = 0b1101;
1272 let Inst{20-16} = src1;
1273 let Inst{13} = offsetBits{8};
1274 let Inst{12-11} = MajOp;
1275 let Inst{10-8} = src3;
1276 let Inst{7-0} = offsetBits{7-0};
1279 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1280 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1281 bits<2>MajOp, bit PredNot, bit isPredNew>
1282 : NVInst_V4 <(outs),
1283 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1284 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1285 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1286 [],"",V2LDST_tc_st_SLOT0> {
1291 bits<6> offsetBits; // Represents offset encoding
1293 let isPredicatedNew = isPredNew;
1294 let isPredicatedFalse = PredNot;
1295 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1296 !if (!eq(mnemonic, "memh"), 7,
1297 !if (!eq(mnemonic, "memw"), 8, 0)));
1299 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1300 !if (!eq(mnemonic, "memh"), 1,
1301 !if (!eq(mnemonic, "memw"), 2, 0)));
1303 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1304 !if (!eq(mnemonic, "memh"), src3{6-1},
1305 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1307 let IClass = 0b0100;
1310 let Inst{26} = PredNot;
1311 let Inst{25} = isPredNew;
1312 let Inst{24-21} = 0b0101;
1313 let Inst{20-16} = src2;
1314 let Inst{13} = offsetBits{5};
1315 let Inst{12-11} = MajOp;
1316 let Inst{10-8} = src4;
1317 let Inst{7-3} = offsetBits{4-0};
1319 let Inst{1-0} = src1;
1322 // multiclass for new-value store instructions with base + immediate offset.
1324 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1326 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1327 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1329 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1330 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1332 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1333 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1335 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1337 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1342 let addrMode = BaseImmOffset, InputType = "imm" in {
1343 let accessSize = ByteAccess in
1344 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1345 u6_0Ext, 0b00>, AddrModeRel;
1347 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1348 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1349 u6_1Ext, 0b01>, AddrModeRel;
1351 let accessSize = WordAccess, opExtentAlign = 2 in
1352 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1353 u6_2Ext, 0b10>, AddrModeRel;
1356 //===----------------------------------------------------------------------===//
1357 // Post increment loads with register offset.
1358 //===----------------------------------------------------------------------===//
1360 let hasNewValue = 1 in
1361 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1363 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1365 let hasSideEffects = 0, addrMode = PostInc in
1366 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1367 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1368 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1369 "$dst = "#mnemonic#"($src2++$src3)", [],
1370 "$src1 = $dst, $src2 = $_dst_"> {
1375 let accessSize = AccessSz;
1376 let IClass = 0b1001;
1378 let Inst{27-25} = 0b110;
1379 let Inst{24-21} = MajOp;
1380 let Inst{20-16} = src2;
1381 let Inst{13} = src3;
1384 let Inst{4-0} = dst;
1387 def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
1388 def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
1390 //===----------------------------------------------------------------------===//
1391 // Template class for non-predicated post increment .new stores
1392 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1393 //===----------------------------------------------------------------------===//
1394 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1395 isNewValue = 1, opNewValue = 3 in
1396 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1397 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1398 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1399 mnemonic#"($src1++#$offset) = $src2.new",
1400 [], "$src1 = $_dst_">,
1407 string ImmOpStr = !cast<string>(ImmOp);
1408 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1409 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1410 /* s4_0Imm */ offset{3-0}));
1411 let IClass = 0b1010;
1413 let Inst{27-21} = 0b1011101;
1414 let Inst{20-16} = src1;
1416 let Inst{12-11} = MajOp;
1417 let Inst{10-8} = src2;
1419 let Inst{6-3} = offsetBits;
1423 //===----------------------------------------------------------------------===//
1424 // Template class for predicated post increment .new stores
1425 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1426 //===----------------------------------------------------------------------===//
1427 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1428 isNewValue = 1, opNewValue = 4 in
1429 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1430 bits<2> MajOp, bit isPredNot, bit isPredNew >
1431 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1432 (ins PredRegs:$src1, IntRegs:$src2,
1433 ImmOp:$offset, IntRegs:$src3),
1434 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1435 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1436 [], "$src2 = $_dst_">,
1444 string ImmOpStr = !cast<string>(ImmOp);
1445 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1446 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1447 /* s4_0Imm */ offset{3-0}));
1448 let isPredicatedNew = isPredNew;
1449 let isPredicatedFalse = isPredNot;
1451 let IClass = 0b1010;
1453 let Inst{27-21} = 0b1011101;
1454 let Inst{20-16} = src2;
1456 let Inst{12-11} = MajOp;
1457 let Inst{10-8} = src3;
1458 let Inst{7} = isPredNew;
1459 let Inst{6-3} = offsetBits;
1460 let Inst{2} = isPredNot;
1461 let Inst{1-0} = src1;
1464 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1465 bits<2> MajOp, bit PredNot> {
1466 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1469 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1472 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1474 let BaseOpcode = "POST_"#BaseOp in {
1475 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1478 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1479 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1483 let accessSize = ByteAccess in
1484 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1486 let accessSize = HalfWordAccess in
1487 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1489 let accessSize = WordAccess in
1490 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1492 //===----------------------------------------------------------------------===//
1493 // Template class for post increment .new stores with register offset
1494 //===----------------------------------------------------------------------===//
1495 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1496 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1497 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1498 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1499 #mnemonic#"($src1++$src2) = $src3.new",
1500 [], "$src1 = $_dst_"> {
1504 let accessSize = AccessSz;
1506 let IClass = 0b1010;
1508 let Inst{27-21} = 0b1101101;
1509 let Inst{20-16} = src1;
1510 let Inst{13} = src2;
1511 let Inst{12-11} = MajOp;
1512 let Inst{10-8} = src3;
1516 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1517 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1518 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1520 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1521 // memb(Rx++I:circ(Mu))=Nt.new
1522 // memb(Rx++Mu:brev)=Nt.new
1523 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1524 // memh(Rx++I:circ(Mu))=Nt.new
1525 // memh(Rx++Mu)=Nt.new
1526 // memh(Rx++Mu:brev)=Nt.new
1528 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1529 // memw(Rx++I:circ(Mu))=Nt.new
1530 // memw(Rx++Mu)=Nt.new
1531 // memw(Rx++Mu:brev)=Nt.new
1533 //===----------------------------------------------------------------------===//
1535 //===----------------------------------------------------------------------===//
1537 //===----------------------------------------------------------------------===//
1539 //===----------------------------------------------------------------------===//
1541 //===----------------------------------------------------------------------===//
1542 // multiclass/template class for the new-value compare jumps with the register
1544 //===----------------------------------------------------------------------===//
1546 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1547 opExtentAlign = 2 in
1548 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1549 bit isNegCond, bit isTak>
1551 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1552 "if ("#!if(isNegCond, "!","")#mnemonic#
1553 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1554 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1555 #!if(isTak, "t","nt")#" $offset", []> {
1559 bits<3> Ns; // New-Value Operand
1560 bits<5> RegOp; // Non-New-Value Operand
1563 let isTaken = isTak;
1564 let isPredicatedFalse = isNegCond;
1565 let opNewValue{0} = NvOpNum;
1567 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1568 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1570 let IClass = 0b0010;
1571 let Inst{27-26} = 0b00;
1572 let Inst{25-23} = majOp;
1573 let Inst{22} = isNegCond;
1574 let Inst{18-16} = Ns;
1575 let Inst{13} = isTak;
1576 let Inst{12-8} = RegOp;
1577 let Inst{21-20} = offset{10-9};
1578 let Inst{7-1} = offset{8-2};
1582 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1584 // Branch not taken:
1585 def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1587 def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1590 // NvOpNum = 0 -> First Operand is a new-value Register
1591 // NvOpNum = 1 -> Second Operand is a new-value Register
1593 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1595 let BaseOpcode = BaseOp#_NVJ in {
1596 defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1597 defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1601 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1602 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1603 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1604 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1605 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1607 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1608 Defs = [PC], hasSideEffects = 0 in {
1609 defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1610 defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1611 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1612 defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1613 defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1616 //===----------------------------------------------------------------------===//
1617 // multiclass/template class for the new-value compare jumps instruction
1618 // with a register and an unsigned immediate (U5) operand.
1619 //===----------------------------------------------------------------------===//
1621 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1622 opExtentAlign = 2 in
1623 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1626 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1627 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1628 #!if(isTak, "t","nt")#" $offset", []> {
1630 let isTaken = isTak;
1631 let isPredicatedFalse = isNegCond;
1632 let isTaken = isTak;
1638 let IClass = 0b0010;
1640 let Inst{25-23} = majOp;
1641 let Inst{22} = isNegCond;
1642 let Inst{18-16} = src1;
1643 let Inst{13} = isTak;
1644 let Inst{12-8} = src2;
1645 let Inst{21-20} = offset{10-9};
1646 let Inst{7-1} = offset{8-2};
1649 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1650 // Branch not taken:
1651 def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1653 def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
1656 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1657 let BaseOpcode = BaseOp#_NVJri in {
1658 defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1659 defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1663 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1664 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1665 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1667 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1668 Defs = [PC], hasSideEffects = 0 in {
1669 defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1670 defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1671 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1674 //===----------------------------------------------------------------------===//
1675 // multiclass/template class for the new-value compare jumps instruction
1676 // with a register and an hardcoded 0/-1 immediate value.
1677 //===----------------------------------------------------------------------===//
1679 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1680 opExtentAlign = 2 in
1681 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1682 bit isNegCond, bit isTak>
1684 (ins IntRegs:$src1, brtarget:$offset),
1685 "if ("#!if(isNegCond, "!","")#mnemonic
1686 #"($src1.new, #"#ImmVal#")) jump:"
1687 #!if(isTak, "t","nt")#" $offset", []> {
1689 let isTaken = isTak;
1690 let isPredicatedFalse = isNegCond;
1691 let isTaken = isTak;
1695 let IClass = 0b0010;
1697 let Inst{25-23} = majOp;
1698 let Inst{22} = isNegCond;
1699 let Inst{18-16} = src1;
1700 let Inst{13} = isTak;
1701 let Inst{21-20} = offset{10-9};
1702 let Inst{7-1} = offset{8-2};
1705 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1707 // Branch not taken:
1708 def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1710 def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1713 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1715 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1716 defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1717 defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1721 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1722 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1723 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1725 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1726 Defs = [PC], hasSideEffects = 0 in {
1727 defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1728 defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1729 defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1732 // J4_hintjumpr: Hint indirect conditional jump.
1733 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
1734 def J4_hintjumpr: JRInst <
1739 let IClass = 0b0101;
1740 let Inst{27-21} = 0b0010101;
1741 let Inst{20-16} = Rs;
1744 //===----------------------------------------------------------------------===//
1746 //===----------------------------------------------------------------------===//
1748 //===----------------------------------------------------------------------===//
1750 //===----------------------------------------------------------------------===//
1753 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1754 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
1755 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1756 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1760 let IClass = 0b0110;
1761 let Inst{27-16} = 0b101001001001;
1762 let Inst{12-7} = u6;
1768 let hasSideEffects = 0 in
1769 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1770 : CRInst<(outs PredRegs:$Pd),
1771 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1772 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1773 !if (IsNeg,"!","") # "$Pu))",
1774 [], "", CR_tc_2early_SLOT23> {
1780 let IClass = 0b0110;
1781 let Inst{27-24} = 0b1011;
1782 let Inst{23} = IsNeg;
1783 let Inst{22-21} = OpBits;
1785 let Inst{17-16} = Ps;
1792 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1793 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1794 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1795 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1796 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1797 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1798 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1799 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1801 // op(Ps, op(Pt, Pu))
1802 class LogLog_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1803 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, I1:$Pu))),
1804 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1806 // op(Ps, op(Pt, ~Pu))
1807 class LogLogNot_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1808 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, (not I1:$Pu)))),
1809 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1811 def: LogLog_pat<and, and, C4_and_and>;
1812 def: LogLog_pat<and, or, C4_and_or>;
1813 def: LogLog_pat<or, and, C4_or_and>;
1814 def: LogLog_pat<or, or, C4_or_or>;
1816 def: LogLogNot_pat<and, and, C4_and_andn>;
1817 def: LogLogNot_pat<and, or, C4_and_orn>;
1818 def: LogLogNot_pat<or, and, C4_or_andn>;
1819 def: LogLogNot_pat<or, or, C4_or_orn>;
1821 //===----------------------------------------------------------------------===//
1822 // PIC: Support for PIC compilations. The patterns and SD nodes defined
1823 // below are needed to support code generation for PIC
1824 //===----------------------------------------------------------------------===//
1826 def SDT_HexagonPICAdd
1827 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1828 def SDT_HexagonGOTAdd
1829 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1831 def SDT_HexagonGOTAddInternal : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1832 def SDT_HexagonGOTAddInternalJT : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1833 def SDT_HexagonGOTAddInternalBA : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1835 def Hexagonpic_add : SDNode<"HexagonISD::PIC_ADD", SDT_HexagonPICAdd>;
1836 def Hexagonat_got : SDNode<"HexagonISD::AT_GOT", SDT_HexagonGOTAdd>;
1837 def Hexagongat_pcrel : SDNode<"HexagonISD::AT_PCREL",
1838 SDT_HexagonGOTAddInternal>;
1839 def Hexagongat_pcrel_jt : SDNode<"HexagonISD::AT_PCREL",
1840 SDT_HexagonGOTAddInternalJT>;
1841 def Hexagongat_pcrel_ba : SDNode<"HexagonISD::AT_PCREL",
1842 SDT_HexagonGOTAddInternalBA>;
1844 // PIC: Map from a block address computation to a PC-relative add
1845 def: Pat<(Hexagongat_pcrel_ba tblockaddress:$src1),
1846 (C4_addipc u6ExtPred:$src1)>;
1848 // PIC: Map from the computation to generate a GOT pointer to a PC-relative add
1849 def: Pat<(Hexagonpic_add texternalsym:$src1),
1850 (C4_addipc u6ExtPred:$src1)>;
1852 // PIC: Map from a jump table address computation to a PC-relative add
1853 def: Pat<(Hexagongat_pcrel_jt tjumptable:$src1),
1854 (C4_addipc u6ExtPred:$src1)>;
1856 // PIC: Map from a GOT-relative symbol reference to a load
1857 def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
1858 (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$src2)>;
1860 // PIC: Map from a static symbol reference to a PC-relative add
1861 def: Pat<(Hexagongat_pcrel tglobaladdr:$src1),
1862 (C4_addipc u6ExtPred:$src1)>;
1864 //===----------------------------------------------------------------------===//
1866 //===----------------------------------------------------------------------===//
1868 //===----------------------------------------------------------------------===//
1870 //===----------------------------------------------------------------------===//
1872 // Logical with-not instructions.
1873 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1874 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1876 def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1877 (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1878 def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1879 (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1881 let hasNewValue = 1, hasSideEffects = 0 in
1882 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1883 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1888 let IClass = 0b1101;
1889 let Inst{27-21} = 0b0101111;
1890 let Inst{20-16} = Rs;
1891 let Inst{12-8} = Rt;
1895 // Add and accumulate.
1896 // Rd=add(Rs,add(Ru,#s6))
1897 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1899 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1900 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1901 "$Rd = add($Rs, add($Ru, #$s6))" ,
1902 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1903 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1904 "", ALU64_tc_2_SLOT23> {
1910 let IClass = 0b1101;
1912 let Inst{27-23} = 0b10110;
1913 let Inst{22-21} = s6{5-4};
1914 let Inst{20-16} = Rs;
1915 let Inst{13} = s6{3};
1916 let Inst{12-8} = Rd;
1917 let Inst{7-5} = s6{2-0};
1921 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1922 opExtentBits = 6, opExtendable = 2 in
1923 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1924 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1925 "$Rd = add($Rs, sub(#$s6, $Ru))",
1926 [], "", ALU64_tc_2_SLOT23> {
1932 let IClass = 0b1101;
1934 let Inst{27-23} = 0b10111;
1935 let Inst{22-21} = s6{5-4};
1936 let Inst{20-16} = Rs;
1937 let Inst{13} = s6{3};
1938 let Inst{12-8} = Rd;
1939 let Inst{7-5} = s6{2-0};
1943 // Rd=add(Rs,sub(#s6,Ru))
1944 def: Pat<(add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1945 (i32 IntRegs:$src3))),
1946 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1948 // Rd=sub(add(Rs,#s6),Ru)
1949 def: Pat<(sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1950 (i32 IntRegs:$src3)),
1951 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1953 // Rd=add(sub(Rs,Ru),#s6)
1954 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1955 (s6_10ExtPred:$src2)),
1956 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1959 // Add or subtract doublewords with carry.
1961 // Rdd=add(Rss,Rtt,Px):carry
1963 // Rdd=sub(Rss,Rtt,Px):carry
1966 // Rdd=extract(Rss,#u6,#U6)
1967 // Rdd=extract(Rss,Rtt)
1968 // Rd=extract(Rs,Rtt)
1969 // Rd=extract(Rs,#u5,#U5)
1971 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1972 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1974 let hasNewValue = 1 in {
1975 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1976 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1979 // Complex add/sub halfwords/words
1980 let Defs = [USR_OVF] in {
1981 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1982 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1983 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1984 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1987 let Defs = [USR_OVF] in {
1988 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1989 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
1992 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in {
1993 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1994 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1997 // Logical xor with xor accumulation.
1998 // Rxx^=xor(Rss,Rtt)
1999 let hasSideEffects = 0 in
2001 : SInst <(outs DoubleRegs:$Rxx),
2002 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2003 "$Rxx ^= xor($Rss, $Rtt)",
2004 [(set (i64 DoubleRegs:$Rxx),
2005 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
2006 (i64 DoubleRegs:$Rtt))))],
2007 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
2012 let IClass = 0b1100;
2014 let Inst{27-22} = 0b101010;
2015 let Inst{20-16} = Rss;
2016 let Inst{12-8} = Rtt;
2017 let Inst{7-5} = 0b000;
2018 let Inst{4-0} = Rxx;
2021 // Rotate and reduce bytes
2022 // Rdd=vrcrotate(Rss,Rt,#u2)
2023 let hasSideEffects = 0 in
2025 : SInst <(outs DoubleRegs:$Rdd),
2026 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2027 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
2028 [], "", S_3op_tc_3x_SLOT23> {
2034 let IClass = 0b1100;
2036 let Inst{27-22} = 0b001111;
2037 let Inst{20-16} = Rss;
2038 let Inst{13} = u2{1};
2039 let Inst{12-8} = Rt;
2040 let Inst{7-6} = 0b11;
2041 let Inst{5} = u2{0};
2042 let Inst{4-0} = Rdd;
2045 // Rotate and reduce bytes with accumulation
2046 // Rxx+=vrcrotate(Rss,Rt,#u2)
2047 let hasSideEffects = 0 in
2048 def S4_vrcrotate_acc
2049 : SInst <(outs DoubleRegs:$Rxx),
2050 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2051 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
2052 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2058 let IClass = 0b1100;
2060 let Inst{27-21} = 0b1011101;
2061 let Inst{20-16} = Rss;
2062 let Inst{13} = u2{1};
2063 let Inst{12-8} = Rt;
2064 let Inst{5} = u2{0};
2065 let Inst{4-0} = Rxx;
2068 // Vector reduce conditional negate halfwords
2069 let hasSideEffects = 0 in
2071 : SInst <(outs DoubleRegs:$Rxx),
2072 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2073 "$Rxx += vrcnegh($Rss, $Rt)", [],
2074 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2079 let IClass = 0b1100;
2081 let Inst{27-21} = 0b1011001;
2082 let Inst{20-16} = Rss;
2084 let Inst{12-8} = Rt;
2085 let Inst{7-5} = 0b111;
2086 let Inst{4-0} = Rxx;
2090 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
2092 // Arithmetic/Convergent round
2093 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
2095 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
2097 let Defs = [USR_OVF] in
2098 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
2100 // Logical-logical words.
2101 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
2102 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
2105 ALU64Inst<(outs IntRegs:$Rx),
2106 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2107 "$Rx = or($Ru, and($_src_, #$s10))" ,
2108 [(set (i32 IntRegs:$Rx),
2109 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
2110 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
2115 let IClass = 0b1101;
2117 let Inst{27-22} = 0b101001;
2118 let Inst{20-16} = Rx;
2119 let Inst{21} = s10{9};
2120 let Inst{13-5} = s10{8-0};
2124 // Miscellaneous ALU64 instructions.
2126 let hasNewValue = 1, hasSideEffects = 0 in
2127 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2128 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2133 let IClass = 0b1101;
2134 let Inst{27-21} = 0b0011111;
2135 let Inst{20-16} = Rs;
2136 let Inst{12-8} = Rt;
2137 let Inst{7-5} = 0b111;
2141 let hasSideEffects = 0 in
2142 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2143 (ins IntRegs:$Rs, IntRegs:$Rt),
2144 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2149 let IClass = 0b1101;
2150 let Inst{27-24} = 0b0100;
2152 let Inst{20-16} = Rs;
2153 let Inst{12-8} = Rt;
2157 let hasSideEffects = 0 in
2158 def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
2159 (ins IntRegs:$Rs, IntRegs:$Rt),
2160 "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
2165 let IClass = 0b1101;
2166 let Inst{27-24} = 0b0100;
2168 let Inst{20-16} = Rs;
2169 let Inst{12-8} = Rt;
2173 let hasNewValue = 1, hasSideEffects = 0 in
2174 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2175 (ins IntRegs:$Rs, IntRegs:$Rt),
2176 "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2181 let IClass = 0b1101;
2182 let Inst{27-21} = 0b0101100;
2183 let Inst{20-16} = Rs;
2184 let Inst{12-8} = Rt;
2189 let hasNewValue = 1, hasSideEffects = 0 in
2190 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2191 (ins IntRegs:$Rs, IntRegs:$Rt),
2192 "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2197 let IClass = 0b1101;
2198 let Inst{27-21} = 0b0101100;
2199 let Inst{20-16} = Rt;
2200 let Inst{12-8} = Rs;
2205 // Rx[&|]=xor(Rs,Rt)
2206 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
2207 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
2209 // Rx[&|^]=or(Rs,Rt)
2210 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
2212 let CextOpcode = "ORr_ORr" in
2213 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
2214 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
2216 // Rx[&|^]=and(Rs,Rt)
2217 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
2219 let CextOpcode = "ORr_ANDr" in
2220 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
2221 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
2223 // Rx[&|^]=and(Rs,~Rt)
2224 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
2225 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
2226 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
2228 def: T_MType_acc_pat2 <M4_or_xor, xor, or>;
2229 def: T_MType_acc_pat2 <M4_and_xor, xor, and>;
2230 def: T_MType_acc_pat2 <M4_or_and, and, or>;
2231 def: T_MType_acc_pat2 <M4_and_and, and, and>;
2232 def: T_MType_acc_pat2 <M4_xor_and, and, xor>;
2233 def: T_MType_acc_pat2 <M4_or_or, or, or>;
2234 def: T_MType_acc_pat2 <M4_and_or, or, and>;
2235 def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
2237 class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2238 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
2239 (not IntRegs:$src3)))),
2240 (i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
2242 def: T_MType_acc_pat3 <M4_or_andn, and, or>;
2243 def: T_MType_acc_pat3 <M4_and_andn, and, and>;
2244 def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
2246 // Compound or-or and or-and
2247 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
2248 opExtentBits = 10, opExtendable = 3 in
2249 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2250 : MInst_acc <(outs IntRegs:$Rx),
2251 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2252 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2253 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2254 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
2255 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
2260 let IClass = 0b1101;
2262 let Inst{27-24} = 0b1010;
2263 let Inst{23-22} = MajOp;
2264 let Inst{20-16} = Rs;
2265 let Inst{21} = s10{9};
2266 let Inst{13-5} = s10{8-0};
2270 let CextOpcode = "ORr_ANDr" in
2271 def S4_or_andi : T_CompOR <"and", 0b00, and>;
2273 let CextOpcode = "ORr_ORr" in
2274 def S4_or_ori : T_CompOR <"or", 0b10, or>;
2277 // Rd=modwrap(Rs,Rt)
2279 // Rd=cround(Rs,#u5)
2281 // Rd=round(Rs,#u5)[:sat]
2282 // Rd=round(Rs,Rt)[:sat]
2283 // Vector reduce add unsigned halfwords
2284 // Rd=vraddh(Rss,Rtt)
2286 // Rdd=vaddb(Rss,Rtt)
2287 // Vector conditional negate
2288 // Rdd=vcnegh(Rss,Rt)
2289 // Rxx+=vrcnegh(Rss,Rt)
2290 // Vector maximum bytes
2291 // Rdd=vmaxb(Rtt,Rss)
2292 // Vector reduce maximum halfwords
2293 // Rxx=vrmaxh(Rss,Ru)
2294 // Rxx=vrmaxuh(Rss,Ru)
2295 // Vector reduce maximum words
2296 // Rxx=vrmaxuw(Rss,Ru)
2297 // Rxx=vrmaxw(Rss,Ru)
2298 // Vector minimum bytes
2299 // Rdd=vminb(Rtt,Rss)
2300 // Vector reduce minimum halfwords
2301 // Rxx=vrminh(Rss,Ru)
2302 // Rxx=vrminuh(Rss,Ru)
2303 // Vector reduce minimum words
2304 // Rxx=vrminuw(Rss,Ru)
2305 // Rxx=vrminw(Rss,Ru)
2306 // Vector subtract bytes
2307 // Rdd=vsubb(Rss,Rtt)
2309 //===----------------------------------------------------------------------===//
2311 //===----------------------------------------------------------------------===//
2313 //===----------------------------------------------------------------------===//
2315 //===----------------------------------------------------------------------===//
2318 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2321 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2322 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2323 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2325 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
2326 (S2_ct0p (i64 DoubleRegs:$Rss))>;
2327 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
2328 (S2_ct1p (i64 DoubleRegs:$Rss))>;
2330 let hasSideEffects = 0, hasNewValue = 1 in
2331 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2332 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2336 let IClass = 0b1000;
2337 let Inst{27-24} = 0b1100;
2338 let Inst{23-21} = 0b001;
2339 let Inst{20-16} = Rs;
2340 let Inst{13-8} = s6;
2341 let Inst{7-5} = 0b000;
2345 let hasSideEffects = 0, hasNewValue = 1 in
2346 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2347 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2351 let IClass = 0b1000;
2352 let Inst{27-24} = 0b1000;
2353 let Inst{23-21} = 0b011;
2354 let Inst{20-16} = Rs;
2355 let Inst{13-8} = s6;
2356 let Inst{7-5} = 0b010;
2361 // Bit test/set/clear
2362 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2363 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2365 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2366 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2367 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2368 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2369 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2372 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2373 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2374 // if ([!]tstbit(...)) jump ...
2375 let AddedComplexity = 100 in
2376 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2377 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2379 let AddedComplexity = 100 in
2380 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2381 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2383 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2384 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2385 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2387 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2388 // represented as a compare against "value & 0xFF", which is an exact match
2389 // for cmpb (same for cmph). The patterns below do not contain any additional
2390 // complexity that would make them preferable, and if they were actually used
2391 // instead of cmpb/cmph, they would result in a compare against register that
2392 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2393 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2394 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2395 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2396 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2397 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2398 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2400 //===----------------------------------------------------------------------===//
2402 //===----------------------------------------------------------------------===//
2404 //===----------------------------------------------------------------------===//
2406 //===----------------------------------------------------------------------===//
2408 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2410 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2411 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2412 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2413 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2414 [(set (i32 IntRegs:$Rd),
2415 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2416 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2422 let IClass = 0b1101;
2424 let Inst{27-24} = 0b1000;
2425 let Inst{23} = U6{5};
2426 let Inst{22-21} = u6{5-4};
2427 let Inst{20-16} = Rs;
2428 let Inst{13} = u6{3};
2429 let Inst{12-8} = Rd;
2430 let Inst{7-5} = u6{2-0};
2431 let Inst{4-0} = U6{4-0};
2434 // Rd=add(#u6,mpyi(Rs,Rt))
2435 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2436 isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2437 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2438 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2439 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2440 [(set (i32 IntRegs:$Rd),
2441 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2442 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2448 let IClass = 0b1101;
2450 let Inst{27-23} = 0b01110;
2451 let Inst{22-21} = u6{5-4};
2452 let Inst{20-16} = Rs;
2453 let Inst{13} = u6{3};
2454 let Inst{12-8} = Rt;
2455 let Inst{7-5} = u6{2-0};
2459 let hasNewValue = 1 in
2460 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2461 : ALU64Inst <(outs IntRegs:$dst), ins,
2462 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2464 [(set (i32 IntRegs:$dst),
2465 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2466 "", ALU64_tc_3x_SLOT23> {
2472 let IClass = 0b1101;
2474 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2476 let Inst{27-24} = 0b1111;
2477 let Inst{23} = MajOp;
2478 let Inst{22-21} = ImmValue{5-4};
2479 let Inst{20-16} = src3;
2480 let Inst{13} = ImmValue{3};
2481 let Inst{12-8} = dst;
2482 let Inst{7-5} = ImmValue{2-0};
2483 let Inst{4-0} = src1;
2486 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2487 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2489 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2490 CextOpcode = "ADD_MPY", InputType = "imm" in
2491 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2492 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2494 // Rx=add(Ru,mpyi(Rx,Rs))
2495 let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
2496 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2497 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2498 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2499 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2500 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2501 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2506 let IClass = 0b1110;
2508 let Inst{27-21} = 0b0011000;
2509 let Inst{12-8} = Rx;
2511 let Inst{20-16} = Rs;
2515 // Vector reduce multiply word by signed half (32x16)
2516 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2517 def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
2518 def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
2520 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2521 def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
2522 def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
2524 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
2525 def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
2526 def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
2528 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2529 def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
2530 def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
2532 // Vector multiply halfwords, signed by unsigned
2533 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2534 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
2535 def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
2537 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2538 def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
2539 def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
2541 // Vector polynomial multiply halfwords
2542 // Rdd=vpmpyh(Rs,Rt)
2543 def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
2545 // Rxx^=vpmpyh(Rs,Rt)
2546 def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
2548 // Polynomial multiply words
2550 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2552 // Rxx^=pmpyw(Rs,Rt)
2553 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2555 //===----------------------------------------------------------------------===//
2557 //===----------------------------------------------------------------------===//
2559 //===----------------------------------------------------------------------===//
2560 // ALU64/Vector compare
2561 //===----------------------------------------------------------------------===//
2562 //===----------------------------------------------------------------------===//
2563 // Template class for vector compare
2564 //===----------------------------------------------------------------------===//
2566 let hasSideEffects = 0 in
2567 class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
2568 : ALU64_rr <(outs PredRegs:$Pd),
2569 (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
2570 "$Pd = "#Str#"($Rss, #$Imm)",
2571 [], "", ALU64_tc_2early_SLOT23> {
2576 let ImmBits{6-0} = Imm{6-0};
2577 let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
2579 let IClass = 0b1101;
2581 let Inst{27-24} = 0b1100;
2582 let Inst{22-21} = cmpOp;
2583 let Inst{20-16} = Rss;
2584 let Inst{12-5} = ImmBits;
2585 let Inst{4-3} = minOp;
2589 // Vector compare bytes
2590 def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
2591 def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
2593 let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
2594 def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
2596 def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
2597 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2598 def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
2600 // Vector compare halfwords
2601 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2602 def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
2603 def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
2605 // Vector compare words
2606 def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
2607 def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
2608 def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
2610 //===----------------------------------------------------------------------===//
2612 //===----------------------------------------------------------------------===//
2613 // Shift by immediate and accumulate/logical.
2614 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2615 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2616 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2617 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2618 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2619 hasNewValue = 1, opNewValue = 0 in
2620 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2621 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2622 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2623 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2624 [(set (i32 IntRegs:$Rd),
2625 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2626 "$Rd = $Rx", Itin> {
2633 let IClass = 0b1101;
2634 let Inst{27-24} = 0b1110;
2635 let Inst{23-21} = u8{7-5};
2636 let Inst{20-16} = Rd;
2637 let Inst{13} = u8{4};
2638 let Inst{12-8} = U5;
2639 let Inst{7-5} = u8{3-1};
2640 let Inst{4} = asl_lsr;
2641 let Inst{3} = u8{0};
2642 let Inst{2-1} = MajOp;
2645 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2646 InstrItinClass Itin> {
2647 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2648 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2651 let AddedComplexity = 200 in {
2652 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2653 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2656 let AddedComplexity = 30 in
2657 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2659 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2661 let AddedComplexity = 200 in {
2662 def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2663 (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2664 def: Pat<(add addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2665 (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2666 def: Pat<(sub addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2667 (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2668 def: Pat<(sub addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2669 (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2672 // Vector conditional negate
2673 // Rdd=vcnegh(Rss,Rt)
2674 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2675 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2677 // Rd=[cround|round](Rs,Rt)
2678 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in {
2679 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2680 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2683 // Rd=round(Rs,Rt):sat
2684 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2685 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2687 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2688 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
2689 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2690 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2693 // Rdd=[add|sub](Rss,Rtt,Px):carry
2694 let isPredicateLate = 1, hasSideEffects = 0 in
2695 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2696 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2697 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2698 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2699 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2705 let IClass = 0b1100;
2707 let Inst{27-24} = 0b0010;
2708 let Inst{23-21} = MajOp;
2709 let Inst{20-16} = Rss;
2710 let Inst{12-8} = Rtt;
2712 let Inst{4-0} = Rdd;
2715 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2716 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2718 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2719 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2720 : SInst <(outs DoubleRegs:$Rxx),
2721 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2722 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2723 [] , "$dst2 = $Rxx"> {
2728 let IClass = 0b1100;
2730 let Inst{27-21} = 0b1011001;
2731 let Inst{20-16} = Rss;
2732 let Inst{13} = isUnsigned;
2733 let Inst{12-8} = Rxx;
2734 let Inst{7-5} = MinOp;
2738 // Vector reduce maximum halfwords
2739 // Rxx=vrmax[u]h(Rss,Ru)
2740 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2741 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2743 // Vector reduce maximum words
2744 // Rxx=vrmax[u]w(Rss,Ru)
2745 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2746 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2748 // Vector reduce minimum halfwords
2749 // Rxx=vrmin[u]h(Rss,Ru)
2750 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2751 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2753 // Vector reduce minimum words
2754 // Rxx=vrmin[u]w(Rss,Ru)
2755 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2756 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2758 // Shift an immediate left by register amount.
2759 let hasNewValue = 1, hasSideEffects = 0 in
2760 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2761 "$Rd = lsl(#$s6, $Rt)" ,
2762 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2763 (i32 IntRegs:$Rt)))],
2764 "", S_3op_tc_1_SLOT23> {
2769 let IClass = 0b1100;
2771 let Inst{27-22} = 0b011010;
2772 let Inst{20-16} = s6{5-1};
2773 let Inst{12-8} = Rt;
2774 let Inst{7-6} = 0b11;
2776 let Inst{5} = s6{0};
2779 //===----------------------------------------------------------------------===//
2781 //===----------------------------------------------------------------------===//
2783 //===----------------------------------------------------------------------===//
2784 // MEMOP: Word, Half, Byte
2785 //===----------------------------------------------------------------------===//
2787 def MEMOPIMM : SDNodeXForm<imm, [{
2788 // Call the transformation function XformM5ToU5Imm to get the negative
2789 // immediate's positive counterpart.
2790 int32_t imm = N->getSExtValue();
2791 return XformM5ToU5Imm(imm);
2794 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2795 // -1 .. -31 represented as 65535..65515
2796 // assigning to a short restores our desired signed value.
2797 // Call the transformation function XformM5ToU5Imm to get the negative
2798 // immediate's positive counterpart.
2799 int16_t imm = N->getSExtValue();
2800 return XformM5ToU5Imm(imm);
2803 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2804 // -1 .. -31 represented as 255..235
2805 // assigning to a char restores our desired signed value.
2806 // Call the transformation function XformM5ToU5Imm to get the negative
2807 // immediate's positive counterpart.
2808 int8_t imm = N->getSExtValue();
2809 return XformM5ToU5Imm(imm);
2812 def SETMEMIMM : SDNodeXForm<imm, [{
2813 // Return the bit position we will set [0-31].
2815 int32_t imm = N->getSExtValue();
2816 return XformMskToBitPosU5Imm(imm);
2819 def CLRMEMIMM : SDNodeXForm<imm, [{
2820 // Return the bit position we will clear [0-31].
2822 // we bit negate the value first
2823 int32_t imm = ~(N->getSExtValue());
2824 return XformMskToBitPosU5Imm(imm);
2827 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2828 // Return the bit position we will set [0-15].
2830 int16_t imm = N->getSExtValue();
2831 return XformMskToBitPosU4Imm(imm);
2834 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2835 // Return the bit position we will clear [0-15].
2837 // we bit negate the value first
2838 int16_t imm = ~(N->getSExtValue());
2839 return XformMskToBitPosU4Imm(imm);
2842 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2843 // Return the bit position we will set [0-7].
2845 int8_t imm = N->getSExtValue();
2846 return XformMskToBitPosU3Imm(imm);
2849 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2850 // Return the bit position we will clear [0-7].
2852 // we bit negate the value first
2853 int8_t imm = ~(N->getSExtValue());
2854 return XformMskToBitPosU3Imm(imm);
2857 //===----------------------------------------------------------------------===//
2858 // Template class for MemOp instructions with the register value.
2859 //===----------------------------------------------------------------------===//
2860 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2861 string memOp, bits<2> memOpBits> :
2863 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2864 opc#"($base+#$offset)"#memOp#"$delta",
2866 Requires<[UseMEMOP]> {
2871 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2873 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2874 !if (!eq(opcBits, 0b01), offset{6-1},
2875 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2877 let opExtentAlign = opcBits;
2878 let IClass = 0b0011;
2879 let Inst{27-24} = 0b1110;
2880 let Inst{22-21} = opcBits;
2881 let Inst{20-16} = base;
2883 let Inst{12-7} = offsetBits;
2884 let Inst{6-5} = memOpBits;
2885 let Inst{4-0} = delta;
2888 //===----------------------------------------------------------------------===//
2889 // Template class for MemOp instructions with the immediate value.
2890 //===----------------------------------------------------------------------===//
2891 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2892 string memOp, bits<2> memOpBits> :
2894 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2895 opc#"($base+#$offset)"#memOp#"#$delta"
2896 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2898 Requires<[UseMEMOP]> {
2903 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2905 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2906 !if (!eq(opcBits, 0b01), offset{6-1},
2907 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2909 let opExtentAlign = opcBits;
2910 let IClass = 0b0011;
2911 let Inst{27-24} = 0b1111;
2912 let Inst{22-21} = opcBits;
2913 let Inst{20-16} = base;
2915 let Inst{12-7} = offsetBits;
2916 let Inst{6-5} = memOpBits;
2917 let Inst{4-0} = delta;
2920 // multiclass to define MemOp instructions with register operand.
2921 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2922 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2923 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2924 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2925 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2928 // multiclass to define MemOp instructions with immediate Operand.
2929 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2930 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2931 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2932 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2933 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2936 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2937 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2938 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2941 // Define MemOp instructions.
2942 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
2943 let opExtentBits = 6, accessSize = ByteAccess in
2944 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2946 let opExtentBits = 7, accessSize = HalfWordAccess in
2947 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2949 let opExtentBits = 8, accessSize = WordAccess in
2950 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2953 //===----------------------------------------------------------------------===//
2954 // Multiclass to define 'Def Pats' for ALU operations on the memory
2955 // Here value used for the ALU operation is an immediate value.
2956 // mem[bh](Rs+#0) += #U5
2957 // mem[bh](Rs+#u6) += #U5
2958 //===----------------------------------------------------------------------===//
2960 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2961 InstHexagon MI, SDNode OpNode> {
2962 let AddedComplexity = 180 in
2963 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2965 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
2967 let AddedComplexity = 190 in
2968 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2970 (add IntRegs:$base, ExtPred:$offset)),
2971 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2974 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2975 InstHexagon addMI, InstHexagon subMI> {
2976 defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2977 defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2980 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2982 defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2983 L4_iadd_memoph_io, L4_isub_memoph_io>;
2985 defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2986 L4_iadd_memopb_io, L4_isub_memopb_io>;
2989 let Predicates = [UseMEMOP] in {
2990 defm: MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2991 defm: MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2992 defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2995 defm: MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
2999 //===----------------------------------------------------------------------===//
3000 // multiclass to define 'Def Pats' for ALU operations on the memory.
3001 // Here value used for the ALU operation is a negative value.
3002 // mem[bh](Rs+#0) += #m5
3003 // mem[bh](Rs+#u6) += #m5
3004 //===----------------------------------------------------------------------===//
3006 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3007 PatLeaf immPred, SDNodeXForm xformFunc,
3009 let AddedComplexity = 190 in
3010 def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
3011 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
3013 let AddedComplexity = 195 in
3014 def: Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
3016 (add IntRegs:$base, extPred:$offset)),
3017 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
3020 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3022 defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
3023 MEMOPIMM_HALF, L4_isub_memoph_io>;
3025 defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
3026 MEMOPIMM_BYTE, L4_isub_memopb_io>;
3029 let Predicates = [UseMEMOP] in {
3030 defm: MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
3031 defm: MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
3032 defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
3035 defm: MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
3036 MEMOPIMM, L4_isub_memopw_io>;
3039 //===----------------------------------------------------------------------===//
3040 // Multiclass to define 'def Pats' for bit operations on the memory.
3041 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3042 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
3043 //===----------------------------------------------------------------------===//
3045 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
3046 PatLeaf extPred, SDNodeXForm xformFunc, InstHexagon MI,
3049 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
3050 let AddedComplexity = 250 in
3051 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3053 (add IntRegs:$base, extPred:$offset)),
3054 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
3056 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3057 let AddedComplexity = 225 in
3058 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
3059 (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
3062 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
3064 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
3065 CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
3067 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
3068 SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
3069 // Half Word - clrbit
3070 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
3071 CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
3072 // Half Word - setbit
3073 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
3074 SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
3077 let Predicates = [UseMEMOP] in {
3078 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
3079 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
3080 defm: MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
3081 defm: MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
3082 defm: MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
3084 // memw(Rs+#0) = [clrbit|setbit](#U5)
3085 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
3086 defm: MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, CLRMEMIMM,
3087 L4_iand_memopw_io, and>;
3088 defm: MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, SETMEMIMM,
3089 L4_ior_memopw_io, or>;
3092 //===----------------------------------------------------------------------===//
3093 // Multiclass to define 'def Pats' for ALU operations on the memory
3094 // where addend is a register.
3095 // mem[bhw](Rs+#0) [+-&|]= Rt
3096 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3097 //===----------------------------------------------------------------------===//
3099 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3100 InstHexagon MI, SDNode OpNode> {
3101 let AddedComplexity = 141 in
3102 // mem[bhw](Rs+#0) [+-&|]= Rt
3103 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
3105 (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
3107 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3108 let AddedComplexity = 150 in
3109 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3110 (i32 IntRegs:$orend)),
3111 (add IntRegs:$base, extPred:$offset)),
3112 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
3115 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3116 InstHexagon addMI, InstHexagon subMI,
3117 InstHexagon andMI, InstHexagon orMI> {
3118 defm: MemOpr_Pats <ldOp, stOp, extPred, addMI, add>;
3119 defm: MemOpr_Pats <ldOp, stOp, extPred, subMI, sub>;
3120 defm: MemOpr_Pats <ldOp, stOp, extPred, andMI, and>;
3121 defm: MemOpr_Pats <ldOp, stOp, extPred, orMI, or>;
3124 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3126 defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
3127 L4_add_memoph_io, L4_sub_memoph_io,
3128 L4_and_memoph_io, L4_or_memoph_io>;
3130 defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u6ExtPred,
3131 L4_add_memopb_io, L4_sub_memopb_io,
3132 L4_and_memopb_io, L4_or_memopb_io>;
3135 // Define 'def Pats' for MemOps with register addend.
3136 let Predicates = [UseMEMOP] in {
3138 defm: MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
3139 defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
3140 defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
3142 defm: MemOPr_ALUOp <load, store, u6_2ExtPred, L4_add_memopw_io,
3143 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
3146 //===----------------------------------------------------------------------===//
3148 //===----------------------------------------------------------------------===//
3150 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3151 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3152 // hardware. However, compiler can still implement these patterns through
3153 // appropriate patterns combinations based on current implemented patterns.
3154 // The implemented patterns are: EQ/GT/GTU.
3155 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3157 // Following instruction is not being extended as it results into the
3158 // incorrect code for negative numbers.
3159 // Pd=cmpb.eq(Rs,#u8)
3161 // p=!cmp.eq(r1,#s10)
3162 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
3163 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
3164 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
3166 def : T_CMP_pat <C4_cmpneqi, setne, s10ExtPred>;
3167 def : T_CMP_pat <C4_cmpltei, setle, s10ExtPred>;
3168 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
3170 // rs <= rt -> !(rs > rt).
3172 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
3173 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
3174 // (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
3176 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3177 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
3178 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
3180 // rs != rt -> !(rs == rt).
3181 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
3182 (C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
3184 // SDNode for converting immediate C to C-1.
3185 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
3186 // Return the byte immediate const-1 as an SDNode.
3187 int32_t imm = N->getSExtValue();
3188 return XformU7ToU7M1Imm(imm);
3192 // zext( setult ( and(Rs, 255), u8))
3193 // Use the isdigit transformation below
3195 // Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
3196 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3197 // The isdigit transformation relies on two 'clever' aspects:
3198 // 1) The data type is unsigned which allows us to eliminate a zero test after
3199 // biasing the expression by 48. We are depending on the representation of
3200 // the unsigned types, and semantics.
3201 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3204 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3205 // The code is transformed upstream of llvm into
3206 // retval = (c-48) < 10 ? 1 : 0;
3207 let AddedComplexity = 139 in
3208 def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3209 u7StrictPosImmPred:$src2)))),
3210 (C2_muxii (A4_cmpbgtui IntRegs:$src1,
3211 (DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
3214 //===----------------------------------------------------------------------===//
3216 //===----------------------------------------------------------------------===//
3218 //===----------------------------------------------------------------------===//
3219 // Multiclass for DeallocReturn
3220 //===----------------------------------------------------------------------===//
3221 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3222 : LD0Inst<(outs), (ins PredRegs:$src),
3223 !if(isNot, "if (!$src", "if ($src")#
3224 !if(isPredNew, ".new) ", ") ")#mnemonic#
3225 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3226 [], "", LD_tc_3or4stall_SLOT0> {
3229 let BaseOpcode = "L4_RETURN";
3230 let isPredicatedFalse = isNot;
3231 let isPredicatedNew = isPredNew;
3232 let isTaken = isTak;
3233 let IClass = 0b1001;
3235 let Inst{27-16} = 0b011000011110;
3237 let Inst{13} = isNot;
3238 let Inst{12} = isTak;
3239 let Inst{11} = isPredNew;
3241 let Inst{9-8} = src;
3242 let Inst{4-0} = 0b11110;
3245 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3246 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3247 let isPredicated = 1 in {
3248 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3249 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3250 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3254 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3255 let isBarrier = 1, isPredicable = 1 in
3256 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3257 LD_tc_3or4stall_SLOT0> {
3258 let BaseOpcode = "L4_RETURN";
3259 let IClass = 0b1001;
3260 let Inst{27-16} = 0b011000011110;
3261 let Inst{13-10} = 0b0000;
3262 let Inst{4-0} = 0b11110;
3264 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3265 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3268 let isReturn = 1, isTerminator = 1,
3269 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
3270 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3272 // Restore registers and dealloc return function call.
3273 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3274 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3275 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
3276 (ins calltarget:$dst),
3281 // Restore registers and dealloc frame before a tail call.
3282 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
3283 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3284 (ins calltarget:$dst),
3289 // Save registers function call.
3290 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
3291 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3292 (ins calltarget:$dst),
3293 "call $dst // Save_calle_saved_registers",
3297 //===----------------------------------------------------------------------===//
3298 // Template class for non predicated store instructions with
3299 // GP-Relative or absolute addressing.
3300 //===----------------------------------------------------------------------===//
3301 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3302 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3303 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3304 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3305 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3306 [], "", V2LDST_tc_st_SLOT01> {
3309 bits<16> offsetBits;
3311 string ImmOpStr = !cast<string>(ImmOp);
3312 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3313 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3314 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3315 /* u16_0Imm */ addr{15-0})));
3316 let IClass = 0b0100;
3318 let Inst{26-25} = offsetBits{15-14};
3320 let Inst{23-22} = MajOp;
3321 let Inst{21} = isHalf;
3322 let Inst{20-16} = offsetBits{13-9};
3323 let Inst{13} = offsetBits{8};
3324 let Inst{12-8} = src;
3325 let Inst{7-0} = offsetBits{7-0};
3328 //===----------------------------------------------------------------------===//
3329 // Template class for predicated store instructions with
3330 // GP-Relative or absolute addressing.
3331 //===----------------------------------------------------------------------===//
3332 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3334 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3335 bit isHalf, bit isNot, bit isNew>
3336 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3337 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3338 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3339 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3344 let isPredicatedNew = isNew;
3345 let isPredicatedFalse = isNot;
3347 let IClass = 0b1010;
3349 let Inst{27-24} = 0b1111;
3350 let Inst{23-22} = MajOp;
3351 let Inst{21} = isHalf;
3352 let Inst{17-16} = absaddr{5-4};
3353 let Inst{13} = isNew;
3354 let Inst{12-8} = src2;
3356 let Inst{6-3} = absaddr{3-0};
3357 let Inst{2} = isNot;
3358 let Inst{1-0} = src1;
3361 //===----------------------------------------------------------------------===//
3362 // Template class for predicated store instructions with absolute addressing.
3363 //===----------------------------------------------------------------------===//
3364 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3365 bits<2> MajOp, bit isHalf>
3366 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1, isHalf>,
3368 string ImmOpStr = !cast<string>(ImmOp);
3369 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3370 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3371 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3372 /* u16_0Imm */ 16)));
3374 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3375 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3376 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3377 /* u16_0Imm */ 0)));
3380 //===----------------------------------------------------------------------===//
3381 // Multiclass for store instructions with absolute addressing.
3382 //===----------------------------------------------------------------------===//
3383 let addrMode = Absolute, isExtended = 1 in
3384 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3385 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3386 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3387 let opExtendable = 0, isPredicable = 1 in
3388 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3391 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3392 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3395 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3396 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3400 //===----------------------------------------------------------------------===//
3401 // Template class for non predicated new-value store instructions with
3402 // GP-Relative or absolute addressing.
3403 //===----------------------------------------------------------------------===//
3404 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3405 isNewValue = 1, opNewValue = 1 in
3406 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3407 : NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
3408 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3409 [], "", V2LDST_tc_st_SLOT0> {
3412 bits<16> offsetBits;
3414 string ImmOpStr = !cast<string>(ImmOp);
3415 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3416 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3417 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3418 /* u16_0Imm */ addr{15-0})));
3419 let IClass = 0b0100;
3422 let Inst{26-25} = offsetBits{15-14};
3423 let Inst{24-21} = 0b0101;
3424 let Inst{20-16} = offsetBits{13-9};
3425 let Inst{13} = offsetBits{8};
3426 let Inst{12-11} = MajOp;
3427 let Inst{10-8} = src;
3428 let Inst{7-0} = offsetBits{7-0};
3431 //===----------------------------------------------------------------------===//
3432 // Template class for predicated new-value store instructions with
3433 // absolute addressing.
3434 //===----------------------------------------------------------------------===//
3435 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3436 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3437 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3438 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3439 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3440 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3441 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3446 let isPredicatedNew = isNew;
3447 let isPredicatedFalse = isNot;
3449 let IClass = 0b1010;
3451 let Inst{27-24} = 0b1111;
3452 let Inst{23-21} = 0b101;
3453 let Inst{17-16} = absaddr{5-4};
3454 let Inst{13} = isNew;
3455 let Inst{12-11} = MajOp;
3456 let Inst{10-8} = src2;
3458 let Inst{6-3} = absaddr{3-0};
3459 let Inst{2} = isNot;
3460 let Inst{1-0} = src1;
3463 //===----------------------------------------------------------------------===//
3464 // Template class for non-predicated new-value store instructions with
3465 // absolute addressing.
3466 //===----------------------------------------------------------------------===//
3467 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3468 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3470 string ImmOpStr = !cast<string>(ImmOp);
3471 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3472 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3473 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3474 /* u16_0Imm */ 16)));
3476 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3477 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3478 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3479 /* u16_0Imm */ 0)));
3482 //===----------------------------------------------------------------------===//
3483 // Multiclass for new-value store instructions with absolute addressing.
3484 //===----------------------------------------------------------------------===//
3485 let addrMode = Absolute, isExtended = 1 in
3486 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3488 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3489 let opExtendable = 0, isPredicable = 1 in
3490 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3493 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3494 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3497 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3498 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3502 //===----------------------------------------------------------------------===//
3503 // Stores with absolute addressing
3504 //===----------------------------------------------------------------------===//
3505 let accessSize = ByteAccess in
3506 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3507 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3509 let accessSize = HalfWordAccess in
3510 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3511 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3513 let accessSize = WordAccess in
3514 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3515 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3517 let isNVStorable = 0, accessSize = DoubleWordAccess in
3518 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3520 let isNVStorable = 0, accessSize = HalfWordAccess in
3521 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3523 //===----------------------------------------------------------------------===//
3524 // GP-relative stores.
3525 // mem[bhwd](#global)=Rt
3526 // Once predicated, these instructions map to absolute addressing mode.
3527 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3528 //===----------------------------------------------------------------------===//
3530 let isAsmParserOnly = 1 in
3531 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3532 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3533 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3534 // Set BaseOpcode same as absolute addressing instructions so that
3535 // non-predicated GP-Rel instructions can have relate with predicated
3536 // Absolute instruction.
3537 let BaseOpcode = BaseOp#_abs;
3540 let isAsmParserOnly = 1 in
3541 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3542 bits<2> MajOp, bit isHalf = 0> {
3543 // Set BaseOpcode same as absolute addressing instructions so that
3544 // non-predicated GP-Rel instructions can have relate with predicated
3545 // Absolute instruction.
3546 let BaseOpcode = BaseOp#_abs in {
3547 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3548 globaladdress, 0, isHalf>;
3550 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3554 let accessSize = ByteAccess in
3555 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3557 let accessSize = HalfWordAccess in
3558 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3560 let accessSize = WordAccess in
3561 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3563 let isNVStorable = 0, accessSize = DoubleWordAccess in
3564 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3565 u16_3Imm, 0b11>, PredNewRel;
3567 let isNVStorable = 0, accessSize = HalfWordAccess in
3568 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3569 u16_1Imm, 0b01, 1>, PredNewRel;
3571 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
3572 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
3574 class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
3576 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
3578 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
3579 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
3581 class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
3583 : Pat<(Store Value:$val, Addr:$addr),
3584 (MI Addr:$addr, (ValueMod Value:$val))>;
3586 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
3587 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
3588 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
3589 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdgp>;
3591 let AddedComplexity = 100 in {
3592 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>;
3593 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>;
3594 def: Storea_pat<store, I32, addrgp, S2_storerigp>;
3595 def: Storea_pat<store, I64, addrgp, S2_storerdgp>;
3597 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3598 // to "r0 = 1; memw(#foo) = r0"
3599 let AddedComplexity = 100 in
3600 def: Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3601 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3604 //===----------------------------------------------------------------------===//
3605 // Template class for non predicated load instructions with
3606 // absolute addressing mode.
3607 //===----------------------------------------------------------------------===//
3608 let isPredicable = 1, hasSideEffects = 0 in
3609 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3610 bits<3> MajOp, Operand AddrOp, bit isAbs>
3611 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3612 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3613 [], "", V2LDST_tc_ld_SLOT01> {
3616 bits<16> offsetBits;
3618 string ImmOpStr = !cast<string>(ImmOp);
3619 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3620 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3621 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3622 /* u16_0Imm */ addr{15-0})));
3624 let IClass = 0b0100;
3627 let Inst{26-25} = offsetBits{15-14};
3629 let Inst{23-21} = MajOp;
3630 let Inst{20-16} = offsetBits{13-9};
3631 let Inst{13-5} = offsetBits{8-0};
3632 let Inst{4-0} = dst;
3635 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3637 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1>, AddrModeRel {
3639 string ImmOpStr = !cast<string>(ImmOp);
3640 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3641 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3642 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3643 /* u16_0Imm */ 16)));
3645 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3646 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3647 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3648 /* u16_0Imm */ 0)));
3651 //===----------------------------------------------------------------------===//
3652 // Template class for predicated load instructions with
3653 // absolute addressing mode.
3654 //===----------------------------------------------------------------------===//
3655 let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
3656 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3657 bit isPredNot, bit isPredNew>
3658 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3659 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3660 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3665 let isPredicatedNew = isPredNew;
3666 let isPredicatedFalse = isPredNot;
3667 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
3669 let IClass = 0b1001;
3671 let Inst{27-24} = 0b1111;
3672 let Inst{23-21} = MajOp;
3673 let Inst{20-16} = absaddr{5-1};
3675 let Inst{12} = isPredNew;
3676 let Inst{11} = isPredNot;
3677 let Inst{10-9} = src1;
3678 let Inst{8} = absaddr{0};
3680 let Inst{4-0} = dst;
3683 //===----------------------------------------------------------------------===//
3684 // Multiclass for the load instructions with absolute addressing mode.
3685 //===----------------------------------------------------------------------===//
3686 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3688 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3690 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3693 let addrMode = Absolute, isExtended = 1 in
3694 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3695 Operand ImmOp, bits<3> MajOp> {
3696 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3697 let opExtendable = 1, isPredicable = 1 in
3698 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3701 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3702 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3706 let accessSize = ByteAccess, hasNewValue = 1 in {
3707 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3708 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3711 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3712 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3713 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3716 let accessSize = WordAccess, hasNewValue = 1 in
3717 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3719 let accessSize = DoubleWordAccess in
3720 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3722 //===----------------------------------------------------------------------===//
3723 // multiclass for load instructions with GP-relative addressing mode.
3724 // Rx=mem[bhwd](##global)
3725 // Once predicated, these instructions map to absolute addressing mode.
3726 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3727 //===----------------------------------------------------------------------===//
3729 let isAsmParserOnly = 1 in
3730 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3732 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3733 let BaseOpcode = BaseOp#_abs;
3736 let accessSize = ByteAccess, hasNewValue = 1 in {
3737 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3738 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3741 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3742 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3743 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3746 let accessSize = WordAccess, hasNewValue = 1 in
3747 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3749 let accessSize = DoubleWordAccess in
3750 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3752 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
3753 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
3754 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
3755 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
3757 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3758 def: Loadam_pat<load, i1, addrga, I32toI1, L4_loadrub_abs>;
3759 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
3761 def: Stoream_pat<store, I1, addrga, I1toI32, S2_storerbabs>;
3762 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
3764 // Map from load(globaladdress) -> mem[u][bhwd](#foo)
3765 class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
3766 : Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
3767 (VT (MI tglobaladdr:$global))>;
3769 let AddedComplexity = 100 in {
3770 def: LoadGP_pats <extloadi8, L2_loadrbgp>;
3771 def: LoadGP_pats <sextloadi8, L2_loadrbgp>;
3772 def: LoadGP_pats <zextloadi8, L2_loadrubgp>;
3773 def: LoadGP_pats <extloadi16, L2_loadrhgp>;
3774 def: LoadGP_pats <sextloadi16, L2_loadrhgp>;
3775 def: LoadGP_pats <zextloadi16, L2_loadruhgp>;
3776 def: LoadGP_pats <load, L2_loadrigp>;
3777 def: LoadGP_pats <load, L2_loadrdgp, i64>;
3780 // When the Interprocedural Global Variable optimizer realizes that a certain
3781 // global variable takes only two constant values, it shrinks the global to
3782 // a boolean. Catch those loads here in the following 3 patterns.
3783 let AddedComplexity = 100 in {
3784 def: LoadGP_pats <extloadi1, L2_loadrubgp>;
3785 def: LoadGP_pats <zextloadi1, L2_loadrubgp>;
3788 // Transfer global address into a register
3789 def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3790 def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3791 def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3793 def: Pat<(i64 (ctlz I64:$src1)), (Zext64 (S2_cl0p I64:$src1))>;
3794 def: Pat<(i64 (cttz I64:$src1)), (Zext64 (S2_ct0p I64:$src1))>;
3796 let AddedComplexity = 30 in {
3797 def: Storea_pat<truncstorei8, I32, u0AlwaysExtPred, S2_storerbabs>;
3798 def: Storea_pat<truncstorei16, I32, u0AlwaysExtPred, S2_storerhabs>;
3799 def: Storea_pat<store, I32, u0AlwaysExtPred, S2_storeriabs>;
3802 let AddedComplexity = 30 in {
3803 def: Loada_pat<load, i32, u0AlwaysExtPred, L4_loadri_abs>;
3804 def: Loada_pat<sextloadi8, i32, u0AlwaysExtPred, L4_loadrb_abs>;
3805 def: Loada_pat<zextloadi8, i32, u0AlwaysExtPred, L4_loadrub_abs>;
3806 def: Loada_pat<sextloadi16, i32, u0AlwaysExtPred, L4_loadrh_abs>;
3807 def: Loada_pat<zextloadi16, i32, u0AlwaysExtPred, L4_loadruh_abs>;
3810 // Indexed store word - global address.
3811 // memw(Rs+#u6:2)=#S8
3812 let AddedComplexity = 100 in
3813 def: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
3815 // Load from a global address that has only one use in the current basic block.
3816 let AddedComplexity = 100 in {
3817 def: Loada_pat<extloadi8, i32, addrga, L4_loadrub_abs>;
3818 def: Loada_pat<sextloadi8, i32, addrga, L4_loadrb_abs>;
3819 def: Loada_pat<zextloadi8, i32, addrga, L4_loadrub_abs>;
3821 def: Loada_pat<extloadi16, i32, addrga, L4_loadruh_abs>;
3822 def: Loada_pat<sextloadi16, i32, addrga, L4_loadrh_abs>;
3823 def: Loada_pat<zextloadi16, i32, addrga, L4_loadruh_abs>;
3825 def: Loada_pat<load, i32, addrga, L4_loadri_abs>;
3826 def: Loada_pat<load, i64, addrga, L4_loadrd_abs>;
3829 // Store to a global address that has only one use in the current basic block.
3830 let AddedComplexity = 100 in {
3831 def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
3832 def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
3833 def: Storea_pat<store, I32, addrga, S2_storeriabs>;
3834 def: Storea_pat<store, I64, addrga, S2_storerdabs>;
3836 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
3839 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3840 let AddedComplexity = 100 in
3841 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3842 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3844 // Transfer global address into a register
3845 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3846 isAsCheapAsAMove = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
3847 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3849 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>;
3851 // Transfer a block address into a register
3852 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3853 (TFRI_V4 tblockaddress:$src1)>;
3855 let AddedComplexity = 50 in
3856 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3857 (TFRI_V4 tglobaladdr:$src1)>;
3859 // i8/i16/i32 -> i64 loads
3860 // We need a complexity of 120 here to override preceding handling of
3862 let AddedComplexity = 120 in {
3863 def: Loadam_pat<extloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3864 def: Loadam_pat<sextloadi8, i64, addrga, Sext64, L4_loadrb_abs>;
3865 def: Loadam_pat<zextloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3867 def: Loadam_pat<extloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3868 def: Loadam_pat<sextloadi16, i64, addrga, Sext64, L4_loadrh_abs>;
3869 def: Loadam_pat<zextloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3871 def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3872 def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
3873 def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3876 let AddedComplexity = 100 in {
3877 def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
3878 def: Loada_pat<sextloadi8, i32, addrgp, L4_loadrb_abs>;
3879 def: Loada_pat<zextloadi8, i32, addrgp, L4_loadrub_abs>;
3881 def: Loada_pat<extloadi16, i32, addrgp, L4_loadruh_abs>;
3882 def: Loada_pat<sextloadi16, i32, addrgp, L4_loadrh_abs>;
3883 def: Loada_pat<zextloadi16, i32, addrgp, L4_loadruh_abs>;
3885 def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
3886 def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
3889 let AddedComplexity = 100 in {
3890 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
3891 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
3892 def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
3893 def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
3896 def: Loada_pat<atomic_load_8, i32, addrgp, L4_loadrub_abs>;
3897 def: Loada_pat<atomic_load_16, i32, addrgp, L4_loadruh_abs>;
3898 def: Loada_pat<atomic_load_32, i32, addrgp, L4_loadri_abs>;
3899 def: Loada_pat<atomic_load_64, i64, addrgp, L4_loadrd_abs>;
3901 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbabs>;
3902 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
3903 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
3904 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
3906 let Constraints = "@earlyclobber $dst" in
3907 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3908 IntRegs:$c, IntRegs:$d),
3909 ".error \"Should never try to emit Insert4\"",
3910 [(set (i64 DoubleRegs:$dst),
3911 (or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))),
3913 (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))),
3914 (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))),
3916 (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))))]>;
3918 //===----------------------------------------------------------------------===//
3919 // :raw for of boundscheck:hi:lo insns
3920 //===----------------------------------------------------------------------===//
3922 // A4_boundscheck_lo: Detect if a register is within bounds.
3923 let hasSideEffects = 0 in
3924 def A4_boundscheck_lo: ALU64Inst <
3925 (outs PredRegs:$Pd),
3926 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3927 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
3932 let IClass = 0b1101;
3934 let Inst{27-23} = 0b00100;
3936 let Inst{7-5} = 0b100;
3938 let Inst{20-16} = Rss;
3939 let Inst{12-8} = Rtt;
3942 // A4_boundscheck_hi: Detect if a register is within bounds.
3943 let hasSideEffects = 0 in
3944 def A4_boundscheck_hi: ALU64Inst <
3945 (outs PredRegs:$Pd),
3946 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3947 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
3952 let IClass = 0b1101;
3954 let Inst{27-23} = 0b00100;
3956 let Inst{7-5} = 0b101;
3958 let Inst{20-16} = Rss;
3959 let Inst{12-8} = Rtt;
3962 let hasSideEffects = 0, isAsmParserOnly = 1 in
3963 def A4_boundscheck : MInst <
3964 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3965 "$Pd=boundscheck($Rs,$Rtt)">;
3967 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
3968 let isPredicateLate = 1, hasSideEffects = 0 in
3969 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
3970 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3971 "$Pd = tlbmatch($Rs, $Rt)",
3972 [], "", ALU64_tc_2early_SLOT23> {
3977 let IClass = 0b1101;
3978 let Inst{27-23} = 0b00100;
3979 let Inst{20-16} = Rs;
3981 let Inst{12-8} = Rt;
3982 let Inst{7-5} = 0b011;
3986 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
3987 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
3988 // We don't really want either one here.
3989 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
3990 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
3993 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
3994 // really do a load.
3995 let hasSideEffects = 1, mayLoad = 0 in
3996 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
3997 "dcfetch($Rs + #$u11_3)",
3998 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
3999 "", LD_tc_ld_SLOT0> {
4003 let IClass = 0b1001;
4004 let Inst{27-21} = 0b0100000;
4005 let Inst{20-16} = Rs;
4007 let Inst{10-0} = u11_3{13-3};
4010 //===----------------------------------------------------------------------===//
4011 // Compound instructions
4012 //===----------------------------------------------------------------------===//
4014 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4015 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4016 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4018 class CJInst_tstbit_R0<string px, bit np, string tnt>
4019 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4020 ""#px#" = tstbit($Rs, #0); if ("
4021 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4022 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4027 let isPredicatedFalse = np;
4028 // tnt: Taken/Not Taken
4029 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4030 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4032 let IClass = 0b0001;
4033 let Inst{27-26} = 0b00;
4034 let Inst{25} = !if (!eq(px, "!p1"), 1,
4035 !if (!eq(px, "p1"), 1, 0));
4036 let Inst{24-23} = 0b11;
4038 let Inst{21-20} = r9_2{10-9};
4039 let Inst{19-16} = Rs;
4040 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4041 let Inst{9-8} = 0b11;
4042 let Inst{7-1} = r9_2{8-2};
4045 let Defs = [PC, P0], Uses = [P0] in {
4046 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4047 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4048 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4049 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4052 let Defs = [PC, P1], Uses = [P1] in {
4053 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4054 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4055 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4056 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4060 let isBranch = 1, hasSideEffects = 0,
4061 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4062 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4063 opExtendable = 2, isTerminator = 1 in
4064 class CJInst_RR<string px, string op, bit np, string tnt>
4065 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4066 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4067 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4068 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4074 let isPredicatedFalse = np;
4075 // tnt: Taken/Not Taken
4076 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4077 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4079 let IClass = 0b0001;
4080 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4081 !if (!eq(op, "gt"), 0b01001,
4082 !if (!eq(op, "gtu"), 0b01010, 0)));
4084 let Inst{21-20} = r9_2{10-9};
4085 let Inst{19-16} = Rs;
4086 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4087 // px: Predicate reg 0/1
4088 let Inst{12} = !if (!eq(px, "!p1"), 1,
4089 !if (!eq(px, "p1"), 1, 0));
4090 let Inst{11-8} = Rt;
4091 let Inst{7-1} = r9_2{8-2};
4094 // P[10] taken/not taken.
4095 multiclass T_tnt_CJInst_RR<string op, bit np> {
4096 let Defs = [PC, P0], Uses = [P0] in {
4097 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4098 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4100 let Defs = [PC, P1], Uses = [P1] in {
4101 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4102 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4105 // Predicate / !Predicate
4106 multiclass T_pnp_CJInst_RR<string op>{
4107 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4108 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4110 // TypeCJ Instructions compare RR and jump
4111 defm eq : T_pnp_CJInst_RR<"eq">;
4112 defm gt : T_pnp_CJInst_RR<"gt">;
4113 defm gtu : T_pnp_CJInst_RR<"gtu">;
4115 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4116 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4117 opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
4118 class CJInst_RU5<string px, string op, bit np, string tnt>
4119 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4120 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4121 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4122 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4128 let isPredicatedFalse = np;
4129 // tnt: Taken/Not Taken
4130 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4131 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4133 let IClass = 0b0001;
4134 let Inst{27-26} = 0b00;
4135 // px: Predicate reg 0/1
4136 let Inst{25} = !if (!eq(px, "!p1"), 1,
4137 !if (!eq(px, "p1"), 1, 0));
4138 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4139 !if (!eq(op, "gt"), 0b01,
4140 !if (!eq(op, "gtu"), 0b10, 0)));
4142 let Inst{21-20} = r9_2{10-9};
4143 let Inst{19-16} = Rs;
4144 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4145 let Inst{12-8} = U5;
4146 let Inst{7-1} = r9_2{8-2};
4148 // P[10] taken/not taken.
4149 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4150 let Defs = [PC, P0], Uses = [P0] in {
4151 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4152 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4154 let Defs = [PC, P1], Uses = [P1] in {
4155 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4156 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4159 // Predicate / !Predicate
4160 multiclass T_pnp_CJInst_RU5<string op>{
4161 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4162 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4164 // TypeCJ Instructions compare RI and jump
4165 defm eq : T_pnp_CJInst_RU5<"eq">;
4166 defm gt : T_pnp_CJInst_RU5<"gt">;
4167 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4169 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4170 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4171 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4173 class CJInst_Rn1<string px, string op, bit np, string tnt>
4174 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4175 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4176 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4177 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4182 let isPredicatedFalse = np;
4183 // tnt: Taken/Not Taken
4184 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4185 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4187 let IClass = 0b0001;
4188 let Inst{27-26} = 0b00;
4189 let Inst{25} = !if (!eq(px, "!p1"), 1,
4190 !if (!eq(px, "p1"), 1, 0));
4192 let Inst{24-23} = 0b11;
4194 let Inst{21-20} = r9_2{10-9};
4195 let Inst{19-16} = Rs;
4196 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4197 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4198 !if (!eq(op, "gt"), 0b01, 0));
4199 let Inst{7-1} = r9_2{8-2};
4202 // P[10] taken/not taken.
4203 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4204 let Defs = [PC, P0], Uses = [P0] in {
4205 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4206 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4208 let Defs = [PC, P1], Uses = [P1] in {
4209 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4210 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4213 // Predicate / !Predicate
4214 multiclass T_pnp_CJInst_Rn1<string op>{
4215 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4216 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4218 // TypeCJ Instructions compare -1 and jump
4219 defm eq : T_pnp_CJInst_Rn1<"eq">;
4220 defm gt : T_pnp_CJInst_Rn1<"gt">;
4222 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4223 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4224 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4225 opExtentAlign = 2, opExtendable = 2 in
4226 def J4_jumpseti: CJInst <
4228 (ins u6Imm:$U6, brtarget:$r9_2),
4229 "$Rd = #$U6 ; jump $r9_2"> {
4234 let IClass = 0b0001;
4235 let Inst{27-24} = 0b0110;
4236 let Inst{21-20} = r9_2{10-9};
4237 let Inst{19-16} = Rd;
4238 let Inst{13-8} = U6;
4239 let Inst{7-1} = r9_2{8-2};
4242 // J4_jumpsetr: Direct unconditional jump and transfer register.
4243 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4244 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4245 opExtentAlign = 2, opExtendable = 2 in
4246 def J4_jumpsetr: CJInst <
4248 (ins IntRegs:$Rs, brtarget:$r9_2),
4249 "$Rd = $Rs ; jump $r9_2"> {
4254 let IClass = 0b0001;
4255 let Inst{27-24} = 0b0111;
4256 let Inst{21-20} = r9_2{10-9};
4257 let Inst{11-8} = Rd;
4258 let Inst{19-16} = Rs;
4259 let Inst{7-1} = r9_2{8-2};