lib/Target/Hexagon/HexagonInstrInfoV4.td

   1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let neverHasSideEffects = 1 in
  15 def IMMEXT : Immext<(outs), (ins),
  16                     "/* immext #... */",
  17                     []>,
  18              Requires<[HasV4T]>;
  19
  20 // Hexagon V4 Architecture spec defines 8 instruction classes:
  21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
  22 // compiler)
  23
  24 // LD Instructions:
  25 // ========================================
  26 // Loads (8/16/32/64 bit)
  27 // Deallocframe
  28
  29 // ST Instructions:
  30 // ========================================
  31 // Stores (8/16/32/64 bit)
  32 // Allocframe
  33
  34 // ALU32 Instructions:
  35 // ========================================
  36 // Arithmetic / Logical (32 bit)
  37 // Vector Halfword
  38
  39 // XTYPE Instructions (32/64 bit):
  40 // ========================================
  41 // Arithmetic, Logical, Bit Manipulation
  42 // Multiply (Integer, Fractional, Complex)
  43 // Permute / Vector Permute Operations
  44 // Predicate Operations
  45 // Shift / Shift with Add/Sub/Logical
  46 // Vector Byte ALU
  47 // Vector Halfword (ALU, Shift, Multiply)
  48 // Vector Word (ALU, Shift)
  49
  50 // J Instructions:
  51 // ========================================
  52 // Jump/Call PC-relative
  53
  54 // JR Instructions:
  55 // ========================================
  56 // Jump/Call Register
  57
  58 // MEMOP Instructions:
  59 // ========================================
  60 // Operation on memory (8/16/32 bit)
  61
  62 // NV Instructions:
  63 // ========================================
  64 // New-value Jumps
  65 // New-value Stores
  66
  67 // CR Instructions:
  68 // ========================================
  69 // Control-Register Transfers
  70 // Hardware Loop Setup
  71 // Predicate Logicals & Reductions
  72
  73 // SYSTEM Instructions (not implemented in the compiler):
  74 // ========================================
  75 // Prefetch
  76 // Cache Maintenance
  77 // Bus Operations
  78
  79
  80 //===----------------------------------------------------------------------===//
  81 // ALU32 +
  82 //===----------------------------------------------------------------------===//
  83
  84 // Shift halfword.
  85
  86 let isPredicated = 1 in
  87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  88             (ins PredRegs:$src1, IntRegs:$src2),
  89             "if ($src1) $dst = aslh($src2)",
  90             []>,
  91             Requires<[HasV4T]>;
  92
  93 let isPredicated = 1 in
  94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  95             (ins PredRegs:$src1, IntRegs:$src2),
  96             "if (!$src1) $dst = aslh($src2)",
  97             []>,
  98             Requires<[HasV4T]>;
  99
 100 let isPredicated = 1 in
 101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 102             (ins PredRegs:$src1, IntRegs:$src2),
 103             "if ($src1.new) $dst = aslh($src2)",
 104             []>,
 105             Requires<[HasV4T]>;
 106
 107 let isPredicated = 1 in
 108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 109             (ins PredRegs:$src1, IntRegs:$src2),
 110             "if (!$src1.new) $dst = aslh($src2)",
 111             []>,
 112             Requires<[HasV4T]>;
 113
 114 let isPredicated = 1 in
 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 116             (ins PredRegs:$src1, IntRegs:$src2),
 117             "if ($src1) $dst = asrh($src2)",
 118             []>,
 119             Requires<[HasV4T]>;
 120
 121 let isPredicated = 1 in
 122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 123             (ins PredRegs:$src1, IntRegs:$src2),
 124             "if (!$src1) $dst = asrh($src2)",
 125             []>,
 126             Requires<[HasV4T]>;
 127
 128 let isPredicated = 1 in
 129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 130             (ins PredRegs:$src1, IntRegs:$src2),
 131             "if ($src1.new) $dst = asrh($src2)",
 132             []>,
 133             Requires<[HasV4T]>;
 134
 135 let isPredicated = 1 in
 136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 137             (ins PredRegs:$src1, IntRegs:$src2),
 138             "if (!$src1.new) $dst = asrh($src2)",
 139             []>,
 140             Requires<[HasV4T]>;
 141
 142 // Sign extend.
 143
 144 let isPredicated = 1 in
 145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 146             (ins PredRegs:$src1, IntRegs:$src2),
 147             "if ($src1) $dst = sxtb($src2)",
 148             []>,
 149             Requires<[HasV4T]>;
 150
 151 let isPredicated = 1 in
 152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 153             (ins PredRegs:$src1, IntRegs:$src2),
 154             "if (!$src1) $dst = sxtb($src2)",
 155             []>,
 156             Requires<[HasV4T]>;
 157
 158 let isPredicated = 1 in
 159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 160             (ins PredRegs:$src1, IntRegs:$src2),
 161             "if ($src1.new) $dst = sxtb($src2)",
 162             []>,
 163             Requires<[HasV4T]>;
 164
 165 let isPredicated = 1 in
 166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 167             (ins PredRegs:$src1, IntRegs:$src2),
 168             "if (!$src1.new) $dst = sxtb($src2)",
 169             []>,
 170             Requires<[HasV4T]>;
 171
 172
 173 let isPredicated = 1 in
 174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 175             (ins PredRegs:$src1, IntRegs:$src2),
 176             "if ($src1) $dst = sxth($src2)",
 177             []>,
 178             Requires<[HasV4T]>;
 179
 180 let isPredicated = 1 in
 181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 182             (ins PredRegs:$src1, IntRegs:$src2),
 183             "if (!$src1) $dst = sxth($src2)",
 184             []>,
 185             Requires<[HasV4T]>;
 186
 187 let isPredicated = 1 in
 188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 189             (ins PredRegs:$src1, IntRegs:$src2),
 190             "if ($src1.new) $dst = sxth($src2)",
 191             []>,
 192             Requires<[HasV4T]>;
 193
 194 let isPredicated = 1 in
 195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 196             (ins PredRegs:$src1, IntRegs:$src2),
 197             "if (!$src1.new) $dst = sxth($src2)",
 198             []>,
 199             Requires<[HasV4T]>;
 200
 201 // Zero exten.
 202
 203 let neverHasSideEffects = 1, isPredicated = 1 in
 204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 205             (ins PredRegs:$src1, IntRegs:$src2),
 206             "if ($src1) $dst = zxtb($src2)",
 207             []>,
 208             Requires<[HasV4T]>;
 209
 210 let neverHasSideEffects = 1, isPredicated = 1 in
 211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 212             (ins PredRegs:$src1, IntRegs:$src2),
 213             "if (!$src1) $dst = zxtb($src2)",
 214             []>,
 215             Requires<[HasV4T]>;
 216
 217 let neverHasSideEffects = 1, isPredicated = 1 in
 218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 219             (ins PredRegs:$src1, IntRegs:$src2),
 220             "if ($src1.new) $dst = zxtb($src2)",
 221             []>,
 222             Requires<[HasV4T]>;
 223
 224 let neverHasSideEffects = 1, isPredicated = 1 in
 225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 226             (ins PredRegs:$src1, IntRegs:$src2),
 227             "if (!$src1.new) $dst = zxtb($src2)",
 228             []>,
 229             Requires<[HasV4T]>;
 230
 231 let neverHasSideEffects = 1, isPredicated = 1 in
 232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 233             (ins PredRegs:$src1, IntRegs:$src2),
 234             "if ($src1) $dst = zxth($src2)",
 235             []>,
 236             Requires<[HasV4T]>;
 237
 238 let neverHasSideEffects = 1, isPredicated = 1 in
 239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 240             (ins PredRegs:$src1, IntRegs:$src2),
 241             "if (!$src1) $dst = zxth($src2)",
 242             []>,
 243             Requires<[HasV4T]>;
 244
 245 let neverHasSideEffects = 1, isPredicated = 1 in
 246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 247             (ins PredRegs:$src1, IntRegs:$src2),
 248             "if ($src1.new) $dst = zxth($src2)",
 249             []>,
 250             Requires<[HasV4T]>;
 251
 252 let neverHasSideEffects = 1, isPredicated = 1 in
 253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 254             (ins PredRegs:$src1, IntRegs:$src2),
 255             "if (!$src1.new) $dst = zxth($src2)",
 256             []>,
 257             Requires<[HasV4T]>;
 258
 259 // Generate frame index addresses.
 260 let neverHasSideEffects = 1, isReMaterializable = 1 in
 261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
 262             (ins IntRegs:$src1, s32Imm:$offset),
 263             "$dst = add($src1, ##$offset)",
 264             []>,
 265             Requires<[HasV4T]>;
 266
 267
 268 //===----------------------------------------------------------------------===//
 269 // ALU32 -
 270 //===----------------------------------------------------------------------===//
 271
 272
 273 //===----------------------------------------------------------------------===//
 274 // ALU32/PERM +
 275 //===----------------------------------------------------------------------===//
 276
 277 // Combine
 278 // Rdd=combine(Rs, #s8)
 279 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
 280     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 281 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
 282             (ins IntRegs:$src1, s8Ext:$src2),
 283             "$dst = combine($src1, #$src2)",
 284             []>,
 285             Requires<[HasV4T]>;
 286
 287 // Rdd=combine(#s8, Rs)
 288 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
 289     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 290 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 291             (ins s8Ext:$src1, IntRegs:$src2),
 292             "$dst = combine(#$src1, $src2)",
 293             []>,
 294             Requires<[HasV4T]>;
 295
 296 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
 297     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 298 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
 299             (ins s8Imm:$src1, u6Ext:$src2),
 300             "$dst = combine(#$src1, #$src2)",
 301             []>,
 302             Requires<[HasV4T]>;
 303
 304 //===----------------------------------------------------------------------===//
 305 // ALU32/PERM +
 306 //===----------------------------------------------------------------------===//
 307
 308 //===----------------------------------------------------------------------===//
 309 // LD +
 310 //===----------------------------------------------------------------------===//
 311 //
 312 // These absolute set addressing mode instructions accept immediate as
 313 // an operand. We have duplicated these patterns to take global address.
 314
 315 let neverHasSideEffects = 1 in
 316 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 317             (ins u6Imm:$addr),
 318             "$dst1 = memd($dst2=#$addr)",
 319             []>,
 320             Requires<[HasV4T]>;
 321
 322 // Rd=memb(Re=#U6)
 323 let neverHasSideEffects = 1 in
 324 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 325             (ins u6Imm:$addr),
 326             "$dst1 = memb($dst2=#$addr)",
 327             []>,
 328             Requires<[HasV4T]>;
 329
 330 // Rd=memh(Re=#U6)
 331 let neverHasSideEffects = 1 in
 332 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 333             (ins u6Imm:$addr),
 334             "$dst1 = memh($dst2=#$addr)",
 335             []>,
 336             Requires<[HasV4T]>;
 337
 338 // Rd=memub(Re=#U6)
 339 let neverHasSideEffects = 1 in
 340 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 341             (ins u6Imm:$addr),
 342             "$dst1 = memub($dst2=#$addr)",
 343             []>,
 344             Requires<[HasV4T]>;
 345
 346 // Rd=memuh(Re=#U6)
 347 let neverHasSideEffects = 1 in
 348 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 349             (ins u6Imm:$addr),
 350             "$dst1 = memuh($dst2=#$addr)",
 351             []>,
 352             Requires<[HasV4T]>;
 353
 354 // Rd=memw(Re=#U6)
 355 let neverHasSideEffects = 1 in
 356 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 357             (ins u6Imm:$addr),
 358             "$dst1 = memw($dst2=#$addr)",
 359             []>,
 360             Requires<[HasV4T]>;
 361
 362 // Following patterns are defined for absolute set addressing mode
 363 // instruction which take global address as operand.
 364 let neverHasSideEffects = 1 in
 365 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 366             (ins globaladdress:$addr),
 367             "$dst1 = memd($dst2=##$addr)",
 368             []>,
 369             Requires<[HasV4T]>;
 370
 371 // Rd=memb(Re=#U6)
 372 let neverHasSideEffects = 1 in
 373 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 374             (ins globaladdress:$addr),
 375             "$dst1 = memb($dst2=##$addr)",
 376             []>,
 377             Requires<[HasV4T]>;
 378
 379 // Rd=memh(Re=#U6)
 380 let neverHasSideEffects = 1 in
 381 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 382             (ins globaladdress:$addr),
 383             "$dst1 = memh($dst2=##$addr)",
 384             []>,
 385             Requires<[HasV4T]>;
 386
 387 // Rd=memub(Re=#U6)
 388 let neverHasSideEffects = 1 in
 389 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 390             (ins globaladdress:$addr),
 391             "$dst1 = memub($dst2=##$addr)",
 392             []>,
 393             Requires<[HasV4T]>;
 394
 395 // Rd=memuh(Re=#U6)
 396 let neverHasSideEffects = 1 in
 397 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 398             (ins globaladdress:$addr),
 399             "$dst1 = memuh($dst2=##$addr)",
 400             []>,
 401             Requires<[HasV4T]>;
 402
 403 // Rd=memw(Re=#U6)
 404 let neverHasSideEffects = 1 in
 405 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 406             (ins globaladdress:$addr),
 407             "$dst1 = memw($dst2=##$addr)",
 408             []>,
 409             Requires<[HasV4T]>;
 410
 411 // Load doubleword.
 412 //
 413 // Make sure that in post increment load, the first operand is always the post
 414 // increment operand.
 415 //
 416 // Rdd=memd(Rs+Rt<<#u2)
 417 // Special case pattern for indexed load without offset which is easier to
 418 // match. AddedComplexity of this pattern should be lower than base+offset load
 419 // and lower yet than the more generic version with offset/shift below
 420 // Similar approach is taken for all other base+index loads.
 421 let AddedComplexity = 10, isPredicable = 1 in
 422 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
 423                     (ins IntRegs:$src1, IntRegs:$src2),
 424                     "$dst=memd($src1+$src2<<#0)",
 425                     [(set (i64 DoubleRegs:$dst),
 426                           (i64 (load (add (i32 IntRegs:$src1),
 427                                           (i32 IntRegs:$src2)))))]>,
 428                     Requires<[HasV4T]>;
 429
 430 // multiclass for load instructions with base + register offset
 431 // addressing mode
 432 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
 433                              bit isPredNew> {
 434   let PNewValue = #!if(isPredNew, "new", "") in
 435   def #NAME# : LDInst2<(outs RC:$dst),
 436             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
 437             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
 438             ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
 439             []>, Requires<[HasV4T]>;
 440 }
 441
 442 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
 443   let PredSense = #!if(PredNot, "false", "true") in {
 444     defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
 445     // Predicate new
 446     defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
 447   }
 448 }
 449
 450 let neverHasSideEffects  = 1 in
 451 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
 452   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
 453     let isPredicable = 1 in
 454     def #NAME#_V4 : LDInst2<(outs RC:$dst),
 455             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 456             "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
 457             []>, Requires<[HasV4T]>;
 458
 459     let isPredicated = 1 in {
 460       defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
 461       defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
 462     }
 463   }
 464 }
 465
 466 let addrMode = BaseRegOffset in {
 467   defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
 468   defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
 469   defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
 470   defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
 471   defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
 472   defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
 473 }
 474
 475 // 'def pats' for load instructions with base + register offset and non-zero
 476 // immediate value. Immediate value is used to left-shift the second
 477 // register operand.
 478 let AddedComplexity = 40 in {
 479 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
 480                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 481            (LDrib_indexed_shl_V4 IntRegs:$src1,
 482             IntRegs:$src2, u2ImmPred:$offset)>,
 483             Requires<[HasV4T]>;
 484
 485 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
 486                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 487            (LDriub_indexed_shl_V4 IntRegs:$src1,
 488             IntRegs:$src2, u2ImmPred:$offset)>,
 489             Requires<[HasV4T]>;
 490
 491 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
 492                                 (shl IntRegs:$src2, u2ImmPred:$offset)))),
 493            (LDriub_indexed_shl_V4 IntRegs:$src1,
 494             IntRegs:$src2, u2ImmPred:$offset)>,
 495             Requires<[HasV4T]>;
 496
 497 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
 498                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 499            (LDrih_indexed_shl_V4 IntRegs:$src1,
 500             IntRegs:$src2, u2ImmPred:$offset)>,
 501             Requires<[HasV4T]>;
 502
 503 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
 504                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 505            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 506             IntRegs:$src2, u2ImmPred:$offset)>,
 507             Requires<[HasV4T]>;
 508
 509 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
 510                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 511            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 512             IntRegs:$src2, u2ImmPred:$offset)>,
 513             Requires<[HasV4T]>;
 514
 515 def : Pat <(i32 (load (add IntRegs:$src1,
 516                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 517            (LDriw_indexed_shl_V4 IntRegs:$src1,
 518             IntRegs:$src2, u2ImmPred:$offset)>,
 519             Requires<[HasV4T]>;
 520
 521 def : Pat <(i64 (load (add IntRegs:$src1,
 522                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 523            (LDrid_indexed_shl_V4 IntRegs:$src1,
 524             IntRegs:$src2, u2ImmPred:$offset)>,
 525             Requires<[HasV4T]>;
 526 }
 527
 528 //// Load doubleword conditionally.
 529 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
 530 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 531 let AddedComplexity = 15, isPredicated = 1 in
 532 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 533                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 534                     "if ($src1) $dst=memd($src2+$src3<<#0)",
 535                     []>,
 536                     Requires<[HasV4T]>;
 537
 538 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 539 let AddedComplexity = 15, isPredicated = 1 in
 540 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 541                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 542                     "if ($src1.new) $dst=memd($src2+$src3<<#0)",
 543                     []>,
 544                     Requires<[HasV4T]>;
 545
 546 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 547 let AddedComplexity = 15, isPredicated = 1 in
 548 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 549                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 550                     "if (!$src1) $dst=memd($src2+$src3<<#0)",
 551                     []>,
 552                     Requires<[HasV4T]>;
 553
 554 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 555 let AddedComplexity = 15, isPredicated = 1 in
 556 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 557                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 558                     "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
 559                     []>,
 560                     Requires<[HasV4T]>;
 561
 562 // Rdd=memd(Rt<<#u2+#U6)
 563
 564 //// Load byte.
 565 // Rd=memb(Rs+Rt<<#u2)
 566 let AddedComplexity = 10, isPredicable = 1 in
 567 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
 568                     (ins IntRegs:$src1, IntRegs:$src2),
 569                     "$dst=memb($src1+$src2<<#0)",
 570                     [(set (i32 IntRegs:$dst),
 571                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 572                                                 (i32 IntRegs:$src2)))))]>,
 573                     Requires<[HasV4T]>;
 574
 575 let AddedComplexity = 10, isPredicable = 1 in
 576 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
 577                     (ins IntRegs:$src1, IntRegs:$src2),
 578                     "$dst=memub($src1+$src2<<#0)",
 579                     [(set (i32 IntRegs:$dst),
 580                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 581                                                 (i32 IntRegs:$src2)))))]>,
 582                     Requires<[HasV4T]>;
 583
 584 let AddedComplexity = 10, isPredicable = 1 in
 585 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 586                     (ins IntRegs:$src1, IntRegs:$src2),
 587                     "$dst=memub($src1+$src2<<#0)",
 588                     [(set (i32 IntRegs:$dst),
 589                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 590                                                (i32 IntRegs:$src2)))))]>,
 591                     Requires<[HasV4T]>;
 592
 593 let AddedComplexity = 40, isPredicable = 1 in
 594 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 595                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 596                     "$dst=memub($src1+$src2<<#$offset)",
 597                     [(set (i32 IntRegs:$dst),
 598                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 599                                                (shl (i32 IntRegs:$src2),
 600                                                     u2ImmPred:$offset)))))]>,
 601                     Requires<[HasV4T]>;
 602
 603 //// Load byte conditionally.
 604 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
 605 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 606 let AddedComplexity = 15, isPredicated = 1 in
 607 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 608                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 609                     "if ($src1) $dst=memb($src2+$src3<<#0)",
 610                     []>,
 611                     Requires<[HasV4T]>;
 612
 613 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 614 let AddedComplexity = 15, isPredicated = 1 in
 615 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 616                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 617                     "if ($src1.new) $dst=memb($src2+$src3<<#0)",
 618                     []>,
 619                     Requires<[HasV4T]>;
 620
 621 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 622 let AddedComplexity = 15, isPredicated = 1 in
 623 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 624                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 625                     "if (!$src1) $dst=memb($src2+$src3<<#0)",
 626                     []>,
 627                     Requires<[HasV4T]>;
 628
 629 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 630 let AddedComplexity = 15, isPredicated = 1 in
 631 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 632                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 633                     "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
 634                     []>,
 635                     Requires<[HasV4T]>;
 636
 637 //// Load unsigned byte conditionally.
 638 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
 639 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 640 let AddedComplexity = 15, isPredicated = 1 in
 641 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 642                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 643                     "if ($src1) $dst=memub($src2+$src3<<#0)",
 644                     []>,
 645                     Requires<[HasV4T]>;
 646
 647 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 648 let AddedComplexity = 15, isPredicated = 1 in
 649 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 650                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 651                     "if ($src1.new) $dst=memub($src2+$src3<<#0)",
 652                     []>,
 653                     Requires<[HasV4T]>;
 654
 655 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 656 let AddedComplexity = 15, isPredicated = 1 in
 657 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 658                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 659                     "if (!$src1) $dst=memub($src2+$src3<<#0)",
 660                     []>,
 661                     Requires<[HasV4T]>;
 662
 663 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 664 let AddedComplexity = 15, isPredicated = 1 in
 665 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 666                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 667                     "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
 668                     []>,
 669                     Requires<[HasV4T]>;
 670
 671 // Rd=memb(Rt<<#u2+#U6)
 672
 673 //// Load halfword
 674 // Rd=memh(Rs+Rt<<#u2)
 675 let AddedComplexity = 10, isPredicable = 1 in
 676 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
 677                     (ins IntRegs:$src1, IntRegs:$src2),
 678                     "$dst=memh($src1+$src2<<#0)",
 679                     [(set (i32 IntRegs:$dst),
 680                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 681                                                  (i32 IntRegs:$src2)))))]>,
 682                     Requires<[HasV4T]>;
 683
 684 let AddedComplexity = 10, isPredicable = 1 in
 685 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
 686                     (ins IntRegs:$src1, IntRegs:$src2),
 687                     "$dst=memuh($src1+$src2<<#0)",
 688                     [(set (i32 IntRegs:$dst),
 689                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 690                                                  (i32 IntRegs:$src2)))))]>,
 691                     Requires<[HasV4T]>;
 692
 693 let AddedComplexity = 10, isPredicable = 1 in
 694 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 695                     (ins IntRegs:$src1, IntRegs:$src2),
 696                     "$dst=memuh($src1+$src2<<#0)",
 697                     [(set (i32 IntRegs:$dst),
 698                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 699                                                 (i32 IntRegs:$src2)))))]>,
 700                     Requires<[HasV4T]>;
 701
 702 let AddedComplexity = 40, isPredicable = 1 in
 703 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 704                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 705                     "$dst=memuh($src1+$src2<<#$offset)",
 706                     [(set (i32 IntRegs:$dst),
 707                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 708                                                 (shl (i32 IntRegs:$src2),
 709                                                      u2ImmPred:$offset)))))]>,
 710                     Requires<[HasV4T]>;
 711
 712 //// Load halfword conditionally.
 713 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
 714 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 715 let AddedComplexity = 15, isPredicated = 1 in
 716 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 717                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 718                     "if ($src1) $dst=memh($src2+$src3<<#0)",
 719                     []>,
 720                     Requires<[HasV4T]>;
 721
 722 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 723 let AddedComplexity = 15, isPredicated = 1 in
 724 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 725                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 726                     "if ($src1.new) $dst=memh($src2+$src3<<#0)",
 727                     []>,
 728                     Requires<[HasV4T]>;
 729
 730 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 731 let AddedComplexity = 15, isPredicated = 1 in
 732 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 733                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 734                     "if (!$src1) $dst=memh($src2+$src3<<#0)",
 735                     []>,
 736                     Requires<[HasV4T]>;
 737
 738 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 739 let AddedComplexity = 15, isPredicated = 1 in
 740 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 741                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 742                     "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
 743                     []>,
 744                     Requires<[HasV4T]>;
 745
 746 //// Load unsigned halfword conditionally.
 747 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
 748 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 749 let AddedComplexity = 15, isPredicated = 1 in
 750 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 751                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 752                     "if ($src1) $dst=memuh($src2+$src3<<#0)",
 753                     []>,
 754                     Requires<[HasV4T]>;
 755
 756 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 757 let AddedComplexity = 15, isPredicated = 1 in
 758 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 759                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 760                     "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
 761                     []>,
 762                     Requires<[HasV4T]>;
 763
 764 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 765 let AddedComplexity = 15, isPredicated = 1 in
 766 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 767                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 768                     "if (!$src1) $dst=memuh($src2+$src3<<#0)",
 769                     []>,
 770                     Requires<[HasV4T]>;
 771
 772 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 773 let AddedComplexity = 15, isPredicated = 1 in
 774 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 775                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 776                     "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
 777                     []>,
 778                     Requires<[HasV4T]>;
 779
 780 // Rd=memh(Rt<<#u2+#U6)
 781
 782 //// Load word.
 783 // Load predicate: Fix for bug 5279.
 784 let neverHasSideEffects = 1 in
 785 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
 786             (ins MEMri:$addr),
 787             "Error; should not emit",
 788             []>,
 789             Requires<[HasV4T]>;
 790
 791 // Rd=memw(Re=#U6)
 792
 793 // Rd=memw(Rs+Rt<<#u2)
 794 let AddedComplexity = 10, isPredicable = 1 in
 795 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
 796                     (ins IntRegs:$src1, IntRegs:$src2),
 797                     "$dst=memw($src1+$src2<<#0)",
 798                     [(set (i32 IntRegs:$dst),
 799                           (i32 (load (add (i32 IntRegs:$src1),
 800                                           (i32 IntRegs:$src2)))))]>,
 801                     Requires<[HasV4T]>;
 802
 803 //// Load word conditionally.
 804 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
 805 // if (Pv) Rd=memw(Rs+Rt<<#u2)
 806 let AddedComplexity = 15, isPredicated = 1 in
 807 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 808                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 809                     "if ($src1) $dst=memw($src2+$src3<<#0)",
 810                     []>,
 811                     Requires<[HasV4T]>;
 812
 813 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 814 let AddedComplexity = 15, isPredicated = 1 in
 815 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 816                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 817                     "if ($src1.new) $dst=memw($src2+$src3<<#0)",
 818                     []>,
 819                     Requires<[HasV4T]>;
 820
 821 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 822 let AddedComplexity = 15, isPredicated = 1 in
 823 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 824                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 825                     "if (!$src1) $dst=memw($src2+$src3<<#0)",
 826                     []>,
 827                     Requires<[HasV4T]>;
 828
 829 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 830 let AddedComplexity = 15, isPredicated = 1 in
 831 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 832                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 833                     "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
 834                     []>,
 835                     Requires<[HasV4T]>;
 836
 837 /// Load from global offset
 838
 839 let isPredicable = 1, neverHasSideEffects = 1 in
 840 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
 841             (ins globaladdress:$global, u16Imm:$offset),
 842             "$dst=memd(#$global+$offset)",
 843             []>,
 844             Requires<[HasV4T]>;
 845
 846 let neverHasSideEffects = 1, isPredicated = 1 in
 847 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 848             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 849             "if ($src1) $dst=memd(##$global+$offset)",
 850             []>,
 851             Requires<[HasV4T]>;
 852
 853 let neverHasSideEffects = 1, isPredicated = 1 in
 854 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 855             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 856             "if (!$src1) $dst=memd(##$global+$offset)",
 857             []>,
 858             Requires<[HasV4T]>;
 859
 860 let neverHasSideEffects = 1, isPredicated = 1 in
 861 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 862             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 863             "if ($src1.new) $dst=memd(##$global+$offset)",
 864             []>,
 865             Requires<[HasV4T]>;
 866
 867 let neverHasSideEffects = 1, isPredicated = 1 in
 868 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 869             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 870             "if (!$src1.new) $dst=memd(##$global+$offset)",
 871             []>,
 872             Requires<[HasV4T]>;
 873
 874 let isPredicable = 1, neverHasSideEffects = 1 in
 875 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
 876             (ins globaladdress:$global, u16Imm:$offset),
 877             "$dst=memb(#$global+$offset)",
 878             []>,
 879             Requires<[HasV4T]>;
 880
 881 let neverHasSideEffects = 1, isPredicated = 1 in
 882 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 883             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 884             "if ($src1) $dst=memb(##$global+$offset)",
 885             []>,
 886             Requires<[HasV4T]>;
 887
 888 let neverHasSideEffects = 1, isPredicated = 1 in
 889 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 890             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 891             "if (!$src1) $dst=memb(##$global+$offset)",
 892             []>,
 893             Requires<[HasV4T]>;
 894
 895 let neverHasSideEffects = 1, isPredicated = 1 in
 896 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 897             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 898             "if ($src1.new) $dst=memb(##$global+$offset)",
 899             []>,
 900             Requires<[HasV4T]>;
 901
 902 let neverHasSideEffects = 1, isPredicated = 1 in
 903 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 904             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 905             "if (!$src1.new) $dst=memb(##$global+$offset)",
 906             []>,
 907             Requires<[HasV4T]>;
 908
 909
 910 let isPredicable = 1, neverHasSideEffects = 1 in
 911 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
 912             (ins globaladdress:$global, u16Imm:$offset),
 913             "$dst=memub(#$global+$offset)",
 914             []>,
 915             Requires<[HasV4T]>;
 916
 917
 918 let neverHasSideEffects = 1, isPredicated = 1 in
 919 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 920             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 921             "if ($src1) $dst=memub(##$global+$offset)",
 922             []>,
 923             Requires<[HasV4T]>;
 924
 925 let neverHasSideEffects = 1, isPredicated = 1 in
 926 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 927             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 928             "if (!$src1) $dst=memub(##$global+$offset)",
 929             []>,
 930             Requires<[HasV4T]>;
 931
 932 let neverHasSideEffects = 1, isPredicated = 1 in
 933 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 934             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 935             "if ($src1.new) $dst=memub(##$global+$offset)",
 936             []>,
 937             Requires<[HasV4T]>;
 938
 939 let neverHasSideEffects = 1, isPredicated = 1 in
 940 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 941             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 942             "if (!$src1.new) $dst=memub(##$global+$offset)",
 943             []>,
 944             Requires<[HasV4T]>;
 945
 946
 947 let isPredicable = 1, neverHasSideEffects = 1 in
 948 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
 949             (ins globaladdress:$global, u16Imm:$offset),
 950             "$dst=memh(#$global+$offset)",
 951             []>,
 952             Requires<[HasV4T]>;
 953
 954
 955 let neverHasSideEffects = 1, isPredicated = 1 in
 956 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 957             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 958             "if ($src1) $dst=memh(##$global+$offset)",
 959             []>,
 960             Requires<[HasV4T]>;
 961
 962 let neverHasSideEffects = 1, isPredicated = 1 in
 963 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 964             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 965             "if (!$src1) $dst=memh(##$global+$offset)",
 966             []>,
 967             Requires<[HasV4T]>;
 968
 969 let neverHasSideEffects = 1, isPredicated = 1 in
 970 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 971             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 972             "if ($src1.new) $dst=memh(##$global+$offset)",
 973             []>,
 974             Requires<[HasV4T]>;
 975
 976 let neverHasSideEffects = 1, isPredicated = 1 in
 977 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 978             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 979             "if (!$src1.new) $dst=memh(##$global+$offset)",
 980             []>,
 981             Requires<[HasV4T]>;
 982
 983
 984 let isPredicable = 1, neverHasSideEffects = 1 in
 985 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
 986             (ins globaladdress:$global, u16Imm:$offset),
 987             "$dst=memuh(#$global+$offset)",
 988             []>,
 989             Requires<[HasV4T]>;
 990
 991 let neverHasSideEffects = 1, isPredicated = 1 in
 992 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 993             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 994             "if ($src1) $dst=memuh(##$global+$offset)",
 995             []>,
 996             Requires<[HasV4T]>;
 997
 998 let neverHasSideEffects = 1, isPredicated = 1 in
 999 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1000             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1001             "if (!$src1) $dst=memuh(##$global+$offset)",
1002             []>,
1003             Requires<[HasV4T]>;
1004
1005 let neverHasSideEffects = 1, isPredicated = 1 in
1006 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1007             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1008             "if ($src1.new) $dst=memuh(##$global+$offset)",
1009             []>,
1010             Requires<[HasV4T]>;
1011
1012 let neverHasSideEffects = 1, isPredicated = 1 in
1013 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1014             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1015             "if (!$src1.new) $dst=memuh(##$global+$offset)",
1016             []>,
1017             Requires<[HasV4T]>;
1018
1019 let isPredicable = 1, neverHasSideEffects = 1 in
1020 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1021             (ins globaladdress:$global, u16Imm:$offset),
1022             "$dst=memw(#$global+$offset)",
1023             []>,
1024             Requires<[HasV4T]>;
1025
1026
1027 let neverHasSideEffects = 1, isPredicated = 1 in
1028 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1029             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1030             "if ($src1) $dst=memw(##$global+$offset)",
1031             []>,
1032             Requires<[HasV4T]>;
1033
1034 let neverHasSideEffects = 1, isPredicated = 1 in
1035 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1036             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1037             "if (!$src1) $dst=memw(##$global+$offset)",
1038             []>,
1039             Requires<[HasV4T]>;
1040
1041
1042 let neverHasSideEffects = 1, isPredicated = 1 in
1043 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1044             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1045             "if ($src1.new) $dst=memw(##$global+$offset)",
1046             []>,
1047             Requires<[HasV4T]>;
1048
1049 let neverHasSideEffects = 1, isPredicated = 1 in
1050 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1051             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1052             "if (!$src1.new) $dst=memw(##$global+$offset)",
1053             []>,
1054             Requires<[HasV4T]>;
1055
1056
1057 let isPredicable = 1, neverHasSideEffects = 1 in
1058 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1059             (ins globaladdress:$global),
1060             "$dst=memd(#$global)",
1061             []>,
1062             Requires<[HasV4T]>;
1063
1064 // if (Pv) Rtt=memd(##global)
1065 let neverHasSideEffects = 1, isPredicated = 1 in
1066 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1067             (ins PredRegs:$src1, globaladdress:$global),
1068             "if ($src1) $dst=memd(##$global)",
1069             []>,
1070             Requires<[HasV4T]>;
1071
1072
1073 // if (!Pv) Rtt=memd(##global)
1074 let neverHasSideEffects = 1, isPredicated = 1 in
1075 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1076             (ins PredRegs:$src1, globaladdress:$global),
1077             "if (!$src1) $dst=memd(##$global)",
1078             []>,
1079             Requires<[HasV4T]>;
1080
1081 // if (Pv) Rtt=memd(##global)
1082 let neverHasSideEffects = 1, isPredicated = 1 in
1083 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1084             (ins PredRegs:$src1, globaladdress:$global),
1085             "if ($src1.new) $dst=memd(##$global)",
1086             []>,
1087             Requires<[HasV4T]>;
1088
1089
1090 // if (!Pv) Rtt=memd(##global)
1091 let neverHasSideEffects = 1, isPredicated = 1 in
1092 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1093             (ins PredRegs:$src1, globaladdress:$global),
1094             "if (!$src1.new) $dst=memd(##$global)",
1095             []>,
1096             Requires<[HasV4T]>;
1097
1098 let isPredicable = 1, neverHasSideEffects = 1 in
1099 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1100             (ins globaladdress:$global),
1101             "$dst=memb(#$global)",
1102             []>,
1103             Requires<[HasV4T]>;
1104
1105 // if (Pv) Rt=memb(##global)
1106 let neverHasSideEffects = 1, isPredicated = 1 in
1107 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1108             (ins PredRegs:$src1, globaladdress:$global),
1109             "if ($src1) $dst=memb(##$global)",
1110             []>,
1111             Requires<[HasV4T]>;
1112
1113 // if (!Pv) Rt=memb(##global)
1114 let neverHasSideEffects = 1, isPredicated = 1 in
1115 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1116             (ins PredRegs:$src1, globaladdress:$global),
1117             "if (!$src1) $dst=memb(##$global)",
1118             []>,
1119             Requires<[HasV4T]>;
1120
1121 // if (Pv) Rt=memb(##global)
1122 let neverHasSideEffects = 1, isPredicated = 1 in
1123 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1124             (ins PredRegs:$src1, globaladdress:$global),
1125             "if ($src1.new) $dst=memb(##$global)",
1126             []>,
1127             Requires<[HasV4T]>;
1128
1129 // if (!Pv) Rt=memb(##global)
1130 let neverHasSideEffects = 1, isPredicated = 1 in
1131 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1132             (ins PredRegs:$src1, globaladdress:$global),
1133             "if (!$src1.new) $dst=memb(##$global)",
1134             []>,
1135             Requires<[HasV4T]>;
1136
1137 let isPredicable = 1, neverHasSideEffects = 1 in
1138 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1139             (ins globaladdress:$global),
1140             "$dst=memub(#$global)",
1141             []>,
1142             Requires<[HasV4T]>;
1143
1144 // if (Pv) Rt=memub(##global)
1145 let neverHasSideEffects = 1, isPredicated = 1 in
1146 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1147             (ins PredRegs:$src1, globaladdress:$global),
1148             "if ($src1) $dst=memub(##$global)",
1149             []>,
1150             Requires<[HasV4T]>;
1151
1152
1153 // if (!Pv) Rt=memub(##global)
1154 let neverHasSideEffects = 1, isPredicated = 1 in
1155 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1156             (ins PredRegs:$src1, globaladdress:$global),
1157             "if (!$src1) $dst=memub(##$global)",
1158             []>,
1159             Requires<[HasV4T]>;
1160
1161 // if (Pv) Rt=memub(##global)
1162 let neverHasSideEffects = 1, isPredicated = 1 in
1163 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1164             (ins PredRegs:$src1, globaladdress:$global),
1165             "if ($src1.new) $dst=memub(##$global)",
1166             []>,
1167             Requires<[HasV4T]>;
1168
1169
1170 // if (!Pv) Rt=memub(##global)
1171 let neverHasSideEffects = 1, isPredicated = 1 in
1172 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1173             (ins PredRegs:$src1, globaladdress:$global),
1174             "if (!$src1.new) $dst=memub(##$global)",
1175             []>,
1176             Requires<[HasV4T]>;
1177
1178 let isPredicable = 1, neverHasSideEffects = 1 in
1179 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1180             (ins globaladdress:$global),
1181             "$dst=memh(#$global)",
1182             []>,
1183             Requires<[HasV4T]>;
1184
1185 // if (Pv) Rt=memh(##global)
1186 let neverHasSideEffects = 1, isPredicated = 1 in
1187 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1188             (ins PredRegs:$src1, globaladdress:$global),
1189             "if ($src1) $dst=memh(##$global)",
1190             []>,
1191             Requires<[HasV4T]>;
1192
1193 // if (!Pv) Rt=memh(##global)
1194 let neverHasSideEffects = 1, isPredicated = 1 in
1195 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1196             (ins PredRegs:$src1, globaladdress:$global),
1197             "if (!$src1) $dst=memh(##$global)",
1198             []>,
1199             Requires<[HasV4T]>;
1200
1201 // if (Pv) Rt=memh(##global)
1202 let neverHasSideEffects = 1, isPredicated = 1 in
1203 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1204             (ins PredRegs:$src1, globaladdress:$global),
1205             "if ($src1.new) $dst=memh(##$global)",
1206             []>,
1207             Requires<[HasV4T]>;
1208
1209 // if (!Pv) Rt=memh(##global)
1210 let neverHasSideEffects = 1, isPredicated = 1 in
1211 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1212             (ins PredRegs:$src1, globaladdress:$global),
1213             "if (!$src1.new) $dst=memh(##$global)",
1214             []>,
1215             Requires<[HasV4T]>;
1216
1217 let isPredicable = 1, neverHasSideEffects = 1 in
1218 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1219             (ins globaladdress:$global),
1220             "$dst=memuh(#$global)",
1221             []>,
1222             Requires<[HasV4T]>;
1223
1224 // if (Pv) Rt=memuh(##global)
1225 let neverHasSideEffects = 1, isPredicated = 1 in
1226 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1227             (ins PredRegs:$src1, globaladdress:$global),
1228             "if ($src1) $dst=memuh(##$global)",
1229             []>,
1230             Requires<[HasV4T]>;
1231
1232 // if (!Pv) Rt=memuh(##global)
1233 let neverHasSideEffects = 1, isPredicated = 1 in
1234 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1235             (ins PredRegs:$src1, globaladdress:$global),
1236             "if (!$src1) $dst=memuh(##$global)",
1237             []>,
1238             Requires<[HasV4T]>;
1239
1240 // if (Pv) Rt=memuh(##global)
1241 let neverHasSideEffects = 1, isPredicated = 1 in
1242 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1243             (ins PredRegs:$src1, globaladdress:$global),
1244             "if ($src1.new) $dst=memuh(##$global)",
1245             []>,
1246             Requires<[HasV4T]>;
1247
1248 // if (!Pv) Rt=memuh(##global)
1249 let neverHasSideEffects = 1, isPredicated = 1 in
1250 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1251             (ins PredRegs:$src1, globaladdress:$global),
1252             "if (!$src1.new) $dst=memuh(##$global)",
1253             []>,
1254             Requires<[HasV4T]>;
1255
1256 let isPredicable = 1, neverHasSideEffects = 1 in
1257 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1258             (ins globaladdress:$global),
1259             "$dst=memw(#$global)",
1260             []>,
1261             Requires<[HasV4T]>;
1262
1263 // if (Pv) Rt=memw(##global)
1264 let neverHasSideEffects = 1, isPredicated = 1 in
1265 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1266             (ins PredRegs:$src1, globaladdress:$global),
1267             "if ($src1) $dst=memw(##$global)",
1268             []>,
1269             Requires<[HasV4T]>;
1270
1271
1272 // if (!Pv) Rt=memw(##global)
1273 let neverHasSideEffects = 1, isPredicated = 1 in
1274 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1275             (ins PredRegs:$src1, globaladdress:$global),
1276             "if (!$src1) $dst=memw(##$global)",
1277             []>,
1278             Requires<[HasV4T]>;
1279
1280 // if (Pv) Rt=memw(##global)
1281 let neverHasSideEffects = 1, isPredicated = 1 in
1282 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1283             (ins PredRegs:$src1, globaladdress:$global),
1284             "if ($src1.new) $dst=memw(##$global)",
1285             []>,
1286             Requires<[HasV4T]>;
1287
1288
1289 // if (!Pv) Rt=memw(##global)
1290 let neverHasSideEffects = 1, isPredicated = 1 in
1291 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1292             (ins PredRegs:$src1, globaladdress:$global),
1293             "if (!$src1.new) $dst=memw(##$global)",
1294             []>,
1295             Requires<[HasV4T]>;
1296
1297
1298
1299 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1300            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1301             Requires<[HasV4T]>;
1302
1303 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1304            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1305             Requires<[HasV4T]>;
1306
1307 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1308            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1309             Requires<[HasV4T]>;
1310
1311 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1312            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1313             Requires<[HasV4T]>;
1314
1315 // Map from load(globaladdress) -> memw(#foo + 0)
1316 let AddedComplexity = 100 in
1317 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1318            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1319             Requires<[HasV4T]>;
1320
1321 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1322 let AddedComplexity = 100 in
1323 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1324            (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1325            Requires<[HasV4T]>;
1326
1327 // When the Interprocedural Global Variable optimizer realizes that a certain
1328 // global variable takes only two constant values, it shrinks the global to
1329 // a boolean. Catch those loads here in the following 3 patterns.
1330 let AddedComplexity = 100 in
1331 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1332            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1333             Requires<[HasV4T]>;
1334
1335 let AddedComplexity = 100 in
1336 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1337            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1338             Requires<[HasV4T]>;
1339
1340 // Map from load(globaladdress) -> memb(#foo)
1341 let AddedComplexity = 100 in
1342 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1343            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1344             Requires<[HasV4T]>;
1345
1346 // Map from load(globaladdress) -> memb(#foo)
1347 let AddedComplexity = 100 in
1348 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1349            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1350             Requires<[HasV4T]>;
1351
1352 let AddedComplexity = 100 in
1353 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1354            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1355             Requires<[HasV4T]>;
1356
1357 // Map from load(globaladdress) -> memub(#foo)
1358 let AddedComplexity = 100 in
1359 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1360            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1361             Requires<[HasV4T]>;
1362
1363 // Map from load(globaladdress) -> memh(#foo)
1364 let AddedComplexity = 100 in
1365 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1366            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1367             Requires<[HasV4T]>;
1368
1369 // Map from load(globaladdress) -> memh(#foo)
1370 let AddedComplexity = 100 in
1371 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1372            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1373             Requires<[HasV4T]>;
1374
1375 // Map from load(globaladdress) -> memuh(#foo)
1376 let AddedComplexity = 100 in
1377 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1378            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1379             Requires<[HasV4T]>;
1380
1381 // Map from load(globaladdress) -> memw(#foo)
1382 let AddedComplexity = 100 in
1383 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1384            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1385             Requires<[HasV4T]>;
1386
1387 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1388                                 u16ImmPred:$offset)),
1389            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1390            Requires<[HasV4T]>;
1391
1392 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1393                                 u16ImmPred:$offset)),
1394            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1395             Requires<[HasV4T]>;
1396
1397 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1398                                 u16ImmPred:$offset)),
1399            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1400             Requires<[HasV4T]>;
1401
1402 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1403                                u16ImmPred:$offset)),
1404            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1405            Requires<[HasV4T]>;
1406
1407 // Map from load(globaladdress + x) -> memd(#foo + x)
1408 let AddedComplexity = 100 in
1409 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1410                            u16ImmPred:$offset))),
1411            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1412            Requires<[HasV4T]>;
1413
1414 // Map from load(globaladdress + x) -> memb(#foo + x)
1415 let AddedComplexity = 100 in
1416 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1417                            u16ImmPred:$offset))),
1418            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1419            Requires<[HasV4T]>;
1420
1421 // Map from load(globaladdress + x) -> memb(#foo + x)
1422 let AddedComplexity = 100 in
1423 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1424                             u16ImmPred:$offset))),
1425            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1426            Requires<[HasV4T]>;
1427
1428 // Map from load(globaladdress + x) -> memub(#foo + x)
1429 let AddedComplexity = 100 in
1430 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1431                             u16ImmPred:$offset))),
1432            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1433            Requires<[HasV4T]>;
1434
1435 // Map from load(globaladdress + x) -> memuh(#foo + x)
1436 let AddedComplexity = 100 in
1437 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1438                             u16ImmPred:$offset))),
1439            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1440             Requires<[HasV4T]>;
1441
1442 // Map from load(globaladdress + x) -> memh(#foo + x)
1443 let AddedComplexity = 100 in
1444 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1445                              u16ImmPred:$offset))),
1446            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1447            Requires<[HasV4T]>;
1448
1449
1450 // Map from load(globaladdress + x) -> memuh(#foo + x)
1451 let AddedComplexity = 100 in
1452 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1453                              u16ImmPred:$offset))),
1454            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1455             Requires<[HasV4T]>;
1456
1457 // Map from load(globaladdress + x) -> memw(#foo + x)
1458 let AddedComplexity = 100 in
1459 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1460                       u16ImmPred:$offset))),
1461            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1462             Requires<[HasV4T]>;
1463
1464
1465 //===----------------------------------------------------------------------===//
1466 // LD -
1467 //===----------------------------------------------------------------------===//
1468
1469 //===----------------------------------------------------------------------===//
1470 // ST +
1471 //===----------------------------------------------------------------------===//
1472 ///
1473 /// Assumptions::: ****** DO NOT IGNORE ********
1474 /// 1. Make sure that in post increment store, the zero'th operand is always the
1475 ///    post increment operand.
1476 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1477 ///    last operand.
1478 ///
1479
1480 // memd(Re=#U6)=Rtt
1481 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1482             (ins DoubleRegs:$src1, u6Imm:$src2),
1483             "memd($dst1=#$src2) = $src1",
1484             []>,
1485             Requires<[HasV4T]>;
1486
1487 // memb(Re=#U6)=Rs
1488 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1489             (ins IntRegs:$src1, u6Imm:$src2),
1490             "memb($dst1=#$src2) = $src1",
1491             []>,
1492             Requires<[HasV4T]>;
1493
1494 // memh(Re=#U6)=Rs
1495 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1496             (ins IntRegs:$src1, u6Imm:$src2),
1497             "memh($dst1=#$src2) = $src1",
1498             []>,
1499             Requires<[HasV4T]>;
1500
1501 // memw(Re=#U6)=Rs
1502 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1503             (ins IntRegs:$src1, u6Imm:$src2),
1504             "memw($dst1=#$src2) = $src1",
1505             []>,
1506             Requires<[HasV4T]>;
1507
1508 // memd(Re=#U6)=Rtt
1509 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1510             (ins DoubleRegs:$src1, globaladdress:$src2),
1511             "memd($dst1=##$src2) = $src1",
1512             []>,
1513             Requires<[HasV4T]>;
1514
1515 // memb(Re=#U6)=Rs
1516 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1517             (ins IntRegs:$src1, globaladdress:$src2),
1518             "memb($dst1=##$src2) = $src1",
1519             []>,
1520             Requires<[HasV4T]>;
1521
1522 // memh(Re=#U6)=Rs
1523 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1524             (ins IntRegs:$src1, globaladdress:$src2),
1525             "memh($dst1=##$src2) = $src1",
1526             []>,
1527             Requires<[HasV4T]>;
1528
1529 // memw(Re=#U6)=Rs
1530 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1531             (ins IntRegs:$src1, globaladdress:$src2),
1532             "memw($dst1=##$src2) = $src1",
1533             []>,
1534             Requires<[HasV4T]>;
1535
1536
1537 // multiclass for store instructions with base + register offset addressing
1538 // mode
1539 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1540                              bit isPredNew> {
1541   let PNewValue = #!if(isPredNew, "new", "") in
1542   def #NAME# : STInst2<(outs),
1543             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1544                  RC:$src5),
1545             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1546             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
1547             []>,
1548             Requires<[HasV4T]>;
1549 }
1550
1551 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1552   let PredSense = #!if(PredNot, "false", "true") in {
1553     defm _c#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
1554     // Predicate new
1555     defm _cdn#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
1556   }
1557 }
1558
1559 let isNVStorable = 1 in
1560 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
1561   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1562     let isPredicable = 1 in
1563     def #NAME#_V4 : STInst2<(outs),
1564             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1565             #mnemonic#"($src1+$src2<<#$src3) = $src4",
1566             []>,
1567             Requires<[HasV4T]>;
1568
1569     let isPredicated = 1 in {
1570       defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
1571       defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
1572     }
1573   }
1574 }
1575
1576 // multiclass for new-value store instructions with base + register offset
1577 // addressing mode.
1578 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
1579                              bit isPredNew> {
1580   let PNewValue = #!if(isPredNew, "new", "") in
1581   def #NAME#_nv_V4 : NVInst_V4<(outs),
1582             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1583                  RC:$src5),
1584             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1585             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
1586             []>,
1587             Requires<[HasV4T]>;
1588 }
1589
1590 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
1591   let PredSense = #!if(PredNot, "false", "true") in {
1592     defm _c#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
1593     // Predicate new
1594     defm _cdn#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
1595   }
1596 }
1597
1598 let mayStore = 1, isNVStore = 1 in
1599 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
1600   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1601     let isPredicable = 1 in
1602     def #NAME#_nv_V4 : NVInst_V4<(outs),
1603             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1604             #mnemonic#"($src1+$src2<<#$src3) = $src4.new",
1605             []>,
1606             Requires<[HasV4T]>;
1607
1608     let isPredicated = 1 in {
1609       defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
1610       defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
1611     }
1612   }
1613 }
1614
1615 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
1616 validSubTargets = HasV4SubT in {
1617   defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
1618                           ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
1619
1620   defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
1621                           ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
1622
1623   defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
1624                           ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
1625
1626   let isNVStorable = 0 in
1627   defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
1628 }
1629
1630 let Predicates = [HasV4T], AddedComplexity = 10 in {
1631 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
1632                        (add IntRegs:$src1, (shl IntRegs:$src2,
1633                                                 u2ImmPred:$src3))),
1634           (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1635                                 u2ImmPred:$src3, IntRegs:$src4)>;
1636
1637 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
1638                         (add IntRegs:$src1, (shl IntRegs:$src2,
1639                                                  u2ImmPred:$src3))),
1640           (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1641                                 u2ImmPred:$src3, IntRegs:$src4)>;
1642
1643 def : Pat<(store (i32 IntRegs:$src4),
1644                  (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1645           (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1646                                 u2ImmPred:$src3, IntRegs:$src4)>;
1647
1648 def : Pat<(store (i64 DoubleRegs:$src4),
1649                 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1650           (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1651                                 u2ImmPred:$src3, DoubleRegs:$src4)>;
1652 }
1653
1654 // memd(Ru<<#u2+#U6)=Rtt
1655 let AddedComplexity = 10 in
1656 def STrid_shl_V4 : STInst<(outs),
1657             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1658             "memd($src1<<#$src2+#$src3) = $src4",
1659             [(store (i64 DoubleRegs:$src4),
1660                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1661                          u6ImmPred:$src3))]>,
1662             Requires<[HasV4T]>;
1663
1664 // memd(Rx++#s4:3)=Rtt
1665 // memd(Rx++#s4:3:circ(Mu))=Rtt
1666 // memd(Rx++I:circ(Mu))=Rtt
1667 // memd(Rx++Mu)=Rtt
1668 // memd(Rx++Mu:brev)=Rtt
1669 // memd(gp+#u16:3)=Rtt
1670
1671 // Store doubleword conditionally.
1672 // if ([!]Pv[.new]) memd(#u6)=Rtt
1673 // TODO: needs to be implemented.
1674
1675 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1676 // if (Pv) memd(Rx++#s4:3)=Rtt
1677 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1678 let AddedComplexity = 10, neverHasSideEffects = 1,
1679     isPredicated = 1 in
1680 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1681             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1682                  s4_3Imm:$offset),
1683             "if ($src1.new) memd($src3++#$offset) = $src2",
1684             [],
1685             "$src3 = $dst">,
1686             Requires<[HasV4T]>;
1687
1688 // if (!Pv) memd(Rx++#s4:3)=Rtt
1689 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1690 let AddedComplexity = 10, neverHasSideEffects = 1,
1691     isPredicated = 1 in
1692 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1693             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1694                  s4_3Imm:$offset),
1695             "if (!$src1.new) memd($src3++#$offset) = $src2",
1696             [],
1697             "$src3 = $dst">,
1698             Requires<[HasV4T]>;
1699
1700
1701 // multiclass for store instructions with base + immediate offset
1702 // addressing mode and immediate stored value.
1703 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
1704                         bit isPredNew> {
1705   let PNewValue = #!if(isPredNew, "new", "") in
1706   def #NAME# : STInst2<(outs),
1707             (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
1708             #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1709             ") ")#mnemonic#"($src2+#$src3) = #$src4",
1710             []>,
1711             Requires<[HasV4T]>;
1712 }
1713
1714 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
1715   let PredSense = #!if(PredNot, "false", "true") in {
1716     defm _c#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
1717     // Predicate new
1718     defm _cdn#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
1719   }
1720 }
1721
1722 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
1723 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
1724   let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1725     let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
1726     def #NAME#_V4 : STInst2<(outs),
1727             (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
1728             #mnemonic#"($src1+#$src2) = #$src3",
1729             []>,
1730             Requires<[HasV4T]>;
1731
1732     let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
1733       defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
1734       defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
1735     }
1736   }
1737 }
1738
1739 let addrMode = BaseImmOffset, InputType = "imm",
1740     validSubTargets = HasV4SubT in {
1741   defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel;
1742   defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel;
1743   defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel;
1744 }
1745
1746 let Predicates = [HasV4T], AddedComplexity = 10 in {
1747 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1748             (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1749
1750 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1751                                               u6_1ImmPred:$src2)),
1752             (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1753
1754 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1755             (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1756 }
1757
1758 let AddedComplexity = 6 in
1759 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1760            (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1761            Requires<[HasV4T]>;
1762
1763 // memb(Ru<<#u2+#U6)=Rt
1764 let AddedComplexity = 10 in
1765 def STrib_shl_V4 : STInst<(outs),
1766             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1767             "memb($src1<<#$src2+#$src3) = $src4",
1768             [(truncstorei8 (i32 IntRegs:$src4),
1769                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1770                                 u6ImmPred:$src3))]>,
1771             Requires<[HasV4T]>;
1772
1773 // memb(Rx++#s4:0:circ(Mu))=Rt
1774 // memb(Rx++I:circ(Mu))=Rt
1775 // memb(Rx++Mu)=Rt
1776 // memb(Rx++Mu:brev)=Rt
1777 // memb(gp+#u16:0)=Rt
1778
1779
1780 // Store byte conditionally.
1781 // if ([!]Pv[.new]) memb(#u6)=Rt
1782 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1783 // if (Pv) memb(Rx++#s4:0)=Rt
1784 // if (Pv.new) memb(Rx++#s4:0)=Rt
1785 let hasCtrlDep = 1,
1786     isPredicated = 1 in
1787 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1788             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1789             "if ($src1.new) memb($src3++#$offset) = $src2",
1790             [],"$src3 = $dst">,
1791             Requires<[HasV4T]>;
1792
1793 // if (!Pv) memb(Rx++#s4:0)=Rt
1794 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1795 let hasCtrlDep = 1,
1796     isPredicated = 1 in
1797 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1798             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1799             "if (!$src1.new) memb($src3++#$offset) = $src2",
1800             [],"$src3 = $dst">,
1801             Requires<[HasV4T]>;
1802
1803
1804 // Store halfword.
1805 // TODO: needs to be implemented
1806 // memh(Re=#U6)=Rt.H
1807 // memh(Rs+#s11:1)=Rt.H
1808 let AddedComplexity = 6 in
1809 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1810            (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1811            Requires<[HasV4T]>;
1812
1813 // memh(Rs+Ru<<#u2)=Rt.H
1814 // TODO: needs to be implemented.
1815
1816 // memh(Ru<<#u2+#U6)=Rt.H
1817 // memh(Ru<<#u2+#U6)=Rt
1818 let AddedComplexity = 10 in
1819 def STrih_shl_V4 : STInst<(outs),
1820             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1821             "memh($src1<<#$src2+#$src3) = $src4",
1822             [(truncstorei16 (i32 IntRegs:$src4),
1823                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1824                                  u6ImmPred:$src3))]>,
1825             Requires<[HasV4T]>;
1826
1827 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1828 // memh(Rx++#s4:1:circ(Mu))=Rt
1829 // memh(Rx++I:circ(Mu))=Rt.H
1830 // memh(Rx++I:circ(Mu))=Rt
1831 // memh(Rx++Mu)=Rt.H
1832 // memh(Rx++Mu)=Rt
1833 // memh(Rx++Mu:brev)=Rt.H
1834 // memh(Rx++Mu:brev)=Rt
1835 // memh(gp+#u16:1)=Rt
1836 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1837 // if ([!]Pv[.new]) memh(#u6)=Rt
1838
1839
1840 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1841 // TODO: needs to be implemented.
1842
1843 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1844 // TODO: Needs to be implemented.
1845
1846 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1847 // if (Pv) memh(Rx++#s4:1)=Rt
1848 // if (Pv.new) memh(Rx++#s4:1)=Rt
1849 let hasCtrlDep = 1,
1850     isPredicated = 1 in
1851 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1852             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1853             "if ($src1.new) memh($src3++#$offset) = $src2",
1854             [],"$src3 = $dst">,
1855             Requires<[HasV4T]>;
1856
1857 // if (!Pv) memh(Rx++#s4:1)=Rt
1858 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1859 let hasCtrlDep = 1,
1860     isPredicated = 1 in
1861 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1862             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1863             "if (!$src1.new) memh($src3++#$offset) = $src2",
1864             [],"$src3 = $dst">,
1865             Requires<[HasV4T]>;
1866
1867
1868 // Store word.
1869 // memw(Re=#U6)=Rt
1870 // TODO: Needs to be implemented.
1871
1872 // Store predicate:
1873 let neverHasSideEffects = 1 in
1874 def STriw_pred_V4 : STInst2<(outs),
1875             (ins MEMri:$addr, PredRegs:$src1),
1876             "Error; should not emit",
1877             []>,
1878             Requires<[HasV4T]>;
1879
1880 let AddedComplexity = 6 in
1881 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1882            (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1883            Requires<[HasV4T]>;
1884
1885 // memw(Ru<<#u2+#U6)=Rt
1886 let AddedComplexity = 10 in
1887 def STriw_shl_V4 : STInst<(outs),
1888             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1889             "memw($src1<<#$src2+#$src3) = $src4",
1890             [(store (i32 IntRegs:$src4),
1891                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1892                               u6ImmPred:$src3))]>,
1893             Requires<[HasV4T]>;
1894
1895 // memw(Rx++#s4:2)=Rt
1896 // memw(Rx++#s4:2:circ(Mu))=Rt
1897 // memw(Rx++I:circ(Mu))=Rt
1898 // memw(Rx++Mu)=Rt
1899 // memw(Rx++Mu:brev)=Rt
1900 // memw(gp+#u16:2)=Rt
1901
1902
1903 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
1904 // if (Pv) memw(Rx++#s4:2)=Rt
1905 // if (Pv.new) memw(Rx++#s4:2)=Rt
1906 let hasCtrlDep = 1,
1907     isPredicated = 1 in
1908 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1909             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1910             "if ($src1.new) memw($src3++#$offset) = $src2",
1911             [],"$src3 = $dst">,
1912             Requires<[HasV4T]>;
1913
1914 // if (!Pv) memw(Rx++#s4:2)=Rt
1915 // if (!Pv.new) memw(Rx++#s4:2)=Rt
1916 let hasCtrlDep = 1,
1917     isPredicated = 1 in
1918 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1919             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1920             "if (!$src1.new) memw($src3++#$offset) = $src2",
1921             [],"$src3 = $dst">,
1922             Requires<[HasV4T]>;
1923
1924
1925 /// store to global address
1926
1927 let isPredicable = 1, neverHasSideEffects = 1 in
1928 def STrid_GP_V4 : STInst2<(outs),
1929             (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1930             "memd(#$global+$offset) = $src",
1931             []>,
1932             Requires<[HasV4T]>;
1933
1934 let neverHasSideEffects = 1, isPredicated = 1 in
1935 def STrid_GP_cPt_V4 : STInst2<(outs),
1936             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1937                                                         DoubleRegs:$src2),
1938             "if ($src1) memd(##$global+$offset) = $src2",
1939             []>,
1940             Requires<[HasV4T]>;
1941
1942 let neverHasSideEffects = 1, isPredicated = 1 in
1943 def STrid_GP_cNotPt_V4 : STInst2<(outs),
1944             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1945                                                         DoubleRegs:$src2),
1946             "if (!$src1) memd(##$global+$offset) = $src2",
1947             []>,
1948             Requires<[HasV4T]>;
1949
1950 let neverHasSideEffects = 1, isPredicated = 1 in
1951 def STrid_GP_cdnPt_V4 : STInst2<(outs),
1952             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1953                                                         DoubleRegs:$src2),
1954             "if ($src1.new) memd(##$global+$offset) = $src2",
1955             []>,
1956             Requires<[HasV4T]>;
1957
1958 let neverHasSideEffects = 1, isPredicated = 1 in
1959 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
1960             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1961                                                         DoubleRegs:$src2),
1962             "if (!$src1.new) memd(##$global+$offset) = $src2",
1963             []>,
1964             Requires<[HasV4T]>;
1965
1966 let isPredicable = 1, neverHasSideEffects = 1 in
1967 def STrib_GP_V4 : STInst2<(outs),
1968             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1969             "memb(#$global+$offset) = $src",
1970             []>,
1971             Requires<[HasV4T]>;
1972
1973 let neverHasSideEffects = 1, isPredicated = 1 in
1974 def STrib_GP_cPt_V4 : STInst2<(outs),
1975             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1976                                                         IntRegs:$src2),
1977             "if ($src1) memb(##$global+$offset) = $src2",
1978             []>,
1979             Requires<[HasV4T]>;
1980
1981 let neverHasSideEffects = 1, isPredicated = 1 in
1982 def STrib_GP_cNotPt_V4 : STInst2<(outs),
1983             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1984                                                         IntRegs:$src2),
1985             "if (!$src1) memb(##$global+$offset) = $src2",
1986             []>,
1987             Requires<[HasV4T]>;
1988
1989 let neverHasSideEffects = 1, isPredicated = 1 in
1990 def STrib_GP_cdnPt_V4 : STInst2<(outs),
1991             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1992                                                         IntRegs:$src2),
1993             "if ($src1.new) memb(##$global+$offset) = $src2",
1994             []>,
1995             Requires<[HasV4T]>;
1996
1997 let neverHasSideEffects = 1, isPredicated = 1 in
1998 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
1999             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2000                                                         IntRegs:$src2),
2001             "if (!$src1.new) memb(##$global+$offset) = $src2",
2002             []>,
2003             Requires<[HasV4T]>;
2004
2005 let isPredicable = 1, neverHasSideEffects = 1 in
2006 def STrih_GP_V4 : STInst2<(outs),
2007             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2008             "memh(#$global+$offset) = $src",
2009             []>,
2010             Requires<[HasV4T]>;
2011
2012 let neverHasSideEffects = 1, isPredicated = 1 in
2013 def STrih_GP_cPt_V4 : STInst2<(outs),
2014             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2015                                                         IntRegs:$src2),
2016             "if ($src1) memh(##$global+$offset) = $src2",
2017             []>,
2018             Requires<[HasV4T]>;
2019
2020 let neverHasSideEffects = 1, isPredicated = 1 in
2021 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2022             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2023                                                         IntRegs:$src2),
2024             "if (!$src1) memh(##$global+$offset) = $src2",
2025             []>,
2026             Requires<[HasV4T]>;
2027
2028 let neverHasSideEffects = 1, isPredicated = 1 in
2029 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2030             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2031                                                         IntRegs:$src2),
2032             "if ($src1.new) memh(##$global+$offset) = $src2",
2033             []>,
2034             Requires<[HasV4T]>;
2035
2036 let neverHasSideEffects = 1, isPredicated = 1 in
2037 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2038             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2039                                                         IntRegs:$src2),
2040             "if (!$src1.new) memh(##$global+$offset) = $src2",
2041             []>,
2042             Requires<[HasV4T]>;
2043
2044 let isPredicable = 1, neverHasSideEffects = 1 in
2045 def STriw_GP_V4 : STInst2<(outs),
2046             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2047             "memw(#$global+$offset) = $src",
2048             []>,
2049             Requires<[HasV4T]>;
2050
2051 let neverHasSideEffects = 1, isPredicated = 1 in
2052 def STriw_GP_cPt_V4 : STInst2<(outs),
2053             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2054                                                         IntRegs:$src2),
2055             "if ($src1) memw(##$global+$offset) = $src2",
2056             []>,
2057             Requires<[HasV4T]>;
2058
2059 let neverHasSideEffects = 1, isPredicated = 1 in
2060 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2061             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2062                                                         IntRegs:$src2),
2063             "if (!$src1) memw(##$global+$offset) = $src2",
2064             []>,
2065             Requires<[HasV4T]>;
2066
2067 let neverHasSideEffects = 1, isPredicated = 1 in
2068 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2069             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2070                                                         IntRegs:$src2),
2071             "if ($src1.new) memw(##$global+$offset) = $src2",
2072             []>,
2073             Requires<[HasV4T]>;
2074
2075 let neverHasSideEffects = 1, isPredicated = 1 in
2076 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2077             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2078                                                         IntRegs:$src2),
2079             "if (!$src1.new) memw(##$global+$offset) = $src2",
2080             []>,
2081             Requires<[HasV4T]>;
2082
2083 // memd(#global)=Rtt
2084 let isPredicable = 1, neverHasSideEffects = 1 in
2085 def STd_GP_V4 : STInst2<(outs),
2086             (ins globaladdress:$global, DoubleRegs:$src),
2087             "memd(#$global) = $src",
2088             []>,
2089             Requires<[HasV4T]>;
2090
2091 // if (Pv) memd(##global) = Rtt
2092 let neverHasSideEffects = 1, isPredicated = 1 in
2093 def STd_GP_cPt_V4 : STInst2<(outs),
2094             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2095             "if ($src1) memd(##$global) = $src2",
2096             []>,
2097             Requires<[HasV4T]>;
2098
2099 // if (!Pv) memd(##global) = Rtt
2100 let neverHasSideEffects = 1, isPredicated = 1 in
2101 def STd_GP_cNotPt_V4 : STInst2<(outs),
2102             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2103             "if (!$src1) memd(##$global) = $src2",
2104             []>,
2105               Requires<[HasV4T]>;
2106
2107 // if (Pv) memd(##global) = Rtt
2108 let neverHasSideEffects = 1, isPredicated = 1 in
2109 def STd_GP_cdnPt_V4 : STInst2<(outs),
2110             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2111             "if ($src1.new) memd(##$global) = $src2",
2112             []>,
2113               Requires<[HasV4T]>;
2114
2115 // if (!Pv) memd(##global) = Rtt
2116 let neverHasSideEffects = 1, isPredicated = 1 in
2117 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2118             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2119             "if (!$src1.new) memd(##$global) = $src2",
2120             []>,
2121             Requires<[HasV4T]>;
2122
2123 // memb(#global)=Rt
2124 let isPredicable = 1, neverHasSideEffects = 1 in
2125 def STb_GP_V4 : STInst2<(outs),
2126             (ins globaladdress:$global, IntRegs:$src),
2127             "memb(#$global) = $src",
2128             []>,
2129             Requires<[HasV4T]>;
2130
2131 // if (Pv) memb(##global) = Rt
2132 let neverHasSideEffects = 1, isPredicated = 1 in
2133 def STb_GP_cPt_V4 : STInst2<(outs),
2134             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2135             "if ($src1) memb(##$global) = $src2",
2136               []>,
2137               Requires<[HasV4T]>;
2138
2139 // if (!Pv) memb(##global) = Rt
2140 let neverHasSideEffects = 1, isPredicated = 1 in
2141 def STb_GP_cNotPt_V4 : STInst2<(outs),
2142             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2143             "if (!$src1) memb(##$global) = $src2",
2144               []>,
2145               Requires<[HasV4T]>;
2146
2147 // if (Pv) memb(##global) = Rt
2148 let neverHasSideEffects = 1, isPredicated = 1 in
2149 def STb_GP_cdnPt_V4 : STInst2<(outs),
2150             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2151             "if ($src1.new) memb(##$global) = $src2",
2152               []>,
2153               Requires<[HasV4T]>;
2154
2155 // if (!Pv) memb(##global) = Rt
2156 let neverHasSideEffects = 1, isPredicated = 1 in
2157 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2158             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2159             "if (!$src1.new) memb(##$global) = $src2",
2160               []>,
2161               Requires<[HasV4T]>;
2162
2163 // memh(#global)=Rt
2164 let isPredicable = 1, neverHasSideEffects = 1 in
2165 def STh_GP_V4 : STInst2<(outs),
2166             (ins globaladdress:$global, IntRegs:$src),
2167             "memh(#$global) = $src",
2168             []>,
2169             Requires<[HasV4T]>;
2170
2171 // if (Pv) memh(##global) = Rt
2172 let neverHasSideEffects = 1, isPredicated = 1 in
2173 def STh_GP_cPt_V4 : STInst2<(outs),
2174             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2175             "if ($src1) memh(##$global) = $src2",
2176               []>,
2177               Requires<[HasV4T]>;
2178
2179 // if (!Pv) memh(##global) = Rt
2180 let neverHasSideEffects = 1, isPredicated = 1 in
2181 def STh_GP_cNotPt_V4 : STInst2<(outs),
2182             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2183             "if (!$src1) memh(##$global) = $src2",
2184               []>,
2185               Requires<[HasV4T]>;
2186
2187 // if (Pv) memh(##global) = Rt
2188 let neverHasSideEffects = 1, isPredicated = 1 in
2189 def STh_GP_cdnPt_V4 : STInst2<(outs),
2190             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2191             "if ($src1.new) memh(##$global) = $src2",
2192               []>,
2193               Requires<[HasV4T]>;
2194
2195 // if (!Pv) memh(##global) = Rt
2196 let neverHasSideEffects = 1, isPredicated = 1 in
2197 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2198             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2199             "if (!$src1.new) memh(##$global) = $src2",
2200               []>,
2201               Requires<[HasV4T]>;
2202
2203 // memw(#global)=Rt
2204 let isPredicable = 1, neverHasSideEffects = 1 in
2205 def STw_GP_V4 : STInst2<(outs),
2206             (ins globaladdress:$global, IntRegs:$src),
2207             "memw(#$global) = $src",
2208               []>,
2209               Requires<[HasV4T]>;
2210
2211 // if (Pv) memw(##global) = Rt
2212 let neverHasSideEffects = 1, isPredicated = 1 in
2213 def STw_GP_cPt_V4 : STInst2<(outs),
2214             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2215             "if ($src1) memw(##$global) = $src2",
2216               []>,
2217               Requires<[HasV4T]>;
2218
2219 // if (!Pv) memw(##global) = Rt
2220 let neverHasSideEffects = 1, isPredicated = 1 in
2221 def STw_GP_cNotPt_V4 : STInst2<(outs),
2222             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2223             "if (!$src1) memw(##$global) = $src2",
2224               []>,
2225               Requires<[HasV4T]>;
2226
2227 // if (Pv) memw(##global) = Rt
2228 let neverHasSideEffects = 1, isPredicated = 1 in
2229 def STw_GP_cdnPt_V4 : STInst2<(outs),
2230             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2231             "if ($src1.new) memw(##$global) = $src2",
2232               []>,
2233               Requires<[HasV4T]>;
2234
2235 // if (!Pv) memw(##global) = Rt
2236 let neverHasSideEffects = 1, isPredicated = 1 in
2237 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2238             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2239             "if (!$src1.new) memw(##$global) = $src2",
2240             []>,
2241               Requires<[HasV4T]>;
2242
2243 // 64 bit atomic store
2244 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2245                             (i64 DoubleRegs:$src1)),
2246            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2247            Requires<[HasV4T]>;
2248
2249 // Map from store(globaladdress) -> memd(#foo)
2250 let AddedComplexity = 100 in
2251 def : Pat <(store (i64 DoubleRegs:$src1),
2252                   (HexagonCONST32_GP tglobaladdr:$global)),
2253            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2254            Requires<[HasV4T]>;
2255
2256 // 8 bit atomic store
2257 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2258                             (i32 IntRegs:$src1)),
2259             (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2260               Requires<[HasV4T]>;
2261
2262 // Map from store(globaladdress) -> memb(#foo)
2263 let AddedComplexity = 100 in
2264 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2265           (HexagonCONST32_GP tglobaladdr:$global)),
2266           (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2267           Requires<[HasV4T]>;
2268
2269 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2270 //       to "r0 = 1; memw(#foo) = r0"
2271 let AddedComplexity = 100 in
2272 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2273           (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2274           Requires<[HasV4T]>;
2275
2276 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2277                            (i32 IntRegs:$src1)),
2278           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2279           Requires<[HasV4T]>;
2280
2281 // Map from store(globaladdress) -> memh(#foo)
2282 let AddedComplexity = 100 in
2283 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2284                          (HexagonCONST32_GP tglobaladdr:$global)),
2285           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2286           Requires<[HasV4T]>;
2287
2288 // 32 bit atomic store
2289 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2290                            (i32 IntRegs:$src1)),
2291           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2292           Requires<[HasV4T]>;
2293
2294 // Map from store(globaladdress) -> memw(#foo)
2295 let AddedComplexity = 100 in
2296 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2297           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2298           Requires<[HasV4T]>;
2299
2300 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2301                                 u16ImmPred:$offset),
2302                            (i64 DoubleRegs:$src1)),
2303           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2304                                             (i64 DoubleRegs:$src1))>,
2305           Requires<[HasV4T]>;
2306
2307 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2308                                 u16ImmPred:$offset),
2309                            (i32 IntRegs:$src1)),
2310           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2311                                             (i32 IntRegs:$src1))>,
2312           Requires<[HasV4T]>;
2313
2314 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2315                                 u16ImmPred:$offset),
2316                            (i32 IntRegs:$src1)),
2317           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2318                                             (i32 IntRegs:$src1))>,
2319           Requires<[HasV4T]>;
2320
2321 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2322                                u16ImmPred:$offset),
2323                           (i32 IntRegs:$src1)),
2324           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2325                                             (i32 IntRegs:$src1))>,
2326           Requires<[HasV4T]>;
2327
2328 // Map from store(globaladdress + x) -> memd(#foo + x)
2329 let AddedComplexity = 100 in
2330 def : Pat<(store (i64 DoubleRegs:$src1),
2331                     (add (HexagonCONST32_GP tglobaladdr:$global),
2332                                         u16ImmPred:$offset)),
2333           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2334                                             (i64 DoubleRegs:$src1))>,
2335           Requires<[HasV4T]>;
2336
2337 // Map from store(globaladdress + x) -> memb(#foo + x)
2338 let AddedComplexity = 100 in
2339 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2340                         (add (HexagonCONST32_GP tglobaladdr:$global),
2341                              u16ImmPred:$offset)),
2342           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2343                                             (i32 IntRegs:$src1))>,
2344           Requires<[HasV4T]>;
2345
2346 // Map from store(globaladdress + x) -> memh(#foo + x)
2347 let AddedComplexity = 100 in
2348 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2349                          (add (HexagonCONST32_GP tglobaladdr:$global),
2350                               u16ImmPred:$offset)),
2351           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2352                                             (i32 IntRegs:$src1))>,
2353           Requires<[HasV4T]>;
2354
2355 // Map from store(globaladdress + x) -> memw(#foo + x)
2356 let AddedComplexity = 100 in
2357 def : Pat<(store (i32 IntRegs:$src1),
2358                  (add (HexagonCONST32_GP tglobaladdr:$global),
2359                                 u16ImmPred:$offset)),
2360           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2361                                             (i32 IntRegs:$src1))>,
2362           Requires<[HasV4T]>;
2363
2364
2365
2366 //===----------------------------------------------------------------------===
2367 // ST -
2368 //===----------------------------------------------------------------------===
2369
2370
2371 //===----------------------------------------------------------------------===//
2372 // NV/ST +
2373 //===----------------------------------------------------------------------===//
2374
2375 // multiclass for new-value store instructions with base + immediate offset.
2376 //
2377 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
2378                             Operand predImmOp, bit isNot, bit isPredNew> {
2379   let PNewValue = #!if(isPredNew, "new", "") in
2380   def #NAME#_nv_V4 : NVInst_V4<(outs),
2381             (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
2382             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2383             ") ")#mnemonic#"($src2+#$src3) = $src4.new",
2384             []>,
2385             Requires<[HasV4T]>;
2386 }
2387
2388 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
2389                            bit PredNot> {
2390   let PredSense = #!if(PredNot, "false", "true") in {
2391     defm _c#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
2392     // Predicate new
2393     defm _cdn#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
2394   }
2395 }
2396
2397 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
2398 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
2399                    Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
2400                    bits<5> PredImmBits> {
2401
2402   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2403     let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2404     isPredicable = 1 in
2405     def #NAME#_nv_V4 : NVInst_V4<(outs),
2406             (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2407             #mnemonic#"($src1+#$src2) = $src3.new",
2408             []>,
2409             Requires<[HasV4T]>;
2410
2411     let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2412     isPredicated = 1 in {
2413       defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
2414       defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
2415     }
2416   }
2417 }
2418
2419 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
2420   defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
2421                                  u6_0Ext, 11, 6>, AddrModeRel;
2422   defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
2423                                  u6_1Ext, 12, 7>, AddrModeRel;
2424   defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
2425                                  u6_2Ext, 13, 8>, AddrModeRel;
2426 }
2427
2428 // multiclass for new-value store instructions with base + immediate offset.
2429 // and MEMri operand.
2430 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
2431                           bit isPredNew> {
2432   let PNewValue = #!if(isPredNew, "new", "") in
2433   def #NAME#_nv_V4 : NVInst_V4<(outs),
2434             (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
2435             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2436             ") ")#mnemonic#"($addr) = $src2.new",
2437             []>,
2438             Requires<[HasV4T]>;
2439 }
2440
2441 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
2442   let PredSense = #!if(PredNot, "false", "true") in {
2443     defm _c#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
2444
2445     // Predicate new
2446     defm _cdn#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
2447   }
2448 }
2449
2450 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
2451 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
2452                     bits<5> ImmBits, bits<5> PredImmBits> {
2453
2454   let CextOpcode = CextOp, BaseOpcode = CextOp in {
2455     let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2456          isPredicable = 1 in
2457     def #NAME#_nv_V4 : NVInst_V4<(outs),
2458             (ins MEMri:$addr, RC:$src),
2459             #mnemonic#"($addr) = $src.new",
2460             []>,
2461             Requires<[HasV4T]>;
2462
2463     let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2464         neverHasSideEffects = 1, isPredicated = 1 in {
2465       defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
2466       defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
2467     }
2468   }
2469 }
2470
2471 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
2472 mayStore = 1 in {
2473   defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
2474   defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
2475   defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
2476 }
2477
2478 // memb(Ru<<#u2+#U6)=Nt.new
2479 let mayStore = 1, AddedComplexity = 10 in
2480 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2481             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2482             "memb($src1<<#$src2+#$src3) = $src4.new",
2483             []>,
2484             Requires<[HasV4T]>;
2485
2486 // memb(Rx++#s4:0)=Nt.new
2487 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2488 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2489             (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2490             "memb($src2++#$offset) = $src1.new",
2491             [],
2492             "$src2 = $dst">,
2493             Requires<[HasV4T]>;
2494
2495 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2496 // memb(Rx++I:circ(Mu))=Nt.new
2497 // memb(Rx++Mu)=Nt.new
2498 // memb(Rx++Mu:brev)=Nt.new
2499
2500 // memb(gp+#u16:0)=Nt.new
2501 let mayStore = 1, neverHasSideEffects = 1 in
2502 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2503             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2504             "memb(#$global+$offset) = $src.new",
2505             []>,
2506             Requires<[HasV4T]>;
2507
2508 // memb(#global)=Nt.new
2509 let mayStore = 1, neverHasSideEffects = 1 in
2510 def STb_GP_nv_V4 : NVInst_V4<(outs),
2511             (ins globaladdress:$global, IntRegs:$src),
2512             "memb(#$global) = $src.new",
2513             []>,
2514             Requires<[HasV4T]>;
2515
2516 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
2517 // if (Pv) memb(Rx++#s4:0)=Nt.new
2518 let mayStore = 1, hasCtrlDep = 1,
2519     isPredicated = 1 in
2520 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2521             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2522             "if ($src1) memb($src3++#$offset) = $src2.new",
2523             [],"$src3 = $dst">,
2524             Requires<[HasV4T]>;
2525
2526 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
2527 let mayStore = 1, hasCtrlDep = 1,
2528     isPredicated = 1 in
2529 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2530             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2531             "if ($src1.new) memb($src3++#$offset) = $src2.new",
2532             [],"$src3 = $dst">,
2533             Requires<[HasV4T]>;
2534
2535 // if (!Pv) memb(Rx++#s4:0)=Nt.new
2536 let mayStore = 1, hasCtrlDep = 1,
2537     isPredicated = 1 in
2538 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2539             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2540             "if (!$src1) memb($src3++#$offset) = $src2.new",
2541             [],"$src3 = $dst">,
2542             Requires<[HasV4T]>;
2543
2544 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
2545 let mayStore = 1, hasCtrlDep = 1,
2546     isPredicated = 1 in
2547 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2548             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2549             "if (!$src1.new) memb($src3++#$offset) = $src2.new",
2550             [],"$src3 = $dst">,
2551             Requires<[HasV4T]>;
2552
2553 // memh(Ru<<#u2+#U6)=Nt.new
2554 let mayStore = 1, AddedComplexity = 10 in
2555 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2556             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2557             "memh($src1<<#$src2+#$src3) = $src4.new",
2558             []>,
2559             Requires<[HasV4T]>;
2560
2561 // memh(Rx++#s4:1)=Nt.new
2562 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2563 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2564             (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
2565             "memh($src2++#$offset) = $src1.new",
2566             [],
2567             "$src2 = $dst">,
2568             Requires<[HasV4T]>;
2569
2570 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2571 // memh(Rx++I:circ(Mu))=Nt.new
2572 // memh(Rx++Mu)=Nt.new
2573 // memh(Rx++Mu:brev)=Nt.new
2574
2575 // memh(gp+#u16:1)=Nt.new
2576 let mayStore = 1, neverHasSideEffects = 1 in
2577 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2578             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2579             "memh(#$global+$offset) = $src.new",
2580             []>,
2581             Requires<[HasV4T]>;
2582
2583 // memh(#global)=Nt.new
2584 let mayStore = 1, neverHasSideEffects = 1 in
2585 def STh_GP_nv_V4 : NVInst_V4<(outs),
2586             (ins globaladdress:$global, IntRegs:$src),
2587             "memh(#$global) = $src.new",
2588             []>,
2589             Requires<[HasV4T]>;
2590
2591
2592 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2593 // if (Pv) memh(Rx++#s4:1)=Nt.new
2594 let mayStore = 1, hasCtrlDep = 1,
2595     isPredicated = 1 in
2596 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2597             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2598             "if ($src1) memh($src3++#$offset) = $src2.new",
2599             [],"$src3 = $dst">,
2600             Requires<[HasV4T]>;
2601
2602 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2603 let mayStore = 1, hasCtrlDep = 1,
2604     isPredicated = 1 in
2605 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2606             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2607             "if ($src1.new) memh($src3++#$offset) = $src2.new",
2608             [],"$src3 = $dst">,
2609             Requires<[HasV4T]>;
2610
2611 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2612 let mayStore = 1, hasCtrlDep = 1,
2613     isPredicated = 1 in
2614 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2615             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2616             "if (!$src1) memh($src3++#$offset) = $src2.new",
2617             [],"$src3 = $dst">,
2618             Requires<[HasV4T]>;
2619
2620 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2621 let mayStore = 1, hasCtrlDep = 1,
2622     isPredicated = 1 in
2623 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2624             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2625             "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2626             [],"$src3 = $dst">,
2627             Requires<[HasV4T]>;
2628
2629 // memw(Ru<<#u2+#U6)=Nt.new
2630 let mayStore = 1, AddedComplexity = 10 in
2631 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2632             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2633             "memw($src1<<#$src2+#$src3) = $src4.new",
2634             []>,
2635             Requires<[HasV4T]>;
2636
2637 // memw(Rx++#s4:2)=Nt.new
2638 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2639 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2640             (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
2641             "memw($src2++#$offset) = $src1.new",
2642             [],
2643             "$src2 = $dst">,
2644             Requires<[HasV4T]>;
2645
2646 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2647 // memw(Rx++I:circ(Mu))=Nt.new
2648 // memw(Rx++Mu)=Nt.new
2649 // memw(Rx++Mu:brev)=Nt.new
2650 // memw(gp+#u16:2)=Nt.new
2651 let mayStore = 1, neverHasSideEffects = 1 in
2652 def STriw_GP_nv_V4 : NVInst_V4<(outs),
2653             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2654             "memw(#$global+$offset) = $src.new",
2655             []>,
2656             Requires<[HasV4T]>;
2657
2658 let mayStore = 1, neverHasSideEffects = 1 in
2659 def STw_GP_nv_V4 : NVInst_V4<(outs),
2660             (ins globaladdress:$global, IntRegs:$src),
2661             "memw(#$global) = $src.new",
2662             []>,
2663             Requires<[HasV4T]>;
2664
2665 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
2666 // if (Pv) memw(Rx++#s4:2)=Nt.new
2667 let mayStore = 1, hasCtrlDep = 1,
2668     isPredicated = 1 in
2669 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2670             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2671             "if ($src1) memw($src3++#$offset) = $src2.new",
2672             [],"$src3 = $dst">,
2673             Requires<[HasV4T]>;
2674
2675 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
2676 let mayStore = 1, hasCtrlDep = 1,
2677     isPredicated = 1 in
2678 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2679             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2680             "if ($src1.new) memw($src3++#$offset) = $src2.new",
2681             [],"$src3 = $dst">,
2682             Requires<[HasV4T]>;
2683
2684 // if (!Pv) memw(Rx++#s4:2)=Nt.new
2685 let mayStore = 1, hasCtrlDep = 1,
2686     isPredicated = 1 in
2687 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2688             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2689             "if (!$src1) memw($src3++#$offset) = $src2.new",
2690             [],"$src3 = $dst">,
2691             Requires<[HasV4T]>;
2692
2693 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
2694 let mayStore = 1, hasCtrlDep = 1,
2695     isPredicated = 1 in
2696 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2697             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2698             "if (!$src1.new) memw($src3++#$offset) = $src2.new",
2699             [],"$src3 = $dst">,
2700             Requires<[HasV4T]>;
2701
2702
2703
2704 // if (Pv) memb(##global) = Rt
2705 let mayStore = 1, neverHasSideEffects = 1 in
2706 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
2707             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2708             "if ($src1) memb(##$global) = $src2.new",
2709             []>,
2710             Requires<[HasV4T]>;
2711
2712 // if (!Pv) memb(##global) = Rt
2713 let mayStore = 1, neverHasSideEffects = 1 in
2714 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2715             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2716             "if (!$src1) memb(##$global) = $src2.new",
2717             []>,
2718             Requires<[HasV4T]>;
2719
2720 // if (Pv) memb(##global) = Rt
2721 let mayStore = 1, neverHasSideEffects = 1 in
2722 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2723             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2724             "if ($src1.new) memb(##$global) = $src2.new",
2725             []>,
2726             Requires<[HasV4T]>;
2727
2728 // if (!Pv) memb(##global) = Rt
2729 let mayStore = 1, neverHasSideEffects = 1 in
2730 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2731             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2732             "if (!$src1.new) memb(##$global) = $src2.new",
2733             []>,
2734             Requires<[HasV4T]>;
2735
2736 // if (Pv) memh(##global) = Rt
2737 let mayStore = 1, neverHasSideEffects = 1 in
2738 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
2739             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2740             "if ($src1) memh(##$global) = $src2.new",
2741             []>,
2742             Requires<[HasV4T]>;
2743
2744 // if (!Pv) memh(##global) = Rt
2745 let mayStore = 1, neverHasSideEffects = 1 in
2746 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2747             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2748             "if (!$src1) memh(##$global) = $src2.new",
2749             []>,
2750             Requires<[HasV4T]>;
2751
2752 // if (Pv) memh(##global) = Rt
2753 let mayStore = 1, neverHasSideEffects = 1 in
2754 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2755             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2756             "if ($src1.new) memh(##$global) = $src2.new",
2757             []>,
2758             Requires<[HasV4T]>;
2759
2760 // if (!Pv) memh(##global) = Rt
2761 let mayStore = 1, neverHasSideEffects = 1 in
2762 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2763             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2764             "if (!$src1.new) memh(##$global) = $src2.new",
2765             []>,
2766             Requires<[HasV4T]>;
2767
2768 // if (Pv) memw(##global) = Rt
2769 let mayStore = 1, neverHasSideEffects = 1 in
2770 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2771             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2772             "if ($src1) memw(##$global) = $src2.new",
2773             []>,
2774             Requires<[HasV4T]>;
2775
2776 // if (!Pv) memw(##global) = Rt
2777 let mayStore = 1, neverHasSideEffects = 1 in
2778 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2779             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2780             "if (!$src1) memw(##$global) = $src2.new",
2781             []>,
2782             Requires<[HasV4T]>;
2783
2784 // if (Pv) memw(##global) = Rt
2785 let mayStore = 1, neverHasSideEffects = 1 in
2786 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2787             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2788             "if ($src1.new) memw(##$global) = $src2.new",
2789             []>,
2790             Requires<[HasV4T]>;
2791
2792 // if (!Pv) memw(##global) = Rt
2793 let mayStore = 1, neverHasSideEffects = 1 in
2794 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2795             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2796             "if (!$src1.new) memw(##$global) = $src2.new",
2797             []>,
2798             Requires<[HasV4T]>;
2799
2800 let mayStore = 1, neverHasSideEffects = 1 in
2801 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
2802             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2803                                                         IntRegs:$src2),
2804             "if ($src1) memb(##$global+$offset) = $src2.new",
2805             []>,
2806             Requires<[HasV4T]>;
2807
2808 let mayStore = 1, neverHasSideEffects = 1 in
2809 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2810             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2811                                                         IntRegs:$src2),
2812             "if (!$src1) memb(##$global+$offset) = $src2.new",
2813             []>,
2814             Requires<[HasV4T]>;
2815
2816 let mayStore = 1, neverHasSideEffects = 1 in
2817 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2818             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2819                                                         IntRegs:$src2),
2820             "if ($src1.new) memb(##$global+$offset) = $src2.new",
2821             []>,
2822             Requires<[HasV4T]>;
2823
2824 let mayStore = 1, neverHasSideEffects = 1 in
2825 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2826             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2827                                                         IntRegs:$src2),
2828             "if (!$src1.new) memb(##$global+$offset) = $src2.new",
2829             []>,
2830             Requires<[HasV4T]>;
2831
2832 let mayStore = 1, neverHasSideEffects = 1 in
2833 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
2834             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2835                                                         IntRegs:$src2),
2836             "if ($src1) memh(##$global+$offset) = $src2.new",
2837             []>,
2838             Requires<[HasV4T]>;
2839
2840 let mayStore = 1, neverHasSideEffects = 1 in
2841 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2842             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2843                                                         IntRegs:$src2),
2844             "if (!$src1) memh(##$global+$offset) = $src2.new",
2845             []>,
2846             Requires<[HasV4T]>;
2847
2848 let mayStore = 1, neverHasSideEffects = 1 in
2849 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2850             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2851                                                         IntRegs:$src2),
2852             "if ($src1.new) memh(##$global+$offset) = $src2.new",
2853             []>,
2854             Requires<[HasV4T]>;
2855
2856 let mayStore = 1, neverHasSideEffects = 1 in
2857 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2858             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2859                                                         IntRegs:$src2),
2860             "if (!$src1.new) memh(##$global+$offset) = $src2.new",
2861             []>,
2862             Requires<[HasV4T]>;
2863
2864 let mayStore = 1, neverHasSideEffects = 1 in
2865 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2866             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2867                                                         IntRegs:$src2),
2868             "if ($src1) memw(##$global+$offset) = $src2.new",
2869             []>,
2870             Requires<[HasV4T]>;
2871
2872 let mayStore = 1, neverHasSideEffects = 1 in
2873 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2874             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2875                                                         IntRegs:$src2),
2876             "if (!$src1) memw(##$global+$offset) = $src2.new",
2877             []>,
2878             Requires<[HasV4T]>;
2879
2880 let mayStore = 1, neverHasSideEffects = 1 in
2881 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2882             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2883                                                         IntRegs:$src2),
2884             "if ($src1.new) memw(##$global+$offset) = $src2.new",
2885             []>,
2886             Requires<[HasV4T]>;
2887
2888 let mayStore = 1, neverHasSideEffects = 1 in
2889 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2890             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2891                                                         IntRegs:$src2),
2892             "if (!$src1.new) memw(##$global+$offset) = $src2.new",
2893             []>,
2894             Requires<[HasV4T]>;
2895
2896 //===----------------------------------------------------------------------===//
2897 // NV/ST -
2898 //===----------------------------------------------------------------------===//
2899
2900 //===----------------------------------------------------------------------===//
2901 // NV/J +
2902 //===----------------------------------------------------------------------===//
2903
2904 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
2905   def _ie_nv_V4 : NVInst_V4<(outs),
2906             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2907             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2908             !strconcat("($src1.new, $src2)) jump:",
2909             !strconcat(TakenStr, " $offset"))))),
2910             []>,
2911             Requires<[HasV4T]>;
2912
2913   def _nv_V4 : NVInst_V4<(outs),
2914             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2915             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2916             !strconcat("($src1.new, $src2)) jump:",
2917             !strconcat(TakenStr, " $offset"))))),
2918             []>,
2919             Requires<[HasV4T]>;
2920 }
2921
2922 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
2923                                                    string TakenStr> {
2924   def _ie_nv_V4 : NVInst_V4<(outs),
2925             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2926             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2927             !strconcat("($src1, $src2.new)) jump:",
2928             !strconcat(TakenStr, " $offset"))))),
2929             []>,
2930             Requires<[HasV4T]>;
2931
2932   def _nv_V4 : NVInst_V4<(outs),
2933             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2934             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2935             !strconcat("($src1, $src2.new)) jump:",
2936             !strconcat(TakenStr, " $offset"))))),
2937             []>,
2938             Requires<[HasV4T]>;
2939 }
2940
2941 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
2942   def _ie_nv_V4 : NVInst_V4<(outs),
2943             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2944             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2945             !strconcat("($src1.new, #$src2)) jump:",
2946             !strconcat(TakenStr, " $offset"))))),
2947             []>,
2948             Requires<[HasV4T]>;
2949
2950   def _nv_V4 : NVInst_V4<(outs),
2951             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2952             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2953             !strconcat("($src1.new, #$src2)) jump:",
2954             !strconcat(TakenStr, " $offset"))))),
2955             []>,
2956             Requires<[HasV4T]>;
2957 }
2958
2959 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
2960   def _ie_nv_V4 : NVInst_V4<(outs),
2961             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2962             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2963             !strconcat("($src1.new, #$src2)) jump:",
2964             !strconcat(TakenStr, " $offset"))))),
2965             []>,
2966             Requires<[HasV4T]>;
2967
2968   def _nv_V4 : NVInst_V4<(outs),
2969             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2970             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2971             !strconcat("($src1.new, #$src2)) jump:",
2972             !strconcat(TakenStr, " $offset"))))),
2973             []>,
2974             Requires<[HasV4T]>;
2975 }
2976
2977 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
2978                                                 string TakenStr> {
2979   def _ie_nv_V4 : NVInst_V4<(outs),
2980             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2981             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2982             !strconcat("($src1.new, #$src2)) jump:",
2983             !strconcat(TakenStr, " $offset"))))),
2984             []>,
2985             Requires<[HasV4T]>;
2986
2987   def _nv_V4 : NVInst_V4<(outs),
2988             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2989             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2990             !strconcat("($src1.new, #$src2)) jump:",
2991             !strconcat(TakenStr, " $offset"))))),
2992             []>,
2993             Requires<[HasV4T]>;
2994 }
2995
2996 // Multiclass for regular dot new of Ist operand register.
2997 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
2998   defm Pt  : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
2999   defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
3000 }
3001
3002 // Multiclass for dot new of 2nd operand register.
3003 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
3004   defm Pt  : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
3005   defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
3006 }
3007
3008 // Multiclass for 2nd operand immediate, including -1.
3009 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
3010   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3011   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3012   defm Ptneg  : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
3013   defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
3014 }
3015
3016 // Multiclass for 2nd operand immediate, excluding -1.
3017 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
3018   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3019   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3020 }
3021
3022 // Multiclass for tstbit, where 2nd operand is always #0.
3023 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3024   defm Pt     : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3025   defm Pnt    : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3026 }
3027
3028 // Multiclass for GT.
3029 multiclass NVJ_type_rr_ri<string OpcStr> {
3030   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3031   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3032   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3033   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3034   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3035   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3036 }
3037
3038 // Multiclass for EQ.
3039 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3040   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3041   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3042   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3043   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3044 }
3045
3046 // Multiclass for GTU.
3047 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3048   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3049   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3050   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3051   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3052   defm riNot   : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3053   defm ri      : NVJ_type_br_pred_imm_only<"",  OpcStr>;
3054 }
3055
3056 // Multiclass for tstbit.
3057 multiclass NVJ_type_r0<string OpcStr> {
3058   defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3059   defm r0    : NVJ_type_br_pred_tstbit<"",  OpcStr>;
3060  }
3061
3062 // Base Multiclass for New Value Jump.
3063 multiclass NVJ_type {
3064   defm GT     : NVJ_type_rr_ri<"cmp.gt">;
3065   defm EQ     : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3066   defm GTU    : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3067   defm TSTBIT : NVJ_type_r0<"tstbit">;
3068 }
3069
3070 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3071   defm JMP_ : NVJ_type;
3072 }
3073
3074 //===----------------------------------------------------------------------===//
3075 // NV/J -
3076 //===----------------------------------------------------------------------===//
3077
3078 //===----------------------------------------------------------------------===//
3079 // XTYPE/ALU +
3080 //===----------------------------------------------------------------------===//
3081
3082 //  Add and accumulate.
3083 //  Rd=add(Rs,add(Ru,#s6))
3084 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3085           (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3086           "$dst = add($src1, add($src2, #$src3))",
3087           [(set (i32 IntRegs:$dst),
3088            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3089                                           s6ImmPred:$src3)))]>,
3090           Requires<[HasV4T]>;
3091
3092 //  Rd=add(Rs,sub(#s6,Ru))
3093 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3094           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3095           "$dst = add($src1, sub(#$src2, $src3))",
3096           [(set (i32 IntRegs:$dst),
3097            (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3098                                           (i32 IntRegs:$src3))))]>,
3099           Requires<[HasV4T]>;
3100
3101 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3102 // pattern.
3103 //  Rd=add(Rs,sub(#s6,Ru))
3104 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3105           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3106           "$dst = add($src1, sub(#$src2, $src3))",
3107           [(set (i32 IntRegs:$dst),
3108                 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3109                      (i32 IntRegs:$src3)))]>,
3110           Requires<[HasV4T]>;
3111
3112
3113 //  Add or subtract doublewords with carry.
3114 //TODO:
3115 //  Rdd=add(Rss,Rtt,Px):carry
3116 //TODO:
3117 //  Rdd=sub(Rss,Rtt,Px):carry
3118
3119
3120 //  Logical doublewords.
3121 //  Rdd=and(Rtt,~Rss)
3122 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3123           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3124           "$dst = and($src1, ~$src2)",
3125           [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3126                                       (not (i64 DoubleRegs:$src2))))]>,
3127           Requires<[HasV4T]>;
3128
3129 //  Rdd=or(Rtt,~Rss)
3130 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3131           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3132           "$dst = or($src1, ~$src2)",
3133           [(set (i64 DoubleRegs:$dst),
3134            (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3135           Requires<[HasV4T]>;
3136
3137
3138 //  Logical-logical doublewords.
3139 //  Rxx^=xor(Rss,Rtt)
3140 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3141           (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3142           "$dst ^= xor($src2, $src3)",
3143           [(set (i64 DoubleRegs:$dst),
3144            (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3145                                              (i64 DoubleRegs:$src3))))],
3146           "$src1 = $dst">,
3147           Requires<[HasV4T]>;
3148
3149
3150 // Logical-logical words.
3151 // Rx=or(Ru,and(Rx,#s10))
3152 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3153             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3154             "$dst = or($src1, and($src2, #$src3))",
3155             [(set (i32 IntRegs:$dst),
3156                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3157                                                 s10ImmPred:$src3)))],
3158             "$src2 = $dst">,
3159             Requires<[HasV4T]>;
3160
3161 // Rx[&|^]=and(Rs,Rt)
3162 // Rx&=and(Rs,Rt)
3163 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3164             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3165             "$dst &= and($src2, $src3)",
3166             [(set (i32 IntRegs:$dst),
3167                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3168                                                  (i32 IntRegs:$src3))))],
3169             "$src1 = $dst">,
3170             Requires<[HasV4T]>;
3171
3172 // Rx|=and(Rs,Rt)
3173 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3174             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3175             "$dst |= and($src2, $src3)",
3176             [(set (i32 IntRegs:$dst),
3177                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3178                                                 (i32 IntRegs:$src3))))],
3179             "$src1 = $dst">,
3180             Requires<[HasV4T]>;
3181
3182 // Rx^=and(Rs,Rt)
3183 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3184             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3185             "$dst ^= and($src2, $src3)",
3186             [(set (i32 IntRegs:$dst),
3187              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3188                                             (i32 IntRegs:$src3))))],
3189             "$src1 = $dst">,
3190             Requires<[HasV4T]>;
3191
3192 // Rx[&|^]=and(Rs,~Rt)
3193 // Rx&=and(Rs,~Rt)
3194 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3195             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3196             "$dst &= and($src2, ~$src3)",
3197             [(set (i32 IntRegs:$dst),
3198                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3199                                                  (not (i32 IntRegs:$src3)))))],
3200             "$src1 = $dst">,
3201             Requires<[HasV4T]>;
3202
3203 // Rx|=and(Rs,~Rt)
3204 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3205             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3206             "$dst |= and($src2, ~$src3)",
3207             [(set (i32 IntRegs:$dst),
3208              (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3209                                            (not (i32 IntRegs:$src3)))))],
3210             "$src1 = $dst">,
3211             Requires<[HasV4T]>;
3212
3213 // Rx^=and(Rs,~Rt)
3214 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3215             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3216             "$dst ^= and($src2, ~$src3)",
3217             [(set (i32 IntRegs:$dst),
3218              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3219                                             (not (i32 IntRegs:$src3)))))],
3220             "$src1 = $dst">,
3221             Requires<[HasV4T]>;
3222
3223 // Rx[&|^]=or(Rs,Rt)
3224 // Rx&=or(Rs,Rt)
3225 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3226             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3227             "$dst &= or($src2, $src3)",
3228             [(set (i32 IntRegs:$dst),
3229                   (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3230                                                 (i32 IntRegs:$src3))))],
3231             "$src1 = $dst">,
3232             Requires<[HasV4T]>;
3233
3234 // Rx|=or(Rs,Rt)
3235 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3236             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3237             "$dst |= or($src2, $src3)",
3238             [(set (i32 IntRegs:$dst),
3239                   (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3240                                                (i32 IntRegs:$src3))))],
3241             "$src1 = $dst">,
3242             Requires<[HasV4T]>;
3243
3244 // Rx^=or(Rs,Rt)
3245 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3246             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3247             "$dst ^= or($src2, $src3)",
3248             [(set (i32 IntRegs:$dst),
3249              (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3250                                            (i32 IntRegs:$src3))))],
3251             "$src1 = $dst">,
3252             Requires<[HasV4T]>;
3253
3254 // Rx[&|^]=xor(Rs,Rt)
3255 // Rx&=xor(Rs,Rt)
3256 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3257             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3258             "$dst &= xor($src2, $src3)",
3259             [(set (i32 IntRegs:$dst),
3260                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3261                                                  (i32 IntRegs:$src3))))],
3262             "$src1 = $dst">,
3263             Requires<[HasV4T]>;
3264
3265 // Rx|=xor(Rs,Rt)
3266 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3267             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3268             "$dst |= xor($src2, $src3)",
3269             [(set (i32 IntRegs:$dst),
3270                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3271                                                  (i32 IntRegs:$src3))))],
3272             "$src1 = $dst">,
3273             Requires<[HasV4T]>;
3274
3275 // Rx^=xor(Rs,Rt)
3276 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3277             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3278             "$dst ^= xor($src2, $src3)",
3279             [(set (i32 IntRegs:$dst),
3280              (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3281                                             (i32 IntRegs:$src3))))],
3282             "$src1 = $dst">,
3283             Requires<[HasV4T]>;
3284
3285 // Rx|=and(Rs,#s10)
3286 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3287             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3288             "$dst |= and($src2, #$src3)",
3289             [(set (i32 IntRegs:$dst),
3290                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3291                                                 s10ImmPred:$src3)))],
3292             "$src1 = $dst">,
3293             Requires<[HasV4T]>;
3294
3295 // Rx|=or(Rs,#s10)
3296 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3297             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3298             "$dst |= or($src2, #$src3)",
3299             [(set (i32 IntRegs:$dst),
3300                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3301                                                 s10ImmPred:$src3)))],
3302             "$src1 = $dst">,
3303             Requires<[HasV4T]>;
3304
3305
3306 //    Modulo wrap
3307 //        Rd=modwrap(Rs,Rt)
3308 //    Round
3309 //        Rd=cround(Rs,#u5)
3310 //        Rd=cround(Rs,Rt)
3311 //        Rd=round(Rs,#u5)[:sat]
3312 //        Rd=round(Rs,Rt)[:sat]
3313 //    Vector reduce add unsigned halfwords
3314 //        Rd=vraddh(Rss,Rtt)
3315 //    Vector add bytes
3316 //        Rdd=vaddb(Rss,Rtt)
3317 //    Vector conditional negate
3318 //        Rdd=vcnegh(Rss,Rt)
3319 //        Rxx+=vrcnegh(Rss,Rt)
3320 //    Vector maximum bytes
3321 //        Rdd=vmaxb(Rtt,Rss)
3322 //    Vector reduce maximum halfwords
3323 //        Rxx=vrmaxh(Rss,Ru)
3324 //        Rxx=vrmaxuh(Rss,Ru)
3325 //    Vector reduce maximum words
3326 //        Rxx=vrmaxuw(Rss,Ru)
3327 //        Rxx=vrmaxw(Rss,Ru)
3328 //    Vector minimum bytes
3329 //        Rdd=vminb(Rtt,Rss)
3330 //    Vector reduce minimum halfwords
3331 //        Rxx=vrminh(Rss,Ru)
3332 //        Rxx=vrminuh(Rss,Ru)
3333 //    Vector reduce minimum words
3334 //        Rxx=vrminuw(Rss,Ru)
3335 //        Rxx=vrminw(Rss,Ru)
3336 //    Vector subtract bytes
3337 //        Rdd=vsubb(Rss,Rtt)
3338
3339 //===----------------------------------------------------------------------===//
3340 // XTYPE/ALU -
3341 //===----------------------------------------------------------------------===//
3342
3343
3344 //===----------------------------------------------------------------------===//
3345 // XTYPE/MPY +
3346 //===----------------------------------------------------------------------===//
3347
3348 // Multiply and user lower result.
3349 // Rd=add(#u6,mpyi(Rs,#U6))
3350 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3351             (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
3352             "$dst = add(#$src1, mpyi($src2, #$src3))",
3353             [(set (i32 IntRegs:$dst),
3354                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3355                        u6ImmPred:$src1))]>,
3356             Requires<[HasV4T]>;
3357
3358 // Rd=add(#u6,mpyi(Rs,Rt))
3359
3360 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3361             (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
3362             "$dst = add(#$src1, mpyi($src2, $src3))",
3363             [(set (i32 IntRegs:$dst),
3364                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3365                        u6ImmPred:$src1))]>,
3366             Requires<[HasV4T]>;
3367
3368 // Rd=add(Ru,mpyi(#u6:2,Rs))
3369 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
3370             (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
3371             "$dst = add($src1, mpyi(#$src2, $src3))",
3372             [(set (i32 IntRegs:$dst),
3373              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
3374                                             u6_2ImmPred:$src2)))]>,
3375             Requires<[HasV4T]>;
3376
3377 // Rd=add(Ru,mpyi(Rs,#u6))
3378 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
3379             (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
3380             "$dst = add($src1, mpyi($src2, #$src3))",
3381             [(set (i32 IntRegs:$dst),
3382                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3383                                                  u6ImmPred:$src3)))]>,
3384             Requires<[HasV4T]>;
3385
3386 // Rx=add(Ru,mpyi(Rx,Rs))
3387 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
3388             (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3389             "$dst = add($src1, mpyi($src2, $src3))",
3390             [(set (i32 IntRegs:$dst),
3391              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3392                                             (i32 IntRegs:$src3))))],
3393             "$src2 = $dst">,
3394             Requires<[HasV4T]>;
3395
3396
3397 // Polynomial multiply words
3398 // Rdd=pmpyw(Rs,Rt)
3399 // Rxx^=pmpyw(Rs,Rt)
3400
3401 // Vector reduce multiply word by signed half (32x16)
3402 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
3403 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
3404 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
3405 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
3406
3407 // Multiply and use upper result
3408 // Rd=mpy(Rs,Rt.H):<<1:sat
3409 // Rd=mpy(Rs,Rt.L):<<1:sat
3410 // Rd=mpy(Rs,Rt):<<1
3411 // Rd=mpy(Rs,Rt):<<1:sat
3412 // Rd=mpysu(Rs,Rt)
3413 // Rx+=mpy(Rs,Rt):<<1:sat
3414 // Rx-=mpy(Rs,Rt):<<1:sat
3415
3416 // Vector multiply bytes
3417 // Rdd=vmpybsu(Rs,Rt)
3418 // Rdd=vmpybu(Rs,Rt)
3419 // Rxx+=vmpybsu(Rs,Rt)
3420 // Rxx+=vmpybu(Rs,Rt)
3421
3422 // Vector polynomial multiply halfwords
3423 // Rdd=vpmpyh(Rs,Rt)
3424 // Rxx^=vpmpyh(Rs,Rt)
3425
3426 //===----------------------------------------------------------------------===//
3427 // XTYPE/MPY -
3428 //===----------------------------------------------------------------------===//
3429
3430
3431 //===----------------------------------------------------------------------===//
3432 // XTYPE/SHIFT +
3433 //===----------------------------------------------------------------------===//
3434
3435 // Shift by immediate and accumulate.
3436 // Rx=add(#u8,asl(Rx,#U5))
3437 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3438             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3439             "$dst = add(#$src1, asl($src2, #$src3))",
3440             [(set (i32 IntRegs:$dst),
3441                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3442                        u8ImmPred:$src1))],
3443             "$src2 = $dst">,
3444             Requires<[HasV4T]>;
3445
3446 // Rx=add(#u8,lsr(Rx,#U5))
3447 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3448             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3449             "$dst = add(#$src1, lsr($src2, #$src3))",
3450             [(set (i32 IntRegs:$dst),
3451                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3452                        u8ImmPred:$src1))],
3453             "$src2 = $dst">,
3454             Requires<[HasV4T]>;
3455
3456 // Rx=sub(#u8,asl(Rx,#U5))
3457 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3458             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3459             "$dst = sub(#$src1, asl($src2, #$src3))",
3460             [(set (i32 IntRegs:$dst),
3461                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3462                        u8ImmPred:$src1))],
3463             "$src2 = $dst">,
3464             Requires<[HasV4T]>;
3465
3466 // Rx=sub(#u8,lsr(Rx,#U5))
3467 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3468             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3469             "$dst = sub(#$src1, lsr($src2, #$src3))",
3470             [(set (i32 IntRegs:$dst),
3471                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3472                        u8ImmPred:$src1))],
3473             "$src2 = $dst">,
3474             Requires<[HasV4T]>;
3475
3476
3477 //Shift by immediate and logical.
3478 //Rx=and(#u8,asl(Rx,#U5))
3479 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3480             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3481             "$dst = and(#$src1, asl($src2, #$src3))",
3482             [(set (i32 IntRegs:$dst),
3483                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3484                        u8ImmPred:$src1))],
3485             "$src2 = $dst">,
3486             Requires<[HasV4T]>;
3487
3488 //Rx=and(#u8,lsr(Rx,#U5))
3489 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3490             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3491             "$dst = and(#$src1, lsr($src2, #$src3))",
3492             [(set (i32 IntRegs:$dst),
3493                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3494                        u8ImmPred:$src1))],
3495             "$src2 = $dst">,
3496             Requires<[HasV4T]>;
3497
3498 //Rx=or(#u8,asl(Rx,#U5))
3499 let AddedComplexity = 30 in
3500 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3501             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3502             "$dst = or(#$src1, asl($src2, #$src3))",
3503             [(set (i32 IntRegs:$dst),
3504                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3505                       u8ImmPred:$src1))],
3506             "$src2 = $dst">,
3507             Requires<[HasV4T]>;
3508
3509 //Rx=or(#u8,lsr(Rx,#U5))
3510 let AddedComplexity = 30 in
3511 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3512             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3513             "$dst = or(#$src1, lsr($src2, #$src3))",
3514             [(set (i32 IntRegs:$dst),
3515                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3516                       u8ImmPred:$src1))],
3517             "$src2 = $dst">,
3518             Requires<[HasV4T]>;
3519
3520
3521 //Shift by register.
3522 //Rd=lsl(#s6,Rt)
3523 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
3524             "$dst = lsl(#$src1, $src2)",
3525             [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
3526                                            (i32 IntRegs:$src2)))]>,
3527             Requires<[HasV4T]>;
3528
3529
3530 //Shift by register and logical.
3531 //Rxx^=asl(Rss,Rt)
3532 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3533             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3534             "$dst ^= asl($src2, $src3)",
3535             [(set (i64 DoubleRegs:$dst),
3536                   (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
3537                                                     (i32 IntRegs:$src3))))],
3538             "$src1 = $dst">,
3539             Requires<[HasV4T]>;
3540
3541 //Rxx^=asr(Rss,Rt)
3542 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3543             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3544             "$dst ^= asr($src2, $src3)",
3545             [(set (i64 DoubleRegs:$dst),
3546                   (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
3547                                                     (i32 IntRegs:$src3))))],
3548             "$src1 = $dst">,
3549             Requires<[HasV4T]>;
3550
3551 //Rxx^=lsl(Rss,Rt)
3552 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3553             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3554             "$dst ^= lsl($src2, $src3)",
3555             [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
3556                                               (shl (i64 DoubleRegs:$src2),
3557                                                    (i32 IntRegs:$src3))))],
3558             "$src1 = $dst">,
3559             Requires<[HasV4T]>;
3560
3561 //Rxx^=lsr(Rss,Rt)
3562 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3563             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3564             "$dst ^= lsr($src2, $src3)",
3565             [(set (i64 DoubleRegs:$dst),
3566                   (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
3567                                                     (i32 IntRegs:$src3))))],
3568             "$src1 = $dst">,
3569             Requires<[HasV4T]>;
3570
3571
3572 //===----------------------------------------------------------------------===//
3573 // XTYPE/SHIFT -
3574 //===----------------------------------------------------------------------===//
3575
3576 //===----------------------------------------------------------------------===//
3577 // MEMOP: Word, Half, Byte
3578 //===----------------------------------------------------------------------===//
3579
3580 //===----------------------------------------------------------------------===//
3581 // MEMOP: Word
3582 //
3583 //  Implemented:
3584 //     MEMw_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3585 //     MEMw_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3586 //     MEMw_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3587 //     MEMw_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3588 //     MEMw_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3589 //     MEMw_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3590 //     MEMw_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3591 //     MEMw_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3592 //     MEMw_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3593 //     MEMw_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3594 //     MEMw_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3595 //     MEMw_SETr_V4          : memw(Rs+#u6:2)|=Rt
3596 //
3597 //   Not implemented:
3598 //     MEMw_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3599 //     MEMw_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3600 //     MEMw_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3601 //     MEMw_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3602 //===----------------------------------------------------------------------===//
3603
3604
3605
3606 // memw(Rs+#u6:2) += #U5
3607 let AddedComplexity = 30 in
3608 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3609             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
3610             "memw($base+#$offset) += #$addend",
3611             []>,
3612             Requires<[HasV4T, UseMEMOP]>;
3613
3614 // memw(Rs+#u6:2) -= #U5
3615 let AddedComplexity = 30 in
3616 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3617             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
3618             "memw($base+#$offset) -= #$subend",
3619             []>,
3620             Requires<[HasV4T, UseMEMOP]>;
3621
3622 // memw(Rs+#u6:2) += Rt
3623 let AddedComplexity = 30 in
3624 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3625             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
3626             "memw($base+#$offset) += $addend",
3627             [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3628                          (i32 IntRegs:$addend)),
3629                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3630             Requires<[HasV4T, UseMEMOP]>;
3631
3632 // memw(Rs+#u6:2) -= Rt
3633 let AddedComplexity = 30 in
3634 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3635             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
3636             "memw($base+#$offset) -= $subend",
3637             [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3638                          (i32 IntRegs:$subend)),
3639                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3640             Requires<[HasV4T, UseMEMOP]>;
3641
3642 // memw(Rs+#u6:2) &= Rt
3643 let AddedComplexity = 30 in
3644 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3645             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
3646             "memw($base+#$offset) &= $andend",
3647             [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3648                          (i32 IntRegs:$andend)),
3649                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3650             Requires<[HasV4T, UseMEMOP]>;
3651
3652 // memw(Rs+#u6:2) |= Rt
3653 let AddedComplexity = 30 in
3654 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3655             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
3656             "memw($base+#$offset) |= $orend",
3657             [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3658                         (i32 IntRegs:$orend)),
3659                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3660             Requires<[HasV4T, UseMEMOP]>;
3661
3662 // memw(Rs+#u6:2) += #U5
3663 let AddedComplexity = 30 in
3664 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
3665             (ins MEMri:$addr, u5Imm:$addend),
3666             "memw($addr) += $addend",
3667             []>,
3668             Requires<[HasV4T, UseMEMOP]>;
3669
3670 // memw(Rs+#u6:2) -= #U5
3671 let AddedComplexity = 30 in
3672 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
3673             (ins MEMri:$addr, u5Imm:$subend),
3674             "memw($addr) -= $subend",
3675             []>,
3676             Requires<[HasV4T, UseMEMOP]>;
3677
3678 // memw(Rs+#u6:2) += Rt
3679 let AddedComplexity = 30 in
3680 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
3681             (ins MEMri:$addr, IntRegs:$addend),
3682             "memw($addr) += $addend",
3683             [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
3684                     ADDRriU6_2:$addr)]>,
3685             Requires<[HasV4T, UseMEMOP]>;
3686
3687 // memw(Rs+#u6:2) -= Rt
3688 let AddedComplexity = 30 in
3689 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
3690             (ins MEMri:$addr, IntRegs:$subend),
3691             "memw($addr) -= $subend",
3692             [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
3693                     ADDRriU6_2:$addr)]>,
3694             Requires<[HasV4T, UseMEMOP]>;
3695
3696 // memw(Rs+#u6:2) &= Rt
3697 let AddedComplexity = 30 in
3698 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
3699             (ins MEMri:$addr, IntRegs:$andend),
3700             "memw($addr) &= $andend",
3701             [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
3702                     ADDRriU6_2:$addr)]>,
3703             Requires<[HasV4T, UseMEMOP]>;
3704
3705 // memw(Rs+#u6:2) |= Rt
3706 let AddedComplexity = 30 in
3707 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
3708             (ins MEMri:$addr, IntRegs:$orend),
3709             "memw($addr) |= $orend",
3710             [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
3711                     ADDRriU6_2:$addr)]>,
3712             Requires<[HasV4T, UseMEMOP]>;
3713
3714 //===----------------------------------------------------------------------===//
3715 // MEMOP: Halfword
3716 //
3717 //  Implemented:
3718 //     MEMh_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3719 //     MEMh_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3720 //     MEMh_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3721 //     MEMh_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3722 //     MEMh_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3723 //     MEMh_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3724 //     MEMh_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3725 //     MEMh_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3726 //     MEMh_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3727 //     MEMh_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3728 //     MEMh_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3729 //     MEMh_SETr_V4          : memw(Rs+#u6:2)|=Rt
3730 //
3731 //   Not implemented:
3732 //     MEMh_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3733 //     MEMh_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3734 //     MEMh_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3735 //     MEMh_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3736 //===----------------------------------------------------------------------===//
3737
3738
3739 // memh(Rs+#u6:1) += #U5
3740 let AddedComplexity = 30 in
3741 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3742             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
3743             "memh($base+#$offset) += $addend",
3744             []>,
3745             Requires<[HasV4T, UseMEMOP]>;
3746
3747 // memh(Rs+#u6:1) -= #U5
3748 let AddedComplexity = 30 in
3749 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3750             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
3751             "memh($base+#$offset) -= $subend",
3752             []>,
3753             Requires<[HasV4T, UseMEMOP]>;
3754
3755 // memh(Rs+#u6:1) += Rt
3756 let AddedComplexity = 30 in
3757 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3758             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
3759             "memh($base+#$offset) += $addend",
3760             [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
3761                                                    u6_1ImmPred:$offset)),
3762                                  (i32 IntRegs:$addend)),
3763                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3764             Requires<[HasV4T, UseMEMOP]>;
3765
3766 // memh(Rs+#u6:1) -= Rt
3767 let AddedComplexity = 30 in
3768 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3769             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
3770             "memh($base+#$offset) -= $subend",
3771             [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
3772                                                    u6_1ImmPred:$offset)),
3773                                  (i32 IntRegs:$subend)),
3774                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3775             Requires<[HasV4T, UseMEMOP]>;
3776
3777 // memh(Rs+#u6:1) &= Rt
3778 let AddedComplexity = 30 in
3779 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3780             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
3781             "memh($base+#$offset) += $andend",
3782             [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
3783                                                    u6_1ImmPred:$offset)),
3784                                  (i32 IntRegs:$andend)),
3785                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3786             Requires<[HasV4T, UseMEMOP]>;
3787
3788 // memh(Rs+#u6:1) |= Rt
3789 let AddedComplexity = 30 in
3790 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3791             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
3792             "memh($base+#$offset) |= $orend",
3793             [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
3794                                               u6_1ImmPred:$offset)),
3795                              (i32 IntRegs:$orend)),
3796                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3797             Requires<[HasV4T, UseMEMOP]>;
3798
3799 // memh(Rs+#u6:1) += #U5
3800 let AddedComplexity = 30 in
3801 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
3802             (ins MEMri:$addr, u5Imm:$addend),
3803             "memh($addr) += $addend",
3804             []>,
3805             Requires<[HasV4T, UseMEMOP]>;
3806
3807 // memh(Rs+#u6:1) -= #U5
3808 let AddedComplexity = 30 in
3809 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
3810             (ins MEMri:$addr, u5Imm:$subend),
3811             "memh($addr) -= $subend",
3812             []>,
3813             Requires<[HasV4T, UseMEMOP]>;
3814
3815 // memh(Rs+#u6:1) += Rt
3816 let AddedComplexity = 30 in
3817 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
3818             (ins MEMri:$addr, IntRegs:$addend),
3819             "memh($addr) += $addend",
3820             [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
3821                                  (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
3822             Requires<[HasV4T, UseMEMOP]>;
3823
3824 // memh(Rs+#u6:1) -= Rt
3825 let AddedComplexity = 30 in
3826 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
3827             (ins MEMri:$addr, IntRegs:$subend),
3828             "memh($addr) -= $subend",
3829             [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
3830                                  (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
3831             Requires<[HasV4T, UseMEMOP]>;
3832
3833 // memh(Rs+#u6:1) &= Rt
3834 let AddedComplexity = 30 in
3835 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
3836             (ins MEMri:$addr, IntRegs:$andend),
3837             "memh($addr) &= $andend",
3838             [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
3839                                  (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
3840             Requires<[HasV4T, UseMEMOP]>;
3841
3842 // memh(Rs+#u6:1) |= Rt
3843 let AddedComplexity = 30 in
3844 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
3845             (ins MEMri:$addr, IntRegs:$orend),
3846             "memh($addr) |= $orend",
3847             [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
3848                                 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
3849             Requires<[HasV4T, UseMEMOP]>;
3850
3851
3852 //===----------------------------------------------------------------------===//
3853 // MEMOP: Byte
3854 //
3855 //  Implemented:
3856 //     MEMb_ADDi_indexed_V4  : memb(Rs+#u6:0)+=#U5
3857 //     MEMb_SUBi_indexed_V4  : memb(Rs+#u6:0)-=#U5
3858 //     MEMb_ADDr_indexed_V4  : memb(Rs+#u6:0)+=Rt
3859 //     MEMb_SUBr_indexed_V4  : memb(Rs+#u6:0)-=Rt
3860 //     MEMb_CLRr_indexed_V4  : memb(Rs+#u6:0)&=Rt
3861 //     MEMb_SETr_indexed_V4  : memb(Rs+#u6:0)|=Rt
3862 //     MEMb_ADDi_V4          : memb(Rs+#u6:0)+=#U5
3863 //     MEMb_SUBi_V4          : memb(Rs+#u6:0)-=#U5
3864 //     MEMb_ADDr_V4          : memb(Rs+#u6:0)+=Rt
3865 //     MEMb_SUBr_V4          : memb(Rs+#u6:0)-=Rt
3866 //     MEMb_CLRr_V4          : memb(Rs+#u6:0)&=Rt
3867 //     MEMb_SETr_V4          : memb(Rs+#u6:0)|=Rt
3868 //
3869 //   Not implemented:
3870 //     MEMb_CLRi_indexed_V4  : memb(Rs+#u6:0)=clrbit(#U5)
3871 //     MEMb_SETi_indexed_V4  : memb(Rs+#u6:0)=setbit(#U5)
3872 //     MEMb_CLRi_V4          : memb(Rs+#u6:0)=clrbit(#U5)
3873 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
3874 //===----------------------------------------------------------------------===//
3875
3876 // memb(Rs+#u6:0) += #U5
3877 let AddedComplexity = 30 in
3878 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3879             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
3880             "memb($base+#$offset) += $addend",
3881             []>,
3882             Requires<[HasV4T, UseMEMOP]>;
3883
3884 // memb(Rs+#u6:0) -= #U5
3885 let AddedComplexity = 30 in
3886 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3887             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
3888             "memb($base+#$offset) -= $subend",
3889             []>,
3890             Requires<[HasV4T, UseMEMOP]>;
3891
3892 // memb(Rs+#u6:0) += Rt
3893 let AddedComplexity = 30 in
3894 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3895             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
3896             "memb($base+#$offset) += $addend",
3897             [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
3898                                                  u6_0ImmPred:$offset)),
3899                                 (i32 IntRegs:$addend)),
3900                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3901             Requires<[HasV4T, UseMEMOP]>;
3902
3903 // memb(Rs+#u6:0) -= Rt
3904 let AddedComplexity = 30 in
3905 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3906             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
3907             "memb($base+#$offset) -= $subend",
3908             [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
3909                                                  u6_0ImmPred:$offset)),
3910                                 (i32 IntRegs:$subend)),
3911                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3912             Requires<[HasV4T, UseMEMOP]>;
3913
3914 // memb(Rs+#u6:0) &= Rt
3915 let AddedComplexity = 30 in
3916 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3917             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
3918             "memb($base+#$offset) += $andend",
3919             [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
3920                                                  u6_0ImmPred:$offset)),
3921                                 (i32 IntRegs:$andend)),
3922                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3923             Requires<[HasV4T, UseMEMOP]>;
3924
3925 // memb(Rs+#u6:0) |= Rt
3926 let AddedComplexity = 30 in
3927 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3928             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
3929             "memb($base+#$offset) |= $orend",
3930             [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
3931                                                 u6_0ImmPred:$offset)),
3932                                (i32 IntRegs:$orend)),
3933                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3934             Requires<[HasV4T, UseMEMOP]>;
3935
3936 // memb(Rs+#u6:0) += #U5
3937 let AddedComplexity = 30 in
3938 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
3939             (ins MEMri:$addr, u5Imm:$addend),
3940             "memb($addr) += $addend",
3941             []>,
3942             Requires<[HasV4T, UseMEMOP]>;
3943
3944 // memb(Rs+#u6:0) -= #U5
3945 let AddedComplexity = 30 in
3946 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
3947             (ins MEMri:$addr, u5Imm:$subend),
3948             "memb($addr) -= $subend",
3949             []>,
3950             Requires<[HasV4T, UseMEMOP]>;
3951
3952 // memb(Rs+#u6:0) += Rt
3953 let AddedComplexity = 30 in
3954 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
3955             (ins MEMri:$addr, IntRegs:$addend),
3956             "memb($addr) += $addend",
3957             [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3958                                 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
3959             Requires<[HasV4T, UseMEMOP]>;
3960
3961 // memb(Rs+#u6:0) -= Rt
3962 let AddedComplexity = 30 in
3963 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
3964             (ins MEMri:$addr, IntRegs:$subend),
3965             "memb($addr) -= $subend",
3966             [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
3967                                 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
3968             Requires<[HasV4T, UseMEMOP]>;
3969
3970 // memb(Rs+#u6:0) &= Rt
3971 let AddedComplexity = 30 in
3972 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
3973             (ins MEMri:$addr, IntRegs:$andend),
3974             "memb($addr) &= $andend",
3975             [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
3976                                 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
3977             Requires<[HasV4T, UseMEMOP]>;
3978
3979 // memb(Rs+#u6:0) |= Rt
3980 let AddedComplexity = 30 in
3981 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
3982             (ins MEMri:$addr, IntRegs:$orend),
3983             "memb($addr) |= $orend",
3984             [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
3985                                (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
3986             Requires<[HasV4T, UseMEMOP]>;
3987
3988
3989 //===----------------------------------------------------------------------===//
3990 // XTYPE/PRED +
3991 //===----------------------------------------------------------------------===//
3992
3993 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3994 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3995 // hardware. However, compiler can still implement these patterns through
3996 // appropriate patterns combinations based on current implemented patterns.
3997 // The implemented patterns are: EQ/GT/GTU.
3998 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3999
4000 // Following instruction is not being extended as it results into the
4001 // incorrect code for negative numbers.
4002 // Pd=cmpb.eq(Rs,#u8)
4003
4004 let isCompare = 1 in
4005 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
4006             (ins IntRegs:$src1, u8Imm:$src2),
4007             "$dst = cmpb.eq($src1, #$src2)",
4008             [(set (i1 PredRegs:$dst),
4009                   (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
4010             Requires<[HasV4T]>;
4011
4012 // Pd=cmpb.eq(Rs,Rt)
4013 let isCompare = 1 in
4014 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
4015             (ins IntRegs:$src1, IntRegs:$src2),
4016             "$dst = cmpb.eq($src1, $src2)",
4017             [(set (i1 PredRegs:$dst),
4018                   (seteq (and (xor (i32 IntRegs:$src1),
4019                                    (i32 IntRegs:$src2)), 255), 0))]>,
4020             Requires<[HasV4T]>;
4021
4022 // Pd=cmpb.eq(Rs,Rt)
4023 let isCompare = 1 in
4024 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4025             (ins IntRegs:$src1, IntRegs:$src2),
4026             "$dst = cmpb.eq($src1, $src2)",
4027             [(set (i1 PredRegs:$dst),
4028                   (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4029                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4030             Requires<[HasV4T]>;
4031
4032 // Pd=cmpb.gt(Rs,Rt)
4033 let isCompare = 1 in
4034 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4035             (ins IntRegs:$src1, IntRegs:$src2),
4036             "$dst = cmpb.gt($src1, $src2)",
4037             [(set (i1 PredRegs:$dst),
4038                   (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4039                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4040             Requires<[HasV4T]>;
4041
4042 // Pd=cmpb.gtu(Rs,#u7)
4043 let isCompare = 1 in
4044 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4045             (ins IntRegs:$src1, u7Imm:$src2),
4046             "$dst = cmpb.gtu($src1, #$src2)",
4047             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4048                                               u7ImmPred:$src2))]>,
4049             Requires<[HasV4T]>;
4050
4051 // Pd=cmpb.gtu(Rs,Rt)
4052 let isCompare = 1 in
4053 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4054             (ins IntRegs:$src1, IntRegs:$src2),
4055             "$dst = cmpb.gtu($src1, $src2)",
4056             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4057                                              (and (i32 IntRegs:$src2), 255)))]>,
4058             Requires<[HasV4T]>;
4059
4060 // Following instruction is not being extended as it results into the incorrect
4061 // code for negative numbers.
4062
4063 // Signed half compare(.eq) ri.
4064 // Pd=cmph.eq(Rs,#s8)
4065 let isCompare = 1 in
4066 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4067             (ins IntRegs:$src1, s8Imm:$src2),
4068             "$dst = cmph.eq($src1, #$src2)",
4069             [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4070                                              s8ImmPred:$src2))]>,
4071             Requires<[HasV4T]>;
4072
4073 // Signed half compare(.eq) rr.
4074 // Case 1: xor + and, then compare:
4075 //   r0=xor(r0,r1)
4076 //   r0=and(r0,#0xffff)
4077 //   p0=cmp.eq(r0,#0)
4078 // Pd=cmph.eq(Rs,Rt)
4079 let isCompare = 1 in
4080 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4081             (ins IntRegs:$src1, IntRegs:$src2),
4082             "$dst = cmph.eq($src1, $src2)",
4083             [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4084                                                        (i32 IntRegs:$src2)),
4085                                                   65535), 0))]>,
4086             Requires<[HasV4T]>;
4087
4088 // Signed half compare(.eq) rr.
4089 // Case 2: shift left 16 bits then compare:
4090 //   r0=asl(r0,16)
4091 //   r1=asl(r1,16)
4092 //   p0=cmp.eq(r0,r1)
4093 // Pd=cmph.eq(Rs,Rt)
4094 let isCompare = 1 in
4095 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4096             (ins IntRegs:$src1, IntRegs:$src2),
4097             "$dst = cmph.eq($src1, $src2)",
4098             [(set (i1 PredRegs:$dst),
4099                   (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4100                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4101             Requires<[HasV4T]>;
4102
4103 /* Incorrect Pattern -- immediate should be right shifted before being
4104 used in the cmph.gt instruction.
4105 // Signed half compare(.gt) ri.
4106 // Pd=cmph.gt(Rs,#s8)
4107
4108 let isCompare = 1 in
4109 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4110             (ins IntRegs:$src1, s8Imm:$src2),
4111             "$dst = cmph.gt($src1, #$src2)",
4112             [(set (i1 PredRegs:$dst),
4113                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4114                          s8ImmPred:$src2))]>,
4115             Requires<[HasV4T]>;
4116 */
4117
4118 // Signed half compare(.gt) rr.
4119 // Pd=cmph.gt(Rs,Rt)
4120 let isCompare = 1 in
4121 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4122             (ins IntRegs:$src1, IntRegs:$src2),
4123             "$dst = cmph.gt($src1, $src2)",
4124             [(set (i1 PredRegs:$dst),
4125                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4126                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4127             Requires<[HasV4T]>;
4128
4129 // Unsigned half compare rr (.gtu).
4130 // Pd=cmph.gtu(Rs,Rt)
4131 let isCompare = 1 in
4132 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4133             (ins IntRegs:$src1, IntRegs:$src2),
4134             "$dst = cmph.gtu($src1, $src2)",
4135             [(set (i1 PredRegs:$dst),
4136                   (setugt (and (i32 IntRegs:$src1), 65535),
4137                           (and (i32 IntRegs:$src2), 65535)))]>,
4138             Requires<[HasV4T]>;
4139
4140 // Unsigned half compare ri (.gtu).
4141 // Pd=cmph.gtu(Rs,#u7)
4142 let isCompare = 1 in
4143 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4144             (ins IntRegs:$src1, u7Imm:$src2),
4145             "$dst = cmph.gtu($src1, #$src2)",
4146             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4147                                               u7ImmPred:$src2))]>,
4148             Requires<[HasV4T]>;
4149
4150 //===----------------------------------------------------------------------===//
4151 // XTYPE/PRED -
4152 //===----------------------------------------------------------------------===//
4153
4154 //Deallocate frame and return.
4155 //    dealloc_return
4156 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4157   Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4158   def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4159             "dealloc_return",
4160             []>,
4161             Requires<[HasV4T]>;
4162 }
4163
4164 // Restore registers and dealloc return function call.
4165 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4166   Defs = [R29, R30, R31, PC] in {
4167   def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4168                                    (ins calltarget:$dst),
4169              "jump $dst // Restore_and_dealloc_return",
4170              []>,
4171              Requires<[HasV4T]>;
4172 }
4173
4174 // Restore registers and dealloc frame before a tail call.
4175 let isCall = 1, isBarrier = 1,
4176   Defs = [R29, R30, R31, PC] in {
4177   def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4178                                            (ins calltarget:$dst),
4179              "call $dst // Restore_and_dealloc_before_tailcall",
4180              []>,
4181              Requires<[HasV4T]>;
4182 }
4183
4184 // Save registers function call.
4185 let isCall = 1, isBarrier = 1,
4186   Uses = [R29, R31] in {
4187   def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4188                                (ins calltarget:$dst),
4189              "call $dst // Save_calle_saved_registers",
4190              []>,
4191              Requires<[HasV4T]>;
4192 }
4193
4194 //    if (Ps) dealloc_return
4195 let isReturn = 1, isTerminator = 1,
4196     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4197     isPredicated = 1 in {
4198   def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4199                            (ins PredRegs:$src1, i32imm:$amt1),
4200             "if ($src1) dealloc_return",
4201             []>,
4202             Requires<[HasV4T]>;
4203 }
4204
4205 //    if (!Ps) dealloc_return
4206 let isReturn = 1, isTerminator = 1,
4207     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4208     isPredicated = 1 in {
4209   def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4210                                                      i32imm:$amt1),
4211             "if (!$src1) dealloc_return",
4212             []>,
4213             Requires<[HasV4T]>;
4214 }
4215
4216 //    if (Ps.new) dealloc_return:nt
4217 let isReturn = 1, isTerminator = 1,
4218     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4219     isPredicated = 1 in {
4220   def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4221                                                      i32imm:$amt1),
4222             "if ($src1.new) dealloc_return:nt",
4223             []>,
4224             Requires<[HasV4T]>;
4225 }
4226
4227 //    if (!Ps.new) dealloc_return:nt
4228 let isReturn = 1, isTerminator = 1,
4229     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4230     isPredicated = 1 in {
4231   def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4232                                                         i32imm:$amt1),
4233             "if (!$src1.new) dealloc_return:nt",
4234             []>,
4235             Requires<[HasV4T]>;
4236 }
4237
4238 //    if (Ps.new) dealloc_return:t
4239 let isReturn = 1, isTerminator = 1,
4240     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4241     isPredicated = 1 in {
4242   def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4243                                                     i32imm:$amt1),
4244             "if ($src1.new) dealloc_return:t",
4245             []>,
4246             Requires<[HasV4T]>;
4247 }
4248
4249 //    if (!Ps.new) dealloc_return:nt
4250 let isReturn = 1, isTerminator = 1,
4251     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4252     isPredicated = 1 in {
4253   def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4254                                                        i32imm:$amt1),
4255             "if (!$src1.new) dealloc_return:t",
4256             []>,
4257             Requires<[HasV4T]>;
4258 }
4259
4260
4261 // Load/Store with absolute addressing mode
4262 // memw(#u6)=Rt
4263
4264 multiclass ST_abs<string OpcStr> {
4265   let isPredicable = 1 in
4266   def _abs_V4 : STInst2<(outs),
4267             (ins globaladdress:$absaddr, IntRegs:$src),
4268             !strconcat(OpcStr, "(##$absaddr) = $src"),
4269             []>,
4270             Requires<[HasV4T]>;
4271
4272   let isPredicated = 1 in
4273   def _abs_cPt_V4 : STInst2<(outs),
4274             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4275             !strconcat("if ($src1)",
4276             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4277             []>,
4278             Requires<[HasV4T]>;
4279
4280   let isPredicated = 1 in
4281   def _abs_cNotPt_V4 : STInst2<(outs),
4282             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4283             !strconcat("if (!$src1)",
4284             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4285             []>,
4286             Requires<[HasV4T]>;
4287
4288   let isPredicated = 1 in
4289   def _abs_cdnPt_V4 : STInst2<(outs),
4290             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4291             !strconcat("if ($src1.new)",
4292             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4293             []>,
4294             Requires<[HasV4T]>;
4295
4296   let isPredicated = 1 in
4297   def _abs_cdnNotPt_V4 : STInst2<(outs),
4298             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4299             !strconcat("if (!$src1.new)",
4300             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4301             []>,
4302             Requires<[HasV4T]>;
4303
4304   def _abs_nv_V4 : STInst2<(outs),
4305             (ins globaladdress:$absaddr, IntRegs:$src),
4306             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4307             []>,
4308             Requires<[HasV4T]>;
4309
4310   let isPredicated = 1 in
4311   def _abs_cPt_nv_V4 : STInst2<(outs),
4312             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4313             !strconcat("if ($src1)",
4314             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4315             []>,
4316             Requires<[HasV4T]>;
4317
4318   let isPredicated = 1 in
4319   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4320             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4321             !strconcat("if (!$src1)",
4322             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4323             []>,
4324             Requires<[HasV4T]>;
4325
4326   let isPredicated = 1 in
4327   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4328             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4329             !strconcat("if ($src1.new)",
4330             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4331             []>,
4332             Requires<[HasV4T]>;
4333
4334   let isPredicated = 1 in
4335   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4336             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4337             !strconcat("if (!$src1.new)",
4338             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4339             []>,
4340             Requires<[HasV4T]>;
4341 }
4342
4343 let AddedComplexity = 30, isPredicable = 1 in
4344 def STrid_abs_V4 : STInst<(outs),
4345           (ins globaladdress:$absaddr, DoubleRegs:$src),
4346            "memd(##$absaddr) = $src",
4347           [(store (i64 DoubleRegs:$src),
4348                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
4349           Requires<[HasV4T]>;
4350
4351 let AddedComplexity = 30, isPredicated = 1 in
4352 def STrid_abs_cPt_V4 : STInst2<(outs),
4353           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4354           "if ($src1) memd(##$absaddr) = $src2",
4355           []>,
4356           Requires<[HasV4T]>;
4357
4358 let AddedComplexity = 30, isPredicated = 1 in
4359 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4360           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4361           "if (!$src1) memd(##$absaddr) = $src2",
4362           []>,
4363           Requires<[HasV4T]>;
4364
4365 let AddedComplexity = 30, isPredicated = 1 in
4366 def STrid_abs_cdnPt_V4 : STInst2<(outs),
4367           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4368           "if ($src1.new) memd(##$absaddr) = $src2",
4369           []>,
4370           Requires<[HasV4T]>;
4371
4372 let AddedComplexity = 30, isPredicated = 1 in
4373 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
4374           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4375           "if (!$src1.new) memd(##$absaddr) = $src2",
4376           []>,
4377           Requires<[HasV4T]>;
4378
4379 defm STrib : ST_abs<"memb">;
4380 defm STrih : ST_abs<"memh">;
4381 defm STriw : ST_abs<"memw">;
4382
4383 let Predicates = [HasV4T], AddedComplexity  = 30 in
4384 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
4385                         (HexagonCONST32 tglobaladdr:$absaddr)),
4386           (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4387
4388 let Predicates = [HasV4T], AddedComplexity  = 30 in
4389 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
4390                           (HexagonCONST32 tglobaladdr:$absaddr)),
4391           (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4392
4393 let Predicates = [HasV4T], AddedComplexity  = 30 in
4394 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
4395           (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4396
4397
4398 multiclass LD_abs<string OpcStr> {
4399   let isPredicable = 1 in
4400   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4401             (ins globaladdress:$absaddr),
4402             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
4403             []>,
4404             Requires<[HasV4T]>;
4405
4406   let isPredicated = 1 in
4407   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4408             (ins PredRegs:$src1, globaladdress:$absaddr),
4409             !strconcat("if ($src1) $dst = ",
4410             !strconcat(OpcStr, "(##$absaddr)")),
4411             []>,
4412             Requires<[HasV4T]>;
4413
4414   let isPredicated = 1 in
4415   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4416             (ins PredRegs:$src1, globaladdress:$absaddr),
4417             !strconcat("if (!$src1) $dst = ",
4418             !strconcat(OpcStr, "(##$absaddr)")),
4419             []>,
4420             Requires<[HasV4T]>;
4421
4422   let isPredicated = 1 in
4423   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4424             (ins PredRegs:$src1, globaladdress:$absaddr),
4425             !strconcat("if ($src1.new) $dst = ",
4426             !strconcat(OpcStr, "(##$absaddr)")),
4427             []>,
4428             Requires<[HasV4T]>;
4429
4430   let isPredicated = 1 in
4431   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4432             (ins PredRegs:$src1, globaladdress:$absaddr),
4433             !strconcat("if (!$src1.new) $dst = ",
4434             !strconcat(OpcStr, "(##$absaddr)")),
4435             []>,
4436             Requires<[HasV4T]>;
4437 }
4438
4439 let AddedComplexity = 30 in
4440 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
4441           (ins globaladdress:$absaddr),
4442           "$dst = memd(##$absaddr)",
4443           [(set (i64 DoubleRegs:$dst),
4444                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
4445           Requires<[HasV4T]>;
4446
4447 let AddedComplexity = 30, isPredicated = 1 in
4448 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4449           (ins PredRegs:$src1, globaladdress:$absaddr),
4450           "if ($src1) $dst = memd(##$absaddr)",
4451           []>,
4452           Requires<[HasV4T]>;
4453
4454 let AddedComplexity = 30, isPredicated = 1 in
4455 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4456           (ins PredRegs:$src1, globaladdress:$absaddr),
4457           "if (!$src1) $dst = memd(##$absaddr)",
4458           []>,
4459           Requires<[HasV4T]>;
4460
4461 let AddedComplexity = 30, isPredicated = 1 in
4462 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4463           (ins PredRegs:$src1, globaladdress:$absaddr),
4464           "if ($src1.new) $dst = memd(##$absaddr)",
4465           []>,
4466           Requires<[HasV4T]>;
4467
4468 let AddedComplexity = 30, isPredicated = 1 in
4469 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4470           (ins PredRegs:$src1, globaladdress:$absaddr),
4471           "if (!$src1.new) $dst = memd(##$absaddr)",
4472           []>,
4473           Requires<[HasV4T]>;
4474
4475 defm LDrib : LD_abs<"memb">;
4476 defm LDriub : LD_abs<"memub">;
4477 defm LDrih : LD_abs<"memh">;
4478 defm LDriuh : LD_abs<"memuh">;
4479 defm LDriw : LD_abs<"memw">;
4480
4481
4482 let Predicates = [HasV4T], AddedComplexity  = 30 in
4483 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
4484           (LDriw_abs_V4 tglobaladdr: $absaddr)>;
4485
4486 let Predicates = [HasV4T], AddedComplexity=30 in
4487 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4488           (LDrib_abs_V4 tglobaladdr:$absaddr)>;
4489
4490 let Predicates = [HasV4T], AddedComplexity=30 in
4491 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4492           (LDriub_abs_V4 tglobaladdr:$absaddr)>;
4493
4494 let Predicates = [HasV4T], AddedComplexity=30 in
4495 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4496           (LDrih_abs_V4 tglobaladdr:$absaddr)>;
4497
4498 let Predicates = [HasV4T], AddedComplexity=30 in
4499 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4500           (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
4501
4502 // Transfer global address into a register
4503 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
4504 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
4505            "$dst = ##$src1",
4506            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
4507            Requires<[HasV4T]>;
4508
4509 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4510 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4511                            (ins PredRegs:$src1, globaladdress:$src2),
4512            "if($src1) $dst = ##$src2",
4513            []>,
4514            Requires<[HasV4T]>;
4515
4516 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4517 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4518                               (ins PredRegs:$src1, globaladdress:$src2),
4519            "if(!$src1) $dst = ##$src2",
4520            []>,
4521            Requires<[HasV4T]>;
4522
4523 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4524 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4525                              (ins PredRegs:$src1, globaladdress:$src2),
4526            "if($src1.new) $dst = ##$src2",
4527            []>,
4528            Requires<[HasV4T]>;
4529
4530 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4531 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4532                                 (ins PredRegs:$src1, globaladdress:$src2),
4533            "if(!$src1.new) $dst = ##$src2",
4534            []>,
4535            Requires<[HasV4T]>;
4536
4537 let AddedComplexity = 50, Predicates = [HasV4T] in
4538 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
4539            (TFRI_V4 tglobaladdr:$src1)>;
4540
4541
4542 // Load - Indirect with long offset: These instructions take global address
4543 // as an operand
4544 let AddedComplexity = 10 in
4545 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
4546             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4547             "$dst=memd($src1<<#$src2+##$offset)",
4548             [(set (i64 DoubleRegs:$dst),
4549                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
4550                         (HexagonCONST32 tglobaladdr:$offset))))]>,
4551             Requires<[HasV4T]>;
4552
4553 let AddedComplexity = 10 in
4554 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
4555   def _lo_V4 : LDInst<(outs IntRegs:$dst),
4556             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4557             !strconcat("$dst = ",
4558             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
4559             [(set IntRegs:$dst,
4560                   (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
4561                           (HexagonCONST32 tglobaladdr:$offset)))))]>,
4562             Requires<[HasV4T]>;
4563 }
4564
4565 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
4566 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
4567 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
4568 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
4569 defm LDriw_ind : LD_indirect_lo<"memw", load>;
4570
4571 // Store - Indirect with long offset: These instructions take global address
4572 // as an operand
4573 let AddedComplexity = 10 in
4574 def STrid_ind_lo_V4 : STInst<(outs),
4575             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4576                  DoubleRegs:$src4),
4577             "memd($src1<<#$src2+#$src3) = $src4",
4578             [(store (i64 DoubleRegs:$src4),
4579                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4580                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4581              Requires<[HasV4T]>;
4582
4583 let AddedComplexity = 10 in
4584 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
4585   def _lo_V4 : STInst<(outs),
4586             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4587                  IntRegs:$src4),
4588             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
4589             [(OpNode (i32 IntRegs:$src4),
4590                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4591                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4592              Requires<[HasV4T]>;
4593 }
4594
4595 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
4596 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
4597 defm STriw_ind : ST_indirect_lo<"memw", store>;
4598
4599 // Store - absolute addressing mode: These instruction take constant
4600 // value as the extended operand
4601 multiclass ST_absimm<string OpcStr> {
4602   let isPredicable = 1 in
4603   def _abs_V4 : STInst2<(outs),
4604             (ins u6Imm:$src1, IntRegs:$src2),
4605             !strconcat(OpcStr, "(#$src1) = $src2"),
4606             []>,
4607             Requires<[HasV4T]>;
4608
4609   let isPredicated = 1 in
4610   def _abs_cPt_V4 : STInst2<(outs),
4611             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4612             !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4613             []>,
4614             Requires<[HasV4T]>;
4615
4616   let isPredicated = 1 in
4617   def _abs_cNotPt_V4 : STInst2<(outs),
4618             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4619             !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4620             []>,
4621             Requires<[HasV4T]>;
4622
4623   let isPredicated = 1 in
4624   def _abs_cdnPt_V4 : STInst2<(outs),
4625             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4626             !strconcat("if ($src1.new)",
4627             !strconcat(OpcStr, "(#$src2) = $src3")),
4628             []>,
4629             Requires<[HasV4T]>;
4630
4631   let isPredicated = 1 in
4632   def _abs_cdnNotPt_V4 : STInst2<(outs),
4633             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4634             !strconcat("if (!$src1.new)",
4635             !strconcat(OpcStr, "(#$src2) = $src3")),
4636             []>,
4637             Requires<[HasV4T]>;
4638
4639   def _abs_nv_V4 : STInst2<(outs),
4640             (ins u6Imm:$src1, IntRegs:$src2),
4641             !strconcat(OpcStr, "(#$src1) = $src2.new"),
4642             []>,
4643             Requires<[HasV4T]>;
4644
4645   let isPredicated = 1 in
4646   def _abs_cPt_nv_V4 : STInst2<(outs),
4647             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4648             !strconcat("if ($src1)",
4649             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4650             []>,
4651             Requires<[HasV4T]>;
4652
4653   let isPredicated = 1 in
4654   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4655             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4656             !strconcat("if (!$src1)",
4657             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4658             []>,
4659             Requires<[HasV4T]>;
4660
4661   let isPredicated = 1 in
4662   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4663             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4664             !strconcat("if ($src1.new)",
4665             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4666             []>,
4667             Requires<[HasV4T]>;
4668
4669   let isPredicated = 1 in
4670   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4671             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4672             !strconcat("if (!$src1.new)",
4673             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4674             []>,
4675             Requires<[HasV4T]>;
4676 }
4677
4678 defm STrib_imm : ST_absimm<"memb">;
4679 defm STrih_imm : ST_absimm<"memh">;
4680 defm STriw_imm : ST_absimm<"memw">;
4681
4682 let Predicates = [HasV4T], AddedComplexity  = 30 in
4683 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
4684           (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4685
4686 let Predicates = [HasV4T], AddedComplexity  = 30 in
4687 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
4688           (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4689
4690 let Predicates = [HasV4T], AddedComplexity  = 30 in
4691 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
4692           (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4693
4694
4695 // Load - absolute addressing mode: These instruction take constant
4696 // value as the extended operand
4697
4698 multiclass LD_absimm<string OpcStr> {
4699   let isPredicable = 1 in
4700   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4701             (ins u6Imm:$src),
4702             !strconcat("$dst = ",
4703             !strconcat(OpcStr, "(#$src)")),
4704             []>,
4705             Requires<[HasV4T]>;
4706
4707   let isPredicated = 1 in
4708   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4709             (ins PredRegs:$src1, u6Imm:$src2),
4710             !strconcat("if ($src1) $dst = ",
4711             !strconcat(OpcStr, "(#$src2)")),
4712             []>,
4713             Requires<[HasV4T]>;
4714
4715   let isPredicated = 1 in
4716   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4717             (ins PredRegs:$src1, u6Imm:$src2),
4718             !strconcat("if (!$src1) $dst = ",
4719             !strconcat(OpcStr, "(#$src2)")),
4720             []>,
4721             Requires<[HasV4T]>;
4722
4723   let isPredicated = 1 in
4724   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4725             (ins PredRegs:$src1, u6Imm:$src2),
4726             !strconcat("if ($src1.new) $dst = ",
4727             !strconcat(OpcStr, "(#$src2)")),
4728             []>,
4729             Requires<[HasV4T]>;
4730
4731   let isPredicated = 1 in
4732   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4733             (ins PredRegs:$src1, u6Imm:$src2),
4734             !strconcat("if (!$src1.new) $dst = ",
4735             !strconcat(OpcStr, "(#$src2)")),
4736             []>,
4737             Requires<[HasV4T]>;
4738 }
4739
4740 defm LDrib_imm : LD_absimm<"memb">;
4741 defm LDriub_imm : LD_absimm<"memub">;
4742 defm LDrih_imm : LD_absimm<"memh">;
4743 defm LDriuh_imm : LD_absimm<"memuh">;
4744 defm LDriw_imm : LD_absimm<"memw">;
4745
4746 let Predicates = [HasV4T], AddedComplexity  = 30 in
4747 def : Pat<(i32 (load u6ImmPred:$src)),
4748           (LDriw_imm_abs_V4 u6ImmPred:$src)>;
4749
4750 let Predicates = [HasV4T], AddedComplexity=30 in
4751 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
4752           (LDrib_imm_abs_V4 u6ImmPred:$src)>;
4753
4754 let Predicates = [HasV4T], AddedComplexity=30 in
4755 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
4756           (LDriub_imm_abs_V4 u6ImmPred:$src)>;
4757
4758 let Predicates = [HasV4T], AddedComplexity=30 in
4759 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
4760           (LDrih_imm_abs_V4 u6ImmPred:$src)>;
4761
4762 let Predicates = [HasV4T], AddedComplexity=30 in
4763 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
4764           (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
4765
4766
4767 // Indexed store double word - global address.
4768 // memw(Rs+#u6:2)=#S8
4769 let AddedComplexity = 10 in
4770 def STriw_offset_ext_V4 : STInst<(outs),
4771             (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
4772             "memw($src1+#$src2) = ##$src3",
4773             [(store (HexagonCONST32 tglobaladdr:$src3),
4774                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
4775             Requires<[HasV4T]>;
4776
4777
4778 // Indexed store double word - global address.
4779 // memw(Rs+#u6:2)=#S8
4780 let AddedComplexity = 10 in
4781 def STrih_offset_ext_V4 : STInst<(outs),
4782             (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
4783             "memh($src1+#$src2) = ##$src3",
4784             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
4785                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
4786             Requires<[HasV4T]>;