1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in
15 class T_Immext<dag ins> :
16 EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
20 def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
21 def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
22 def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
24 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
25 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
27 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
28 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
30 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
31 (HexagonCONST32 node:$addr), [{
32 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
35 // Hexagon V4 Architecture spec defines 8 instruction classes:
36 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
40 // ========================================
41 // Loads (8/16/32/64 bit)
45 // ========================================
46 // Stores (8/16/32/64 bit)
49 // ALU32 Instructions:
50 // ========================================
51 // Arithmetic / Logical (32 bit)
54 // XTYPE Instructions (32/64 bit):
55 // ========================================
56 // Arithmetic, Logical, Bit Manipulation
57 // Multiply (Integer, Fractional, Complex)
58 // Permute / Vector Permute Operations
59 // Predicate Operations
60 // Shift / Shift with Add/Sub/Logical
62 // Vector Halfword (ALU, Shift, Multiply)
63 // Vector Word (ALU, Shift)
66 // ========================================
67 // Jump/Call PC-relative
70 // ========================================
73 // MEMOP Instructions:
74 // ========================================
75 // Operation on memory (8/16/32 bit)
78 // ========================================
83 // ========================================
84 // Control-Register Transfers
85 // Hardware Loop Setup
86 // Predicate Logicals & Reductions
88 // SYSTEM Instructions (not implemented in the compiler):
89 // ========================================
95 //===----------------------------------------------------------------------===//
97 //===----------------------------------------------------------------------===//
101 let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
102 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
103 (ins PredRegs:$src1, IntRegs:$src2),
104 "if ($src1) $dst = aslh($src2)",
108 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
109 (ins PredRegs:$src1, IntRegs:$src2),
110 "if (!$src1) $dst = aslh($src2)",
114 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
115 (ins PredRegs:$src1, IntRegs:$src2),
116 "if ($src1.new) $dst = aslh($src2)",
120 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
121 (ins PredRegs:$src1, IntRegs:$src2),
122 "if (!$src1.new) $dst = aslh($src2)",
126 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
127 (ins PredRegs:$src1, IntRegs:$src2),
128 "if ($src1) $dst = asrh($src2)",
132 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
133 (ins PredRegs:$src1, IntRegs:$src2),
134 "if (!$src1) $dst = asrh($src2)",
138 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
139 (ins PredRegs:$src1, IntRegs:$src2),
140 "if ($src1.new) $dst = asrh($src2)",
144 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
145 (ins PredRegs:$src1, IntRegs:$src2),
146 "if (!$src1.new) $dst = asrh($src2)",
153 let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
154 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
155 (ins PredRegs:$src1, IntRegs:$src2),
156 "if ($src1) $dst = sxtb($src2)",
160 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
161 (ins PredRegs:$src1, IntRegs:$src2),
162 "if (!$src1) $dst = sxtb($src2)",
166 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
167 (ins PredRegs:$src1, IntRegs:$src2),
168 "if ($src1.new) $dst = sxtb($src2)",
172 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
173 (ins PredRegs:$src1, IntRegs:$src2),
174 "if (!$src1.new) $dst = sxtb($src2)",
179 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
180 (ins PredRegs:$src1, IntRegs:$src2),
181 "if ($src1) $dst = sxth($src2)",
185 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
186 (ins PredRegs:$src1, IntRegs:$src2),
187 "if (!$src1) $dst = sxth($src2)",
191 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
192 (ins PredRegs:$src1, IntRegs:$src2),
193 "if ($src1.new) $dst = sxth($src2)",
197 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
198 (ins PredRegs:$src1, IntRegs:$src2),
199 "if (!$src1.new) $dst = sxth($src2)",
206 let neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in {
207 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
208 (ins PredRegs:$src1, IntRegs:$src2),
209 "if ($src1) $dst = zxtb($src2)",
213 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
214 (ins PredRegs:$src1, IntRegs:$src2),
215 "if (!$src1) $dst = zxtb($src2)",
219 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
220 (ins PredRegs:$src1, IntRegs:$src2),
221 "if ($src1.new) $dst = zxtb($src2)",
225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
226 (ins PredRegs:$src1, IntRegs:$src2),
227 "if (!$src1.new) $dst = zxtb($src2)",
231 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
232 (ins PredRegs:$src1, IntRegs:$src2),
233 "if ($src1) $dst = zxth($src2)",
237 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
238 (ins PredRegs:$src1, IntRegs:$src2),
239 "if (!$src1) $dst = zxth($src2)",
243 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
244 (ins PredRegs:$src1, IntRegs:$src2),
245 "if ($src1.new) $dst = zxth($src2)",
249 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
250 (ins PredRegs:$src1, IntRegs:$src2),
251 "if (!$src1.new) $dst = zxth($src2)",
256 // Generate frame index addresses.
257 let neverHasSideEffects = 1, isReMaterializable = 1,
258 isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
259 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
260 (ins IntRegs:$src1, s32Imm:$offset),
261 "$dst = add($src1, ##$offset)",
266 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
267 isExtentSigned = 1, opExtentBits = 8 in
268 def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
269 (ins IntRegs:$Rs, s8Ext:$s8),
270 "$Rd = cmp.eq($Rs, #$s8)",
271 [(set (i32 IntRegs:$Rd),
272 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
273 s8ExtPred:$s8)))))]>,
276 // Preserve the TSTBIT generation
277 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
278 (i32 IntRegs:$src1))), 0)))),
279 (i32 (MUX_ii (i1 (TSTBIT_rr (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
282 // Interfered with tstbit generation, above pattern preserves, see : tstbit.ll
284 let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
285 isExtentSigned = 1, opExtentBits = 8 in
286 def V4_A4_rcmpneqi : ALU32_ri<(outs IntRegs:$Rd),
287 (ins IntRegs:$Rs, s8Ext:$s8),
288 "$Rd = !cmp.eq($Rs, #$s8)",
289 [(set (i32 IntRegs:$Rd),
290 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
291 s8ExtPred:$s8)))))]>,
295 let validSubTargets = HasV4SubT in
296 def V4_A4_rcmpeq : ALU32_ri<(outs IntRegs:$Rd),
297 (ins IntRegs:$Rs, IntRegs:$Rt),
298 "$Rd = cmp.eq($Rs, $Rt)",
299 [(set (i32 IntRegs:$Rd),
300 (i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
305 let validSubTargets = HasV4SubT in
306 def V4_A4_rcmpneq : ALU32_ri<(outs IntRegs:$Rd),
307 (ins IntRegs:$Rs, IntRegs:$Rt),
308 "$Rd = !cmp.eq($Rs, $Rt)",
309 [(set (i32 IntRegs:$Rd),
310 (i32 (zext (i1 (setne (i32 IntRegs:$Rs),
314 //===----------------------------------------------------------------------===//
316 //===----------------------------------------------------------------------===//
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
324 // Rdd=combine(Rs, #s8)
325 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
326 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
327 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
328 (ins IntRegs:$src1, s8Ext:$src2),
329 "$dst = combine($src1, #$src2)",
333 // Rdd=combine(#s8, Rs)
334 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
335 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
336 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
337 (ins s8Ext:$src1, IntRegs:$src2),
338 "$dst = combine(#$src1, $src2)",
342 def HexagonWrapperCombineRI_V4 :
343 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
344 def HexagonWrapperCombineIR_V4 :
345 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
347 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
348 (COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>,
351 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
352 (COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>,
355 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
356 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
357 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
358 (ins s8Imm:$src1, u6Ext:$src2),
359 "$dst = combine(#$src1, #$src2)",
363 //===----------------------------------------------------------------------===//
365 //===----------------------------------------------------------------------===//
367 //===----------------------------------------------------------------------===//
369 //===----------------------------------------------------------------------===//
371 // These absolute set addressing mode instructions accept immediate as
372 // an operand. We have duplicated these patterns to take global address.
374 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
375 validSubTargets = HasV4SubT in {
376 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
377 (ins u0AlwaysExt:$addr),
378 "$dst1 = memd($dst2=##$addr)",
383 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
384 (ins u0AlwaysExt:$addr),
385 "$dst1 = memb($dst2=##$addr)",
390 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
391 (ins u0AlwaysExt:$addr),
392 "$dst1 = memh($dst2=##$addr)",
397 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
398 (ins u0AlwaysExt:$addr),
399 "$dst1 = memub($dst2=##$addr)",
404 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
405 (ins u0AlwaysExt:$addr),
406 "$dst1 = memuh($dst2=##$addr)",
411 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
412 (ins u0AlwaysExt:$addr),
413 "$dst1 = memw($dst2=##$addr)",
418 // Following patterns are defined for absolute set addressing mode
419 // instruction which take global address as operand.
420 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
421 validSubTargets = HasV4SubT in {
422 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
423 (ins globaladdressExt:$addr),
424 "$dst1 = memd($dst2=##$addr)",
429 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
430 (ins globaladdressExt:$addr),
431 "$dst1 = memb($dst2=##$addr)",
436 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
437 (ins globaladdressExt:$addr),
438 "$dst1 = memh($dst2=##$addr)",
443 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
444 (ins globaladdressExt:$addr),
445 "$dst1 = memub($dst2=##$addr)",
450 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
451 (ins globaladdressExt:$addr),
452 "$dst1 = memuh($dst2=##$addr)",
457 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
458 (ins globaladdressExt:$addr),
459 "$dst1 = memw($dst2=##$addr)",
464 // multiclass for load instructions with base + register offset
466 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
468 let PNewValue = !if(isPredNew, "new", "") in
469 def NAME : LDInst2<(outs RC:$dst),
470 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
471 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
472 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
473 []>, Requires<[HasV4T]>;
476 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
477 let PredSense = !if(PredNot, "false", "true") in {
478 defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
480 defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
484 let neverHasSideEffects = 1 in
485 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
486 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
487 let isPredicable = 1 in
488 def NAME#_V4 : LDInst2<(outs RC:$dst),
489 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
490 "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
491 []>, Requires<[HasV4T]>;
493 let isPredicated = 1 in {
494 defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
495 defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
500 let addrMode = BaseRegOffset in {
501 defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
502 defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
503 defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
504 defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
505 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
506 defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
509 // 'def pats' for load instructions with base + register offset and non-zero
510 // immediate value. Immediate value is used to left-shift the second
512 let AddedComplexity = 40 in {
513 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
514 (shl IntRegs:$src2, u2ImmPred:$offset)))),
515 (LDrib_indexed_shl_V4 IntRegs:$src1,
516 IntRegs:$src2, u2ImmPred:$offset)>,
519 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
520 (shl IntRegs:$src2, u2ImmPred:$offset)))),
521 (LDriub_indexed_shl_V4 IntRegs:$src1,
522 IntRegs:$src2, u2ImmPred:$offset)>,
525 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
526 (shl IntRegs:$src2, u2ImmPred:$offset)))),
527 (LDriub_indexed_shl_V4 IntRegs:$src1,
528 IntRegs:$src2, u2ImmPred:$offset)>,
531 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
532 (shl IntRegs:$src2, u2ImmPred:$offset)))),
533 (LDrih_indexed_shl_V4 IntRegs:$src1,
534 IntRegs:$src2, u2ImmPred:$offset)>,
537 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
538 (shl IntRegs:$src2, u2ImmPred:$offset)))),
539 (LDriuh_indexed_shl_V4 IntRegs:$src1,
540 IntRegs:$src2, u2ImmPred:$offset)>,
543 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
544 (shl IntRegs:$src2, u2ImmPred:$offset)))),
545 (LDriuh_indexed_shl_V4 IntRegs:$src1,
546 IntRegs:$src2, u2ImmPred:$offset)>,
549 def : Pat <(i32 (load (add IntRegs:$src1,
550 (shl IntRegs:$src2, u2ImmPred:$offset)))),
551 (LDriw_indexed_shl_V4 IntRegs:$src1,
552 IntRegs:$src2, u2ImmPred:$offset)>,
555 def : Pat <(i64 (load (add IntRegs:$src1,
556 (shl IntRegs:$src2, u2ImmPred:$offset)))),
557 (LDrid_indexed_shl_V4 IntRegs:$src1,
558 IntRegs:$src2, u2ImmPred:$offset)>,
563 // 'def pats' for load instruction base + register offset and
564 // zero immediate value.
565 let AddedComplexity = 10 in {
566 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
567 (LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
570 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
571 (LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
574 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
575 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
578 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
579 (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
582 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
583 (LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
586 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
587 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
590 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
591 (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
594 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
595 (LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
599 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
600 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
601 (ins globaladdress:$global),
602 "$dst=memd(#$global)",
606 // if (Pv) Rtt=memd(##global)
607 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
608 validSubTargets = HasV4SubT in {
609 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
610 (ins PredRegs:$src1, globaladdress:$global),
611 "if ($src1) $dst=memd(##$global)",
616 // if (!Pv) Rtt=memd(##global)
617 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
618 (ins PredRegs:$src1, globaladdress:$global),
619 "if (!$src1) $dst=memd(##$global)",
623 // if (Pv) Rtt=memd(##global)
624 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
625 (ins PredRegs:$src1, globaladdress:$global),
626 "if ($src1.new) $dst=memd(##$global)",
631 // if (!Pv) Rtt=memd(##global)
632 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
633 (ins PredRegs:$src1, globaladdress:$global),
634 "if (!$src1.new) $dst=memd(##$global)",
639 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
640 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
641 (ins globaladdress:$global),
642 "$dst=memb(#$global)",
646 // if (Pv) Rt=memb(##global)
647 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
648 validSubTargets = HasV4SubT in {
649 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
650 (ins PredRegs:$src1, globaladdress:$global),
651 "if ($src1) $dst=memb(##$global)",
655 // if (!Pv) Rt=memb(##global)
656 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
657 (ins PredRegs:$src1, globaladdress:$global),
658 "if (!$src1) $dst=memb(##$global)",
662 // if (Pv) Rt=memb(##global)
663 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
664 (ins PredRegs:$src1, globaladdress:$global),
665 "if ($src1.new) $dst=memb(##$global)",
669 // if (!Pv) Rt=memb(##global)
670 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
671 (ins PredRegs:$src1, globaladdress:$global),
672 "if (!$src1.new) $dst=memb(##$global)",
677 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
678 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
679 (ins globaladdress:$global),
680 "$dst=memub(#$global)",
684 // if (Pv) Rt=memub(##global)
685 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
686 validSubTargets = HasV4SubT in {
687 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
688 (ins PredRegs:$src1, globaladdress:$global),
689 "if ($src1) $dst=memub(##$global)",
694 // if (!Pv) Rt=memub(##global)
695 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
696 (ins PredRegs:$src1, globaladdress:$global),
697 "if (!$src1) $dst=memub(##$global)",
701 // if (Pv) Rt=memub(##global)
702 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
703 (ins PredRegs:$src1, globaladdress:$global),
704 "if ($src1.new) $dst=memub(##$global)",
709 // if (!Pv) Rt=memub(##global)
710 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
711 (ins PredRegs:$src1, globaladdress:$global),
712 "if (!$src1.new) $dst=memub(##$global)",
717 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
718 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
719 (ins globaladdress:$global),
720 "$dst=memh(#$global)",
724 // if (Pv) Rt=memh(##global)
725 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
726 validSubTargets = HasV4SubT in {
727 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
728 (ins PredRegs:$src1, globaladdress:$global),
729 "if ($src1) $dst=memh(##$global)",
733 // if (!Pv) Rt=memh(##global)
734 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
735 (ins PredRegs:$src1, globaladdress:$global),
736 "if (!$src1) $dst=memh(##$global)",
740 // if (Pv) Rt=memh(##global)
741 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
742 (ins PredRegs:$src1, globaladdress:$global),
743 "if ($src1.new) $dst=memh(##$global)",
747 // if (!Pv) Rt=memh(##global)
748 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
749 (ins PredRegs:$src1, globaladdress:$global),
750 "if (!$src1.new) $dst=memh(##$global)",
755 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
756 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
757 (ins globaladdress:$global),
758 "$dst=memuh(#$global)",
762 // if (Pv) Rt=memuh(##global)
763 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
764 validSubTargets = HasV4SubT in {
765 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
766 (ins PredRegs:$src1, globaladdress:$global),
767 "if ($src1) $dst=memuh(##$global)",
771 // if (!Pv) Rt=memuh(##global)
772 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
773 (ins PredRegs:$src1, globaladdress:$global),
774 "if (!$src1) $dst=memuh(##$global)",
778 // if (Pv) Rt=memuh(##global)
779 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
780 (ins PredRegs:$src1, globaladdress:$global),
781 "if ($src1.new) $dst=memuh(##$global)",
785 // if (!Pv) Rt=memuh(##global)
786 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
787 (ins PredRegs:$src1, globaladdress:$global),
788 "if (!$src1.new) $dst=memuh(##$global)",
793 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
794 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
795 (ins globaladdress:$global),
796 "$dst=memw(#$global)",
800 // if (Pv) Rt=memw(##global)
801 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
802 validSubTargets = HasV4SubT in {
803 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
804 (ins PredRegs:$src1, globaladdress:$global),
805 "if ($src1) $dst=memw(##$global)",
810 // if (!Pv) Rt=memw(##global)
811 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
812 (ins PredRegs:$src1, globaladdress:$global),
813 "if (!$src1) $dst=memw(##$global)",
817 // if (Pv) Rt=memw(##global)
818 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
819 (ins PredRegs:$src1, globaladdress:$global),
820 "if ($src1.new) $dst=memw(##$global)",
825 // if (!Pv) Rt=memw(##global)
826 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
827 (ins PredRegs:$src1, globaladdress:$global),
828 "if (!$src1.new) $dst=memw(##$global)",
834 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
835 (i64 (LDd_GP_V4 tglobaladdr:$global))>,
838 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
839 (i32 (LDw_GP_V4 tglobaladdr:$global))>,
842 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
843 (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
846 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
847 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
850 // Map from load(globaladdress) -> memw(#foo + 0)
851 let AddedComplexity = 100 in
852 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
853 (i64 (LDd_GP_V4 tglobaladdr:$global))>,
856 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
857 let AddedComplexity = 100 in
858 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
859 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
862 // When the Interprocedural Global Variable optimizer realizes that a certain
863 // global variable takes only two constant values, it shrinks the global to
864 // a boolean. Catch those loads here in the following 3 patterns.
865 let AddedComplexity = 100 in
866 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
867 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
870 let AddedComplexity = 100 in
871 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
872 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
875 // Map from load(globaladdress) -> memb(#foo)
876 let AddedComplexity = 100 in
877 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
878 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
881 // Map from load(globaladdress) -> memb(#foo)
882 let AddedComplexity = 100 in
883 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
884 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
887 let AddedComplexity = 100 in
888 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
889 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
892 // Map from load(globaladdress) -> memub(#foo)
893 let AddedComplexity = 100 in
894 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
895 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
898 // Map from load(globaladdress) -> memh(#foo)
899 let AddedComplexity = 100 in
900 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
901 (i32 (LDh_GP_V4 tglobaladdr:$global))>,
904 // Map from load(globaladdress) -> memh(#foo)
905 let AddedComplexity = 100 in
906 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
907 (i32 (LDh_GP_V4 tglobaladdr:$global))>,
910 // Map from load(globaladdress) -> memuh(#foo)
911 let AddedComplexity = 100 in
912 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
913 (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
916 // Map from load(globaladdress) -> memw(#foo)
917 let AddedComplexity = 100 in
918 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
919 (i32 (LDw_GP_V4 tglobaladdr:$global))>,
923 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
924 (i64 (COMBINE_Ir_V4 0, (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
928 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
929 (i64 (COMBINE_Ir_V4 0, (i32 IntRegs:$src1)))>,
932 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
933 (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>,
936 let AddedComplexity = 20 in
937 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
938 s11_0ExtPred:$offset))),
939 (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1,
940 s11_0ExtPred:$offset)))>,
944 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
945 (i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>,
948 let AddedComplexity = 20 in
949 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
950 s11_1ExtPred:$offset))),
951 (i64 (COMBINE_Ir_V4 0, (LDriuh_indexed IntRegs:$src1,
952 s11_1ExtPred:$offset)))>,
956 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
957 (i64 (COMBINE_Ir_V4 0, (LDrih ADDRriS11_2:$src1)))>,
960 let AddedComplexity = 20 in
961 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
962 s11_1ExtPred:$offset))),
963 (i64 (COMBINE_Ir_V4 0, (LDrih_indexed IntRegs:$src1,
964 s11_1ExtPred:$offset)))>,
968 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
969 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
972 let AddedComplexity = 100 in
973 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
974 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
975 s11_2ExtPred:$offset)))>,
979 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
980 (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,
983 let AddedComplexity = 100 in
984 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
985 (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,
986 s11_2ExtPred:$offset)))>,
991 //===----------------------------------------------------------------------===//
993 //===----------------------------------------------------------------------===//
995 //===----------------------------------------------------------------------===//
997 //===----------------------------------------------------------------------===//
999 /// Assumptions::: ****** DO NOT IGNORE ********
1000 /// 1. Make sure that in post increment store, the zero'th operand is always the
1001 /// post increment operand.
1002 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1007 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
1008 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1009 (ins DoubleRegs:$src1, u0AlwaysExt:$src2),
1010 "memd($dst1=##$src2) = $src1",
1015 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1016 (ins IntRegs:$src1, u0AlwaysExt:$src2),
1017 "memb($dst1=##$src2) = $src1",
1022 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1023 (ins IntRegs:$src1, u0AlwaysExt:$src2),
1024 "memh($dst1=##$src2) = $src1",
1029 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1030 (ins IntRegs:$src1, u0AlwaysExt:$src2),
1031 "memw($dst1=##$src2) = $src1",
1037 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
1038 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1039 (ins DoubleRegs:$src1, globaladdressExt:$src2),
1040 "memd($dst1=##$src2) = $src1",
1045 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1046 (ins IntRegs:$src1, globaladdressExt:$src2),
1047 "memb($dst1=##$src2) = $src1",
1052 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1053 (ins IntRegs:$src1, globaladdressExt:$src2),
1054 "memh($dst1=##$src2) = $src1",
1059 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1060 (ins IntRegs:$src1, globaladdressExt:$src2),
1061 "memw($dst1=##$src2) = $src1",
1066 // multiclass for store instructions with base + register offset addressing
1068 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1070 let PNewValue = !if(isPredNew, "new", "") in
1071 def NAME : STInst2<(outs),
1072 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1074 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1075 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
1080 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1081 let PredSense = !if(PredNot, "false", "true") in {
1082 defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
1084 defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
1088 let isNVStorable = 1 in
1089 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
1090 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1091 let isPredicable = 1 in
1092 def NAME#_V4 : STInst2<(outs),
1093 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1094 mnemonic#"($src1+$src2<<#$src3) = $src4",
1098 let isPredicated = 1 in {
1099 defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
1100 defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
1105 // multiclass for new-value store instructions with base + register offset
1107 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
1109 let PNewValue = !if(isPredNew, "new", "") in
1110 def NAME#_nv_V4 : NVInst_V4<(outs),
1111 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1113 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1114 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
1119 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
1120 let PredSense = !if(PredNot, "false", "true") in {
1121 defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
1123 defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
1127 let mayStore = 1, isNVStore = 1 in
1128 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
1129 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1130 let isPredicable = 1 in
1131 def NAME#_nv_V4 : NVInst_V4<(outs),
1132 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1133 mnemonic#"($src1+$src2<<#$src3) = $src4.new",
1137 let isPredicated = 1 in {
1138 defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
1139 defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
1144 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
1145 validSubTargets = HasV4SubT in {
1146 defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
1147 ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
1149 defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
1150 ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
1152 defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
1153 ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
1155 let isNVStorable = 0 in
1156 defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
1159 let Predicates = [HasV4T], AddedComplexity = 10 in {
1160 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
1161 (add IntRegs:$src1, (shl IntRegs:$src2,
1163 (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1164 u2ImmPred:$src3, IntRegs:$src4)>;
1166 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
1167 (add IntRegs:$src1, (shl IntRegs:$src2,
1169 (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1170 u2ImmPred:$src3, IntRegs:$src4)>;
1172 def : Pat<(store (i32 IntRegs:$src4),
1173 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1174 (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1175 u2ImmPred:$src3, IntRegs:$src4)>;
1177 def : Pat<(store (i64 DoubleRegs:$src4),
1178 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1179 (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1180 u2ImmPred:$src3, DoubleRegs:$src4)>;
1183 // memd(Ru<<#u2+#U6)=Rtt
1184 let isExtended = 1, opExtendable = 2, AddedComplexity = 10,
1185 validSubTargets = HasV4SubT in
1186 def STrid_shl_V4 : STInst<(outs),
1187 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, DoubleRegs:$src4),
1188 "memd($src1<<#$src2+#$src3) = $src4",
1189 [(store (i64 DoubleRegs:$src4),
1190 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1191 u0AlwaysExtPred:$src3))]>,
1194 // memd(Rx++#s4:3)=Rtt
1195 // memd(Rx++#s4:3:circ(Mu))=Rtt
1196 // memd(Rx++I:circ(Mu))=Rtt
1198 // memd(Rx++Mu:brev)=Rtt
1199 // memd(gp+#u16:3)=Rtt
1201 // Store doubleword conditionally.
1202 // if ([!]Pv[.new]) memd(#u6)=Rtt
1203 // TODO: needs to be implemented.
1205 //===----------------------------------------------------------------------===//
1206 // multiclass for store instructions with base + immediate offset
1207 // addressing mode and immediate stored value.
1208 // mem[bhw](Rx++#s4:3)=#s8
1209 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1210 //===----------------------------------------------------------------------===//
1211 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
1213 let PNewValue = !if(isPredNew, "new", "") in
1214 def NAME : STInst2<(outs),
1215 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
1216 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1217 ") ")#mnemonic#"($src2+#$src3) = #$src4",
1222 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
1223 let PredSense = !if(PredNot, "false", "true") in {
1224 defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
1226 defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
1230 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
1231 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
1232 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1233 let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
1234 def NAME#_V4 : STInst2<(outs),
1235 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
1236 mnemonic#"($src1+#$src2) = #$src3",
1240 let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
1241 defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
1242 defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
1247 let addrMode = BaseImmOffset, InputType = "imm",
1248 validSubTargets = HasV4SubT in {
1249 defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
1250 defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
1251 defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
1254 let Predicates = [HasV4T], AddedComplexity = 10 in {
1255 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1256 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1258 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1259 u6_1ImmPred:$src2)),
1260 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1262 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1263 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1266 let AddedComplexity = 6 in
1267 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1268 (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1271 // memb(Ru<<#u2+#U6)=Rt
1272 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
1273 validSubTargets = HasV4SubT in
1274 def STrib_shl_V4 : STInst<(outs),
1275 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1276 "memb($src1<<#$src2+#$src3) = $src4",
1277 [(truncstorei8 (i32 IntRegs:$src4),
1278 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1279 u0AlwaysExtPred:$src3))]>,
1282 // memb(Rx++#s4:0:circ(Mu))=Rt
1283 // memb(Rx++I:circ(Mu))=Rt
1285 // memb(Rx++Mu:brev)=Rt
1286 // memb(gp+#u16:0)=Rt
1290 // TODO: needs to be implemented
1291 // memh(Re=#U6)=Rt.H
1292 // memh(Rs+#s11:1)=Rt.H
1293 let AddedComplexity = 6 in
1294 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1295 (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1298 // memh(Rs+Ru<<#u2)=Rt.H
1299 // TODO: needs to be implemented.
1301 // memh(Ru<<#u2+#U6)=Rt.H
1302 // memh(Ru<<#u2+#U6)=Rt
1303 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
1304 validSubTargets = HasV4SubT in
1305 def STrih_shl_V4 : STInst<(outs),
1306 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1307 "memh($src1<<#$src2+#$src3) = $src4",
1308 [(truncstorei16 (i32 IntRegs:$src4),
1309 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1310 u0AlwaysExtPred:$src3))]>,
1313 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1314 // memh(Rx++#s4:1:circ(Mu))=Rt
1315 // memh(Rx++I:circ(Mu))=Rt.H
1316 // memh(Rx++I:circ(Mu))=Rt
1317 // memh(Rx++Mu)=Rt.H
1319 // memh(Rx++Mu:brev)=Rt.H
1320 // memh(Rx++Mu:brev)=Rt
1321 // memh(gp+#u16:1)=Rt
1322 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1323 // if ([!]Pv[.new]) memh(#u6)=Rt
1326 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1327 // TODO: needs to be implemented.
1329 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1330 // TODO: Needs to be implemented.
1334 // TODO: Needs to be implemented.
1337 let neverHasSideEffects = 1 in
1338 def STriw_pred_V4 : STInst2<(outs),
1339 (ins MEMri:$addr, PredRegs:$src1),
1340 "Error; should not emit",
1344 let AddedComplexity = 6 in
1345 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1346 (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1349 // memw(Ru<<#u2+#U6)=Rt
1350 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
1351 validSubTargets = HasV4SubT in
1352 def STriw_shl_V4 : STInst<(outs),
1353 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1354 "memw($src1<<#$src2+#$src3) = $src4",
1355 [(store (i32 IntRegs:$src4),
1356 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1357 u0AlwaysExtPred:$src3))]>,
1360 // memw(Rx++#s4:2)=Rt
1361 // memw(Rx++#s4:2:circ(Mu))=Rt
1362 // memw(Rx++I:circ(Mu))=Rt
1364 // memw(Rx++Mu:brev)=Rt
1365 // memw(gp+#u16:2)=Rt
1368 // memd(#global)=Rtt
1369 let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1,
1370 validSubTargets = HasV4SubT in
1371 def STd_GP_V4 : STInst2<(outs),
1372 (ins globaladdress:$global, DoubleRegs:$src),
1373 "memd(#$global) = $src",
1377 // if (Pv) memd(##global) = Rtt
1378 let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1,
1379 isExtended = 1, opExtendable = 1, validSubTargets = HasV4SubT in {
1380 def STd_GP_cPt_V4 : STInst2<(outs),
1381 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
1382 "if ($src1) memd(##$global) = $src2",
1386 // if (!Pv) memd(##global) = Rtt
1387 def STd_GP_cNotPt_V4 : STInst2<(outs),
1388 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
1389 "if (!$src1) memd(##$global) = $src2",
1393 // if (Pv) memd(##global) = Rtt
1394 def STd_GP_cdnPt_V4 : STInst2<(outs),
1395 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
1396 "if ($src1.new) memd(##$global) = $src2",
1400 // if (!Pv) memd(##global) = Rtt
1401 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
1402 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
1403 "if (!$src1.new) memd(##$global) = $src2",
1409 let isPredicable = 1, neverHasSideEffects = 1, isNVStorable = 1,
1410 validSubTargets = HasV4SubT in
1411 def STb_GP_V4 : STInst2<(outs),
1412 (ins globaladdress:$global, IntRegs:$src),
1413 "memb(#$global) = $src",
1417 // if (Pv) memb(##global) = Rt
1418 let neverHasSideEffects = 1, isPredicated = 1, isNVStorable = 1,
1419 isExtended = 1, opExtendable = 1, validSubTargets = HasV4SubT in {
1420 def STb_GP_cPt_V4 : STInst2<(outs),
1421 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1422 "if ($src1) memb(##$global) = $src2",
1426 // if (!Pv) memb(##global) = Rt
1427 def STb_GP_cNotPt_V4 : STInst2<(outs),
1428 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1429 "if (!$src1) memb(##$global) = $src2",
1433 // if (Pv) memb(##global) = Rt
1434 def STb_GP_cdnPt_V4 : STInst2<(outs),
1435 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1436 "if ($src1.new) memb(##$global) = $src2",
1440 // if (!Pv) memb(##global) = Rt
1441 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
1442 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1443 "if (!$src1.new) memb(##$global) = $src2",
1449 let isPredicable = 1, neverHasSideEffects = 1, isNVStorable = 1,
1450 validSubTargets = HasV4SubT in
1451 def STh_GP_V4 : STInst2<(outs),
1452 (ins globaladdress:$global, IntRegs:$src),
1453 "memh(#$global) = $src",
1457 // if (Pv) memh(##global) = Rt
1458 let neverHasSideEffects = 1, isPredicated = 1, isNVStorable = 1,
1459 isExtended = 1, opExtendable = 1, validSubTargets = HasV4SubT in {
1460 def STh_GP_cPt_V4 : STInst2<(outs),
1461 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1462 "if ($src1) memh(##$global) = $src2",
1466 // if (!Pv) memh(##global) = Rt
1467 def STh_GP_cNotPt_V4 : STInst2<(outs),
1468 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1469 "if (!$src1) memh(##$global) = $src2",
1473 // if (Pv) memh(##global) = Rt
1474 def STh_GP_cdnPt_V4 : STInst2<(outs),
1475 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1476 "if ($src1.new) memh(##$global) = $src2",
1480 // if (!Pv) memh(##global) = Rt
1481 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
1482 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1483 "if (!$src1.new) memh(##$global) = $src2",
1489 let isPredicable = 1, neverHasSideEffects = 1, isNVStorable = 1,
1490 validSubTargets = HasV4SubT in
1491 def STw_GP_V4 : STInst2<(outs),
1492 (ins globaladdress:$global, IntRegs:$src),
1493 "memw(#$global) = $src",
1497 // if (Pv) memw(##global) = Rt
1498 let neverHasSideEffects = 1, isPredicated = 1, isNVStorable = 1,
1499 isExtended = 1, opExtendable = 1, validSubTargets = HasV4SubT in {
1500 def STw_GP_cPt_V4 : STInst2<(outs),
1501 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1502 "if ($src1) memw(##$global) = $src2",
1506 // if (!Pv) memw(##global) = Rt
1507 def STw_GP_cNotPt_V4 : STInst2<(outs),
1508 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1509 "if (!$src1) memw(##$global) = $src2",
1513 // if (Pv) memw(##global) = Rt
1514 def STw_GP_cdnPt_V4 : STInst2<(outs),
1515 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1516 "if ($src1.new) memw(##$global) = $src2",
1520 // if (!Pv) memw(##global) = Rt
1521 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
1522 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1523 "if (!$src1.new) memw(##$global) = $src2",
1528 // 64 bit atomic store
1529 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
1530 (i64 DoubleRegs:$src1)),
1531 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
1534 // Map from store(globaladdress) -> memd(#foo)
1535 let AddedComplexity = 100 in
1536 def : Pat <(store (i64 DoubleRegs:$src1),
1537 (HexagonCONST32_GP tglobaladdr:$global)),
1538 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
1541 // 8 bit atomic store
1542 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
1543 (i32 IntRegs:$src1)),
1544 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
1547 // Map from store(globaladdress) -> memb(#foo)
1548 let AddedComplexity = 100 in
1549 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
1550 (HexagonCONST32_GP tglobaladdr:$global)),
1551 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
1554 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
1555 // to "r0 = 1; memw(#foo) = r0"
1556 let AddedComplexity = 100 in
1557 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
1558 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
1561 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
1562 (i32 IntRegs:$src1)),
1563 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
1566 // Map from store(globaladdress) -> memh(#foo)
1567 let AddedComplexity = 100 in
1568 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
1569 (HexagonCONST32_GP tglobaladdr:$global)),
1570 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
1573 // 32 bit atomic store
1574 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
1575 (i32 IntRegs:$src1)),
1576 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
1579 // Map from store(globaladdress) -> memw(#foo)
1580 let AddedComplexity = 100 in
1581 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
1582 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
1585 //===----------------------------------------------------------------------===
1587 //===----------------------------------------------------------------------===
1590 //===----------------------------------------------------------------------===//
1592 //===----------------------------------------------------------------------===//
1594 // multiclass for new-value store instructions with base + immediate offset.
1596 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
1597 Operand predImmOp, bit isNot, bit isPredNew> {
1598 let PNewValue = !if(isPredNew, "new", "") in
1599 def NAME#_nv_V4 : NVInst_V4<(outs),
1600 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1601 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1602 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1607 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
1609 let PredSense = !if(PredNot, "false", "true") in {
1610 defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
1612 defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
1616 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
1617 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1618 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1619 bits<5> PredImmBits> {
1621 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1622 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1624 def NAME#_nv_V4 : NVInst_V4<(outs),
1625 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1626 mnemonic#"($src1+#$src2) = $src3.new",
1630 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1631 isPredicated = 1 in {
1632 defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
1633 defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
1638 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
1639 defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1640 u6_0Ext, 11, 6>, AddrModeRel;
1641 defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1642 u6_1Ext, 12, 7>, AddrModeRel;
1643 defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1644 u6_2Ext, 13, 8>, AddrModeRel;
1647 // multiclass for new-value store instructions with base + immediate offset.
1648 // and MEMri operand.
1649 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
1651 let PNewValue = !if(isPredNew, "new", "") in
1652 def NAME#_nv_V4 : NVInst_V4<(outs),
1653 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1654 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1655 ") ")#mnemonic#"($addr) = $src2.new",
1660 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
1661 let PredSense = !if(PredNot, "false", "true") in {
1662 defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
1665 defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
1669 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
1670 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
1671 bits<5> ImmBits, bits<5> PredImmBits> {
1673 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1674 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1676 def NAME#_nv_V4 : NVInst_V4<(outs),
1677 (ins MEMri:$addr, RC:$src),
1678 mnemonic#"($addr) = $src.new",
1682 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1683 neverHasSideEffects = 1, isPredicated = 1 in {
1684 defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
1685 defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
1690 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
1692 defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1693 defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1694 defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1697 // memb(Ru<<#u2+#U6)=Nt.new
1698 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
1699 isNVStore = 1, validSubTargets = HasV4SubT in
1700 def STrib_shl_nv_V4 : NVInst_V4<(outs),
1701 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1702 "memb($src1<<#$src2+#$src3) = $src4.new",
1706 //===----------------------------------------------------------------------===//
1707 // Post increment store
1708 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1709 //===----------------------------------------------------------------------===//
1711 multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
1712 bit isNot, bit isPredNew> {
1713 let PNewValue = !if(isPredNew, "new", "") in
1714 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1715 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1716 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1717 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1723 multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
1724 Operand ImmOp, bit PredNot> {
1725 let PredSense = !if(PredNot, "false", "true") in {
1726 defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
1728 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1729 defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
1733 let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
1734 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
1737 let BaseOpcode = "POST_"#BaseOp in {
1738 let isPredicable = 1 in
1739 def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
1740 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1741 mnemonic#"($src1++#$offset) = $src2.new",
1746 let isPredicated = 1 in {
1747 defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
1748 defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
1753 let validSubTargets = HasV4SubT in {
1754 defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1755 defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1756 defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1759 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1760 // memb(Rx++I:circ(Mu))=Nt.new
1761 // memb(Rx++Mu)=Nt.new
1762 // memb(Rx++Mu:brev)=Nt.new
1764 // memb(#global)=Nt.new
1765 let mayStore = 1, neverHasSideEffects = 1 in
1766 def STb_GP_nv_V4 : NVInst_V4<(outs),
1767 (ins globaladdress:$global, IntRegs:$src),
1768 "memb(#$global) = $src.new",
1772 // memh(Ru<<#u2+#U6)=Nt.new
1773 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
1774 isNVStore = 1, validSubTargets = HasV4SubT in
1775 def STrih_shl_nv_V4 : NVInst_V4<(outs),
1776 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1777 "memh($src1<<#$src2+#$src3) = $src4.new",
1781 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1782 // memh(Rx++I:circ(Mu))=Nt.new
1783 // memh(Rx++Mu)=Nt.new
1784 // memh(Rx++Mu:brev)=Nt.new
1786 // memh(#global)=Nt.new
1787 let mayStore = 1, neverHasSideEffects = 1 in
1788 def STh_GP_nv_V4 : NVInst_V4<(outs),
1789 (ins globaladdress:$global, IntRegs:$src),
1790 "memh(#$global) = $src.new",
1794 // memw(Ru<<#u2+#U6)=Nt.new
1795 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
1796 isNVStore = 1, validSubTargets = HasV4SubT in
1797 def STriw_shl_nv_V4 : NVInst_V4<(outs),
1798 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1799 "memw($src1<<#$src2+#$src3) = $src4.new",
1803 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1804 // memw(Rx++I:circ(Mu))=Nt.new
1805 // memw(Rx++Mu)=Nt.new
1806 // memw(Rx++Mu:brev)=Nt.new
1807 // memw(gp+#u16:2)=Nt.new
1809 let mayStore = 1, neverHasSideEffects = 1, isNVStore = 1,
1810 validSubTargets = HasV4SubT in
1811 def STw_GP_nv_V4 : NVInst_V4<(outs),
1812 (ins globaladdress:$global, IntRegs:$src),
1813 "memw(#$global) = $src.new",
1817 // if (Pv) memb(##global) = Rt
1818 let mayStore = 1, neverHasSideEffects = 1, isNVStore = 1,
1819 isExtended = 1, opExtendable = 1, validSubTargets = HasV4SubT in {
1820 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
1821 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1822 "if ($src1) memb(##$global) = $src2.new",
1826 // if (!Pv) memb(##global) = Rt
1827 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
1828 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1829 "if (!$src1) memb(##$global) = $src2.new",
1833 // if (Pv) memb(##global) = Rt
1834 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
1835 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1836 "if ($src1.new) memb(##$global) = $src2.new",
1840 // if (!Pv) memb(##global) = Rt
1841 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1842 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1843 "if (!$src1.new) memb(##$global) = $src2.new",
1847 // if (Pv) memh(##global) = Rt
1848 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
1849 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1850 "if ($src1) memh(##$global) = $src2.new",
1854 // if (!Pv) memh(##global) = Rt
1855 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
1856 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1857 "if (!$src1) memh(##$global) = $src2.new",
1861 // if (Pv) memh(##global) = Rt
1862 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
1863 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1864 "if ($src1.new) memh(##$global) = $src2.new",
1868 // if (!Pv) memh(##global) = Rt
1869 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1870 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1871 "if (!$src1.new) memh(##$global) = $src2.new",
1875 // if (Pv) memw(##global) = Rt
1876 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
1877 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1878 "if ($src1) memw(##$global) = $src2.new",
1882 // if (!Pv) memw(##global) = Rt
1883 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
1884 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1885 "if (!$src1) memw(##$global) = $src2.new",
1889 // if (Pv) memw(##global) = Rt
1890 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
1891 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1892 "if ($src1.new) memw(##$global) = $src2.new",
1896 // if (!Pv) memw(##global) = Rt
1897 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
1898 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
1899 "if (!$src1.new) memw(##$global) = $src2.new",
1904 //===----------------------------------------------------------------------===//
1906 //===----------------------------------------------------------------------===//
1908 //===----------------------------------------------------------------------===//
1910 //===----------------------------------------------------------------------===//
1912 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
1913 def _ie_nv_V4 : NVInst_V4<(outs),
1914 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1915 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1916 !strconcat("($src1.new, $src2)) jump:",
1917 !strconcat(TakenStr, " $offset"))))),
1921 def _nv_V4 : NVInst_V4<(outs),
1922 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1923 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1924 !strconcat("($src1.new, $src2)) jump:",
1925 !strconcat(TakenStr, " $offset"))))),
1930 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
1932 def _ie_nv_V4 : NVInst_V4<(outs),
1933 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1934 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1935 !strconcat("($src1, $src2.new)) jump:",
1936 !strconcat(TakenStr, " $offset"))))),
1940 def _nv_V4 : NVInst_V4<(outs),
1941 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1942 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1943 !strconcat("($src1, $src2.new)) jump:",
1944 !strconcat(TakenStr, " $offset"))))),
1949 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
1950 def _ie_nv_V4 : NVInst_V4<(outs),
1951 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1952 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1953 !strconcat("($src1.new, #$src2)) jump:",
1954 !strconcat(TakenStr, " $offset"))))),
1958 def _nv_V4 : NVInst_V4<(outs),
1959 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1960 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1961 !strconcat("($src1.new, #$src2)) jump:",
1962 !strconcat(TakenStr, " $offset"))))),
1967 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
1968 def _ie_nv_V4 : NVInst_V4<(outs),
1969 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
1970 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1971 !strconcat("($src1.new, #$src2)) jump:",
1972 !strconcat(TakenStr, " $offset"))))),
1976 def _nv_V4 : NVInst_V4<(outs),
1977 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
1978 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1979 !strconcat("($src1.new, #$src2)) jump:",
1980 !strconcat(TakenStr, " $offset"))))),
1985 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
1987 def _ie_nv_V4 : NVInst_V4<(outs),
1988 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
1989 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1990 !strconcat("($src1.new, #$src2)) jump:",
1991 !strconcat(TakenStr, " $offset"))))),
1995 def _nv_V4 : NVInst_V4<(outs),
1996 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
1997 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
1998 !strconcat("($src1.new, #$src2)) jump:",
1999 !strconcat(TakenStr, " $offset"))))),
2004 // Multiclass for regular dot new of Ist operand register.
2005 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
2006 defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
2007 defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
2010 // Multiclass for dot new of 2nd operand register.
2011 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
2012 defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
2013 defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
2016 // Multiclass for 2nd operand immediate, including -1.
2017 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
2018 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2019 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
2020 defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
2021 defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
2024 // Multiclass for 2nd operand immediate, excluding -1.
2025 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
2026 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2027 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
2030 // Multiclass for tstbit, where 2nd operand is always #0.
2031 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
2032 defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
2033 defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
2036 // Multiclass for GT.
2037 multiclass NVJ_type_rr_ri<string OpcStr> {
2038 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
2039 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
2040 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
2041 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
2042 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
2043 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
2046 // Multiclass for EQ.
2047 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
2048 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
2049 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
2050 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
2051 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
2054 // Multiclass for GTU.
2055 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
2056 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
2057 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
2058 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
2059 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
2060 defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
2061 defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
2064 // Multiclass for tstbit.
2065 multiclass NVJ_type_r0<string OpcStr> {
2066 defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
2067 defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
2070 // Base Multiclass for New Value Jump.
2071 multiclass NVJ_type {
2072 defm GT : NVJ_type_rr_ri<"cmp.gt">;
2073 defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
2074 defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
2075 defm TSTBIT : NVJ_type_r0<"tstbit">;
2078 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
2079 defm JMP_ : NVJ_type;
2082 //===----------------------------------------------------------------------===//
2084 //===----------------------------------------------------------------------===//
2086 //===----------------------------------------------------------------------===//
2088 //===----------------------------------------------------------------------===//
2090 // Add and accumulate.
2091 // Rd=add(Rs,add(Ru,#s6))
2092 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
2093 validSubTargets = HasV4SubT in
2094 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
2095 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
2096 "$dst = add($src1, add($src2, #$src3))",
2097 [(set (i32 IntRegs:$dst),
2098 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
2099 s6_16ExtPred:$src3)))]>,
2102 // Rd=add(Rs,sub(#s6,Ru))
2103 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
2104 validSubTargets = HasV4SubT in
2105 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
2106 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
2107 "$dst = add($src1, sub(#$src2, $src3))",
2108 [(set (i32 IntRegs:$dst),
2109 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
2110 (i32 IntRegs:$src3))))]>,
2113 // Generates the same instruction as ADDr_SUBri_V4 but matches different
2115 // Rd=add(Rs,sub(#s6,Ru))
2116 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
2117 validSubTargets = HasV4SubT in
2118 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
2119 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
2120 "$dst = add($src1, sub(#$src2, $src3))",
2121 [(set (i32 IntRegs:$dst),
2122 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
2123 (i32 IntRegs:$src3)))]>,
2127 // Add or subtract doublewords with carry.
2129 // Rdd=add(Rss,Rtt,Px):carry
2131 // Rdd=sub(Rss,Rtt,Px):carry
2134 // Logical doublewords.
2135 // Rdd=and(Rtt,~Rss)
2136 let validSubTargets = HasV4SubT in
2137 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2138 (ins DoubleRegs:$src1, DoubleRegs:$src2),
2139 "$dst = and($src1, ~$src2)",
2140 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
2141 (not (i64 DoubleRegs:$src2))))]>,
2145 let validSubTargets = HasV4SubT in
2146 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2147 (ins DoubleRegs:$src1, DoubleRegs:$src2),
2148 "$dst = or($src1, ~$src2)",
2149 [(set (i64 DoubleRegs:$dst),
2150 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
2154 // Logical-logical doublewords.
2155 // Rxx^=xor(Rss,Rtt)
2156 let validSubTargets = HasV4SubT in
2157 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
2158 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
2159 "$dst ^= xor($src2, $src3)",
2160 [(set (i64 DoubleRegs:$dst),
2161 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
2162 (i64 DoubleRegs:$src3))))],
2167 // Logical-logical words.
2168 // Rx=or(Ru,and(Rx,#s10))
2169 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
2170 validSubTargets = HasV4SubT in
2171 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
2172 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
2173 "$dst = or($src1, and($src2, #$src3))",
2174 [(set (i32 IntRegs:$dst),
2175 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2176 s10ExtPred:$src3)))],
2180 // Rx[&|^]=and(Rs,Rt)
2182 let validSubTargets = HasV4SubT in
2183 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2184 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2185 "$dst &= and($src2, $src3)",
2186 [(set (i32 IntRegs:$dst),
2187 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2188 (i32 IntRegs:$src3))))],
2193 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
2194 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2195 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2196 "$dst |= and($src2, $src3)",
2197 [(set (i32 IntRegs:$dst),
2198 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2199 (i32 IntRegs:$src3))))],
2201 Requires<[HasV4T]>, ImmRegRel;
2204 let validSubTargets = HasV4SubT in
2205 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2206 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2207 "$dst ^= and($src2, $src3)",
2208 [(set (i32 IntRegs:$dst),
2209 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2210 (i32 IntRegs:$src3))))],
2214 // Rx[&|^]=and(Rs,~Rt)
2216 let validSubTargets = HasV4SubT in
2217 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2218 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2219 "$dst &= and($src2, ~$src3)",
2220 [(set (i32 IntRegs:$dst),
2221 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2222 (not (i32 IntRegs:$src3)))))],
2227 let validSubTargets = HasV4SubT in
2228 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2229 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2230 "$dst |= and($src2, ~$src3)",
2231 [(set (i32 IntRegs:$dst),
2232 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2233 (not (i32 IntRegs:$src3)))))],
2238 let validSubTargets = HasV4SubT in
2239 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
2240 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2241 "$dst ^= and($src2, ~$src3)",
2242 [(set (i32 IntRegs:$dst),
2243 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2244 (not (i32 IntRegs:$src3)))))],
2248 // Rx[&|^]=or(Rs,Rt)
2250 let validSubTargets = HasV4SubT in
2251 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2252 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2253 "$dst &= or($src2, $src3)",
2254 [(set (i32 IntRegs:$dst),
2255 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
2256 (i32 IntRegs:$src3))))],
2261 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
2262 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2263 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2264 "$dst |= or($src2, $src3)",
2265 [(set (i32 IntRegs:$dst),
2266 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
2267 (i32 IntRegs:$src3))))],
2269 Requires<[HasV4T]>, ImmRegRel;
2272 let validSubTargets = HasV4SubT in
2273 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2274 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2275 "$dst ^= or($src2, $src3)",
2276 [(set (i32 IntRegs:$dst),
2277 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
2278 (i32 IntRegs:$src3))))],
2282 // Rx[&|^]=xor(Rs,Rt)
2284 let validSubTargets = HasV4SubT in
2285 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2286 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2287 "$dst &= xor($src2, $src3)",
2288 [(set (i32 IntRegs:$dst),
2289 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
2290 (i32 IntRegs:$src3))))],
2295 let validSubTargets = HasV4SubT in
2296 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2297 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2298 "$dst |= xor($src2, $src3)",
2299 [(set (i32 IntRegs:$dst),
2300 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
2301 (i32 IntRegs:$src3))))],
2306 let validSubTargets = HasV4SubT in
2307 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
2308 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2309 "$dst ^= xor($src2, $src3)",
2310 [(set (i32 IntRegs:$dst),
2311 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
2312 (i32 IntRegs:$src3))))],
2317 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
2318 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
2319 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
2320 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
2321 "$dst |= and($src2, #$src3)",
2322 [(set (i32 IntRegs:$dst),
2323 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2324 s10ExtPred:$src3)))],
2326 Requires<[HasV4T]>, ImmRegRel;
2329 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
2330 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
2331 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
2332 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
2333 "$dst |= or($src2, #$src3)",
2334 [(set (i32 IntRegs:$dst),
2335 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2336 s10ExtPred:$src3)))],
2338 Requires<[HasV4T]>, ImmRegRel;
2342 // Rd=modwrap(Rs,Rt)
2344 // Rd=cround(Rs,#u5)
2346 // Rd=round(Rs,#u5)[:sat]
2347 // Rd=round(Rs,Rt)[:sat]
2348 // Vector reduce add unsigned halfwords
2349 // Rd=vraddh(Rss,Rtt)
2351 // Rdd=vaddb(Rss,Rtt)
2352 // Vector conditional negate
2353 // Rdd=vcnegh(Rss,Rt)
2354 // Rxx+=vrcnegh(Rss,Rt)
2355 // Vector maximum bytes
2356 // Rdd=vmaxb(Rtt,Rss)
2357 // Vector reduce maximum halfwords
2358 // Rxx=vrmaxh(Rss,Ru)
2359 // Rxx=vrmaxuh(Rss,Ru)
2360 // Vector reduce maximum words
2361 // Rxx=vrmaxuw(Rss,Ru)
2362 // Rxx=vrmaxw(Rss,Ru)
2363 // Vector minimum bytes
2364 // Rdd=vminb(Rtt,Rss)
2365 // Vector reduce minimum halfwords
2366 // Rxx=vrminh(Rss,Ru)
2367 // Rxx=vrminuh(Rss,Ru)
2368 // Vector reduce minimum words
2369 // Rxx=vrminuw(Rss,Ru)
2370 // Rxx=vrminw(Rss,Ru)
2371 // Vector subtract bytes
2372 // Rdd=vsubb(Rss,Rtt)
2374 //===----------------------------------------------------------------------===//
2376 //===----------------------------------------------------------------------===//
2379 //===----------------------------------------------------------------------===//
2381 //===----------------------------------------------------------------------===//
2383 // Multiply and user lower result.
2384 // Rd=add(#u6,mpyi(Rs,#U6))
2385 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
2386 validSubTargets = HasV4SubT in
2387 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
2388 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
2389 "$dst = add(#$src1, mpyi($src2, #$src3))",
2390 [(set (i32 IntRegs:$dst),
2391 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2392 u6ExtPred:$src1))]>,
2395 // Rd=add(##,mpyi(Rs,#U6))
2396 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2397 (HexagonCONST32 tglobaladdr:$src1)),
2398 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
2401 // Rd=add(#u6,mpyi(Rs,Rt))
2402 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
2403 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
2404 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
2405 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
2406 "$dst = add(#$src1, mpyi($src2, $src3))",
2407 [(set (i32 IntRegs:$dst),
2408 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2409 u6ExtPred:$src1))]>,
2410 Requires<[HasV4T]>, ImmRegRel;
2412 // Rd=add(##,mpyi(Rs,Rt))
2413 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2414 (HexagonCONST32 tglobaladdr:$src1)),
2415 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
2418 // Rd=add(Ru,mpyi(#u6:2,Rs))
2419 let validSubTargets = HasV4SubT in
2420 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
2421 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
2422 "$dst = add($src1, mpyi(#$src2, $src3))",
2423 [(set (i32 IntRegs:$dst),
2424 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
2425 u6_2ImmPred:$src2)))]>,
2428 // Rd=add(Ru,mpyi(Rs,#u6))
2429 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
2430 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
2431 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
2432 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
2433 "$dst = add($src1, mpyi($src2, #$src3))",
2434 [(set (i32 IntRegs:$dst),
2435 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
2436 u6ExtPred:$src3)))]>,
2437 Requires<[HasV4T]>, ImmRegRel;
2439 // Rx=add(Ru,mpyi(Rx,Rs))
2440 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
2441 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
2442 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2443 "$dst = add($src1, mpyi($src2, $src3))",
2444 [(set (i32 IntRegs:$dst),
2445 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
2446 (i32 IntRegs:$src3))))],
2448 Requires<[HasV4T]>, ImmRegRel;
2451 // Polynomial multiply words
2453 // Rxx^=pmpyw(Rs,Rt)
2455 // Vector reduce multiply word by signed half (32x16)
2456 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2457 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2458 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
2459 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
2461 // Multiply and use upper result
2462 // Rd=mpy(Rs,Rt.H):<<1:sat
2463 // Rd=mpy(Rs,Rt.L):<<1:sat
2464 // Rd=mpy(Rs,Rt):<<1
2465 // Rd=mpy(Rs,Rt):<<1:sat
2467 // Rx+=mpy(Rs,Rt):<<1:sat
2468 // Rx-=mpy(Rs,Rt):<<1:sat
2470 // Vector multiply bytes
2471 // Rdd=vmpybsu(Rs,Rt)
2472 // Rdd=vmpybu(Rs,Rt)
2473 // Rxx+=vmpybsu(Rs,Rt)
2474 // Rxx+=vmpybu(Rs,Rt)
2476 // Vector polynomial multiply halfwords
2477 // Rdd=vpmpyh(Rs,Rt)
2478 // Rxx^=vpmpyh(Rs,Rt)
2480 //===----------------------------------------------------------------------===//
2482 //===----------------------------------------------------------------------===//
2485 //===----------------------------------------------------------------------===//
2487 //===----------------------------------------------------------------------===//
2489 // Shift by immediate and accumulate.
2490 // Rx=add(#u8,asl(Rx,#U5))
2491 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2492 validSubTargets = HasV4SubT in
2493 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2494 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2495 "$dst = add(#$src1, asl($src2, #$src3))",
2496 [(set (i32 IntRegs:$dst),
2497 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2502 // Rx=add(#u8,lsr(Rx,#U5))
2503 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2504 validSubTargets = HasV4SubT in
2505 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2506 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2507 "$dst = add(#$src1, lsr($src2, #$src3))",
2508 [(set (i32 IntRegs:$dst),
2509 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2514 // Rx=sub(#u8,asl(Rx,#U5))
2515 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2516 validSubTargets = HasV4SubT in
2517 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2518 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2519 "$dst = sub(#$src1, asl($src2, #$src3))",
2520 [(set (i32 IntRegs:$dst),
2521 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2526 // Rx=sub(#u8,lsr(Rx,#U5))
2527 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2528 validSubTargets = HasV4SubT in
2529 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2530 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2531 "$dst = sub(#$src1, lsr($src2, #$src3))",
2532 [(set (i32 IntRegs:$dst),
2533 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2539 //Shift by immediate and logical.
2540 //Rx=and(#u8,asl(Rx,#U5))
2541 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2542 validSubTargets = HasV4SubT in
2543 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2544 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2545 "$dst = and(#$src1, asl($src2, #$src3))",
2546 [(set (i32 IntRegs:$dst),
2547 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2552 //Rx=and(#u8,lsr(Rx,#U5))
2553 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2554 validSubTargets = HasV4SubT in
2555 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2556 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2557 "$dst = and(#$src1, lsr($src2, #$src3))",
2558 [(set (i32 IntRegs:$dst),
2559 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2564 //Rx=or(#u8,asl(Rx,#U5))
2565 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2566 AddedComplexity = 30, validSubTargets = HasV4SubT in
2567 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2568 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2569 "$dst = or(#$src1, asl($src2, #$src3))",
2570 [(set (i32 IntRegs:$dst),
2571 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2576 //Rx=or(#u8,lsr(Rx,#U5))
2577 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2578 AddedComplexity = 30, validSubTargets = HasV4SubT in
2579 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2580 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2581 "$dst = or(#$src1, lsr($src2, #$src3))",
2582 [(set (i32 IntRegs:$dst),
2583 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2589 //Shift by register.
2591 let validSubTargets = HasV4SubT in {
2592 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
2593 "$dst = lsl(#$src1, $src2)",
2594 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
2595 (i32 IntRegs:$src2)))]>,
2599 //Shift by register and logical.
2601 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2602 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2603 "$dst ^= asl($src2, $src3)",
2604 [(set (i64 DoubleRegs:$dst),
2605 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
2606 (i32 IntRegs:$src3))))],
2611 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2612 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2613 "$dst ^= asr($src2, $src3)",
2614 [(set (i64 DoubleRegs:$dst),
2615 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
2616 (i32 IntRegs:$src3))))],
2621 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2622 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2623 "$dst ^= lsl($src2, $src3)",
2624 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
2625 (shl (i64 DoubleRegs:$src2),
2626 (i32 IntRegs:$src3))))],
2631 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2632 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2633 "$dst ^= lsr($src2, $src3)",
2634 [(set (i64 DoubleRegs:$dst),
2635 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
2636 (i32 IntRegs:$src3))))],
2641 //===----------------------------------------------------------------------===//
2643 //===----------------------------------------------------------------------===//
2645 //===----------------------------------------------------------------------===//
2646 // MEMOP: Word, Half, Byte
2647 //===----------------------------------------------------------------------===//
2649 //===----------------------------------------------------------------------===//
2653 // MEMw_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
2654 // MEMw_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
2655 // MEMw_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
2656 // MEMw_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
2657 // MEMw_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
2658 // MEMw_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
2659 // MEMw_ADDi_V4 : memw(Rs+#u6:2)+=#U5
2660 // MEMw_SUBi_V4 : memw(Rs+#u6:2)-=#U5
2661 // MEMw_ADDr_V4 : memw(Rs+#u6:2)+=Rt
2662 // MEMw_SUBr_V4 : memw(Rs+#u6:2)-=Rt
2663 // MEMw_CLRr_V4 : memw(Rs+#u6:2)&=Rt
2664 // MEMw_SETr_V4 : memw(Rs+#u6:2)|=Rt
2667 // MEMw_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2668 // MEMw_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
2669 // MEMw_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2670 // MEMw_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
2671 //===----------------------------------------------------------------------===//
2675 // memw(Rs+#u6:2) += #U5
2676 let AddedComplexity = 30 in
2677 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
2678 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
2679 "memw($base+#$offset) += #$addend",
2681 Requires<[HasV4T, UseMEMOP]>;
2683 // memw(Rs+#u6:2) -= #U5
2684 let AddedComplexity = 30 in
2685 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2686 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
2687 "memw($base+#$offset) -= #$subend",
2689 Requires<[HasV4T, UseMEMOP]>;
2691 // memw(Rs+#u6:2) += Rt
2692 let AddedComplexity = 30 in
2693 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2694 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
2695 "memw($base+#$offset) += $addend",
2696 [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
2697 (i32 IntRegs:$addend)),
2698 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
2699 Requires<[HasV4T, UseMEMOP]>;
2701 // memw(Rs+#u6:2) -= Rt
2702 let AddedComplexity = 30 in
2703 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
2704 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
2705 "memw($base+#$offset) -= $subend",
2706 [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
2707 (i32 IntRegs:$subend)),
2708 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
2709 Requires<[HasV4T, UseMEMOP]>;
2711 // memw(Rs+#u6:2) &= Rt
2712 let AddedComplexity = 30 in
2713 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2714 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
2715 "memw($base+#$offset) &= $andend",
2716 [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
2717 (i32 IntRegs:$andend)),
2718 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
2719 Requires<[HasV4T, UseMEMOP]>;
2721 // memw(Rs+#u6:2) |= Rt
2722 let AddedComplexity = 30 in
2723 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
2724 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
2725 "memw($base+#$offset) |= $orend",
2726 [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
2727 (i32 IntRegs:$orend)),
2728 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
2729 Requires<[HasV4T, UseMEMOP]>;
2731 // memw(Rs+#u6:2) += #U5
2732 let AddedComplexity = 30 in
2733 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
2734 (ins MEMri:$addr, u5Imm:$addend),
2735 "memw($addr) += $addend",
2737 Requires<[HasV4T, UseMEMOP]>;
2739 // memw(Rs+#u6:2) -= #U5
2740 let AddedComplexity = 30 in
2741 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
2742 (ins MEMri:$addr, u5Imm:$subend),
2743 "memw($addr) -= $subend",
2745 Requires<[HasV4T, UseMEMOP]>;
2747 // memw(Rs+#u6:2) += Rt
2748 let AddedComplexity = 30 in
2749 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
2750 (ins MEMri:$addr, IntRegs:$addend),
2751 "memw($addr) += $addend",
2752 [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
2753 ADDRriU6_2:$addr)]>,
2754 Requires<[HasV4T, UseMEMOP]>;
2756 // memw(Rs+#u6:2) -= Rt
2757 let AddedComplexity = 30 in
2758 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
2759 (ins MEMri:$addr, IntRegs:$subend),
2760 "memw($addr) -= $subend",
2761 [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
2762 ADDRriU6_2:$addr)]>,
2763 Requires<[HasV4T, UseMEMOP]>;
2765 // memw(Rs+#u6:2) &= Rt
2766 let AddedComplexity = 30 in
2767 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
2768 (ins MEMri:$addr, IntRegs:$andend),
2769 "memw($addr) &= $andend",
2770 [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
2771 ADDRriU6_2:$addr)]>,
2772 Requires<[HasV4T, UseMEMOP]>;
2774 // memw(Rs+#u6:2) |= Rt
2775 let AddedComplexity = 30 in
2776 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
2777 (ins MEMri:$addr, IntRegs:$orend),
2778 "memw($addr) |= $orend",
2779 [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
2780 ADDRriU6_2:$addr)]>,
2781 Requires<[HasV4T, UseMEMOP]>;
2783 //===----------------------------------------------------------------------===//
2787 // MEMh_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
2788 // MEMh_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
2789 // MEMh_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
2790 // MEMh_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
2791 // MEMh_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
2792 // MEMh_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
2793 // MEMh_ADDi_V4 : memw(Rs+#u6:2)+=#U5
2794 // MEMh_SUBi_V4 : memw(Rs+#u6:2)-=#U5
2795 // MEMh_ADDr_V4 : memw(Rs+#u6:2)+=Rt
2796 // MEMh_SUBr_V4 : memw(Rs+#u6:2)-=Rt
2797 // MEMh_CLRr_V4 : memw(Rs+#u6:2)&=Rt
2798 // MEMh_SETr_V4 : memw(Rs+#u6:2)|=Rt
2801 // MEMh_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2802 // MEMh_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
2803 // MEMh_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
2804 // MEMh_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
2805 //===----------------------------------------------------------------------===//
2808 // memh(Rs+#u6:1) += #U5
2809 let AddedComplexity = 30 in
2810 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
2811 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
2812 "memh($base+#$offset) += $addend",
2814 Requires<[HasV4T, UseMEMOP]>;
2816 // memh(Rs+#u6:1) -= #U5
2817 let AddedComplexity = 30 in
2818 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2819 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
2820 "memh($base+#$offset) -= $subend",
2822 Requires<[HasV4T, UseMEMOP]>;
2824 // memh(Rs+#u6:1) += Rt
2825 let AddedComplexity = 30 in
2826 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2827 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
2828 "memh($base+#$offset) += $addend",
2829 [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
2830 u6_1ImmPred:$offset)),
2831 (i32 IntRegs:$addend)),
2832 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
2833 Requires<[HasV4T, UseMEMOP]>;
2835 // memh(Rs+#u6:1) -= Rt
2836 let AddedComplexity = 30 in
2837 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
2838 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
2839 "memh($base+#$offset) -= $subend",
2840 [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
2841 u6_1ImmPred:$offset)),
2842 (i32 IntRegs:$subend)),
2843 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
2844 Requires<[HasV4T, UseMEMOP]>;
2846 // memh(Rs+#u6:1) &= Rt
2847 let AddedComplexity = 30 in
2848 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2849 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
2850 "memh($base+#$offset) += $andend",
2851 [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
2852 u6_1ImmPred:$offset)),
2853 (i32 IntRegs:$andend)),
2854 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
2855 Requires<[HasV4T, UseMEMOP]>;
2857 // memh(Rs+#u6:1) |= Rt
2858 let AddedComplexity = 30 in
2859 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
2860 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
2861 "memh($base+#$offset) |= $orend",
2862 [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
2863 u6_1ImmPred:$offset)),
2864 (i32 IntRegs:$orend)),
2865 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
2866 Requires<[HasV4T, UseMEMOP]>;
2868 // memh(Rs+#u6:1) += #U5
2869 let AddedComplexity = 30 in
2870 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
2871 (ins MEMri:$addr, u5Imm:$addend),
2872 "memh($addr) += $addend",
2874 Requires<[HasV4T, UseMEMOP]>;
2876 // memh(Rs+#u6:1) -= #U5
2877 let AddedComplexity = 30 in
2878 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
2879 (ins MEMri:$addr, u5Imm:$subend),
2880 "memh($addr) -= $subend",
2882 Requires<[HasV4T, UseMEMOP]>;
2884 // memh(Rs+#u6:1) += Rt
2885 let AddedComplexity = 30 in
2886 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
2887 (ins MEMri:$addr, IntRegs:$addend),
2888 "memh($addr) += $addend",
2889 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
2890 (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
2891 Requires<[HasV4T, UseMEMOP]>;
2893 // memh(Rs+#u6:1) -= Rt
2894 let AddedComplexity = 30 in
2895 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
2896 (ins MEMri:$addr, IntRegs:$subend),
2897 "memh($addr) -= $subend",
2898 [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
2899 (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
2900 Requires<[HasV4T, UseMEMOP]>;
2902 // memh(Rs+#u6:1) &= Rt
2903 let AddedComplexity = 30 in
2904 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
2905 (ins MEMri:$addr, IntRegs:$andend),
2906 "memh($addr) &= $andend",
2907 [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
2908 (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
2909 Requires<[HasV4T, UseMEMOP]>;
2911 // memh(Rs+#u6:1) |= Rt
2912 let AddedComplexity = 30 in
2913 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
2914 (ins MEMri:$addr, IntRegs:$orend),
2915 "memh($addr) |= $orend",
2916 [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
2917 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
2918 Requires<[HasV4T, UseMEMOP]>;
2921 //===----------------------------------------------------------------------===//
2925 // MEMb_ADDi_indexed_V4 : memb(Rs+#u6:0)+=#U5
2926 // MEMb_SUBi_indexed_V4 : memb(Rs+#u6:0)-=#U5
2927 // MEMb_ADDr_indexed_V4 : memb(Rs+#u6:0)+=Rt
2928 // MEMb_SUBr_indexed_V4 : memb(Rs+#u6:0)-=Rt
2929 // MEMb_CLRr_indexed_V4 : memb(Rs+#u6:0)&=Rt
2930 // MEMb_SETr_indexed_V4 : memb(Rs+#u6:0)|=Rt
2931 // MEMb_ADDi_V4 : memb(Rs+#u6:0)+=#U5
2932 // MEMb_SUBi_V4 : memb(Rs+#u6:0)-=#U5
2933 // MEMb_ADDr_V4 : memb(Rs+#u6:0)+=Rt
2934 // MEMb_SUBr_V4 : memb(Rs+#u6:0)-=Rt
2935 // MEMb_CLRr_V4 : memb(Rs+#u6:0)&=Rt
2936 // MEMb_SETr_V4 : memb(Rs+#u6:0)|=Rt
2939 // MEMb_CLRi_indexed_V4 : memb(Rs+#u6:0)=clrbit(#U5)
2940 // MEMb_SETi_indexed_V4 : memb(Rs+#u6:0)=setbit(#U5)
2941 // MEMb_CLRi_V4 : memb(Rs+#u6:0)=clrbit(#U5)
2942 // MEMb_SETi_V4 : memb(Rs+#u6:0)=setbit(#U5)
2943 //===----------------------------------------------------------------------===//
2945 // memb(Rs+#u6:0) += #U5
2946 let AddedComplexity = 30 in
2947 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
2948 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
2949 "memb($base+#$offset) += $addend",
2951 Requires<[HasV4T, UseMEMOP]>;
2953 // memb(Rs+#u6:0) -= #U5
2954 let AddedComplexity = 30 in
2955 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
2956 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
2957 "memb($base+#$offset) -= $subend",
2959 Requires<[HasV4T, UseMEMOP]>;
2961 // memb(Rs+#u6:0) += Rt
2962 let AddedComplexity = 30 in
2963 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2964 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
2965 "memb($base+#$offset) += $addend",
2966 [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
2967 u6_0ImmPred:$offset)),
2968 (i32 IntRegs:$addend)),
2969 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
2970 Requires<[HasV4T, UseMEMOP]>;
2972 // memb(Rs+#u6:0) -= Rt
2973 let AddedComplexity = 30 in
2974 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
2975 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
2976 "memb($base+#$offset) -= $subend",
2977 [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
2978 u6_0ImmPred:$offset)),
2979 (i32 IntRegs:$subend)),
2980 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
2981 Requires<[HasV4T, UseMEMOP]>;
2983 // memb(Rs+#u6:0) &= Rt
2984 let AddedComplexity = 30 in
2985 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
2986 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
2987 "memb($base+#$offset) += $andend",
2988 [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
2989 u6_0ImmPred:$offset)),
2990 (i32 IntRegs:$andend)),
2991 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
2992 Requires<[HasV4T, UseMEMOP]>;
2994 // memb(Rs+#u6:0) |= Rt
2995 let AddedComplexity = 30 in
2996 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
2997 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
2998 "memb($base+#$offset) |= $orend",
2999 [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
3000 u6_0ImmPred:$offset)),
3001 (i32 IntRegs:$orend)),
3002 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3003 Requires<[HasV4T, UseMEMOP]>;
3005 // memb(Rs+#u6:0) += #U5
3006 let AddedComplexity = 30 in
3007 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
3008 (ins MEMri:$addr, u5Imm:$addend),
3009 "memb($addr) += $addend",
3011 Requires<[HasV4T, UseMEMOP]>;
3013 // memb(Rs+#u6:0) -= #U5
3014 let AddedComplexity = 30 in
3015 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
3016 (ins MEMri:$addr, u5Imm:$subend),
3017 "memb($addr) -= $subend",
3019 Requires<[HasV4T, UseMEMOP]>;
3021 // memb(Rs+#u6:0) += Rt
3022 let AddedComplexity = 30 in
3023 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
3024 (ins MEMri:$addr, IntRegs:$addend),
3025 "memb($addr) += $addend",
3026 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3027 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
3028 Requires<[HasV4T, UseMEMOP]>;
3030 // memb(Rs+#u6:0) -= Rt
3031 let AddedComplexity = 30 in
3032 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
3033 (ins MEMri:$addr, IntRegs:$subend),
3034 "memb($addr) -= $subend",
3035 [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
3036 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
3037 Requires<[HasV4T, UseMEMOP]>;
3039 // memb(Rs+#u6:0) &= Rt
3040 let AddedComplexity = 30 in
3041 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
3042 (ins MEMri:$addr, IntRegs:$andend),
3043 "memb($addr) &= $andend",
3044 [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
3045 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
3046 Requires<[HasV4T, UseMEMOP]>;
3048 // memb(Rs+#u6:0) |= Rt
3049 let AddedComplexity = 30 in
3050 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
3051 (ins MEMri:$addr, IntRegs:$orend),
3052 "memb($addr) |= $orend",
3053 [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
3054 (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
3055 Requires<[HasV4T, UseMEMOP]>;
3058 //===----------------------------------------------------------------------===//
3060 //===----------------------------------------------------------------------===//
3062 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3063 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3064 // hardware. However, compiler can still implement these patterns through
3065 // appropriate patterns combinations based on current implemented patterns.
3066 // The implemented patterns are: EQ/GT/GTU.
3067 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3069 // Following instruction is not being extended as it results into the
3070 // incorrect code for negative numbers.
3071 // Pd=cmpb.eq(Rs,#u8)
3074 let isCompare = 1, validSubTargets = HasV4SubT in
3075 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
3076 (ins IntRegs:$src1, IntRegs:$src2),
3077 "$dst = !cmp.eq($src1, $src2)",
3078 [(set (i1 PredRegs:$dst),
3079 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
3082 // p=!cmp.eq(r1,#s10)
3083 let isCompare = 1, validSubTargets = HasV4SubT in
3084 def CMPnotEQ_ri : ALU32_ri<(outs PredRegs:$dst),
3085 (ins IntRegs:$src1, s10Ext:$src2),
3086 "$dst = !cmp.eq($src1, #$src2)",
3087 [(set (i1 PredRegs:$dst),
3088 (setne (i32 IntRegs:$src1), s10ImmPred:$src2))]>,
3092 let isCompare = 1, validSubTargets = HasV4SubT in
3093 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
3094 (ins IntRegs:$src1, IntRegs:$src2),
3095 "$dst = !cmp.gt($src1, $src2)",
3096 [(set (i1 PredRegs:$dst),
3097 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
3100 // p=!cmp.gt(r1,#s10)
3101 let isCompare = 1, validSubTargets = HasV4SubT in
3102 def CMPnotGT_ri : ALU32_ri<(outs PredRegs:$dst),
3103 (ins IntRegs:$src1, s10Ext:$src2),
3104 "$dst = !cmp.gt($src1, #$src2)",
3105 [(set (i1 PredRegs:$dst),
3106 (not (setgt (i32 IntRegs:$src1), s10ImmPred:$src2)))]>,
3109 // p=!cmp.gtu(r1,r2)
3110 let isCompare = 1, validSubTargets = HasV4SubT in
3111 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
3112 (ins IntRegs:$src1, IntRegs:$src2),
3113 "$dst = !cmp.gtu($src1, $src2)",
3114 [(set (i1 PredRegs:$dst),
3115 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
3118 // p=!cmp.gtu(r1,#u9)
3119 let isCompare = 1, validSubTargets = HasV4SubT in
3120 def CMPnotGTU_ri : ALU32_ri<(outs PredRegs:$dst),
3121 (ins IntRegs:$src1, u9Ext:$src2),
3122 "$dst = !cmp.gtu($src1, #$src2)",
3123 [(set (i1 PredRegs:$dst),
3124 (not (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)))]>,
3127 let isCompare = 1, validSubTargets = HasV4SubT in
3128 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
3129 (ins IntRegs:$src1, u8Imm:$src2),
3130 "$dst = cmpb.eq($src1, #$src2)",
3131 [(set (i1 PredRegs:$dst),
3132 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
3135 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
3137 (JMP_cNot (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
3141 // Pd=cmpb.eq(Rs,Rt)
3142 let isCompare = 1, validSubTargets = HasV4SubT in
3143 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
3144 (ins IntRegs:$src1, IntRegs:$src2),
3145 "$dst = cmpb.eq($src1, $src2)",
3146 [(set (i1 PredRegs:$dst),
3147 (seteq (and (xor (i32 IntRegs:$src1),
3148 (i32 IntRegs:$src2)), 255), 0))]>,
3151 // Pd=cmpb.eq(Rs,Rt)
3152 let isCompare = 1, validSubTargets = HasV4SubT in
3153 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
3154 (ins IntRegs:$src1, IntRegs:$src2),
3155 "$dst = cmpb.eq($src1, $src2)",
3156 [(set (i1 PredRegs:$dst),
3157 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
3158 (shl (i32 IntRegs:$src2), (i32 24))))]>,
3161 // Pd=cmpb.gt(Rs,Rt)
3162 let isCompare = 1, validSubTargets = HasV4SubT in
3163 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
3164 (ins IntRegs:$src1, IntRegs:$src2),
3165 "$dst = cmpb.gt($src1, $src2)",
3166 [(set (i1 PredRegs:$dst),
3167 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
3168 (shl (i32 IntRegs:$src2), (i32 24))))]>,
3171 // Pd=cmpb.gtu(Rs,#u7)
3172 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
3173 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
3174 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
3175 (ins IntRegs:$src1, u7Ext:$src2),
3176 "$dst = cmpb.gtu($src1, #$src2)",
3177 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
3178 u7ExtPred:$src2))]>,
3179 Requires<[HasV4T]>, ImmRegRel;
3181 // SDNode for converting immediate C to C-1.
3182 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
3183 // Return the byte immediate const-1 as an SDNode.
3184 int32_t imm = N->getSExtValue();
3185 return XformU7ToU7M1Imm(imm);
3189 // zext( seteq ( and(Rs, 255), u8))
3191 // Pd=cmpb.eq(Rs, #u8)
3192 // if (Pd.new) Rd=#1
3193 // if (!Pd.new) Rd=#0
3194 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
3196 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
3202 // zext( setne ( and(Rs, 255), u8))
3204 // Pd=cmpb.eq(Rs, #u8)
3205 // if (Pd.new) Rd=#0
3206 // if (!Pd.new) Rd=#1
3207 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
3209 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
3215 // zext( seteq (Rs, and(Rt, 255)))
3217 // Pd=cmpb.eq(Rs, Rt)
3218 // if (Pd.new) Rd=#1
3219 // if (!Pd.new) Rd=#0
3220 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
3221 (i32 (and (i32 IntRegs:$Rs), 255)))))),
3222 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
3223 (i32 IntRegs:$Rt))),
3228 // zext( setne (Rs, and(Rt, 255)))
3230 // Pd=cmpb.eq(Rs, Rt)
3231 // if (Pd.new) Rd=#0
3232 // if (!Pd.new) Rd=#1
3233 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
3234 (i32 (and (i32 IntRegs:$Rs), 255)))))),
3235 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
3236 (i32 IntRegs:$Rt))),
3241 // zext( setugt ( and(Rs, 255), u8))
3243 // Pd=cmpb.gtu(Rs, #u8)
3244 // if (Pd.new) Rd=#1
3245 // if (!Pd.new) Rd=#0
3246 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
3248 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
3254 // zext( setugt ( and(Rs, 254), u8))
3256 // Pd=cmpb.gtu(Rs, #u8)
3257 // if (Pd.new) Rd=#1
3258 // if (!Pd.new) Rd=#0
3259 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
3261 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
3267 // zext( setult ( Rs, Rt))
3269 // Pd=cmp.ltu(Rs, Rt)
3270 // if (Pd.new) Rd=#1
3271 // if (!Pd.new) Rd=#0
3272 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
3273 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3274 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
3275 (i32 IntRegs:$Rs))),
3280 // zext( setlt ( Rs, Rt))
3282 // Pd=cmp.lt(Rs, Rt)
3283 // if (Pd.new) Rd=#1
3284 // if (!Pd.new) Rd=#0
3285 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3286 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3287 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
3288 (i32 IntRegs:$Rs))),
3293 // zext( setugt ( Rs, Rt))
3295 // Pd=cmp.gtu(Rs, Rt)
3296 // if (Pd.new) Rd=#1
3297 // if (!Pd.new) Rd=#0
3298 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3299 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
3300 (i32 IntRegs:$Rt))),
3304 // This pattern interefers with coremark performance, not implementing at this
3307 // zext( setgt ( Rs, Rt))
3309 // Pd=cmp.gt(Rs, Rt)
3310 // if (Pd.new) Rd=#1
3311 // if (!Pd.new) Rd=#0
3314 // zext( setuge ( Rs, Rt))
3316 // Pd=cmp.ltu(Rs, Rt)
3317 // if (Pd.new) Rd=#0
3318 // if (!Pd.new) Rd=#1
3319 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
3320 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3321 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
3322 (i32 IntRegs:$Rs))),
3327 // zext( setge ( Rs, Rt))
3329 // Pd=cmp.lt(Rs, Rt)
3330 // if (Pd.new) Rd=#0
3331 // if (!Pd.new) Rd=#1
3332 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3333 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3334 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
3335 (i32 IntRegs:$Rs))),
3340 // zext( setule ( Rs, Rt))
3342 // Pd=cmp.gtu(Rs, Rt)
3343 // if (Pd.new) Rd=#0
3344 // if (!Pd.new) Rd=#1
3345 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3346 (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
3347 (i32 IntRegs:$Rt))),
3352 // zext( setle ( Rs, Rt))
3354 // Pd=cmp.gt(Rs, Rt)
3355 // if (Pd.new) Rd=#0
3356 // if (!Pd.new) Rd=#1
3357 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3358 (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rs),
3359 (i32 IntRegs:$Rt))),
3364 // zext( setult ( and(Rs, 255), u8))
3365 // Use the isdigit transformation below
3367 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
3368 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3369 // The isdigit transformation relies on two 'clever' aspects:
3370 // 1) The data type is unsigned which allows us to eliminate a zero test after
3371 // biasing the expression by 48. We are depending on the representation of
3372 // the unsigned types, and semantics.
3373 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3376 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3377 // The code is transformed upstream of llvm into
3378 // retval = (c-48) < 10 ? 1 : 0;
3379 let AddedComplexity = 139 in
3380 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3381 u7StrictPosImmPred:$src2)))),
3382 (i32 (MUX_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
3383 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
3387 // Pd=cmpb.gtu(Rs,Rt)
3388 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
3389 InputType = "reg" in
3390 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
3391 (ins IntRegs:$src1, IntRegs:$src2),
3392 "$dst = cmpb.gtu($src1, $src2)",
3393 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
3394 (and (i32 IntRegs:$src2), 255)))]>,
3395 Requires<[HasV4T]>, ImmRegRel;
3397 // Following instruction is not being extended as it results into the incorrect
3398 // code for negative numbers.
3400 // Signed half compare(.eq) ri.
3401 // Pd=cmph.eq(Rs,#s8)
3402 let isCompare = 1, validSubTargets = HasV4SubT in
3403 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
3404 (ins IntRegs:$src1, s8Imm:$src2),
3405 "$dst = cmph.eq($src1, #$src2)",
3406 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
3407 s8ImmPred:$src2))]>,
3410 // Signed half compare(.eq) rr.
3411 // Case 1: xor + and, then compare:
3413 // r0=and(r0,#0xffff)
3415 // Pd=cmph.eq(Rs,Rt)
3416 let isCompare = 1, validSubTargets = HasV4SubT in
3417 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
3418 (ins IntRegs:$src1, IntRegs:$src2),
3419 "$dst = cmph.eq($src1, $src2)",
3420 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
3421 (i32 IntRegs:$src2)),
3425 // Signed half compare(.eq) rr.
3426 // Case 2: shift left 16 bits then compare:
3430 // Pd=cmph.eq(Rs,Rt)
3431 let isCompare = 1, validSubTargets = HasV4SubT in
3432 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
3433 (ins IntRegs:$src1, IntRegs:$src2),
3434 "$dst = cmph.eq($src1, $src2)",
3435 [(set (i1 PredRegs:$dst),
3436 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
3437 (shl (i32 IntRegs:$src2), (i32 16))))]>,
3440 /* Incorrect Pattern -- immediate should be right shifted before being
3441 used in the cmph.gt instruction.
3442 // Signed half compare(.gt) ri.
3443 // Pd=cmph.gt(Rs,#s8)
3445 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
3446 isCompare = 1, validSubTargets = HasV4SubT in
3447 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
3448 (ins IntRegs:$src1, s8Ext:$src2),
3449 "$dst = cmph.gt($src1, #$src2)",
3450 [(set (i1 PredRegs:$dst),
3451 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3452 s8ExtPred:$src2))]>,
3456 // Signed half compare(.gt) rr.
3457 // Pd=cmph.gt(Rs,Rt)
3458 let isCompare = 1, validSubTargets = HasV4SubT in
3459 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
3460 (ins IntRegs:$src1, IntRegs:$src2),
3461 "$dst = cmph.gt($src1, $src2)",
3462 [(set (i1 PredRegs:$dst),
3463 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3464 (shl (i32 IntRegs:$src2), (i32 16))))]>,
3467 // Unsigned half compare rr (.gtu).
3468 // Pd=cmph.gtu(Rs,Rt)
3469 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
3470 InputType = "reg" in
3471 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
3472 (ins IntRegs:$src1, IntRegs:$src2),
3473 "$dst = cmph.gtu($src1, $src2)",
3474 [(set (i1 PredRegs:$dst),
3475 (setugt (and (i32 IntRegs:$src1), 65535),
3476 (and (i32 IntRegs:$src2), 65535)))]>,
3477 Requires<[HasV4T]>, ImmRegRel;
3479 // Unsigned half compare ri (.gtu).
3480 // Pd=cmph.gtu(Rs,#u7)
3481 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
3482 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
3483 InputType = "imm" in
3484 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
3485 (ins IntRegs:$src1, u7Ext:$src2),
3486 "$dst = cmph.gtu($src1, #$src2)",
3487 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
3488 u7ExtPred:$src2))]>,
3489 Requires<[HasV4T]>, ImmRegRel;
3491 let validSubTargets = HasV4SubT in
3492 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3493 "$dst = !tstbit($src1, $src2)",
3494 [(set (i1 PredRegs:$dst),
3495 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
3498 let validSubTargets = HasV4SubT in
3499 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
3500 "$dst = !tstbit($src1, $src2)",
3501 [(set (i1 PredRegs:$dst),
3502 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
3505 //===----------------------------------------------------------------------===//
3507 //===----------------------------------------------------------------------===//
3509 //Deallocate frame and return.
3511 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
3512 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
3513 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
3519 // Restore registers and dealloc return function call.
3520 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3521 Defs = [R29, R30, R31, PC] in {
3522 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
3523 (ins calltarget:$dst),
3524 "jump $dst // Restore_and_dealloc_return",
3529 // Restore registers and dealloc frame before a tail call.
3530 let isCall = 1, isBarrier = 1,
3531 Defs = [R29, R30, R31, PC] in {
3532 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3533 (ins calltarget:$dst),
3534 "call $dst // Restore_and_dealloc_before_tailcall",
3539 // Save registers function call.
3540 let isCall = 1, isBarrier = 1,
3541 Uses = [R29, R31] in {
3542 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3543 (ins calltarget:$dst),
3544 "call $dst // Save_calle_saved_registers",
3549 // if (Ps) dealloc_return
3550 let isReturn = 1, isTerminator = 1,
3551 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
3552 isPredicated = 1 in {
3553 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
3554 (ins PredRegs:$src1, i32imm:$amt1),
3555 "if ($src1) dealloc_return",
3560 // if (!Ps) dealloc_return
3561 let isReturn = 1, isTerminator = 1,
3562 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
3563 isPredicated = 1 in {
3564 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3566 "if (!$src1) dealloc_return",
3571 // if (Ps.new) dealloc_return:nt
3572 let isReturn = 1, isTerminator = 1,
3573 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
3574 isPredicated = 1 in {
3575 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3577 "if ($src1.new) dealloc_return:nt",
3582 // if (!Ps.new) dealloc_return:nt
3583 let isReturn = 1, isTerminator = 1,
3584 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
3585 isPredicated = 1 in {
3586 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3588 "if (!$src1.new) dealloc_return:nt",
3593 // if (Ps.new) dealloc_return:t
3594 let isReturn = 1, isTerminator = 1,
3595 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
3596 isPredicated = 1 in {
3597 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3599 "if ($src1.new) dealloc_return:t",
3604 // if (!Ps.new) dealloc_return:nt
3605 let isReturn = 1, isTerminator = 1,
3606 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
3607 isPredicated = 1 in {
3608 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
3610 "if (!$src1.new) dealloc_return:t",
3615 // Load/Store with absolute addressing mode
3618 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3620 let PNewValue = !if(isPredNew, "new", "") in
3621 def NAME#_V4 : STInst2<(outs),
3622 (ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
3623 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3624 ") ")#mnemonic#"(##$absaddr) = $src2",
3629 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3630 let PredSense = !if(PredNot, "false", "true") in {
3631 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3633 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3637 let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
3638 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3639 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3640 let opExtendable = 0, isPredicable = 1 in
3641 def NAME#_V4 : STInst2<(outs),
3642 (ins globaladdressExt:$absaddr, RC:$src),
3643 mnemonic#"(##$absaddr) = $src",
3647 let opExtendable = 1, isPredicated = 1 in {
3648 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
3649 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
3654 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
3656 let PNewValue = !if(isPredNew, "new", "") in
3657 def NAME#_nv_V4 : NVInst_V4<(outs),
3658 (ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
3659 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3660 ") ")#mnemonic#"(##$absaddr) = $src2.new",
3665 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
3666 let PredSense = !if(PredNot, "false", "true") in {
3667 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
3669 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
3673 let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
3674 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
3675 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3676 let opExtendable = 0, isPredicable = 1 in
3677 def NAME#_nv_V4 : NVInst_V4<(outs),
3678 (ins globaladdressExt:$absaddr, RC:$src),
3679 mnemonic#"(##$absaddr) = $src.new",
3683 let opExtendable = 1, isPredicated = 1 in {
3684 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3685 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3690 let addrMode = Absolute in {
3691 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
3692 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
3694 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
3695 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
3697 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
3698 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
3700 let isNVStorable = 0 in
3701 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
3704 let Predicates = [HasV4T], AddedComplexity = 30 in {
3705 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3706 (HexagonCONST32 tglobaladdr:$absaddr)),
3707 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3709 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3710 (HexagonCONST32 tglobaladdr:$absaddr)),
3711 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3713 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3714 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3716 def : Pat<(store (i64 DoubleRegs:$src1),
3717 (HexagonCONST32 tglobaladdr:$absaddr)),
3718 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3721 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3723 let PNewValue = !if(isPredNew, "new", "") in
3724 def NAME : LDInst2<(outs RC:$dst),
3725 (ins PredRegs:$src1, globaladdressExt:$absaddr),
3726 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3727 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
3732 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3733 let PredSense = !if(PredNot, "false", "true") in {
3734 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3736 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3740 let isExtended = 1, neverHasSideEffects = 1 in
3741 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3742 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3743 let opExtendable = 1, isPredicable = 1 in
3744 def NAME#_V4 : LDInst2<(outs RC:$dst),
3745 (ins globaladdressExt:$absaddr),
3746 "$dst = "#mnemonic#"(##$absaddr)",
3750 let opExtendable = 2, isPredicated = 1 in {
3751 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3752 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3757 let addrMode = Absolute in {
3758 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
3759 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
3760 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
3761 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
3762 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
3763 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
3766 let Predicates = [HasV4T], AddedComplexity = 30 in
3767 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3768 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
3770 let Predicates = [HasV4T], AddedComplexity=30 in
3771 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3772 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
3774 let Predicates = [HasV4T], AddedComplexity=30 in
3775 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3776 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
3778 let Predicates = [HasV4T], AddedComplexity=30 in
3779 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3780 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
3782 let Predicates = [HasV4T], AddedComplexity=30 in
3783 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3784 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
3786 // Transfer global address into a register
3787 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
3788 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
3790 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3793 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3794 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3795 (ins PredRegs:$src1, globaladdress:$src2),
3796 "if($src1) $dst = ##$src2",
3800 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3801 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3802 (ins PredRegs:$src1, globaladdress:$src2),
3803 "if(!$src1) $dst = ##$src2",
3807 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3808 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3809 (ins PredRegs:$src1, globaladdress:$src2),
3810 "if($src1.new) $dst = ##$src2",
3814 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
3815 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3816 (ins PredRegs:$src1, globaladdress:$src2),
3817 "if(!$src1.new) $dst = ##$src2",
3821 let AddedComplexity = 50, Predicates = [HasV4T] in
3822 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3823 (TFRI_V4 tglobaladdr:$src1)>;
3826 // Load - Indirect with long offset: These instructions take global address
3828 let AddedComplexity = 10 in
3829 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3830 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
3831 "$dst=memd($src1<<#$src2+##$offset)",
3832 [(set (i64 DoubleRegs:$dst),
3833 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3834 (HexagonCONST32 tglobaladdr:$offset))))]>,
3837 let AddedComplexity = 10 in
3838 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3839 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3840 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
3841 !strconcat("$dst = ",
3842 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3844 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3845 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3849 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3850 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3851 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3852 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3853 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3855 // Store - Indirect with long offset: These instructions take global address
3857 let AddedComplexity = 10 in
3858 def STrid_ind_lo_V4 : STInst<(outs),
3859 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
3861 "memd($src1<<#$src2+#$src3) = $src4",
3862 [(store (i64 DoubleRegs:$src4),
3863 (add (shl IntRegs:$src1, u2ImmPred:$src2),
3864 (HexagonCONST32 tglobaladdr:$src3)))]>,
3867 let AddedComplexity = 10 in
3868 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
3869 def _lo_V4 : STInst<(outs),
3870 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
3872 !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
3873 [(OpNode (i32 IntRegs:$src4),
3874 (add (shl IntRegs:$src1, u2ImmPred:$src2),
3875 (HexagonCONST32 tglobaladdr:$src3)))]>,
3879 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
3880 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
3881 defm STriw_ind : ST_indirect_lo<"memw", store>;
3883 // Store - absolute addressing mode: These instruction take constant
3884 // value as the extended operand.
3885 multiclass ST_absimm<string OpcStr> {
3886 let isExtended = 1, opExtendable = 0, isPredicable = 1,
3887 validSubTargets = HasV4SubT in
3888 def _abs_V4 : STInst2<(outs),
3889 (ins u0AlwaysExt:$src1, IntRegs:$src2),
3890 !strconcat(OpcStr, "(##$src1) = $src2"),
3894 let isExtended = 1, opExtendable = 1, isPredicated = 1,
3895 validSubTargets = HasV4SubT in {
3896 def _abs_cPt_V4 : STInst2<(outs),
3897 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3898 !strconcat("if ($src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
3902 def _abs_cNotPt_V4 : STInst2<(outs),
3903 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3904 !strconcat("if (!$src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
3908 def _abs_cdnPt_V4 : STInst2<(outs),
3909 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3910 !strconcat("if ($src1.new)",
3911 !strconcat(OpcStr, "(##$src2) = $src3")),
3915 def _abs_cdnNotPt_V4 : STInst2<(outs),
3916 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3917 !strconcat("if (!$src1.new)",
3918 !strconcat(OpcStr, "(##$src2) = $src3")),
3923 let isExtended = 1, opExtendable = 0, mayStore = 1, isNVStore = 1,
3924 validSubTargets = HasV4SubT in
3925 def _abs_nv_V4 : NVInst_V4<(outs),
3926 (ins u0AlwaysExt:$src1, IntRegs:$src2),
3927 !strconcat(OpcStr, "(##$src1) = $src2.new"),
3931 let isExtended = 1, opExtendable = 1, mayStore = 1, isPredicated = 1,
3932 isNVStore = 1, validSubTargets = HasV4SubT in {
3933 def _abs_cPt_nv_V4 : NVInst_V4<(outs),
3934 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3935 !strconcat("if ($src1)",
3936 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3940 def _abs_cNotPt_nv_V4 : NVInst_V4<(outs),
3941 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3942 !strconcat("if (!$src1)",
3943 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3947 def _abs_cdnPt_nv_V4 : NVInst_V4<(outs),
3948 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3949 !strconcat("if ($src1.new)",
3950 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3954 def _abs_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3955 (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
3956 !strconcat("if (!$src1.new)",
3957 !strconcat(OpcStr, "(##$src2) = $src3.new")),
3963 defm STrib_imm : ST_absimm<"memb">;
3964 defm STrih_imm : ST_absimm<"memh">;
3965 defm STriw_imm : ST_absimm<"memw">;
3967 let Predicates = [HasV4T], AddedComplexity = 30 in {
3968 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3969 (STrib_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3971 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3972 (STrih_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3974 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3975 (STriw_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3978 // Load - absolute addressing mode: These instruction take constant
3979 // value as the extended operand
3981 multiclass LD_absimm<string OpcStr> {
3982 let isExtended = 1, opExtendable = 1, isPredicable = 1,
3983 validSubTargets = HasV4SubT in
3984 def _abs_V4 : LDInst2<(outs IntRegs:$dst),
3985 (ins u0AlwaysExt:$src),
3986 !strconcat("$dst = ",
3987 !strconcat(OpcStr, "(##$src)")),
3991 let isExtended = 1, opExtendable = 2, isPredicated = 1,
3992 validSubTargets = HasV4SubT in {
3993 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
3994 (ins PredRegs:$src1, u0AlwaysExt:$src2),
3995 !strconcat("if ($src1) $dst = ",
3996 !strconcat(OpcStr, "(##$src2)")),
4000 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4001 (ins PredRegs:$src1, u0AlwaysExt:$src2),
4002 !strconcat("if (!$src1) $dst = ",
4003 !strconcat(OpcStr, "(##$src2)")),
4007 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4008 (ins PredRegs:$src1, u0AlwaysExt:$src2),
4009 !strconcat("if ($src1.new) $dst = ",
4010 !strconcat(OpcStr, "(##$src2)")),
4014 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4015 (ins PredRegs:$src1, u0AlwaysExt:$src2),
4016 !strconcat("if (!$src1.new) $dst = ",
4017 !strconcat(OpcStr, "(##$src2)")),
4023 defm LDrib_imm : LD_absimm<"memb">;
4024 defm LDriub_imm : LD_absimm<"memub">;
4025 defm LDrih_imm : LD_absimm<"memh">;
4026 defm LDriuh_imm : LD_absimm<"memuh">;
4027 defm LDriw_imm : LD_absimm<"memw">;
4029 let Predicates = [HasV4T], AddedComplexity = 30 in {
4030 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
4031 (LDriw_imm_abs_V4 u0AlwaysExtPred:$src)>;
4033 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
4034 (LDrib_imm_abs_V4 u0AlwaysExtPred:$src)>;
4036 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
4037 (LDriub_imm_abs_V4 u0AlwaysExtPred:$src)>;
4039 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
4040 (LDrih_imm_abs_V4 u0AlwaysExtPred:$src)>;
4042 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
4043 (LDriuh_imm_abs_V4 u0AlwaysExtPred:$src)>;
4046 // Indexed store double word - global address.
4047 // memw(Rs+#u6:2)=#S8
4048 let AddedComplexity = 10 in
4049 def STriw_offset_ext_V4 : STInst<(outs),
4050 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
4051 "memw($src1+#$src2) = ##$src3",
4052 [(store (HexagonCONST32 tglobaladdr:$src3),
4053 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
4057 // Indexed store double word - global address.
4058 // memw(Rs+#u6:2)=#S8
4059 let AddedComplexity = 10 in
4060 def STrih_offset_ext_V4 : STInst<(outs),
4061 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
4062 "memh($src1+#$src2) = ##$src3",
4063 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
4064 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
4066 // Map from store(globaladdress + x) -> memd(#foo + x)
4067 let AddedComplexity = 100 in
4068 def : Pat<(store (i64 DoubleRegs:$src1),
4069 FoldGlobalAddrGP:$addr),
4070 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
4073 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
4074 (i64 DoubleRegs:$src1)),
4075 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
4078 // Map from store(globaladdress + x) -> memb(#foo + x)
4079 let AddedComplexity = 100 in
4080 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
4081 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4084 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
4085 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4088 // Map from store(globaladdress + x) -> memh(#foo + x)
4089 let AddedComplexity = 100 in
4090 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
4091 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4094 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
4095 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4098 // Map from store(globaladdress + x) -> memw(#foo + x)
4099 let AddedComplexity = 100 in
4100 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
4101 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4104 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
4105 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4108 // Map from load(globaladdress + x) -> memd(#foo + x)
4109 let AddedComplexity = 100 in
4110 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
4111 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
4114 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
4115 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
4118 // Map from load(globaladdress + x) -> memb(#foo + x)
4119 let AddedComplexity = 100 in
4120 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
4121 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
4124 // Map from load(globaladdress + x) -> memb(#foo + x)
4125 let AddedComplexity = 100 in
4126 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
4127 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
4130 //let AddedComplexity = 100 in
4131 let AddedComplexity = 100 in
4132 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
4133 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
4136 // Map from load(globaladdress + x) -> memh(#foo + x)
4137 let AddedComplexity = 100 in
4138 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
4139 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
4142 // Map from load(globaladdress + x) -> memuh(#foo + x)
4143 let AddedComplexity = 100 in
4144 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
4145 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
4148 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
4149 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
4152 // Map from load(globaladdress + x) -> memub(#foo + x)
4153 let AddedComplexity = 100 in
4154 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
4155 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
4158 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
4159 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
4162 // Map from load(globaladdress + x) -> memw(#foo + x)
4163 let AddedComplexity = 100 in
4164 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
4165 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
4168 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
4169 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,