1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def DuplexIClass0: InstDuplex < 0 >;
15 def DuplexIClass1: InstDuplex < 1 >;
16 def DuplexIClass2: InstDuplex < 2 >;
17 let isExtendable = 1 in {
18 def DuplexIClass3: InstDuplex < 3 >;
19 def DuplexIClass4: InstDuplex < 4 >;
20 def DuplexIClass5: InstDuplex < 5 >;
21 def DuplexIClass6: InstDuplex < 6 >;
22 def DuplexIClass7: InstDuplex < 7 >;
24 def DuplexIClass8: InstDuplex < 8 >;
25 def DuplexIClass9: InstDuplex < 9 >;
26 def DuplexIClassA: InstDuplex < 0xA >;
27 def DuplexIClassB: InstDuplex < 0xB >;
28 def DuplexIClassC: InstDuplex < 0xC >;
29 def DuplexIClassD: InstDuplex < 0xD >;
30 def DuplexIClassE: InstDuplex < 0xE >;
31 def DuplexIClassF: InstDuplex < 0xF >;
33 def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
34 def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
36 let hasSideEffects = 0 in
37 class T_Immext<Operand ImmType>
38 : EXTENDERInst<(outs), (ins ImmType:$imm),
39 "immext(#$imm)", []> {
43 let Inst{27-16} = imm{31-20};
44 let Inst{13-0} = imm{19-6};
47 def A4_ext : T_Immext<u26_6Imm>;
48 let isCodeGenOnly = 1 in {
50 def A4_ext_b : T_Immext<brtarget>;
52 def A4_ext_c : T_Immext<calltarget>;
53 def A4_ext_g : T_Immext<globaladdress>;
56 def BITPOS32 : SDNodeXForm<imm, [{
57 // Return the bit position we will set [0-31].
59 int32_t imm = N->getSExtValue();
60 return XformMskToBitPosU5Imm(imm);
63 // Hexagon V4 Architecture spec defines 8 instruction classes:
64 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
68 // ========================================
69 // Loads (8/16/32/64 bit)
73 // ========================================
74 // Stores (8/16/32/64 bit)
77 // ALU32 Instructions:
78 // ========================================
79 // Arithmetic / Logical (32 bit)
82 // XTYPE Instructions (32/64 bit):
83 // ========================================
84 // Arithmetic, Logical, Bit Manipulation
85 // Multiply (Integer, Fractional, Complex)
86 // Permute / Vector Permute Operations
87 // Predicate Operations
88 // Shift / Shift with Add/Sub/Logical
90 // Vector Halfword (ALU, Shift, Multiply)
91 // Vector Word (ALU, Shift)
94 // ========================================
95 // Jump/Call PC-relative
98 // ========================================
101 // MEMOP Instructions:
102 // ========================================
103 // Operation on memory (8/16/32 bit)
106 // ========================================
111 // ========================================
112 // Control-Register Transfers
113 // Hardware Loop Setup
114 // Predicate Logicals & Reductions
116 // SYSTEM Instructions (not implemented in the compiler):
117 // ========================================
123 //===----------------------------------------------------------------------===//
125 //===----------------------------------------------------------------------===//
127 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
129 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
130 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
133 let BaseOpcode = "andn_rr", CextOpcode = "andn" in
134 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
135 let BaseOpcode = "orn_rr", CextOpcode = "orn" in
136 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
138 let CextOpcode = "rcmp.eq" in
139 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
140 let CextOpcode = "!rcmp.eq" in
141 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
143 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
144 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
145 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
147 // Pats for instruction selection.
149 // A class to embed the usual comparison patfrags within a zext to i32.
150 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
151 // names, or else the frag's "body" won't match the operands.
152 class CmpInReg<PatFrag Op>
153 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
155 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
156 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
158 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
159 def: T_cmp32_rr_pat<C4_cmplteu, setule, i1>;
161 def: T_cmp32_rr_pat<C4_cmplteu, RevCmp<setuge>, i1>;
163 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
164 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
165 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
167 let InputType = "reg";
168 let CextOpcode = mnemonic;
170 let isCommutable = IsComm;
171 let hasSideEffects = 0;
178 let Inst{27-21} = 0b0111110;
179 let Inst{20-16} = Rs;
181 let Inst{7-5} = MinOp;
185 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
186 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
187 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
188 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
189 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
190 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
192 let AddedComplexity = 100 in {
193 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
195 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
196 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
198 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
199 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
201 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
202 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
204 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
207 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
208 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
209 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
210 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
212 let InputType = "imm";
213 let CextOpcode = mnemonic;
215 let isCommutable = IsComm;
216 let hasSideEffects = 0;
217 let isExtendable = IsImmExt;
218 let opExtendable = !if (IsImmExt, 2, 0);
219 let isExtentSigned = IsImmSigned;
220 let opExtentBits = ImmBits;
227 let Inst{27-24} = 0b1101;
228 let Inst{22-21} = MajOp;
229 let Inst{20-16} = Rs;
230 let Inst{12-5} = Imm;
232 let Inst{3} = IsHalf;
236 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
237 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
238 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
239 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
240 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
241 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
243 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
244 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
245 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
247 let InputType = "imm";
248 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
249 let isExtendable = 1;
250 let opExtendable = 2;
251 let isExtentSigned = 1;
252 let opExtentBits = 8;
260 let Inst{27-24} = 0b0011;
262 let Inst{21} = IsNeg;
263 let Inst{20-16} = Rs;
269 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
270 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
272 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
273 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
274 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
275 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
277 // Preserve the S2_tstbit_r generation
278 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
279 (i32 IntRegs:$src1))), 0)))),
280 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
282 //===----------------------------------------------------------------------===//
284 //===----------------------------------------------------------------------===//
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 // Combine a word and an immediate into a register pair.
292 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
294 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
295 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
301 let Inst{27-24} = 0b0011;
302 let Inst{22-21} = MajOp;
303 let Inst{20-16} = Rs;
309 let opExtendable = 2 in
310 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
311 "$Rdd = combine($Rs, #$s8)">;
313 let opExtendable = 1 in
314 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
315 "$Rdd = combine(#$s8, $Rs)">;
317 // The complexity of the combines involving immediates should be greater
318 // than the complexity of the combine with two registers.
319 let AddedComplexity = 50 in {
320 def: Pat<(HexagonCOMBINE IntRegs:$r, s8ExtPred:$i),
321 (A4_combineri IntRegs:$r, s8ExtPred:$i)>;
323 def: Pat<(HexagonCOMBINE s8ExtPred:$i, IntRegs:$r),
324 (A4_combineir s8ExtPred:$i, IntRegs:$r)>;
327 // A4_combineii: Set two small immediates.
328 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
329 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
330 "$Rdd = combine(#$s8, #$U6)"> {
336 let Inst{27-23} = 0b11001;
337 let Inst{20-16} = U6{5-1};
338 let Inst{13} = U6{0};
343 // The complexity of the combine with two immediates should be greater than
344 // the complexity of a combine involving a register.
345 let AddedComplexity = 75 in
346 def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u6ExtPred:$u6),
347 (A4_combineii imm:$s8, imm:$u6)>;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 def Zext64: OutPatFrag<(ops node:$Rs),
358 (i64 (A4_combineir 0, (i32 $Rs)))>;
359 def Sext64: OutPatFrag<(ops node:$Rs),
360 (i64 (A2_sxtw (i32 $Rs)))>;
362 // Patterns to generate indexed loads with different forms of the address:
365 // - base (without offset).
366 multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
367 PatLeaf ImmPred, InstHexagon MI> {
368 def: Pat<(VT (Load AddrFI:$fi)),
369 (VT (ValueMod (MI AddrFI:$fi, 0)))>;
370 def: Pat<(VT (Load (add AddrFI:$fi, ImmPred:$Off))),
371 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
372 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
373 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
374 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
375 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
378 defm: Loadxm_pat<extloadi1, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
379 defm: Loadxm_pat<extloadi8, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
380 defm: Loadxm_pat<extloadi16, i64, Zext64, s11_1ExtPred, L2_loadruh_io>;
381 defm: Loadxm_pat<zextloadi1, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
382 defm: Loadxm_pat<zextloadi8, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
383 defm: Loadxm_pat<zextloadi16, i64, Zext64, s11_1ExtPred, L2_loadruh_io>;
384 defm: Loadxm_pat<sextloadi8, i64, Sext64, s11_0ExtPred, L2_loadrb_io>;
385 defm: Loadxm_pat<sextloadi16, i64, Sext64, s11_1ExtPred, L2_loadrh_io>;
387 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
388 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
390 //===----------------------------------------------------------------------===//
391 // Template class for load instructions with Absolute set addressing mode.
392 //===----------------------------------------------------------------------===//
393 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
394 hasSideEffects = 0 in
395 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
396 LDInst<(outs RC:$dst1, IntRegs:$dst2),
398 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
406 let Inst{27-25} = 0b101;
407 let Inst{24-21} = MajOp;
408 let Inst{13-12} = 0b01;
409 let Inst{4-0} = dst1;
410 let Inst{20-16} = dst2;
411 let Inst{11-8} = addr{5-2};
412 let Inst{6-5} = addr{1-0};
415 let accessSize = ByteAccess, hasNewValue = 1 in {
416 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
417 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
420 let accessSize = HalfWordAccess, hasNewValue = 1 in {
421 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
422 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
423 def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
424 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
427 let accessSize = WordAccess, hasNewValue = 1 in
428 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
430 let accessSize = WordAccess in {
431 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
432 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
435 let accessSize = DoubleWordAccess in
436 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
438 let accessSize = ByteAccess in
439 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
441 let accessSize = HalfWordAccess in
442 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
444 // Load - Indirect with long offset
445 let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
446 opExtentBits = 6, opExtendable = 3 in
447 class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
449 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
450 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
456 let CextOpcode = CextOp;
457 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
460 let Inst{27-25} = 0b110;
461 let Inst{24-21} = MajOp;
462 let Inst{20-16} = src1;
463 let Inst{13} = src2{1};
465 let Inst{11-8} = src3{5-2};
466 let Inst{7} = src2{0};
467 let Inst{6-5} = src3{1-0};
471 let accessSize = ByteAccess in {
472 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
473 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
474 def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
478 let accessSize = HalfWordAccess in {
479 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
480 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
481 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
482 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
483 def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
487 let accessSize = WordAccess in {
488 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
489 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
490 def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
493 let accessSize = DoubleWordAccess in
494 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
497 multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
498 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
499 (HexagonCONST32 tglobaladdr:$src3)))),
500 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
502 def : Pat <(VT (ldOp (add IntRegs:$src1,
503 (HexagonCONST32 tglobaladdr:$src2)))),
504 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
507 let AddedComplexity = 60 in {
508 defm : T_LoadAbsReg_Pat <sextloadi8, L4_loadrb_ur>;
509 defm : T_LoadAbsReg_Pat <zextloadi8, L4_loadrub_ur>;
510 defm : T_LoadAbsReg_Pat <extloadi8, L4_loadrub_ur>;
512 defm : T_LoadAbsReg_Pat <sextloadi16, L4_loadrh_ur>;
513 defm : T_LoadAbsReg_Pat <zextloadi16, L4_loadruh_ur>;
514 defm : T_LoadAbsReg_Pat <extloadi16, L4_loadruh_ur>;
516 defm : T_LoadAbsReg_Pat <load, L4_loadri_ur>;
517 defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
520 //===----------------------------------------------------------------------===//
521 // Template classes for the non-predicated load instructions with
522 // base + register offset addressing mode
523 //===----------------------------------------------------------------------===//
524 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
525 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
526 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
527 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
535 let Inst{27-24} = 0b1010;
536 let Inst{23-21} = MajOp;
537 let Inst{20-16} = src1;
538 let Inst{12-8} = src2;
539 let Inst{13} = u2{1};
544 //===----------------------------------------------------------------------===//
545 // Template classes for the predicated load instructions with
546 // base + register offset addressing mode
547 //===----------------------------------------------------------------------===//
548 let isPredicated = 1 in
549 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
550 bit isNot, bit isPredNew>:
551 LDInst <(outs RC:$dst),
552 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
553 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
554 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
555 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
562 let isPredicatedFalse = isNot;
563 let isPredicatedNew = isPredNew;
567 let Inst{27-26} = 0b00;
568 let Inst{25} = isPredNew;
569 let Inst{24} = isNot;
570 let Inst{23-21} = MajOp;
571 let Inst{20-16} = src2;
572 let Inst{12-8} = src3;
573 let Inst{13} = u2{1};
575 let Inst{6-5} = src1;
579 //===----------------------------------------------------------------------===//
580 // multiclass for load instructions with base + register offset
582 //===----------------------------------------------------------------------===//
583 let hasSideEffects = 0, addrMode = BaseRegOffset in
584 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
586 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
587 InputType = "reg" in {
588 let isPredicable = 1 in
589 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
592 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
593 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
596 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
597 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
601 let hasNewValue = 1, accessSize = ByteAccess in {
602 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
603 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
606 let hasNewValue = 1, accessSize = HalfWordAccess in {
607 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
608 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
611 let hasNewValue = 1, accessSize = WordAccess in
612 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
614 let accessSize = DoubleWordAccess in
615 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
617 // 'def pats' for load instructions with base + register offset and non-zero
618 // immediate value. Immediate value is used to left-shift the second
620 class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
621 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
622 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
623 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
625 let AddedComplexity = 40 in {
626 def: Loadxs_pat<extloadi8, i32, L4_loadrub_rr>;
627 def: Loadxs_pat<zextloadi8, i32, L4_loadrub_rr>;
628 def: Loadxs_pat<sextloadi8, i32, L4_loadrb_rr>;
629 def: Loadxs_pat<extloadi16, i32, L4_loadruh_rr>;
630 def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
631 def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
632 def: Loadxs_pat<load, i32, L4_loadri_rr>;
633 def: Loadxs_pat<load, i64, L4_loadrd_rr>;
636 // 'def pats' for load instruction base + register offset and
637 // zero immediate value.
638 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
639 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
640 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
642 let AddedComplexity = 20 in {
643 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
644 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
645 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
646 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
647 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
648 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
649 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
650 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
654 def: Pat<(i64 (zext (i1 PredRegs:$src1))),
655 (Zext64 (C2_muxii PredRegs:$src1, 1, 0))>;
658 def: Pat<(i64 (zext (i32 IntRegs:$src1))),
659 (Zext64 IntRegs:$src1)>;
662 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
663 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
665 let AddedComplexity = 100 in
666 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
667 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
668 s11_2ExtPred:$offset)))>;
671 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
672 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
678 //===----------------------------------------------------------------------===//
680 //===----------------------------------------------------------------------===//
682 //===----------------------------------------------------------------------===//
683 // Template class for store instructions with Absolute set addressing mode.
684 //===----------------------------------------------------------------------===//
685 let isExtended = 1, opExtendable = 1, opExtentBits = 6,
686 addrMode = AbsoluteSet, isNVStorable = 1 in
687 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
688 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
689 : STInst<(outs IntRegs:$dst),
690 (ins u6Ext:$addr, RC:$src),
691 mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
695 let accessSize = AccessSz;
696 let BaseOpcode = BaseOp#"_AbsSet";
700 let Inst{27-24} = 0b1011;
701 let Inst{23-21} = MajOp;
702 let Inst{20-16} = dst;
704 let Inst{12-8} = src;
706 let Inst{5-0} = addr;
709 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
710 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
712 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
714 let isNVStorable = 0 in {
715 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
716 0b011, HalfWordAccess, 1>;
717 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
718 0b110, DoubleWordAccess>;
721 let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
722 isExtended = 1, opExtentBits= 6 in
723 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
724 MemAccessSize AccessSz >
725 : NVInst <(outs IntRegs:$dst),
726 (ins u6Ext:$addr, IntRegs:$src),
727 mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
731 let accessSize = AccessSz;
732 let BaseOpcode = BaseOp#"_AbsSet";
736 let Inst{27-21} = 0b1011101;
737 let Inst{20-16} = dst;
738 let Inst{13-11} = 0b000;
739 let Inst{12-11} = MajOp;
740 let Inst{10-8} = src;
742 let Inst{5-0} = addr;
745 let mayStore = 1, addrMode = AbsoluteSet in {
746 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
747 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
748 def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
751 let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
752 addrMode = BaseLongOffset, AddedComplexity = 40 in
753 class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
754 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
756 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
757 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
758 []>, ImmRegShl, NewValueRel {
765 let accessSize = AccessSz;
766 let CextOpcode = CextOp;
767 let BaseOpcode = CextOp#"_shl";
770 let Inst{27-24} =0b1101;
771 let Inst{23-21} = MajOp;
772 let Inst{20-16} = src1;
773 let Inst{13} = src2{1};
774 let Inst{12-8} = src4;
776 let Inst{6} = src2{0};
777 let Inst{5-0} = src3;
780 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
781 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
783 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
785 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
786 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
789 let AddedComplexity = 40 in
790 multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
792 def : Pat<(stOp (VT RC:$src4),
793 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
794 u0AlwaysExtPred:$src3)),
795 (MI IntRegs:$src1, u2ImmPred:$src2, u0AlwaysExtPred:$src3, RC:$src4)>;
797 def : Pat<(stOp (VT RC:$src4),
798 (add (shl IntRegs:$src1, u2ImmPred:$src2),
799 (HexagonCONST32 tglobaladdr:$src3))),
800 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
802 def : Pat<(stOp (VT RC:$src4),
803 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
804 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
807 defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
808 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
809 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
810 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
812 let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
813 opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
814 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
815 MemAccessSize AccessSz>
817 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
818 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
824 let CextOpcode = CextOp;
825 let BaseOpcode = CextOp#"_shl";
828 let Inst{27-21} = 0b1101101;
829 let Inst{12-11} = 0b00;
831 let Inst{20-16} = src1;
832 let Inst{13} = src2{1};
833 let Inst{12-11} = MajOp;
834 let Inst{10-8} = src4;
835 let Inst{6} = src2{0};
836 let Inst{5-0} = src3;
839 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
840 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
841 def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
843 //===----------------------------------------------------------------------===//
844 // Template classes for the non-predicated store instructions with
845 // base + register offset addressing mode
846 //===----------------------------------------------------------------------===//
847 let isPredicable = 1 in
848 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
849 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
850 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
851 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
860 let Inst{27-24} = 0b1011;
861 let Inst{23-21} = MajOp;
862 let Inst{20-16} = Rs;
864 let Inst{13} = u2{1};
869 //===----------------------------------------------------------------------===//
870 // Template classes for the predicated store instructions with
871 // base + register offset addressing mode
872 //===----------------------------------------------------------------------===//
873 let isPredicated = 1 in
874 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
875 bit isNot, bit isPredNew, bit isH>
877 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
879 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
880 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
881 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
888 let isPredicatedFalse = isNot;
889 let isPredicatedNew = isPredNew;
893 let Inst{27-26} = 0b01;
894 let Inst{25} = isPredNew;
895 let Inst{24} = isNot;
896 let Inst{23-21} = MajOp;
897 let Inst{20-16} = Rs;
899 let Inst{13} = u2{1};
905 //===----------------------------------------------------------------------===//
906 // Template classes for the new-value store instructions with
907 // base + register offset addressing mode
908 //===----------------------------------------------------------------------===//
909 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
910 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
911 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
912 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
913 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
922 let Inst{27-21} = 0b1011101;
923 let Inst{20-16} = Rs;
925 let Inst{13} = u2{1};
927 let Inst{4-3} = MajOp;
931 //===----------------------------------------------------------------------===//
932 // Template classes for the predicated new-value store instructions with
933 // base + register offset addressing mode
934 //===----------------------------------------------------------------------===//
935 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
936 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
938 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
939 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
940 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
941 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
948 let isPredicatedFalse = isNot;
949 let isPredicatedNew = isPredNew;
952 let Inst{27-26} = 0b01;
953 let Inst{25} = isPredNew;
954 let Inst{24} = isNot;
955 let Inst{23-21} = 0b101;
956 let Inst{20-16} = Rs;
958 let Inst{13} = u2{1};
961 let Inst{4-3} = MajOp;
965 //===----------------------------------------------------------------------===//
966 // multiclass for store instructions with base + register offset addressing
968 //===----------------------------------------------------------------------===//
969 let isNVStorable = 1 in
970 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
971 bits<3> MajOp, bit isH = 0> {
972 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
973 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
976 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
977 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
980 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
981 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
985 //===----------------------------------------------------------------------===//
986 // multiclass for new-value store instructions with base + register offset
988 //===----------------------------------------------------------------------===//
989 let mayStore = 1, isNVStore = 1 in
990 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
992 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
993 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
996 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
997 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
1000 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
1001 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
1005 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
1006 let accessSize = ByteAccess in
1007 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1008 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1010 let accessSize = HalfWordAccess in
1011 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1012 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1014 let accessSize = WordAccess in
1015 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1016 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1018 let isNVStorable = 0, accessSize = DoubleWordAccess in
1019 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1021 let isNVStorable = 0, accessSize = HalfWordAccess in
1022 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1025 class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
1026 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1027 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1028 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1030 let AddedComplexity = 40 in {
1031 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1032 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1033 def: Storexs_pat<store, I32, S4_storeri_rr>;
1034 def: Storexs_pat<store, I64, S4_storerd_rr>;
1037 // memd(Rx++#s4:3)=Rtt
1038 // memd(Rx++#s4:3:circ(Mu))=Rtt
1039 // memd(Rx++I:circ(Mu))=Rtt
1041 // memd(Rx++Mu:brev)=Rtt
1042 // memd(gp+#u16:3)=Rtt
1044 // Store doubleword conditionally.
1045 // if ([!]Pv[.new]) memd(#u6)=Rtt
1046 // TODO: needs to be implemented.
1048 //===----------------------------------------------------------------------===//
1050 //===----------------------------------------------------------------------===//
1051 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1053 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1054 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1055 mnemonic#"($Rs+#$offset)=#$S8",
1056 [], "", V4LDST_tc_st_SLOT01>,
1057 ImmRegRel, PredNewRel {
1063 string OffsetOpStr = !cast<string>(OffsetOp);
1064 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1065 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1066 /* u6_0Imm */ offset{5-0}));
1068 let IClass = 0b0011;
1070 let Inst{27-25} = 0b110;
1071 let Inst{22-21} = MajOp;
1072 let Inst{20-16} = Rs;
1073 let Inst{12-7} = offsetBits;
1074 let Inst{13} = S8{7};
1075 let Inst{6-0} = S8{6-0};
1078 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
1080 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1081 bit isPredNot, bit isPredNew >
1083 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1084 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
1085 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1086 [], "", V4LDST_tc_st_SLOT01>,
1087 ImmRegRel, PredNewRel {
1094 string OffsetOpStr = !cast<string>(OffsetOp);
1095 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1096 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1097 /* u6_0Imm */ offset{5-0}));
1098 let isPredicatedNew = isPredNew;
1099 let isPredicatedFalse = isPredNot;
1101 let IClass = 0b0011;
1103 let Inst{27-25} = 0b100;
1104 let Inst{24} = isPredNew;
1105 let Inst{23} = isPredNot;
1106 let Inst{22-21} = MajOp;
1107 let Inst{20-16} = Rs;
1108 let Inst{13} = S6{5};
1109 let Inst{12-7} = offsetBits;
1111 let Inst{4-0} = S6{4-0};
1115 //===----------------------------------------------------------------------===//
1116 // multiclass for store instructions with base + immediate offset
1117 // addressing mode and immediate stored value.
1118 // mem[bhw](Rx++#s4:3)=#s8
1119 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1120 //===----------------------------------------------------------------------===//
1122 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1124 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1126 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1129 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1131 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1132 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1134 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1135 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1139 let hasSideEffects = 0, addrMode = BaseImmOffset,
1140 InputType = "imm" in {
1141 let accessSize = ByteAccess in
1142 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1144 let accessSize = HalfWordAccess in
1145 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1147 let accessSize = WordAccess in
1148 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1151 def IMM_BYTE : SDNodeXForm<imm, [{
1152 // -1 etc is represented as 255 etc
1153 // assigning to a byte restores our desired signed value.
1154 int8_t imm = N->getSExtValue();
1155 return CurDAG->getTargetConstant(imm, MVT::i32);
1158 def IMM_HALF : SDNodeXForm<imm, [{
1159 // -1 etc is represented as 65535 etc
1160 // assigning to a short restores our desired signed value.
1161 int16_t imm = N->getSExtValue();
1162 return CurDAG->getTargetConstant(imm, MVT::i32);
1165 def IMM_WORD : SDNodeXForm<imm, [{
1166 // -1 etc can be represented as 4294967295 etc
1167 // Currently, it's not doing this. But some optimization
1168 // might convert -1 to a large +ve number.
1169 // assigning to a word restores our desired signed value.
1170 int32_t imm = N->getSExtValue();
1171 return CurDAG->getTargetConstant(imm, MVT::i32);
1174 def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
1175 def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
1176 def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
1178 let AddedComplexity = 40 in {
1179 // Not using frameindex patterns for these stores, because the offset
1180 // is not extendable. This could cause problems during removing the frame
1181 // indices, since the offset with respect to R29/R30 may not fit in the
1183 def: Storexm_add_pat<truncstorei8, s8ExtPred, u6_0ImmPred, ToImmByte,
1185 def: Storexm_add_pat<truncstorei16, s8ExtPred, u6_1ImmPred, ToImmHalf,
1187 def: Storexm_add_pat<store, s8ExtPred, u6_2ImmPred, ToImmWord,
1191 def: Storexm_simple_pat<truncstorei8, s8ExtPred, ToImmByte, S4_storeirb_io>;
1192 def: Storexm_simple_pat<truncstorei16, s8ExtPred, ToImmHalf, S4_storeirh_io>;
1193 def: Storexm_simple_pat<store, s8ExtPred, ToImmWord, S4_storeiri_io>;
1195 // memb(Rx++#s4:0:circ(Mu))=Rt
1196 // memb(Rx++I:circ(Mu))=Rt
1198 // memb(Rx++Mu:brev)=Rt
1199 // memb(gp+#u16:0)=Rt
1202 // TODO: needs to be implemented
1203 // memh(Re=#U6)=Rt.H
1204 // memh(Rs+#s11:1)=Rt.H
1205 // memh(Rs+Ru<<#u2)=Rt.H
1206 // TODO: needs to be implemented.
1208 // memh(Ru<<#u2+#U6)=Rt.H
1209 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1210 // memh(Rx++#s4:1:circ(Mu))=Rt
1211 // memh(Rx++I:circ(Mu))=Rt.H
1212 // memh(Rx++I:circ(Mu))=Rt
1213 // memh(Rx++Mu)=Rt.H
1215 // memh(Rx++Mu:brev)=Rt.H
1216 // memh(Rx++Mu:brev)=Rt
1217 // memh(gp+#u16:1)=Rt
1218 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1219 // if ([!]Pv[.new]) memh(#u6)=Rt
1221 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1222 // TODO: needs to be implemented.
1224 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1225 // TODO: Needs to be implemented.
1229 // TODO: Needs to be implemented.
1230 // memw(Rx++#s4:2)=Rt
1231 // memw(Rx++#s4:2:circ(Mu))=Rt
1232 // memw(Rx++I:circ(Mu))=Rt
1234 // memw(Rx++Mu:brev)=Rt
1236 //===----------------------------------------------------------------------===
1238 //===----------------------------------------------------------------------===
1241 //===----------------------------------------------------------------------===//
1243 //===----------------------------------------------------------------------===//
1245 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1246 class T_store_io_nv <string mnemonic, RegisterClass RC,
1247 Operand ImmOp, bits<2>MajOp>
1248 : NVInst_V4 <(outs),
1249 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1250 mnemonic#"($src1+#$src2) = $src3.new",
1251 [],"",ST_tc_st_SLOT0> {
1253 bits<13> src2; // Actual address offset
1255 bits<11> offsetBits; // Represents offset encoding
1257 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1258 !if (!eq(mnemonic, "memh"), 12,
1259 !if (!eq(mnemonic, "memw"), 13, 0)));
1261 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1262 !if (!eq(mnemonic, "memh"), 1,
1263 !if (!eq(mnemonic, "memw"), 2, 0)));
1265 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1266 !if (!eq(mnemonic, "memh"), src2{11-1},
1267 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1269 let IClass = 0b1010;
1272 let Inst{26-25} = offsetBits{10-9};
1273 let Inst{24-21} = 0b1101;
1274 let Inst{20-16} = src1;
1275 let Inst{13} = offsetBits{8};
1276 let Inst{12-11} = MajOp;
1277 let Inst{10-8} = src3;
1278 let Inst{7-0} = offsetBits{7-0};
1281 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1282 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1283 bits<2>MajOp, bit PredNot, bit isPredNew>
1284 : NVInst_V4 <(outs),
1285 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1286 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1287 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1288 [],"",V2LDST_tc_st_SLOT0> {
1293 bits<6> offsetBits; // Represents offset encoding
1295 let isPredicatedNew = isPredNew;
1296 let isPredicatedFalse = PredNot;
1297 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1298 !if (!eq(mnemonic, "memh"), 7,
1299 !if (!eq(mnemonic, "memw"), 8, 0)));
1301 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1302 !if (!eq(mnemonic, "memh"), 1,
1303 !if (!eq(mnemonic, "memw"), 2, 0)));
1305 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1306 !if (!eq(mnemonic, "memh"), src3{6-1},
1307 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1309 let IClass = 0b0100;
1312 let Inst{26} = PredNot;
1313 let Inst{25} = isPredNew;
1314 let Inst{24-21} = 0b0101;
1315 let Inst{20-16} = src2;
1316 let Inst{13} = offsetBits{5};
1317 let Inst{12-11} = MajOp;
1318 let Inst{10-8} = src4;
1319 let Inst{7-3} = offsetBits{4-0};
1321 let Inst{1-0} = src1;
1324 // multiclass for new-value store instructions with base + immediate offset.
1326 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1328 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1329 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1331 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1332 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1334 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1335 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1337 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1339 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1344 let addrMode = BaseImmOffset, InputType = "imm" in {
1345 let accessSize = ByteAccess in
1346 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1347 u6_0Ext, 0b00>, AddrModeRel;
1349 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1350 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1351 u6_1Ext, 0b01>, AddrModeRel;
1353 let accessSize = WordAccess, opExtentAlign = 2 in
1354 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1355 u6_2Ext, 0b10>, AddrModeRel;
1358 //===----------------------------------------------------------------------===//
1359 // Post increment loads with register offset.
1360 //===----------------------------------------------------------------------===//
1362 let hasNewValue = 1 in
1363 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1365 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1367 let hasSideEffects = 0, addrMode = PostInc in
1368 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1369 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1370 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1371 "$dst = "#mnemonic#"($src2++$src3)", [],
1372 "$src1 = $dst, $src2 = $_dst_"> {
1377 let accessSize = AccessSz;
1378 let IClass = 0b1001;
1380 let Inst{27-25} = 0b110;
1381 let Inst{24-21} = MajOp;
1382 let Inst{20-16} = src2;
1383 let Inst{13} = src3;
1386 let Inst{4-0} = dst;
1389 def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
1390 def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
1392 //===----------------------------------------------------------------------===//
1393 // Template class for non-predicated post increment .new stores
1394 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1395 //===----------------------------------------------------------------------===//
1396 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1397 isNewValue = 1, opNewValue = 3 in
1398 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1399 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1400 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1401 mnemonic#"($src1++#$offset) = $src2.new",
1402 [], "$src1 = $_dst_">,
1409 string ImmOpStr = !cast<string>(ImmOp);
1410 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1411 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1412 /* s4_0Imm */ offset{3-0}));
1413 let IClass = 0b1010;
1415 let Inst{27-21} = 0b1011101;
1416 let Inst{20-16} = src1;
1418 let Inst{12-11} = MajOp;
1419 let Inst{10-8} = src2;
1421 let Inst{6-3} = offsetBits;
1425 //===----------------------------------------------------------------------===//
1426 // Template class for predicated post increment .new stores
1427 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1428 //===----------------------------------------------------------------------===//
1429 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1430 isNewValue = 1, opNewValue = 4 in
1431 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1432 bits<2> MajOp, bit isPredNot, bit isPredNew >
1433 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1434 (ins PredRegs:$src1, IntRegs:$src2,
1435 ImmOp:$offset, IntRegs:$src3),
1436 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1437 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1438 [], "$src2 = $_dst_">,
1446 string ImmOpStr = !cast<string>(ImmOp);
1447 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1448 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1449 /* s4_0Imm */ offset{3-0}));
1450 let isPredicatedNew = isPredNew;
1451 let isPredicatedFalse = isPredNot;
1453 let IClass = 0b1010;
1455 let Inst{27-21} = 0b1011101;
1456 let Inst{20-16} = src2;
1458 let Inst{12-11} = MajOp;
1459 let Inst{10-8} = src3;
1460 let Inst{7} = isPredNew;
1461 let Inst{6-3} = offsetBits;
1462 let Inst{2} = isPredNot;
1463 let Inst{1-0} = src1;
1466 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1467 bits<2> MajOp, bit PredNot> {
1468 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1471 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1474 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1476 let BaseOpcode = "POST_"#BaseOp in {
1477 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1480 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1481 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1485 let accessSize = ByteAccess in
1486 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1488 let accessSize = HalfWordAccess in
1489 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1491 let accessSize = WordAccess in
1492 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1494 //===----------------------------------------------------------------------===//
1495 // Template class for post increment .new stores with register offset
1496 //===----------------------------------------------------------------------===//
1497 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1498 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1499 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1500 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1501 #mnemonic#"($src1++$src2) = $src3.new",
1502 [], "$src1 = $_dst_"> {
1506 let accessSize = AccessSz;
1508 let IClass = 0b1010;
1510 let Inst{27-21} = 0b1101101;
1511 let Inst{20-16} = src1;
1512 let Inst{13} = src2;
1513 let Inst{12-11} = MajOp;
1514 let Inst{10-8} = src3;
1518 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1519 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1520 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1522 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1523 // memb(Rx++I:circ(Mu))=Nt.new
1524 // memb(Rx++Mu:brev)=Nt.new
1525 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1526 // memh(Rx++I:circ(Mu))=Nt.new
1527 // memh(Rx++Mu)=Nt.new
1528 // memh(Rx++Mu:brev)=Nt.new
1530 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1531 // memw(Rx++I:circ(Mu))=Nt.new
1532 // memw(Rx++Mu)=Nt.new
1533 // memw(Rx++Mu:brev)=Nt.new
1535 //===----------------------------------------------------------------------===//
1537 //===----------------------------------------------------------------------===//
1539 //===----------------------------------------------------------------------===//
1541 //===----------------------------------------------------------------------===//
1543 //===----------------------------------------------------------------------===//
1544 // multiclass/template class for the new-value compare jumps with the register
1546 //===----------------------------------------------------------------------===//
1548 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1549 opExtentAlign = 2 in
1550 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1551 bit isNegCond, bit isTak>
1553 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1554 "if ("#!if(isNegCond, "!","")#mnemonic#
1555 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1556 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1557 #!if(isTak, "t","nt")#" $offset", []> {
1561 bits<3> Ns; // New-Value Operand
1562 bits<5> RegOp; // Non-New-Value Operand
1565 let isTaken = isTak;
1566 let isPredicatedFalse = isNegCond;
1567 let opNewValue{0} = NvOpNum;
1569 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1570 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1572 let IClass = 0b0010;
1573 let Inst{27-26} = 0b00;
1574 let Inst{25-23} = majOp;
1575 let Inst{22} = isNegCond;
1576 let Inst{18-16} = Ns;
1577 let Inst{13} = isTak;
1578 let Inst{12-8} = RegOp;
1579 let Inst{21-20} = offset{10-9};
1580 let Inst{7-1} = offset{8-2};
1584 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1586 // Branch not taken:
1587 def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1589 def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1592 // NvOpNum = 0 -> First Operand is a new-value Register
1593 // NvOpNum = 1 -> Second Operand is a new-value Register
1595 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1597 let BaseOpcode = BaseOp#_NVJ in {
1598 defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1599 defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1603 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1604 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1605 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1606 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1607 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1609 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1610 Defs = [PC], hasSideEffects = 0 in {
1611 defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1612 defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1613 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1614 defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1615 defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1618 //===----------------------------------------------------------------------===//
1619 // multiclass/template class for the new-value compare jumps instruction
1620 // with a register and an unsigned immediate (U5) operand.
1621 //===----------------------------------------------------------------------===//
1623 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1624 opExtentAlign = 2 in
1625 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1628 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1629 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1630 #!if(isTak, "t","nt")#" $offset", []> {
1632 let isTaken = isTak;
1633 let isPredicatedFalse = isNegCond;
1634 let isTaken = isTak;
1640 let IClass = 0b0010;
1642 let Inst{25-23} = majOp;
1643 let Inst{22} = isNegCond;
1644 let Inst{18-16} = src1;
1645 let Inst{13} = isTak;
1646 let Inst{12-8} = src2;
1647 let Inst{21-20} = offset{10-9};
1648 let Inst{7-1} = offset{8-2};
1651 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1652 // Branch not taken:
1653 def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1655 def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
1658 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1659 let BaseOpcode = BaseOp#_NVJri in {
1660 defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1661 defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1665 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1666 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1667 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1669 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1670 Defs = [PC], hasSideEffects = 0 in {
1671 defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1672 defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1673 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1676 //===----------------------------------------------------------------------===//
1677 // multiclass/template class for the new-value compare jumps instruction
1678 // with a register and an hardcoded 0/-1 immediate value.
1679 //===----------------------------------------------------------------------===//
1681 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1682 opExtentAlign = 2 in
1683 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1684 bit isNegCond, bit isTak>
1686 (ins IntRegs:$src1, brtarget:$offset),
1687 "if ("#!if(isNegCond, "!","")#mnemonic
1688 #"($src1.new, #"#ImmVal#")) jump:"
1689 #!if(isTak, "t","nt")#" $offset", []> {
1691 let isTaken = isTak;
1692 let isPredicatedFalse = isNegCond;
1693 let isTaken = isTak;
1697 let IClass = 0b0010;
1699 let Inst{25-23} = majOp;
1700 let Inst{22} = isNegCond;
1701 let Inst{18-16} = src1;
1702 let Inst{13} = isTak;
1703 let Inst{21-20} = offset{10-9};
1704 let Inst{7-1} = offset{8-2};
1707 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1709 // Branch not taken:
1710 def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1712 def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1715 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1717 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1718 defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1719 defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1723 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1724 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1725 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1727 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1728 Defs = [PC], hasSideEffects = 0 in {
1729 defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1730 defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1731 defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1734 // J4_hintjumpr: Hint indirect conditional jump.
1735 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
1736 def J4_hintjumpr: JRInst <
1741 let IClass = 0b0101;
1742 let Inst{27-21} = 0b0010101;
1743 let Inst{20-16} = Rs;
1746 //===----------------------------------------------------------------------===//
1748 //===----------------------------------------------------------------------===//
1750 //===----------------------------------------------------------------------===//
1752 //===----------------------------------------------------------------------===//
1755 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1756 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
1757 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1758 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1762 let IClass = 0b0110;
1763 let Inst{27-16} = 0b101001001001;
1764 let Inst{12-7} = u6;
1770 let hasSideEffects = 0 in
1771 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1772 : CRInst<(outs PredRegs:$Pd),
1773 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1774 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1775 !if (IsNeg,"!","") # "$Pu))",
1776 [], "", CR_tc_2early_SLOT23> {
1782 let IClass = 0b0110;
1783 let Inst{27-24} = 0b1011;
1784 let Inst{23} = IsNeg;
1785 let Inst{22-21} = OpBits;
1787 let Inst{17-16} = Ps;
1794 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1795 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1796 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1797 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1798 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1799 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1800 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1801 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1803 // op(Ps, op(Pt, Pu))
1804 class LogLog_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1805 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, I1:$Pu))),
1806 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1808 // op(Ps, op(Pt, ~Pu))
1809 class LogLogNot_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1810 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, (not I1:$Pu)))),
1811 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1813 def: LogLog_pat<and, and, C4_and_and>;
1814 def: LogLog_pat<and, or, C4_and_or>;
1815 def: LogLog_pat<or, and, C4_or_and>;
1816 def: LogLog_pat<or, or, C4_or_or>;
1818 def: LogLogNot_pat<and, and, C4_and_andn>;
1819 def: LogLogNot_pat<and, or, C4_and_orn>;
1820 def: LogLogNot_pat<or, and, C4_or_andn>;
1821 def: LogLogNot_pat<or, or, C4_or_orn>;
1823 //===----------------------------------------------------------------------===//
1824 // PIC: Support for PIC compilations. The patterns and SD nodes defined
1825 // below are needed to support code generation for PIC
1826 //===----------------------------------------------------------------------===//
1828 def SDT_HexagonPICAdd
1829 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1830 def SDT_HexagonGOTAdd
1831 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1833 def SDT_HexagonGOTAddInternal : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1834 def SDT_HexagonGOTAddInternalJT : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1835 def SDT_HexagonGOTAddInternalBA : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1837 def Hexagonpic_add : SDNode<"HexagonISD::PIC_ADD", SDT_HexagonPICAdd>;
1838 def Hexagonat_got : SDNode<"HexagonISD::AT_GOT", SDT_HexagonGOTAdd>;
1839 def Hexagongat_pcrel : SDNode<"HexagonISD::AT_PCREL",
1840 SDT_HexagonGOTAddInternal>;
1841 def Hexagongat_pcrel_jt : SDNode<"HexagonISD::AT_PCREL",
1842 SDT_HexagonGOTAddInternalJT>;
1843 def Hexagongat_pcrel_ba : SDNode<"HexagonISD::AT_PCREL",
1844 SDT_HexagonGOTAddInternalBA>;
1846 // PIC: Map from a block address computation to a PC-relative add
1847 def: Pat<(Hexagongat_pcrel_ba tblockaddress:$src1),
1848 (C4_addipc u6ExtPred:$src1)>;
1850 // PIC: Map from the computation to generate a GOT pointer to a PC-relative add
1851 def: Pat<(Hexagonpic_add texternalsym:$src1),
1852 (C4_addipc u6ExtPred:$src1)>;
1854 // PIC: Map from a jump table address computation to a PC-relative add
1855 def: Pat<(Hexagongat_pcrel_jt tjumptable:$src1),
1856 (C4_addipc u6ExtPred:$src1)>;
1858 // PIC: Map from a GOT-relative symbol reference to a load
1859 def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
1860 (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$src2)>;
1862 // PIC: Map from a static symbol reference to a PC-relative add
1863 def: Pat<(Hexagongat_pcrel tglobaladdr:$src1),
1864 (C4_addipc u6ExtPred:$src1)>;
1866 //===----------------------------------------------------------------------===//
1868 //===----------------------------------------------------------------------===//
1870 //===----------------------------------------------------------------------===//
1872 //===----------------------------------------------------------------------===//
1874 // Logical with-not instructions.
1875 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1876 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1878 def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1879 (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1880 def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1881 (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1883 let hasNewValue = 1, hasSideEffects = 0 in
1884 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1885 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1890 let IClass = 0b1101;
1891 let Inst{27-21} = 0b0101111;
1892 let Inst{20-16} = Rs;
1893 let Inst{12-8} = Rt;
1897 // Add and accumulate.
1898 // Rd=add(Rs,add(Ru,#s6))
1899 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1901 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1902 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1903 "$Rd = add($Rs, add($Ru, #$s6))" ,
1904 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1905 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1906 "", ALU64_tc_2_SLOT23> {
1912 let IClass = 0b1101;
1914 let Inst{27-23} = 0b10110;
1915 let Inst{22-21} = s6{5-4};
1916 let Inst{20-16} = Rs;
1917 let Inst{13} = s6{3};
1918 let Inst{12-8} = Rd;
1919 let Inst{7-5} = s6{2-0};
1923 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1924 opExtentBits = 6, opExtendable = 2 in
1925 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1926 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1927 "$Rd = add($Rs, sub(#$s6, $Ru))",
1928 [], "", ALU64_tc_2_SLOT23> {
1934 let IClass = 0b1101;
1936 let Inst{27-23} = 0b10111;
1937 let Inst{22-21} = s6{5-4};
1938 let Inst{20-16} = Rs;
1939 let Inst{13} = s6{3};
1940 let Inst{12-8} = Rd;
1941 let Inst{7-5} = s6{2-0};
1945 // Rd=add(Rs,sub(#s6,Ru))
1946 def: Pat<(add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1947 (i32 IntRegs:$src3))),
1948 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1950 // Rd=sub(add(Rs,#s6),Ru)
1951 def: Pat<(sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1952 (i32 IntRegs:$src3)),
1953 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1955 // Rd=add(sub(Rs,Ru),#s6)
1956 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1957 (s6_10ExtPred:$src2)),
1958 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1961 // Add or subtract doublewords with carry.
1963 // Rdd=add(Rss,Rtt,Px):carry
1965 // Rdd=sub(Rss,Rtt,Px):carry
1968 // Rdd=extract(Rss,#u6,#U6)
1969 // Rdd=extract(Rss,Rtt)
1970 // Rd=extract(Rs,Rtt)
1971 // Rd=extract(Rs,#u5,#U5)
1973 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1974 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1976 let hasNewValue = 1 in {
1977 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1978 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1981 // Complex add/sub halfwords/words
1982 let Defs = [USR_OVF] in {
1983 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1984 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1985 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1986 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1989 let Defs = [USR_OVF] in {
1990 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1991 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
1994 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in {
1995 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1996 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1999 // Logical xor with xor accumulation.
2000 // Rxx^=xor(Rss,Rtt)
2001 let hasSideEffects = 0 in
2003 : SInst <(outs DoubleRegs:$Rxx),
2004 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2005 "$Rxx ^= xor($Rss, $Rtt)",
2006 [(set (i64 DoubleRegs:$Rxx),
2007 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
2008 (i64 DoubleRegs:$Rtt))))],
2009 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
2014 let IClass = 0b1100;
2016 let Inst{27-22} = 0b101010;
2017 let Inst{20-16} = Rss;
2018 let Inst{12-8} = Rtt;
2019 let Inst{7-5} = 0b000;
2020 let Inst{4-0} = Rxx;
2023 // Rotate and reduce bytes
2024 // Rdd=vrcrotate(Rss,Rt,#u2)
2025 let hasSideEffects = 0 in
2027 : SInst <(outs DoubleRegs:$Rdd),
2028 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2029 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
2030 [], "", S_3op_tc_3x_SLOT23> {
2036 let IClass = 0b1100;
2038 let Inst{27-22} = 0b001111;
2039 let Inst{20-16} = Rss;
2040 let Inst{13} = u2{1};
2041 let Inst{12-8} = Rt;
2042 let Inst{7-6} = 0b11;
2043 let Inst{5} = u2{0};
2044 let Inst{4-0} = Rdd;
2047 // Rotate and reduce bytes with accumulation
2048 // Rxx+=vrcrotate(Rss,Rt,#u2)
2049 let hasSideEffects = 0 in
2050 def S4_vrcrotate_acc
2051 : SInst <(outs DoubleRegs:$Rxx),
2052 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2053 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
2054 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2060 let IClass = 0b1100;
2062 let Inst{27-21} = 0b1011101;
2063 let Inst{20-16} = Rss;
2064 let Inst{13} = u2{1};
2065 let Inst{12-8} = Rt;
2066 let Inst{5} = u2{0};
2067 let Inst{4-0} = Rxx;
2070 // Vector reduce conditional negate halfwords
2071 let hasSideEffects = 0 in
2073 : SInst <(outs DoubleRegs:$Rxx),
2074 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2075 "$Rxx += vrcnegh($Rss, $Rt)", [],
2076 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2081 let IClass = 0b1100;
2083 let Inst{27-21} = 0b1011001;
2084 let Inst{20-16} = Rss;
2086 let Inst{12-8} = Rt;
2087 let Inst{7-5} = 0b111;
2088 let Inst{4-0} = Rxx;
2092 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
2094 // Arithmetic/Convergent round
2095 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
2097 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
2099 let Defs = [USR_OVF] in
2100 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
2102 // Logical-logical words.
2103 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
2104 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
2107 ALU64Inst<(outs IntRegs:$Rx),
2108 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2109 "$Rx = or($Ru, and($_src_, #$s10))" ,
2110 [(set (i32 IntRegs:$Rx),
2111 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
2112 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
2117 let IClass = 0b1101;
2119 let Inst{27-22} = 0b101001;
2120 let Inst{20-16} = Rx;
2121 let Inst{21} = s10{9};
2122 let Inst{13-5} = s10{8-0};
2126 // Miscellaneous ALU64 instructions.
2128 let hasNewValue = 1, hasSideEffects = 0 in
2129 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2130 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2135 let IClass = 0b1101;
2136 let Inst{27-21} = 0b0011111;
2137 let Inst{20-16} = Rs;
2138 let Inst{12-8} = Rt;
2139 let Inst{7-5} = 0b111;
2143 let hasSideEffects = 0 in
2144 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2145 (ins IntRegs:$Rs, IntRegs:$Rt),
2146 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2151 let IClass = 0b1101;
2152 let Inst{27-24} = 0b0100;
2154 let Inst{20-16} = Rs;
2155 let Inst{12-8} = Rt;
2159 let hasSideEffects = 0 in
2160 def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
2161 (ins IntRegs:$Rs, IntRegs:$Rt),
2162 "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
2167 let IClass = 0b1101;
2168 let Inst{27-24} = 0b0100;
2170 let Inst{20-16} = Rs;
2171 let Inst{12-8} = Rt;
2175 let hasNewValue = 1, hasSideEffects = 0 in
2176 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2177 (ins IntRegs:$Rs, IntRegs:$Rt),
2178 "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2183 let IClass = 0b1101;
2184 let Inst{27-21} = 0b0101100;
2185 let Inst{20-16} = Rs;
2186 let Inst{12-8} = Rt;
2191 let hasNewValue = 1, hasSideEffects = 0 in
2192 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2193 (ins IntRegs:$Rs, IntRegs:$Rt),
2194 "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2199 let IClass = 0b1101;
2200 let Inst{27-21} = 0b0101100;
2201 let Inst{20-16} = Rt;
2202 let Inst{12-8} = Rs;
2207 // Rx[&|]=xor(Rs,Rt)
2208 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
2209 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
2211 // Rx[&|^]=or(Rs,Rt)
2212 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
2214 let CextOpcode = "ORr_ORr" in
2215 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
2216 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
2218 // Rx[&|^]=and(Rs,Rt)
2219 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
2221 let CextOpcode = "ORr_ANDr" in
2222 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
2223 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
2225 // Rx[&|^]=and(Rs,~Rt)
2226 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
2227 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
2228 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
2230 def: T_MType_acc_pat2 <M4_or_xor, xor, or>;
2231 def: T_MType_acc_pat2 <M4_and_xor, xor, and>;
2232 def: T_MType_acc_pat2 <M4_or_and, and, or>;
2233 def: T_MType_acc_pat2 <M4_and_and, and, and>;
2234 def: T_MType_acc_pat2 <M4_xor_and, and, xor>;
2235 def: T_MType_acc_pat2 <M4_or_or, or, or>;
2236 def: T_MType_acc_pat2 <M4_and_or, or, and>;
2237 def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
2239 class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2240 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
2241 (not IntRegs:$src3)))),
2242 (i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
2244 def: T_MType_acc_pat3 <M4_or_andn, and, or>;
2245 def: T_MType_acc_pat3 <M4_and_andn, and, and>;
2246 def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
2248 // Compound or-or and or-and
2249 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
2250 opExtentBits = 10, opExtendable = 3 in
2251 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2252 : MInst_acc <(outs IntRegs:$Rx),
2253 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2254 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2255 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2256 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
2257 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
2262 let IClass = 0b1101;
2264 let Inst{27-24} = 0b1010;
2265 let Inst{23-22} = MajOp;
2266 let Inst{20-16} = Rs;
2267 let Inst{21} = s10{9};
2268 let Inst{13-5} = s10{8-0};
2272 let CextOpcode = "ORr_ANDr" in
2273 def S4_or_andi : T_CompOR <"and", 0b00, and>;
2275 let CextOpcode = "ORr_ORr" in
2276 def S4_or_ori : T_CompOR <"or", 0b10, or>;
2279 // Rd=modwrap(Rs,Rt)
2281 // Rd=cround(Rs,#u5)
2283 // Rd=round(Rs,#u5)[:sat]
2284 // Rd=round(Rs,Rt)[:sat]
2285 // Vector reduce add unsigned halfwords
2286 // Rd=vraddh(Rss,Rtt)
2288 // Rdd=vaddb(Rss,Rtt)
2289 // Vector conditional negate
2290 // Rdd=vcnegh(Rss,Rt)
2291 // Rxx+=vrcnegh(Rss,Rt)
2292 // Vector maximum bytes
2293 // Rdd=vmaxb(Rtt,Rss)
2294 // Vector reduce maximum halfwords
2295 // Rxx=vrmaxh(Rss,Ru)
2296 // Rxx=vrmaxuh(Rss,Ru)
2297 // Vector reduce maximum words
2298 // Rxx=vrmaxuw(Rss,Ru)
2299 // Rxx=vrmaxw(Rss,Ru)
2300 // Vector minimum bytes
2301 // Rdd=vminb(Rtt,Rss)
2302 // Vector reduce minimum halfwords
2303 // Rxx=vrminh(Rss,Ru)
2304 // Rxx=vrminuh(Rss,Ru)
2305 // Vector reduce minimum words
2306 // Rxx=vrminuw(Rss,Ru)
2307 // Rxx=vrminw(Rss,Ru)
2308 // Vector subtract bytes
2309 // Rdd=vsubb(Rss,Rtt)
2311 //===----------------------------------------------------------------------===//
2313 //===----------------------------------------------------------------------===//
2315 //===----------------------------------------------------------------------===//
2317 //===----------------------------------------------------------------------===//
2320 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2323 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2324 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2325 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2327 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
2328 (S2_ct0p (i64 DoubleRegs:$Rss))>;
2329 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
2330 (S2_ct1p (i64 DoubleRegs:$Rss))>;
2332 let hasSideEffects = 0, hasNewValue = 1 in
2333 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2334 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2338 let IClass = 0b1000;
2339 let Inst{27-24} = 0b1100;
2340 let Inst{23-21} = 0b001;
2341 let Inst{20-16} = Rs;
2342 let Inst{13-8} = s6;
2343 let Inst{7-5} = 0b000;
2347 let hasSideEffects = 0, hasNewValue = 1 in
2348 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2349 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2353 let IClass = 0b1000;
2354 let Inst{27-24} = 0b1000;
2355 let Inst{23-21} = 0b011;
2356 let Inst{20-16} = Rs;
2357 let Inst{13-8} = s6;
2358 let Inst{7-5} = 0b010;
2363 // Bit test/set/clear
2364 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2365 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2367 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2368 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2369 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2370 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2371 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2374 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2375 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2376 // if ([!]tstbit(...)) jump ...
2377 let AddedComplexity = 100 in
2378 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2379 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2381 let AddedComplexity = 100 in
2382 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2383 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2385 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2386 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2387 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2389 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2390 // represented as a compare against "value & 0xFF", which is an exact match
2391 // for cmpb (same for cmph). The patterns below do not contain any additional
2392 // complexity that would make them preferable, and if they were actually used
2393 // instead of cmpb/cmph, they would result in a compare against register that
2394 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2395 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2396 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2397 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2398 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2399 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2400 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2402 //===----------------------------------------------------------------------===//
2404 //===----------------------------------------------------------------------===//
2406 //===----------------------------------------------------------------------===//
2408 //===----------------------------------------------------------------------===//
2410 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2412 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2413 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2414 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2415 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2416 [(set (i32 IntRegs:$Rd),
2417 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2418 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2424 let IClass = 0b1101;
2426 let Inst{27-24} = 0b1000;
2427 let Inst{23} = U6{5};
2428 let Inst{22-21} = u6{5-4};
2429 let Inst{20-16} = Rs;
2430 let Inst{13} = u6{3};
2431 let Inst{12-8} = Rd;
2432 let Inst{7-5} = u6{2-0};
2433 let Inst{4-0} = U6{4-0};
2436 // Rd=add(#u6,mpyi(Rs,Rt))
2437 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2438 isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2439 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2440 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2441 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2442 [(set (i32 IntRegs:$Rd),
2443 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2444 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2450 let IClass = 0b1101;
2452 let Inst{27-23} = 0b01110;
2453 let Inst{22-21} = u6{5-4};
2454 let Inst{20-16} = Rs;
2455 let Inst{13} = u6{3};
2456 let Inst{12-8} = Rt;
2457 let Inst{7-5} = u6{2-0};
2461 let hasNewValue = 1 in
2462 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2463 : ALU64Inst <(outs IntRegs:$dst), ins,
2464 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2466 [(set (i32 IntRegs:$dst),
2467 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2468 "", ALU64_tc_3x_SLOT23> {
2474 let IClass = 0b1101;
2476 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2478 let Inst{27-24} = 0b1111;
2479 let Inst{23} = MajOp;
2480 let Inst{22-21} = ImmValue{5-4};
2481 let Inst{20-16} = src3;
2482 let Inst{13} = ImmValue{3};
2483 let Inst{12-8} = dst;
2484 let Inst{7-5} = ImmValue{2-0};
2485 let Inst{4-0} = src1;
2488 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2489 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2491 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2492 CextOpcode = "ADD_MPY", InputType = "imm" in
2493 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2494 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2496 // Rx=add(Ru,mpyi(Rx,Rs))
2497 let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
2498 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2499 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2500 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2501 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2502 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2503 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2508 let IClass = 0b1110;
2510 let Inst{27-21} = 0b0011000;
2511 let Inst{12-8} = Rx;
2513 let Inst{20-16} = Rs;
2517 // Vector reduce multiply word by signed half (32x16)
2518 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2519 def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
2520 def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
2522 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2523 def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
2524 def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
2526 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
2527 def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
2528 def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
2530 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2531 def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
2532 def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
2534 // Vector multiply halfwords, signed by unsigned
2535 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2536 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
2537 def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
2539 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2540 def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
2541 def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
2543 // Vector polynomial multiply halfwords
2544 // Rdd=vpmpyh(Rs,Rt)
2545 def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
2547 // Rxx^=vpmpyh(Rs,Rt)
2548 def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
2550 // Polynomial multiply words
2552 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2554 // Rxx^=pmpyw(Rs,Rt)
2555 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2557 //===----------------------------------------------------------------------===//
2559 //===----------------------------------------------------------------------===//
2561 //===----------------------------------------------------------------------===//
2562 // ALU64/Vector compare
2563 //===----------------------------------------------------------------------===//
2564 //===----------------------------------------------------------------------===//
2565 // Template class for vector compare
2566 //===----------------------------------------------------------------------===//
2568 let hasSideEffects = 0 in
2569 class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
2570 : ALU64_rr <(outs PredRegs:$Pd),
2571 (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
2572 "$Pd = "#Str#"($Rss, #$Imm)",
2573 [], "", ALU64_tc_2early_SLOT23> {
2578 let ImmBits{6-0} = Imm{6-0};
2579 let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
2581 let IClass = 0b1101;
2583 let Inst{27-24} = 0b1100;
2584 let Inst{22-21} = cmpOp;
2585 let Inst{20-16} = Rss;
2586 let Inst{12-5} = ImmBits;
2587 let Inst{4-3} = minOp;
2591 // Vector compare bytes
2592 def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
2593 def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
2595 let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
2596 def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
2598 def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
2599 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2600 def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
2602 // Vector compare halfwords
2603 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2604 def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
2605 def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
2607 // Vector compare words
2608 def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
2609 def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
2610 def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
2612 //===----------------------------------------------------------------------===//
2614 //===----------------------------------------------------------------------===//
2615 // Shift by immediate and accumulate/logical.
2616 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2617 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2618 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2619 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2620 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2621 hasNewValue = 1, opNewValue = 0 in
2622 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2623 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2624 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2625 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2626 [(set (i32 IntRegs:$Rd),
2627 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2628 "$Rd = $Rx", Itin> {
2635 let IClass = 0b1101;
2636 let Inst{27-24} = 0b1110;
2637 let Inst{23-21} = u8{7-5};
2638 let Inst{20-16} = Rd;
2639 let Inst{13} = u8{4};
2640 let Inst{12-8} = U5;
2641 let Inst{7-5} = u8{3-1};
2642 let Inst{4} = asl_lsr;
2643 let Inst{3} = u8{0};
2644 let Inst{2-1} = MajOp;
2647 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2648 InstrItinClass Itin> {
2649 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2650 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2653 let AddedComplexity = 200 in {
2654 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2655 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2658 let AddedComplexity = 30 in
2659 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2661 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2663 let AddedComplexity = 200 in {
2664 def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2665 (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2666 def: Pat<(add addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2667 (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2668 def: Pat<(sub addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2669 (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2670 def: Pat<(sub addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2671 (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2674 // Vector conditional negate
2675 // Rdd=vcnegh(Rss,Rt)
2676 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2677 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2679 // Rd=[cround|round](Rs,Rt)
2680 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in {
2681 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2682 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2685 // Rd=round(Rs,Rt):sat
2686 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2687 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2689 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2690 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
2691 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2692 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2695 // Rdd=[add|sub](Rss,Rtt,Px):carry
2696 let isPredicateLate = 1, hasSideEffects = 0 in
2697 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2698 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2699 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2700 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2701 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2707 let IClass = 0b1100;
2709 let Inst{27-24} = 0b0010;
2710 let Inst{23-21} = MajOp;
2711 let Inst{20-16} = Rss;
2712 let Inst{12-8} = Rtt;
2714 let Inst{4-0} = Rdd;
2717 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2718 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2720 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2721 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2722 : SInst <(outs DoubleRegs:$Rxx),
2723 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2724 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2725 [] , "$dst2 = $Rxx"> {
2730 let IClass = 0b1100;
2732 let Inst{27-21} = 0b1011001;
2733 let Inst{20-16} = Rss;
2734 let Inst{13} = isUnsigned;
2735 let Inst{12-8} = Rxx;
2736 let Inst{7-5} = MinOp;
2740 // Vector reduce maximum halfwords
2741 // Rxx=vrmax[u]h(Rss,Ru)
2742 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2743 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2745 // Vector reduce maximum words
2746 // Rxx=vrmax[u]w(Rss,Ru)
2747 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2748 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2750 // Vector reduce minimum halfwords
2751 // Rxx=vrmin[u]h(Rss,Ru)
2752 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2753 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2755 // Vector reduce minimum words
2756 // Rxx=vrmin[u]w(Rss,Ru)
2757 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2758 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2760 // Shift an immediate left by register amount.
2761 let hasNewValue = 1, hasSideEffects = 0 in
2762 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2763 "$Rd = lsl(#$s6, $Rt)" ,
2764 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2765 (i32 IntRegs:$Rt)))],
2766 "", S_3op_tc_1_SLOT23> {
2771 let IClass = 0b1100;
2773 let Inst{27-22} = 0b011010;
2774 let Inst{20-16} = s6{5-1};
2775 let Inst{12-8} = Rt;
2776 let Inst{7-6} = 0b11;
2778 let Inst{5} = s6{0};
2781 //===----------------------------------------------------------------------===//
2783 //===----------------------------------------------------------------------===//
2785 //===----------------------------------------------------------------------===//
2786 // MEMOP: Word, Half, Byte
2787 //===----------------------------------------------------------------------===//
2789 def MEMOPIMM : SDNodeXForm<imm, [{
2790 // Call the transformation function XformM5ToU5Imm to get the negative
2791 // immediate's positive counterpart.
2792 int32_t imm = N->getSExtValue();
2793 return XformM5ToU5Imm(imm);
2796 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2797 // -1 .. -31 represented as 65535..65515
2798 // assigning to a short restores our desired signed value.
2799 // Call the transformation function XformM5ToU5Imm to get the negative
2800 // immediate's positive counterpart.
2801 int16_t imm = N->getSExtValue();
2802 return XformM5ToU5Imm(imm);
2805 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2806 // -1 .. -31 represented as 255..235
2807 // assigning to a char restores our desired signed value.
2808 // Call the transformation function XformM5ToU5Imm to get the negative
2809 // immediate's positive counterpart.
2810 int8_t imm = N->getSExtValue();
2811 return XformM5ToU5Imm(imm);
2814 def SETMEMIMM : SDNodeXForm<imm, [{
2815 // Return the bit position we will set [0-31].
2817 int32_t imm = N->getSExtValue();
2818 return XformMskToBitPosU5Imm(imm);
2821 def CLRMEMIMM : SDNodeXForm<imm, [{
2822 // Return the bit position we will clear [0-31].
2824 // we bit negate the value first
2825 int32_t imm = ~(N->getSExtValue());
2826 return XformMskToBitPosU5Imm(imm);
2829 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2830 // Return the bit position we will set [0-15].
2832 int16_t imm = N->getSExtValue();
2833 return XformMskToBitPosU4Imm(imm);
2836 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2837 // Return the bit position we will clear [0-15].
2839 // we bit negate the value first
2840 int16_t imm = ~(N->getSExtValue());
2841 return XformMskToBitPosU4Imm(imm);
2844 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2845 // Return the bit position we will set [0-7].
2847 int8_t imm = N->getSExtValue();
2848 return XformMskToBitPosU3Imm(imm);
2851 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2852 // Return the bit position we will clear [0-7].
2854 // we bit negate the value first
2855 int8_t imm = ~(N->getSExtValue());
2856 return XformMskToBitPosU3Imm(imm);
2859 //===----------------------------------------------------------------------===//
2860 // Template class for MemOp instructions with the register value.
2861 //===----------------------------------------------------------------------===//
2862 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2863 string memOp, bits<2> memOpBits> :
2865 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2866 opc#"($base+#$offset)"#memOp#"$delta",
2868 Requires<[UseMEMOP]> {
2873 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2875 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2876 !if (!eq(opcBits, 0b01), offset{6-1},
2877 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2879 let opExtentAlign = opcBits;
2880 let IClass = 0b0011;
2881 let Inst{27-24} = 0b1110;
2882 let Inst{22-21} = opcBits;
2883 let Inst{20-16} = base;
2885 let Inst{12-7} = offsetBits;
2886 let Inst{6-5} = memOpBits;
2887 let Inst{4-0} = delta;
2890 //===----------------------------------------------------------------------===//
2891 // Template class for MemOp instructions with the immediate value.
2892 //===----------------------------------------------------------------------===//
2893 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2894 string memOp, bits<2> memOpBits> :
2896 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2897 opc#"($base+#$offset)"#memOp#"#$delta"
2898 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2900 Requires<[UseMEMOP]> {
2905 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2907 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2908 !if (!eq(opcBits, 0b01), offset{6-1},
2909 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2911 let opExtentAlign = opcBits;
2912 let IClass = 0b0011;
2913 let Inst{27-24} = 0b1111;
2914 let Inst{22-21} = opcBits;
2915 let Inst{20-16} = base;
2917 let Inst{12-7} = offsetBits;
2918 let Inst{6-5} = memOpBits;
2919 let Inst{4-0} = delta;
2922 // multiclass to define MemOp instructions with register operand.
2923 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2924 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2925 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2926 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2927 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2930 // multiclass to define MemOp instructions with immediate Operand.
2931 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2932 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2933 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2934 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2935 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2938 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2939 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2940 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2943 // Define MemOp instructions.
2944 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
2945 let opExtentBits = 6, accessSize = ByteAccess in
2946 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2948 let opExtentBits = 7, accessSize = HalfWordAccess in
2949 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2951 let opExtentBits = 8, accessSize = WordAccess in
2952 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2955 //===----------------------------------------------------------------------===//
2956 // Multiclass to define 'Def Pats' for ALU operations on the memory
2957 // Here value used for the ALU operation is an immediate value.
2958 // mem[bh](Rs+#0) += #U5
2959 // mem[bh](Rs+#u6) += #U5
2960 //===----------------------------------------------------------------------===//
2962 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2963 InstHexagon MI, SDNode OpNode> {
2964 let AddedComplexity = 180 in
2965 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2967 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
2969 let AddedComplexity = 190 in
2970 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2972 (add IntRegs:$base, ExtPred:$offset)),
2973 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2976 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2977 InstHexagon addMI, InstHexagon subMI> {
2978 defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2979 defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2982 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2984 defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2985 L4_iadd_memoph_io, L4_isub_memoph_io>;
2987 defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2988 L4_iadd_memopb_io, L4_isub_memopb_io>;
2991 let Predicates = [UseMEMOP] in {
2992 defm: MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2993 defm: MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2994 defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2997 defm: MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
3001 //===----------------------------------------------------------------------===//
3002 // multiclass to define 'Def Pats' for ALU operations on the memory.
3003 // Here value used for the ALU operation is a negative value.
3004 // mem[bh](Rs+#0) += #m5
3005 // mem[bh](Rs+#u6) += #m5
3006 //===----------------------------------------------------------------------===//
3008 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3009 PatLeaf immPred, SDNodeXForm xformFunc,
3011 let AddedComplexity = 190 in
3012 def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
3013 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
3015 let AddedComplexity = 195 in
3016 def: Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
3018 (add IntRegs:$base, extPred:$offset)),
3019 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
3022 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3024 defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
3025 MEMOPIMM_HALF, L4_isub_memoph_io>;
3027 defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
3028 MEMOPIMM_BYTE, L4_isub_memopb_io>;
3031 let Predicates = [UseMEMOP] in {
3032 defm: MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
3033 defm: MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
3034 defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
3037 defm: MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
3038 MEMOPIMM, L4_isub_memopw_io>;
3041 //===----------------------------------------------------------------------===//
3042 // Multiclass to define 'def Pats' for bit operations on the memory.
3043 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3044 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
3045 //===----------------------------------------------------------------------===//
3047 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
3048 PatLeaf extPred, SDNodeXForm xformFunc, InstHexagon MI,
3051 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
3052 let AddedComplexity = 250 in
3053 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3055 (add IntRegs:$base, extPred:$offset)),
3056 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
3058 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3059 let AddedComplexity = 225 in
3060 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
3061 (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
3064 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
3066 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
3067 CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
3069 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
3070 SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
3071 // Half Word - clrbit
3072 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
3073 CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
3074 // Half Word - setbit
3075 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
3076 SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
3079 let Predicates = [UseMEMOP] in {
3080 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
3081 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
3082 defm: MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
3083 defm: MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
3084 defm: MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
3086 // memw(Rs+#0) = [clrbit|setbit](#U5)
3087 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
3088 defm: MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, CLRMEMIMM,
3089 L4_iand_memopw_io, and>;
3090 defm: MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, SETMEMIMM,
3091 L4_ior_memopw_io, or>;
3094 //===----------------------------------------------------------------------===//
3095 // Multiclass to define 'def Pats' for ALU operations on the memory
3096 // where addend is a register.
3097 // mem[bhw](Rs+#0) [+-&|]= Rt
3098 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3099 //===----------------------------------------------------------------------===//
3101 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3102 InstHexagon MI, SDNode OpNode> {
3103 let AddedComplexity = 141 in
3104 // mem[bhw](Rs+#0) [+-&|]= Rt
3105 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
3107 (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
3109 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3110 let AddedComplexity = 150 in
3111 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3112 (i32 IntRegs:$orend)),
3113 (add IntRegs:$base, extPred:$offset)),
3114 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
3117 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3118 InstHexagon addMI, InstHexagon subMI,
3119 InstHexagon andMI, InstHexagon orMI> {
3120 defm: MemOpr_Pats <ldOp, stOp, extPred, addMI, add>;
3121 defm: MemOpr_Pats <ldOp, stOp, extPred, subMI, sub>;
3122 defm: MemOpr_Pats <ldOp, stOp, extPred, andMI, and>;
3123 defm: MemOpr_Pats <ldOp, stOp, extPred, orMI, or>;
3126 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3128 defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
3129 L4_add_memoph_io, L4_sub_memoph_io,
3130 L4_and_memoph_io, L4_or_memoph_io>;
3132 defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u6ExtPred,
3133 L4_add_memopb_io, L4_sub_memopb_io,
3134 L4_and_memopb_io, L4_or_memopb_io>;
3137 // Define 'def Pats' for MemOps with register addend.
3138 let Predicates = [UseMEMOP] in {
3140 defm: MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
3141 defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
3142 defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
3144 defm: MemOPr_ALUOp <load, store, u6_2ExtPred, L4_add_memopw_io,
3145 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
3148 //===----------------------------------------------------------------------===//
3150 //===----------------------------------------------------------------------===//
3152 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3153 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3154 // hardware. However, compiler can still implement these patterns through
3155 // appropriate patterns combinations based on current implemented patterns.
3156 // The implemented patterns are: EQ/GT/GTU.
3157 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3159 // Following instruction is not being extended as it results into the
3160 // incorrect code for negative numbers.
3161 // Pd=cmpb.eq(Rs,#u8)
3163 // p=!cmp.eq(r1,#s10)
3164 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
3165 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
3166 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
3168 def : T_CMP_pat <C4_cmpneqi, setne, s10ExtPred>;
3169 def : T_CMP_pat <C4_cmpltei, setle, s10ExtPred>;
3170 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
3172 // rs <= rt -> !(rs > rt).
3174 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
3175 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
3176 // (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
3178 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3179 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
3180 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
3182 // rs != rt -> !(rs == rt).
3183 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
3184 (C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
3186 // SDNode for converting immediate C to C-1.
3187 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
3188 // Return the byte immediate const-1 as an SDNode.
3189 int32_t imm = N->getSExtValue();
3190 return XformU7ToU7M1Imm(imm);
3194 // zext( setult ( and(Rs, 255), u8))
3195 // Use the isdigit transformation below
3197 // Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
3198 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3199 // The isdigit transformation relies on two 'clever' aspects:
3200 // 1) The data type is unsigned which allows us to eliminate a zero test after
3201 // biasing the expression by 48. We are depending on the representation of
3202 // the unsigned types, and semantics.
3203 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3206 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3207 // The code is transformed upstream of llvm into
3208 // retval = (c-48) < 10 ? 1 : 0;
3209 let AddedComplexity = 139 in
3210 def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3211 u7StrictPosImmPred:$src2)))),
3212 (C2_muxii (A4_cmpbgtui IntRegs:$src1,
3213 (DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
3216 //===----------------------------------------------------------------------===//
3218 //===----------------------------------------------------------------------===//
3220 //===----------------------------------------------------------------------===//
3221 // Multiclass for DeallocReturn
3222 //===----------------------------------------------------------------------===//
3223 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3224 : LD0Inst<(outs), (ins PredRegs:$src),
3225 !if(isNot, "if (!$src", "if ($src")#
3226 !if(isPredNew, ".new) ", ") ")#mnemonic#
3227 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3228 [], "", LD_tc_3or4stall_SLOT0> {
3231 let BaseOpcode = "L4_RETURN";
3232 let isPredicatedFalse = isNot;
3233 let isPredicatedNew = isPredNew;
3234 let isTaken = isTak;
3235 let IClass = 0b1001;
3237 let Inst{27-16} = 0b011000011110;
3239 let Inst{13} = isNot;
3240 let Inst{12} = isTak;
3241 let Inst{11} = isPredNew;
3243 let Inst{9-8} = src;
3244 let Inst{4-0} = 0b11110;
3247 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3248 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3249 let isPredicated = 1 in {
3250 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3251 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3252 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3256 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3257 let isBarrier = 1, isPredicable = 1 in
3258 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3259 LD_tc_3or4stall_SLOT0> {
3260 let BaseOpcode = "L4_RETURN";
3261 let IClass = 0b1001;
3262 let Inst{27-16} = 0b011000011110;
3263 let Inst{13-10} = 0b0000;
3264 let Inst{4-0} = 0b11110;
3266 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3267 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3270 let isReturn = 1, isTerminator = 1,
3271 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
3272 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3274 // Restore registers and dealloc return function call.
3275 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3276 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3277 def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
3280 // Restore registers and dealloc frame before a tail call.
3281 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
3282 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
3285 // Save registers function call.
3286 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
3287 def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
3290 //===----------------------------------------------------------------------===//
3291 // Template class for non predicated store instructions with
3292 // GP-Relative or absolute addressing.
3293 //===----------------------------------------------------------------------===//
3294 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3295 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3296 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3297 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3298 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3299 [], "", V2LDST_tc_st_SLOT01> {
3302 bits<16> offsetBits;
3304 string ImmOpStr = !cast<string>(ImmOp);
3305 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3306 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3307 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3308 /* u16_0Imm */ addr{15-0})));
3309 let IClass = 0b0100;
3311 let Inst{26-25} = offsetBits{15-14};
3313 let Inst{23-22} = MajOp;
3314 let Inst{21} = isHalf;
3315 let Inst{20-16} = offsetBits{13-9};
3316 let Inst{13} = offsetBits{8};
3317 let Inst{12-8} = src;
3318 let Inst{7-0} = offsetBits{7-0};
3321 //===----------------------------------------------------------------------===//
3322 // Template class for predicated store instructions with
3323 // GP-Relative or absolute addressing.
3324 //===----------------------------------------------------------------------===//
3325 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3327 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3328 bit isHalf, bit isNot, bit isNew>
3329 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3330 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3331 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3332 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3337 let isPredicatedNew = isNew;
3338 let isPredicatedFalse = isNot;
3340 let IClass = 0b1010;
3342 let Inst{27-24} = 0b1111;
3343 let Inst{23-22} = MajOp;
3344 let Inst{21} = isHalf;
3345 let Inst{17-16} = absaddr{5-4};
3346 let Inst{13} = isNew;
3347 let Inst{12-8} = src2;
3349 let Inst{6-3} = absaddr{3-0};
3350 let Inst{2} = isNot;
3351 let Inst{1-0} = src1;
3354 //===----------------------------------------------------------------------===//
3355 // Template class for predicated store instructions with absolute addressing.
3356 //===----------------------------------------------------------------------===//
3357 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3358 bits<2> MajOp, bit isHalf>
3359 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1, isHalf>,
3361 string ImmOpStr = !cast<string>(ImmOp);
3362 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3363 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3364 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3365 /* u16_0Imm */ 16)));
3367 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3368 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3369 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3370 /* u16_0Imm */ 0)));
3373 //===----------------------------------------------------------------------===//
3374 // Multiclass for store instructions with absolute addressing.
3375 //===----------------------------------------------------------------------===//
3376 let addrMode = Absolute, isExtended = 1 in
3377 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3378 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3379 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3380 let opExtendable = 0, isPredicable = 1 in
3381 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3384 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3385 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3388 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3389 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3393 //===----------------------------------------------------------------------===//
3394 // Template class for non predicated new-value store instructions with
3395 // GP-Relative or absolute addressing.
3396 //===----------------------------------------------------------------------===//
3397 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3398 isNewValue = 1, opNewValue = 1 in
3399 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3400 : NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
3401 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3402 [], "", V2LDST_tc_st_SLOT0> {
3405 bits<16> offsetBits;
3407 string ImmOpStr = !cast<string>(ImmOp);
3408 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3409 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3410 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3411 /* u16_0Imm */ addr{15-0})));
3412 let IClass = 0b0100;
3415 let Inst{26-25} = offsetBits{15-14};
3416 let Inst{24-21} = 0b0101;
3417 let Inst{20-16} = offsetBits{13-9};
3418 let Inst{13} = offsetBits{8};
3419 let Inst{12-11} = MajOp;
3420 let Inst{10-8} = src;
3421 let Inst{7-0} = offsetBits{7-0};
3424 //===----------------------------------------------------------------------===//
3425 // Template class for predicated new-value store instructions with
3426 // absolute addressing.
3427 //===----------------------------------------------------------------------===//
3428 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3429 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3430 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3431 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3432 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3433 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3434 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3439 let isPredicatedNew = isNew;
3440 let isPredicatedFalse = isNot;
3442 let IClass = 0b1010;
3444 let Inst{27-24} = 0b1111;
3445 let Inst{23-21} = 0b101;
3446 let Inst{17-16} = absaddr{5-4};
3447 let Inst{13} = isNew;
3448 let Inst{12-11} = MajOp;
3449 let Inst{10-8} = src2;
3451 let Inst{6-3} = absaddr{3-0};
3452 let Inst{2} = isNot;
3453 let Inst{1-0} = src1;
3456 //===----------------------------------------------------------------------===//
3457 // Template class for non-predicated new-value store instructions with
3458 // absolute addressing.
3459 //===----------------------------------------------------------------------===//
3460 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3461 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3463 string ImmOpStr = !cast<string>(ImmOp);
3464 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3465 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3466 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3467 /* u16_0Imm */ 16)));
3469 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3470 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3471 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3472 /* u16_0Imm */ 0)));
3475 //===----------------------------------------------------------------------===//
3476 // Multiclass for new-value store instructions with absolute addressing.
3477 //===----------------------------------------------------------------------===//
3478 let addrMode = Absolute, isExtended = 1 in
3479 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3481 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3482 let opExtendable = 0, isPredicable = 1 in
3483 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3486 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3487 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3490 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3491 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3495 //===----------------------------------------------------------------------===//
3496 // Stores with absolute addressing
3497 //===----------------------------------------------------------------------===//
3498 let accessSize = ByteAccess in
3499 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3500 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3502 let accessSize = HalfWordAccess in
3503 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3504 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3506 let accessSize = WordAccess in
3507 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3508 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3510 let isNVStorable = 0, accessSize = DoubleWordAccess in
3511 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3513 let isNVStorable = 0, accessSize = HalfWordAccess in
3514 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3516 //===----------------------------------------------------------------------===//
3517 // GP-relative stores.
3518 // mem[bhwd](#global)=Rt
3519 // Once predicated, these instructions map to absolute addressing mode.
3520 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3521 //===----------------------------------------------------------------------===//
3523 let isAsmParserOnly = 1 in
3524 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3525 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3526 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3527 // Set BaseOpcode same as absolute addressing instructions so that
3528 // non-predicated GP-Rel instructions can have relate with predicated
3529 // Absolute instruction.
3530 let BaseOpcode = BaseOp#_abs;
3533 let isAsmParserOnly = 1 in
3534 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3535 bits<2> MajOp, bit isHalf = 0> {
3536 // Set BaseOpcode same as absolute addressing instructions so that
3537 // non-predicated GP-Rel instructions can have relate with predicated
3538 // Absolute instruction.
3539 let BaseOpcode = BaseOp#_abs in {
3540 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3541 globaladdress, 0, isHalf>;
3543 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3547 let accessSize = ByteAccess in
3548 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3550 let accessSize = HalfWordAccess in
3551 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3553 let accessSize = WordAccess in
3554 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3556 let isNVStorable = 0, accessSize = DoubleWordAccess in
3557 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3558 u16_3Imm, 0b11>, PredNewRel;
3560 let isNVStorable = 0, accessSize = HalfWordAccess in
3561 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3562 u16_1Imm, 0b01, 1>, PredNewRel;
3564 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
3565 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
3567 class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
3569 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
3571 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
3572 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
3574 class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
3576 : Pat<(Store Value:$val, Addr:$addr),
3577 (MI Addr:$addr, (ValueMod Value:$val))>;
3579 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
3580 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
3581 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
3582 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdgp>;
3584 let AddedComplexity = 100 in {
3585 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>;
3586 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>;
3587 def: Storea_pat<store, I32, addrgp, S2_storerigp>;
3588 def: Storea_pat<store, I64, addrgp, S2_storerdgp>;
3590 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3591 // to "r0 = 1; memw(#foo) = r0"
3592 let AddedComplexity = 100 in
3593 def: Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3594 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3597 //===----------------------------------------------------------------------===//
3598 // Template class for non predicated load instructions with
3599 // absolute addressing mode.
3600 //===----------------------------------------------------------------------===//
3601 let isPredicable = 1, hasSideEffects = 0 in
3602 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3603 bits<3> MajOp, Operand AddrOp, bit isAbs>
3604 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3605 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3606 [], "", V2LDST_tc_ld_SLOT01> {
3609 bits<16> offsetBits;
3611 string ImmOpStr = !cast<string>(ImmOp);
3612 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3613 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3614 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3615 /* u16_0Imm */ addr{15-0})));
3617 let IClass = 0b0100;
3620 let Inst{26-25} = offsetBits{15-14};
3622 let Inst{23-21} = MajOp;
3623 let Inst{20-16} = offsetBits{13-9};
3624 let Inst{13-5} = offsetBits{8-0};
3625 let Inst{4-0} = dst;
3628 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3630 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1>, AddrModeRel {
3632 string ImmOpStr = !cast<string>(ImmOp);
3633 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3634 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3635 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3636 /* u16_0Imm */ 16)));
3638 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3639 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3640 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3641 /* u16_0Imm */ 0)));
3644 //===----------------------------------------------------------------------===//
3645 // Template class for predicated load instructions with
3646 // absolute addressing mode.
3647 //===----------------------------------------------------------------------===//
3648 let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
3649 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3650 bit isPredNot, bit isPredNew>
3651 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3652 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3653 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3658 let isPredicatedNew = isPredNew;
3659 let isPredicatedFalse = isPredNot;
3660 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
3662 let IClass = 0b1001;
3664 let Inst{27-24} = 0b1111;
3665 let Inst{23-21} = MajOp;
3666 let Inst{20-16} = absaddr{5-1};
3668 let Inst{12} = isPredNew;
3669 let Inst{11} = isPredNot;
3670 let Inst{10-9} = src1;
3671 let Inst{8} = absaddr{0};
3673 let Inst{4-0} = dst;
3676 //===----------------------------------------------------------------------===//
3677 // Multiclass for the load instructions with absolute addressing mode.
3678 //===----------------------------------------------------------------------===//
3679 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3681 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3683 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3686 let addrMode = Absolute, isExtended = 1 in
3687 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3688 Operand ImmOp, bits<3> MajOp> {
3689 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3690 let opExtendable = 1, isPredicable = 1 in
3691 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3694 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3695 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3699 let accessSize = ByteAccess, hasNewValue = 1 in {
3700 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3701 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3704 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3705 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3706 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3709 let accessSize = WordAccess, hasNewValue = 1 in
3710 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3712 let accessSize = DoubleWordAccess in
3713 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3715 //===----------------------------------------------------------------------===//
3716 // multiclass for load instructions with GP-relative addressing mode.
3717 // Rx=mem[bhwd](##global)
3718 // Once predicated, these instructions map to absolute addressing mode.
3719 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3720 //===----------------------------------------------------------------------===//
3722 let isAsmParserOnly = 1 in
3723 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3725 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3726 let BaseOpcode = BaseOp#_abs;
3729 let accessSize = ByteAccess, hasNewValue = 1 in {
3730 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3731 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3734 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3735 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3736 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3739 let accessSize = WordAccess, hasNewValue = 1 in
3740 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3742 let accessSize = DoubleWordAccess in
3743 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3745 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
3746 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
3747 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
3748 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
3750 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3751 def: Loadam_pat<load, i1, addrga, I32toI1, L4_loadrub_abs>;
3752 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
3754 def: Stoream_pat<store, I1, addrga, I1toI32, S2_storerbabs>;
3755 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
3757 // Map from load(globaladdress) -> mem[u][bhwd](#foo)
3758 class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
3759 : Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
3760 (VT (MI tglobaladdr:$global))>;
3762 let AddedComplexity = 100 in {
3763 def: LoadGP_pats <extloadi8, L2_loadrbgp>;
3764 def: LoadGP_pats <sextloadi8, L2_loadrbgp>;
3765 def: LoadGP_pats <zextloadi8, L2_loadrubgp>;
3766 def: LoadGP_pats <extloadi16, L2_loadrhgp>;
3767 def: LoadGP_pats <sextloadi16, L2_loadrhgp>;
3768 def: LoadGP_pats <zextloadi16, L2_loadruhgp>;
3769 def: LoadGP_pats <load, L2_loadrigp>;
3770 def: LoadGP_pats <load, L2_loadrdgp, i64>;
3773 // When the Interprocedural Global Variable optimizer realizes that a certain
3774 // global variable takes only two constant values, it shrinks the global to
3775 // a boolean. Catch those loads here in the following 3 patterns.
3776 let AddedComplexity = 100 in {
3777 def: LoadGP_pats <extloadi1, L2_loadrubgp>;
3778 def: LoadGP_pats <zextloadi1, L2_loadrubgp>;
3781 // Transfer global address into a register
3782 def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3783 def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3784 def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3786 def: Pat<(i64 (ctlz I64:$src1)), (Zext64 (S2_cl0p I64:$src1))>;
3787 def: Pat<(i64 (cttz I64:$src1)), (Zext64 (S2_ct0p I64:$src1))>;
3789 let AddedComplexity = 30 in {
3790 def: Storea_pat<truncstorei8, I32, u0AlwaysExtPred, S2_storerbabs>;
3791 def: Storea_pat<truncstorei16, I32, u0AlwaysExtPred, S2_storerhabs>;
3792 def: Storea_pat<store, I32, u0AlwaysExtPred, S2_storeriabs>;
3795 let AddedComplexity = 30 in {
3796 def: Loada_pat<load, i32, u0AlwaysExtPred, L4_loadri_abs>;
3797 def: Loada_pat<sextloadi8, i32, u0AlwaysExtPred, L4_loadrb_abs>;
3798 def: Loada_pat<zextloadi8, i32, u0AlwaysExtPred, L4_loadrub_abs>;
3799 def: Loada_pat<sextloadi16, i32, u0AlwaysExtPred, L4_loadrh_abs>;
3800 def: Loada_pat<zextloadi16, i32, u0AlwaysExtPred, L4_loadruh_abs>;
3803 // Indexed store word - global address.
3804 // memw(Rs+#u6:2)=#S8
3805 let AddedComplexity = 100 in
3806 def: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
3808 // Load from a global address that has only one use in the current basic block.
3809 let AddedComplexity = 100 in {
3810 def: Loada_pat<extloadi8, i32, addrga, L4_loadrub_abs>;
3811 def: Loada_pat<sextloadi8, i32, addrga, L4_loadrb_abs>;
3812 def: Loada_pat<zextloadi8, i32, addrga, L4_loadrub_abs>;
3814 def: Loada_pat<extloadi16, i32, addrga, L4_loadruh_abs>;
3815 def: Loada_pat<sextloadi16, i32, addrga, L4_loadrh_abs>;
3816 def: Loada_pat<zextloadi16, i32, addrga, L4_loadruh_abs>;
3818 def: Loada_pat<load, i32, addrga, L4_loadri_abs>;
3819 def: Loada_pat<load, i64, addrga, L4_loadrd_abs>;
3822 // Store to a global address that has only one use in the current basic block.
3823 let AddedComplexity = 100 in {
3824 def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
3825 def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
3826 def: Storea_pat<store, I32, addrga, S2_storeriabs>;
3827 def: Storea_pat<store, I64, addrga, S2_storerdabs>;
3829 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
3832 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3833 let AddedComplexity = 100 in
3834 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3835 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3837 // Transfer global address into a register
3838 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3839 isAsCheapAsAMove = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
3840 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3842 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>;
3844 // Transfer a block address into a register
3845 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3846 (TFRI_V4 tblockaddress:$src1)>;
3848 let AddedComplexity = 50 in
3849 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3850 (TFRI_V4 tglobaladdr:$src1)>;
3852 // i8/i16/i32 -> i64 loads
3853 // We need a complexity of 120 here to override preceding handling of
3855 let AddedComplexity = 120 in {
3856 def: Loadam_pat<extloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3857 def: Loadam_pat<sextloadi8, i64, addrga, Sext64, L4_loadrb_abs>;
3858 def: Loadam_pat<zextloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3860 def: Loadam_pat<extloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3861 def: Loadam_pat<sextloadi16, i64, addrga, Sext64, L4_loadrh_abs>;
3862 def: Loadam_pat<zextloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3864 def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3865 def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
3866 def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3869 let AddedComplexity = 100 in {
3870 def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
3871 def: Loada_pat<sextloadi8, i32, addrgp, L4_loadrb_abs>;
3872 def: Loada_pat<zextloadi8, i32, addrgp, L4_loadrub_abs>;
3874 def: Loada_pat<extloadi16, i32, addrgp, L4_loadruh_abs>;
3875 def: Loada_pat<sextloadi16, i32, addrgp, L4_loadrh_abs>;
3876 def: Loada_pat<zextloadi16, i32, addrgp, L4_loadruh_abs>;
3878 def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
3879 def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
3882 let AddedComplexity = 100 in {
3883 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
3884 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
3885 def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
3886 def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
3889 def: Loada_pat<atomic_load_8, i32, addrgp, L4_loadrub_abs>;
3890 def: Loada_pat<atomic_load_16, i32, addrgp, L4_loadruh_abs>;
3891 def: Loada_pat<atomic_load_32, i32, addrgp, L4_loadri_abs>;
3892 def: Loada_pat<atomic_load_64, i64, addrgp, L4_loadrd_abs>;
3894 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbabs>;
3895 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
3896 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
3897 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
3899 let Constraints = "@earlyclobber $dst" in
3900 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3901 IntRegs:$c, IntRegs:$d),
3902 ".error \"Should never try to emit Insert4\"",
3903 [(set (i64 DoubleRegs:$dst),
3904 (or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))),
3906 (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))),
3907 (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))),
3909 (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))))]>;
3911 //===----------------------------------------------------------------------===//
3912 // :raw for of boundscheck:hi:lo insns
3913 //===----------------------------------------------------------------------===//
3915 // A4_boundscheck_lo: Detect if a register is within bounds.
3916 let hasSideEffects = 0 in
3917 def A4_boundscheck_lo: ALU64Inst <
3918 (outs PredRegs:$Pd),
3919 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3920 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
3925 let IClass = 0b1101;
3927 let Inst{27-23} = 0b00100;
3929 let Inst{7-5} = 0b100;
3931 let Inst{20-16} = Rss;
3932 let Inst{12-8} = Rtt;
3935 // A4_boundscheck_hi: Detect if a register is within bounds.
3936 let hasSideEffects = 0 in
3937 def A4_boundscheck_hi: ALU64Inst <
3938 (outs PredRegs:$Pd),
3939 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3940 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
3945 let IClass = 0b1101;
3947 let Inst{27-23} = 0b00100;
3949 let Inst{7-5} = 0b101;
3951 let Inst{20-16} = Rss;
3952 let Inst{12-8} = Rtt;
3955 let hasSideEffects = 0, isAsmParserOnly = 1 in
3956 def A4_boundscheck : MInst <
3957 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3958 "$Pd=boundscheck($Rs,$Rtt)">;
3960 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
3961 let isPredicateLate = 1, hasSideEffects = 0 in
3962 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
3963 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3964 "$Pd = tlbmatch($Rs, $Rt)",
3965 [], "", ALU64_tc_2early_SLOT23> {
3970 let IClass = 0b1101;
3971 let Inst{27-23} = 0b00100;
3972 let Inst{20-16} = Rs;
3974 let Inst{12-8} = Rt;
3975 let Inst{7-5} = 0b011;
3979 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
3980 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
3981 // We don't really want either one here.
3982 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
3983 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
3986 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
3987 // really do a load.
3988 let hasSideEffects = 1, mayLoad = 0 in
3989 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
3990 "dcfetch($Rs + #$u11_3)",
3991 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
3992 "", LD_tc_ld_SLOT0> {
3996 let IClass = 0b1001;
3997 let Inst{27-21} = 0b0100000;
3998 let Inst{20-16} = Rs;
4000 let Inst{10-0} = u11_3{13-3};
4003 //===----------------------------------------------------------------------===//
4004 // Compound instructions
4005 //===----------------------------------------------------------------------===//
4007 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4008 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4009 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4011 class CJInst_tstbit_R0<string px, bit np, string tnt>
4012 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4013 ""#px#" = tstbit($Rs, #0); if ("
4014 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4015 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4020 let isPredicatedFalse = np;
4021 // tnt: Taken/Not Taken
4022 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4023 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4025 let IClass = 0b0001;
4026 let Inst{27-26} = 0b00;
4027 let Inst{25} = !if (!eq(px, "!p1"), 1,
4028 !if (!eq(px, "p1"), 1, 0));
4029 let Inst{24-23} = 0b11;
4031 let Inst{21-20} = r9_2{10-9};
4032 let Inst{19-16} = Rs;
4033 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4034 let Inst{9-8} = 0b11;
4035 let Inst{7-1} = r9_2{8-2};
4038 let Defs = [PC, P0], Uses = [P0] in {
4039 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4040 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4041 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4042 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4045 let Defs = [PC, P1], Uses = [P1] in {
4046 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4047 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4048 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4049 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4053 let isBranch = 1, hasSideEffects = 0,
4054 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4055 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4056 opExtendable = 2, isTerminator = 1 in
4057 class CJInst_RR<string px, string op, bit np, string tnt>
4058 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4059 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4060 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4061 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4067 let isPredicatedFalse = np;
4068 // tnt: Taken/Not Taken
4069 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4070 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4072 let IClass = 0b0001;
4073 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4074 !if (!eq(op, "gt"), 0b01001,
4075 !if (!eq(op, "gtu"), 0b01010, 0)));
4077 let Inst{21-20} = r9_2{10-9};
4078 let Inst{19-16} = Rs;
4079 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4080 // px: Predicate reg 0/1
4081 let Inst{12} = !if (!eq(px, "!p1"), 1,
4082 !if (!eq(px, "p1"), 1, 0));
4083 let Inst{11-8} = Rt;
4084 let Inst{7-1} = r9_2{8-2};
4087 // P[10] taken/not taken.
4088 multiclass T_tnt_CJInst_RR<string op, bit np> {
4089 let Defs = [PC, P0], Uses = [P0] in {
4090 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4091 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4093 let Defs = [PC, P1], Uses = [P1] in {
4094 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4095 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4098 // Predicate / !Predicate
4099 multiclass T_pnp_CJInst_RR<string op>{
4100 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4101 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4103 // TypeCJ Instructions compare RR and jump
4104 defm eq : T_pnp_CJInst_RR<"eq">;
4105 defm gt : T_pnp_CJInst_RR<"gt">;
4106 defm gtu : T_pnp_CJInst_RR<"gtu">;
4108 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4109 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4110 opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
4111 class CJInst_RU5<string px, string op, bit np, string tnt>
4112 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4113 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4114 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4115 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4121 let isPredicatedFalse = np;
4122 // tnt: Taken/Not Taken
4123 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4124 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4126 let IClass = 0b0001;
4127 let Inst{27-26} = 0b00;
4128 // px: Predicate reg 0/1
4129 let Inst{25} = !if (!eq(px, "!p1"), 1,
4130 !if (!eq(px, "p1"), 1, 0));
4131 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4132 !if (!eq(op, "gt"), 0b01,
4133 !if (!eq(op, "gtu"), 0b10, 0)));
4135 let Inst{21-20} = r9_2{10-9};
4136 let Inst{19-16} = Rs;
4137 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4138 let Inst{12-8} = U5;
4139 let Inst{7-1} = r9_2{8-2};
4141 // P[10] taken/not taken.
4142 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4143 let Defs = [PC, P0], Uses = [P0] in {
4144 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4145 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4147 let Defs = [PC, P1], Uses = [P1] in {
4148 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4149 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4152 // Predicate / !Predicate
4153 multiclass T_pnp_CJInst_RU5<string op>{
4154 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4155 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4157 // TypeCJ Instructions compare RI and jump
4158 defm eq : T_pnp_CJInst_RU5<"eq">;
4159 defm gt : T_pnp_CJInst_RU5<"gt">;
4160 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4162 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4163 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4164 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4166 class CJInst_Rn1<string px, string op, bit np, string tnt>
4167 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4168 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4169 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4170 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4175 let isPredicatedFalse = np;
4176 // tnt: Taken/Not Taken
4177 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4178 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4180 let IClass = 0b0001;
4181 let Inst{27-26} = 0b00;
4182 let Inst{25} = !if (!eq(px, "!p1"), 1,
4183 !if (!eq(px, "p1"), 1, 0));
4185 let Inst{24-23} = 0b11;
4187 let Inst{21-20} = r9_2{10-9};
4188 let Inst{19-16} = Rs;
4189 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4190 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4191 !if (!eq(op, "gt"), 0b01, 0));
4192 let Inst{7-1} = r9_2{8-2};
4195 // P[10] taken/not taken.
4196 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4197 let Defs = [PC, P0], Uses = [P0] in {
4198 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4199 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4201 let Defs = [PC, P1], Uses = [P1] in {
4202 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4203 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4206 // Predicate / !Predicate
4207 multiclass T_pnp_CJInst_Rn1<string op>{
4208 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4209 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4211 // TypeCJ Instructions compare -1 and jump
4212 defm eq : T_pnp_CJInst_Rn1<"eq">;
4213 defm gt : T_pnp_CJInst_Rn1<"gt">;
4215 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4216 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4217 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4218 opExtentAlign = 2, opExtendable = 2 in
4219 def J4_jumpseti: CJInst <
4221 (ins u6Imm:$U6, brtarget:$r9_2),
4222 "$Rd = #$U6 ; jump $r9_2"> {
4227 let IClass = 0b0001;
4228 let Inst{27-24} = 0b0110;
4229 let Inst{21-20} = r9_2{10-9};
4230 let Inst{19-16} = Rd;
4231 let Inst{13-8} = U6;
4232 let Inst{7-1} = r9_2{8-2};
4235 // J4_jumpsetr: Direct unconditional jump and transfer register.
4236 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4237 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4238 opExtentAlign = 2, opExtendable = 2 in
4239 def J4_jumpsetr: CJInst <
4241 (ins IntRegs:$Rs, brtarget:$r9_2),
4242 "$Rd = $Rs ; jump $r9_2"> {
4247 let IClass = 0b0001;
4248 let Inst{27-24} = 0b0111;
4249 let Inst{21-20} = r9_2{10-9};
4250 let Inst{11-8} = Rd;
4251 let Inst{19-16} = Rs;
4252 let Inst{7-1} = r9_2{8-2};