1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let hasSideEffects = 0 in
15 class T_Immext<Operand ImmType>
16 : EXTENDERInst<(outs), (ins ImmType:$imm),
17 "immext(#$imm)", []> {
21 let Inst{27-16} = imm{31-20};
22 let Inst{13-0} = imm{19-6};
25 def A4_ext : T_Immext<u26_6Imm>;
26 let isCodeGenOnly = 1 in {
28 def A4_ext_b : T_Immext<brtarget>;
30 def A4_ext_c : T_Immext<calltarget>;
31 def A4_ext_g : T_Immext<globaladdress>;
34 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
35 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
37 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
38 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
40 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
41 (HexagonCONST32 node:$addr), [{
42 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
45 // Hexagon V4 Architecture spec defines 8 instruction classes:
46 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
50 // ========================================
51 // Loads (8/16/32/64 bit)
55 // ========================================
56 // Stores (8/16/32/64 bit)
59 // ALU32 Instructions:
60 // ========================================
61 // Arithmetic / Logical (32 bit)
64 // XTYPE Instructions (32/64 bit):
65 // ========================================
66 // Arithmetic, Logical, Bit Manipulation
67 // Multiply (Integer, Fractional, Complex)
68 // Permute / Vector Permute Operations
69 // Predicate Operations
70 // Shift / Shift with Add/Sub/Logical
72 // Vector Halfword (ALU, Shift, Multiply)
73 // Vector Word (ALU, Shift)
76 // ========================================
77 // Jump/Call PC-relative
80 // ========================================
83 // MEMOP Instructions:
84 // ========================================
85 // Operation on memory (8/16/32 bit)
88 // ========================================
93 // ========================================
94 // Control-Register Transfers
95 // Hardware Loop Setup
96 // Predicate Logicals & Reductions
98 // SYSTEM Instructions (not implemented in the compiler):
99 // ========================================
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
109 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
111 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
112 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
115 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
116 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
117 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
118 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
120 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
121 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
122 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
123 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
125 let isCodeGenOnly = 0 in {
126 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
127 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
128 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
131 // Pats for instruction selection.
133 // A class to embed the usual comparison patfrags within a zext to i32.
134 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
135 // names, or else the frag's "body" won't match the operands.
136 class CmpInReg<PatFrag Op>
137 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
139 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
140 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
142 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
143 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
144 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
146 let validSubTargets = HasV4SubT;
147 let InputType = "reg";
148 let CextOpcode = mnemonic;
150 let isCommutable = IsComm;
151 let hasSideEffects = 0;
158 let Inst{27-21} = 0b0111110;
159 let Inst{20-16} = Rs;
161 let Inst{7-5} = MinOp;
165 let isCodeGenOnly = 0 in {
166 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
167 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
168 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
169 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
170 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
171 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
174 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
175 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
176 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
177 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
179 let validSubTargets = HasV4SubT;
180 let InputType = "imm";
181 let CextOpcode = mnemonic;
183 let isCommutable = IsComm;
184 let hasSideEffects = 0;
185 let isExtendable = IsImmExt;
186 let opExtendable = !if (IsImmExt, 2, 0);
187 let isExtentSigned = IsImmSigned;
188 let opExtentBits = ImmBits;
195 let Inst{27-24} = 0b1101;
196 let Inst{22-21} = MajOp;
197 let Inst{20-16} = Rs;
198 let Inst{12-5} = Imm;
200 let Inst{3} = IsHalf;
204 let isCodeGenOnly = 0 in {
205 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
206 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
207 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
208 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
209 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
210 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
212 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
213 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
214 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
216 let validSubTargets = HasV4SubT;
217 let InputType = "imm";
218 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
219 let isExtendable = 1;
220 let opExtendable = 2;
221 let isExtentSigned = 1;
222 let opExtentBits = 8;
230 let Inst{27-24} = 0b0011;
232 let Inst{21} = IsNeg;
233 let Inst{20-16} = Rs;
239 let isCodeGenOnly = 0 in {
240 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
241 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
244 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
245 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
246 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
247 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
249 // Preserve the S2_tstbit_r generation
250 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
251 (i32 IntRegs:$src1))), 0)))),
252 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
255 //===----------------------------------------------------------------------===//
257 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 //===----------------------------------------------------------------------===//
264 // Combine a word and an immediate into a register pair.
265 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
267 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
268 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
274 let Inst{27-24} = 0b0011;
275 let Inst{22-21} = MajOp;
276 let Inst{20-16} = Rs;
282 let opExtendable = 2, isCodeGenOnly = 0 in
283 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
284 "$Rdd = combine($Rs, #$s8)">;
286 let opExtendable = 1, isCodeGenOnly = 0 in
287 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
288 "$Rdd = combine(#$s8, $Rs)">;
290 def HexagonWrapperCombineRI_V4 :
291 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
292 def HexagonWrapperCombineIR_V4 :
293 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
295 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
296 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
299 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
300 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
303 // A4_combineii: Set two small immediates.
304 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
305 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
306 "$Rdd = combine(#$s8, #$U6)"> {
312 let Inst{27-23} = 0b11001;
313 let Inst{20-16} = U6{5-1};
314 let Inst{13} = U6{0};
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
325 //===----------------------------------------------------------------------===//
326 //===----------------------------------------------------------------------===//
327 // Template class for load instructions with Absolute set addressing mode.
328 //===----------------------------------------------------------------------===//
329 let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
330 validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
331 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
332 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
333 (ins u0AlwaysExt:$addr),
334 "$dst1 = "#mnemonic#"($dst2=##$addr)",
338 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
339 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
340 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
341 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
342 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
343 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
345 //===----------------------------------------------------------------------===//
346 // Template classes for the non-predicated load instructions with
347 // base + register offset addressing mode
348 //===----------------------------------------------------------------------===//
349 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
350 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
351 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
352 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
360 let Inst{27-24} = 0b1010;
361 let Inst{23-21} = MajOp;
362 let Inst{20-16} = src1;
363 let Inst{12-8} = src2;
364 let Inst{13} = u2{1};
369 //===----------------------------------------------------------------------===//
370 // Template classes for the predicated load instructions with
371 // base + register offset addressing mode
372 //===----------------------------------------------------------------------===//
373 let isPredicated = 1 in
374 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
375 bit isNot, bit isPredNew>:
376 LDInst <(outs RC:$dst),
377 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
378 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
379 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
380 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
387 let isPredicatedFalse = isNot;
388 let isPredicatedNew = isPredNew;
392 let Inst{27-26} = 0b00;
393 let Inst{25} = isPredNew;
394 let Inst{24} = isNot;
395 let Inst{23-21} = MajOp;
396 let Inst{20-16} = src2;
397 let Inst{12-8} = src3;
398 let Inst{13} = u2{1};
400 let Inst{6-5} = src1;
404 //===----------------------------------------------------------------------===//
405 // multiclass for load instructions with base + register offset
407 //===----------------------------------------------------------------------===//
408 let hasSideEffects = 0, addrMode = BaseRegOffset in
409 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
411 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
412 InputType = "reg" in {
413 let isPredicable = 1 in
414 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
417 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
418 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
421 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
422 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
426 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
427 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
428 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
431 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
432 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
433 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
436 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
437 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
439 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
440 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
442 // 'def pats' for load instructions with base + register offset and non-zero
443 // immediate value. Immediate value is used to left-shift the second
445 let AddedComplexity = 40 in {
446 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
447 (shl IntRegs:$src2, u2ImmPred:$offset)))),
448 (L4_loadrb_rr IntRegs:$src1,
449 IntRegs:$src2, u2ImmPred:$offset)>,
452 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
453 (shl IntRegs:$src2, u2ImmPred:$offset)))),
454 (L4_loadrub_rr IntRegs:$src1,
455 IntRegs:$src2, u2ImmPred:$offset)>,
458 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
459 (shl IntRegs:$src2, u2ImmPred:$offset)))),
460 (L4_loadrub_rr IntRegs:$src1,
461 IntRegs:$src2, u2ImmPred:$offset)>,
464 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
465 (shl IntRegs:$src2, u2ImmPred:$offset)))),
466 (L4_loadrh_rr IntRegs:$src1,
467 IntRegs:$src2, u2ImmPred:$offset)>,
470 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
471 (shl IntRegs:$src2, u2ImmPred:$offset)))),
472 (L4_loadruh_rr IntRegs:$src1,
473 IntRegs:$src2, u2ImmPred:$offset)>,
476 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
477 (shl IntRegs:$src2, u2ImmPred:$offset)))),
478 (L4_loadruh_rr IntRegs:$src1,
479 IntRegs:$src2, u2ImmPred:$offset)>,
482 def : Pat <(i32 (load (add IntRegs:$src1,
483 (shl IntRegs:$src2, u2ImmPred:$offset)))),
484 (L4_loadri_rr IntRegs:$src1,
485 IntRegs:$src2, u2ImmPred:$offset)>,
488 def : Pat <(i64 (load (add IntRegs:$src1,
489 (shl IntRegs:$src2, u2ImmPred:$offset)))),
490 (L4_loadrd_rr IntRegs:$src1,
491 IntRegs:$src2, u2ImmPred:$offset)>,
496 // 'def pats' for load instruction base + register offset and
497 // zero immediate value.
498 let AddedComplexity = 10 in {
499 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
500 (L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>,
503 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
504 (L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>,
507 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
508 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
511 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
512 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
515 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
516 (L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
519 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
520 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
523 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
524 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
527 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
528 (L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>,
533 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
534 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
538 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
539 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
542 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
543 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
546 let AddedComplexity = 20 in
547 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
548 s11_0ExtPred:$offset))),
549 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
550 s11_0ExtPred:$offset)))>,
554 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
555 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
558 let AddedComplexity = 20 in
559 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
560 s11_0ExtPred:$offset))),
561 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
562 s11_0ExtPred:$offset)))>,
566 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
567 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
570 let AddedComplexity = 20 in
571 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
572 s11_1ExtPred:$offset))),
573 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
574 s11_1ExtPred:$offset)))>,
578 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
579 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
582 let AddedComplexity = 20 in
583 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
584 s11_1ExtPred:$offset))),
585 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
586 s11_1ExtPred:$offset)))>,
590 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
591 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
594 let AddedComplexity = 100 in
595 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
596 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
597 s11_2ExtPred:$offset)))>,
601 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
602 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
605 let AddedComplexity = 100 in
606 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
607 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
608 s11_2ExtPred:$offset)))>,
613 //===----------------------------------------------------------------------===//
615 //===----------------------------------------------------------------------===//
617 //===----------------------------------------------------------------------===//
619 //===----------------------------------------------------------------------===//
621 //===----------------------------------------------------------------------===//
622 // Template class for store instructions with Absolute set addressing mode.
623 //===----------------------------------------------------------------------===//
624 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
625 addrMode = AbsoluteSet in
626 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
627 STInst2<(outs IntRegs:$dst1),
628 (ins RC:$src1, u0AlwaysExt:$src2),
629 mnemonic#"($dst1=##$src2) = $src1",
633 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
634 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
635 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
636 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
638 //===----------------------------------------------------------------------===//
639 // Template classes for the non-predicated store instructions with
640 // base + register offset addressing mode
641 //===----------------------------------------------------------------------===//
642 let isPredicable = 1 in
643 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
644 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
645 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
646 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
655 let Inst{27-24} = 0b1011;
656 let Inst{23-21} = MajOp;
657 let Inst{20-16} = Rs;
659 let Inst{13} = u2{1};
664 //===----------------------------------------------------------------------===//
665 // Template classes for the predicated store instructions with
666 // base + register offset addressing mode
667 //===----------------------------------------------------------------------===//
668 let isPredicated = 1 in
669 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
670 bit isNot, bit isPredNew, bit isH>
672 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
674 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
675 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
676 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
683 let isPredicatedFalse = isNot;
684 let isPredicatedNew = isPredNew;
688 let Inst{27-26} = 0b01;
689 let Inst{25} = isPredNew;
690 let Inst{24} = isNot;
691 let Inst{23-21} = MajOp;
692 let Inst{20-16} = Rs;
694 let Inst{13} = u2{1};
700 //===----------------------------------------------------------------------===//
701 // Template classes for the new-value store instructions with
702 // base + register offset addressing mode
703 //===----------------------------------------------------------------------===//
704 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
705 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
706 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
707 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
708 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
717 let Inst{27-21} = 0b1011101;
718 let Inst{20-16} = Rs;
720 let Inst{13} = u2{1};
722 let Inst{4-3} = MajOp;
726 //===----------------------------------------------------------------------===//
727 // Template classes for the predicated new-value store instructions with
728 // base + register offset addressing mode
729 //===----------------------------------------------------------------------===//
730 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
731 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
733 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
734 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
735 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
736 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
743 let isPredicatedFalse = isNot;
744 let isPredicatedNew = isPredNew;
747 let Inst{27-26} = 0b01;
748 let Inst{25} = isPredNew;
749 let Inst{24} = isNot;
750 let Inst{23-21} = 0b101;
751 let Inst{20-16} = Rs;
753 let Inst{13} = u2{1};
756 let Inst{4-3} = MajOp;
760 //===----------------------------------------------------------------------===//
761 // multiclass for store instructions with base + register offset addressing
763 //===----------------------------------------------------------------------===//
764 let isNVStorable = 1 in
765 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
766 bits<3> MajOp, bit isH = 0> {
767 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
768 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
771 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
772 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
775 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
776 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
780 //===----------------------------------------------------------------------===//
781 // multiclass for new-value store instructions with base + register offset
783 //===----------------------------------------------------------------------===//
784 let mayStore = 1, isNVStore = 1 in
785 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
787 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
788 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
791 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
792 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
795 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
796 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
800 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
801 isCodeGenOnly = 0 in {
802 let accessSize = ByteAccess in
803 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
804 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
806 let accessSize = HalfWordAccess in
807 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
808 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
810 let accessSize = WordAccess in
811 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
812 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
814 let isNVStorable = 0, accessSize = DoubleWordAccess in
815 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
817 let isNVStorable = 0, accessSize = HalfWordAccess in
818 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
821 let Predicates = [HasV4T], AddedComplexity = 10 in {
822 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
823 (add IntRegs:$src1, (shl IntRegs:$src2,
825 (S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
826 u2ImmPred:$src3, IntRegs:$src4)>;
828 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
829 (add IntRegs:$src1, (shl IntRegs:$src2,
831 (S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
832 u2ImmPred:$src3, IntRegs:$src4)>;
834 def : Pat<(store (i32 IntRegs:$src4),
835 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
836 (S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
837 u2ImmPred:$src3, IntRegs:$src4)>;
839 def : Pat<(store (i64 DoubleRegs:$src4),
840 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
841 (S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
842 u2ImmPred:$src3, DoubleRegs:$src4)>;
845 let isExtended = 1, opExtendable = 2 in
846 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
848 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
849 mnemonic#"($src1<<#$src2+##$src3) = $src4",
850 [(stOp (VT RC:$src4),
851 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
852 u0AlwaysExtPred:$src3))]>,
855 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
856 class T_ST_LongOff_nv <string mnemonic> :
858 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
859 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
863 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
864 let BaseOpcode = BaseOp#"_shl" in {
865 let isNVStorable = 1 in
866 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
868 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
872 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
873 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
874 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
875 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
876 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
879 let AddedComplexity = 40 in
880 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
882 def : Pat<(stOp (VT RC:$src4),
883 (add (shl IntRegs:$src1, u2ImmPred:$src2),
884 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
885 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
887 def : Pat<(stOp (VT RC:$src4),
889 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
890 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
893 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
894 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
895 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
896 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
898 // memd(Rx++#s4:3)=Rtt
899 // memd(Rx++#s4:3:circ(Mu))=Rtt
900 // memd(Rx++I:circ(Mu))=Rtt
902 // memd(Rx++Mu:brev)=Rtt
903 // memd(gp+#u16:3)=Rtt
905 // Store doubleword conditionally.
906 // if ([!]Pv[.new]) memd(#u6)=Rtt
907 // TODO: needs to be implemented.
909 //===----------------------------------------------------------------------===//
911 //===----------------------------------------------------------------------===//
912 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
914 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
915 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
916 mnemonic#"($Rs+#$offset)=#$S8",
917 [], "", V4LDST_tc_st_SLOT01>,
918 ImmRegRel, PredNewRel {
924 string OffsetOpStr = !cast<string>(OffsetOp);
925 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
926 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
927 /* u6_0Imm */ offset{5-0}));
931 let Inst{27-25} = 0b110;
932 let Inst{22-21} = MajOp;
933 let Inst{20-16} = Rs;
934 let Inst{12-7} = offsetBits;
935 let Inst{13} = S8{7};
936 let Inst{6-0} = S8{6-0};
939 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
941 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
942 bit isPredNot, bit isPredNew >
944 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
945 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
946 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
947 [], "", V4LDST_tc_st_SLOT01>,
948 ImmRegRel, PredNewRel {
955 string OffsetOpStr = !cast<string>(OffsetOp);
956 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
957 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
958 /* u6_0Imm */ offset{5-0}));
959 let isPredicatedNew = isPredNew;
960 let isPredicatedFalse = isPredNot;
964 let Inst{27-25} = 0b100;
965 let Inst{24} = isPredNew;
966 let Inst{23} = isPredNot;
967 let Inst{22-21} = MajOp;
968 let Inst{20-16} = Rs;
969 let Inst{13} = S6{5};
970 let Inst{12-7} = offsetBits;
972 let Inst{4-0} = S6{4-0};
976 //===----------------------------------------------------------------------===//
977 // multiclass for store instructions with base + immediate offset
978 // addressing mode and immediate stored value.
979 // mem[bhw](Rx++#s4:3)=#s8
980 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
981 //===----------------------------------------------------------------------===//
983 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
985 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
987 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
990 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
992 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
993 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
995 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
996 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1000 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1001 InputType = "imm", isCodeGenOnly = 0 in {
1002 let accessSize = ByteAccess in
1003 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1005 let accessSize = HalfWordAccess in
1006 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1008 let accessSize = WordAccess in
1009 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1012 let Predicates = [HasV4T], AddedComplexity = 10 in {
1013 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1014 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1016 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1017 u6_1ImmPred:$src2)),
1018 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1020 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1021 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1024 let AddedComplexity = 6 in
1025 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1026 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1029 // memb(Rx++#s4:0:circ(Mu))=Rt
1030 // memb(Rx++I:circ(Mu))=Rt
1032 // memb(Rx++Mu:brev)=Rt
1033 // memb(gp+#u16:0)=Rt
1037 // TODO: needs to be implemented
1038 // memh(Re=#U6)=Rt.H
1039 // memh(Rs+#s11:1)=Rt.H
1040 let AddedComplexity = 6 in
1041 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1042 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1045 // memh(Rs+Ru<<#u2)=Rt.H
1046 // TODO: needs to be implemented.
1048 // memh(Ru<<#u2+#U6)=Rt.H
1049 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1050 // memh(Rx++#s4:1:circ(Mu))=Rt
1051 // memh(Rx++I:circ(Mu))=Rt.H
1052 // memh(Rx++I:circ(Mu))=Rt
1053 // memh(Rx++Mu)=Rt.H
1055 // memh(Rx++Mu:brev)=Rt.H
1056 // memh(Rx++Mu:brev)=Rt
1057 // memh(gp+#u16:1)=Rt
1058 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1059 // if ([!]Pv[.new]) memh(#u6)=Rt
1062 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1063 // TODO: needs to be implemented.
1065 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1066 // TODO: Needs to be implemented.
1070 // TODO: Needs to be implemented.
1073 let hasSideEffects = 0 in
1074 def STriw_pred_V4 : STInst2<(outs),
1075 (ins MEMri:$addr, PredRegs:$src1),
1076 "Error; should not emit",
1080 let AddedComplexity = 6 in
1081 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1082 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1085 // memw(Rx++#s4:2)=Rt
1086 // memw(Rx++#s4:2:circ(Mu))=Rt
1087 // memw(Rx++I:circ(Mu))=Rt
1089 // memw(Rx++Mu:brev)=Rt
1091 //===----------------------------------------------------------------------===
1093 //===----------------------------------------------------------------------===
1096 //===----------------------------------------------------------------------===//
1098 //===----------------------------------------------------------------------===//
1100 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1101 class T_store_io_nv <string mnemonic, RegisterClass RC,
1102 Operand ImmOp, bits<2>MajOp>
1103 : NVInst_V4 <(outs),
1104 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1105 mnemonic#"($src1+#$src2) = $src3.new",
1106 [],"",ST_tc_st_SLOT0> {
1108 bits<13> src2; // Actual address offset
1110 bits<11> offsetBits; // Represents offset encoding
1112 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1113 !if (!eq(mnemonic, "memh"), 12,
1114 !if (!eq(mnemonic, "memw"), 13, 0)));
1116 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1117 !if (!eq(mnemonic, "memh"), 1,
1118 !if (!eq(mnemonic, "memw"), 2, 0)));
1120 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1121 !if (!eq(mnemonic, "memh"), src2{11-1},
1122 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1124 let IClass = 0b1010;
1127 let Inst{26-25} = offsetBits{10-9};
1128 let Inst{24-21} = 0b1101;
1129 let Inst{20-16} = src1;
1130 let Inst{13} = offsetBits{8};
1131 let Inst{12-11} = MajOp;
1132 let Inst{10-8} = src3;
1133 let Inst{7-0} = offsetBits{7-0};
1136 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1137 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1138 bits<2>MajOp, bit PredNot, bit isPredNew>
1139 : NVInst_V4 <(outs),
1140 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1141 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1142 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1143 [],"",V2LDST_tc_st_SLOT0> {
1148 bits<6> offsetBits; // Represents offset encoding
1150 let isPredicatedNew = isPredNew;
1151 let isPredicatedFalse = PredNot;
1152 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1153 !if (!eq(mnemonic, "memh"), 7,
1154 !if (!eq(mnemonic, "memw"), 8, 0)));
1156 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1157 !if (!eq(mnemonic, "memh"), 1,
1158 !if (!eq(mnemonic, "memw"), 2, 0)));
1160 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1161 !if (!eq(mnemonic, "memh"), src3{6-1},
1162 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1164 let IClass = 0b0100;
1167 let Inst{26} = PredNot;
1168 let Inst{25} = isPredNew;
1169 let Inst{24-21} = 0b0101;
1170 let Inst{20-16} = src2;
1171 let Inst{13} = offsetBits{5};
1172 let Inst{12-11} = MajOp;
1173 let Inst{10-8} = src4;
1174 let Inst{7-3} = offsetBits{4-0};
1176 let Inst{1-0} = src1;
1179 // multiclass for new-value store instructions with base + immediate offset.
1181 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1183 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1184 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1186 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1187 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1189 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1190 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1192 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1194 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1199 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1200 let accessSize = ByteAccess in
1201 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1202 u6_0Ext, 0b00>, AddrModeRel;
1204 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1205 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1206 u6_1Ext, 0b01>, AddrModeRel;
1208 let accessSize = WordAccess, opExtentAlign = 2 in
1209 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1210 u6_2Ext, 0b10>, AddrModeRel;
1213 //===----------------------------------------------------------------------===//
1214 // Template class for non-predicated post increment .new stores
1215 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1216 //===----------------------------------------------------------------------===//
1217 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1218 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1219 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1220 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1221 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1222 mnemonic#"($src1++#$offset) = $src2.new",
1223 [], "$src1 = $_dst_">,
1230 string ImmOpStr = !cast<string>(ImmOp);
1231 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1232 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1233 /* s4_0Imm */ offset{3-0}));
1234 let IClass = 0b1010;
1236 let Inst{27-21} = 0b1011101;
1237 let Inst{20-16} = src1;
1239 let Inst{12-11} = MajOp;
1240 let Inst{10-8} = src2;
1242 let Inst{6-3} = offsetBits;
1246 //===----------------------------------------------------------------------===//
1247 // Template class for predicated post increment .new stores
1248 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1249 //===----------------------------------------------------------------------===//
1250 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1251 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1252 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1253 bits<2> MajOp, bit isPredNot, bit isPredNew >
1254 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1255 (ins PredRegs:$src1, IntRegs:$src2,
1256 ImmOp:$offset, IntRegs:$src3),
1257 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1258 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1259 [], "$src2 = $_dst_">,
1267 string ImmOpStr = !cast<string>(ImmOp);
1268 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1269 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1270 /* s4_0Imm */ offset{3-0}));
1271 let isPredicatedNew = isPredNew;
1272 let isPredicatedFalse = isPredNot;
1274 let IClass = 0b1010;
1276 let Inst{27-21} = 0b1011101;
1277 let Inst{20-16} = src2;
1279 let Inst{12-11} = MajOp;
1280 let Inst{10-8} = src3;
1281 let Inst{7} = isPredNew;
1282 let Inst{6-3} = offsetBits;
1283 let Inst{2} = isPredNot;
1284 let Inst{1-0} = src1;
1287 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1288 bits<2> MajOp, bit PredNot> {
1289 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1292 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1295 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1297 let BaseOpcode = "POST_"#BaseOp in {
1298 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1301 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1302 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1306 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1307 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1309 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1310 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1312 let accessSize = WordAccess, isCodeGenOnly = 0 in
1313 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1315 //===----------------------------------------------------------------------===//
1316 // Template class for post increment .new stores with register offset
1317 //===----------------------------------------------------------------------===//
1318 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1319 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1320 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1321 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1322 #mnemonic#"($src1++$src2) = $src3.new",
1323 [], "$src1 = $_dst_"> {
1327 let accessSize = AccessSz;
1329 let IClass = 0b1010;
1331 let Inst{27-21} = 0b1101101;
1332 let Inst{20-16} = src1;
1333 let Inst{13} = src2;
1334 let Inst{12-11} = MajOp;
1335 let Inst{10-8} = src3;
1339 let isCodeGenOnly = 0 in {
1340 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1341 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1342 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1345 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1346 // memb(Rx++I:circ(Mu))=Nt.new
1347 // memb(Rx++Mu)=Nt.new
1348 // memb(Rx++Mu:brev)=Nt.new
1349 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1350 // memh(Rx++I:circ(Mu))=Nt.new
1351 // memh(Rx++Mu)=Nt.new
1352 // memh(Rx++Mu:brev)=Nt.new
1354 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1355 // memw(Rx++I:circ(Mu))=Nt.new
1356 // memw(Rx++Mu)=Nt.new
1357 // memw(Rx++Mu:brev)=Nt.new
1359 //===----------------------------------------------------------------------===//
1361 //===----------------------------------------------------------------------===//
1363 //===----------------------------------------------------------------------===//
1365 //===----------------------------------------------------------------------===//
1367 //===----------------------------------------------------------------------===//
1368 // multiclass/template class for the new-value compare jumps with the register
1370 //===----------------------------------------------------------------------===//
1372 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1373 opExtentAlign = 2 in
1374 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1375 bit isNegCond, bit isTak>
1377 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1378 "if ("#!if(isNegCond, "!","")#mnemonic#
1379 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1380 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1381 #!if(isTak, "t","nt")#" $offset", []> {
1385 bits<3> Ns; // New-Value Operand
1386 bits<5> RegOp; // Non-New-Value Operand
1389 let isTaken = isTak;
1390 let isPredicatedFalse = isNegCond;
1391 let opNewValue{0} = NvOpNum;
1393 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1394 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1396 let IClass = 0b0010;
1398 let Inst{25-23} = majOp;
1399 let Inst{22} = isNegCond;
1400 let Inst{18-16} = Ns;
1401 let Inst{13} = isTak;
1402 let Inst{12-8} = RegOp;
1403 let Inst{21-20} = offset{10-9};
1404 let Inst{7-1} = offset{8-2};
1408 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1410 // Branch not taken:
1411 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1413 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1416 // NvOpNum = 0 -> First Operand is a new-value Register
1417 // NvOpNum = 1 -> Second Operand is a new-value Register
1419 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1421 let BaseOpcode = BaseOp#_NVJ in {
1422 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1423 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1427 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1428 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1429 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1430 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1431 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1433 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1434 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1435 isCodeGenOnly = 0 in {
1436 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1437 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1438 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1439 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1440 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1443 //===----------------------------------------------------------------------===//
1444 // multiclass/template class for the new-value compare jumps instruction
1445 // with a register and an unsigned immediate (U5) operand.
1446 //===----------------------------------------------------------------------===//
1448 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1449 opExtentAlign = 2 in
1450 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1453 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1454 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1455 #!if(isTak, "t","nt")#" $offset", []> {
1457 let isTaken = isTak;
1458 let isPredicatedFalse = isNegCond;
1459 let isTaken = isTak;
1465 let IClass = 0b0010;
1467 let Inst{25-23} = majOp;
1468 let Inst{22} = isNegCond;
1469 let Inst{18-16} = src1;
1470 let Inst{13} = isTak;
1471 let Inst{12-8} = src2;
1472 let Inst{21-20} = offset{10-9};
1473 let Inst{7-1} = offset{8-2};
1476 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1477 // Branch not taken:
1478 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1480 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1483 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1484 let BaseOpcode = BaseOp#_NVJri in {
1485 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1486 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1490 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1491 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1492 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1494 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1495 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1496 isCodeGenOnly = 0 in {
1497 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1498 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1499 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1502 //===----------------------------------------------------------------------===//
1503 // multiclass/template class for the new-value compare jumps instruction
1504 // with a register and an hardcoded 0/-1 immediate value.
1505 //===----------------------------------------------------------------------===//
1507 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1508 opExtentAlign = 2 in
1509 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1510 bit isNegCond, bit isTak>
1512 (ins IntRegs:$src1, brtarget:$offset),
1513 "if ("#!if(isNegCond, "!","")#mnemonic
1514 #"($src1.new, #"#ImmVal#")) jump:"
1515 #!if(isTak, "t","nt")#" $offset", []> {
1517 let isTaken = isTak;
1518 let isPredicatedFalse = isNegCond;
1519 let isTaken = isTak;
1523 let IClass = 0b0010;
1525 let Inst{25-23} = majOp;
1526 let Inst{22} = isNegCond;
1527 let Inst{18-16} = src1;
1528 let Inst{13} = isTak;
1529 let Inst{21-20} = offset{10-9};
1530 let Inst{7-1} = offset{8-2};
1533 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1535 // Branch not taken:
1536 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1538 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1541 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1543 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1544 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1545 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1549 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1550 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1551 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1553 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1554 Defs = [PC], hasSideEffects = 0, isCodeGenOnly = 0 in {
1555 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1556 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1557 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1560 // J4_hintjumpr: Hint indirect conditional jump.
1561 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1562 def J4_hintjumpr: JRInst <
1567 let IClass = 0b0101;
1568 let Inst{27-21} = 0b0010101;
1569 let Inst{20-16} = Rs;
1572 //===----------------------------------------------------------------------===//
1574 //===----------------------------------------------------------------------===//
1576 //===----------------------------------------------------------------------===//
1578 //===----------------------------------------------------------------------===//
1581 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1582 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0,
1583 Uses = [PC], validSubTargets = HasV4SubT in
1584 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1585 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1589 let IClass = 0b0110;
1590 let Inst{27-16} = 0b101001001001;
1591 let Inst{12-7} = u6;
1597 let hasSideEffects = 0 in
1598 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1599 : CRInst<(outs PredRegs:$Pd),
1600 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1601 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1602 !if (IsNeg,"!","") # "$Pu))",
1603 [], "", CR_tc_2early_SLOT23> {
1609 let IClass = 0b0110;
1610 let Inst{27-24} = 0b1011;
1611 let Inst{23} = IsNeg;
1612 let Inst{22-21} = OpBits;
1614 let Inst{17-16} = Ps;
1621 let isCodeGenOnly = 0 in {
1622 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1623 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1624 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1625 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1626 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1627 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1628 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1629 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1632 //===----------------------------------------------------------------------===//
1634 //===----------------------------------------------------------------------===//
1636 //===----------------------------------------------------------------------===//
1638 //===----------------------------------------------------------------------===//
1640 // Logical with-not instructions.
1641 let validSubTargets = HasV4SubT, isCodeGenOnly = 0 in {
1642 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1643 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1646 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1647 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1648 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1653 let IClass = 0b1101;
1654 let Inst{27-21} = 0b0101111;
1655 let Inst{20-16} = Rs;
1656 let Inst{12-8} = Rt;
1659 // Add and accumulate.
1660 // Rd=add(Rs,add(Ru,#s6))
1661 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1662 opExtendable = 3, isCodeGenOnly = 0 in
1663 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1664 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1665 "$Rd = add($Rs, add($Ru, #$s6))" ,
1666 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1667 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1668 "", ALU64_tc_2_SLOT23> {
1674 let IClass = 0b1101;
1676 let Inst{27-23} = 0b10110;
1677 let Inst{22-21} = s6{5-4};
1678 let Inst{20-16} = Rs;
1679 let Inst{13} = s6{3};
1680 let Inst{12-8} = Rd;
1681 let Inst{7-5} = s6{2-0};
1685 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1686 opExtentBits = 6, opExtendable = 2, isCodeGenOnly = 0 in
1687 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1688 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1689 "$Rd = add($Rs, sub(#$s6, $Ru))",
1690 [], "", ALU64_tc_2_SLOT23> {
1696 let IClass = 0b1101;
1698 let Inst{27-23} = 0b10111;
1699 let Inst{22-21} = s6{5-4};
1700 let Inst{20-16} = Rs;
1701 let Inst{13} = s6{3};
1702 let Inst{12-8} = Rd;
1703 let Inst{7-5} = s6{2-0};
1708 // Rdd=extract(Rss,#u6,#U6)
1709 // Rdd=extract(Rss,Rtt)
1710 // Rd=extract(Rs,Rtt)
1711 // Rd=extract(Rs,#u5,#U5)
1713 let isCodeGenOnly = 0 in {
1714 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1715 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1718 let hasNewValue = 1, isCodeGenOnly = 0 in {
1719 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1720 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1723 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1724 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1725 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1728 // Logical xor with xor accumulation.
1729 // Rxx^=xor(Rss,Rtt)
1730 let hasSideEffects = 0, isCodeGenOnly = 0 in
1732 : SInst <(outs DoubleRegs:$Rxx),
1733 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1734 "$Rxx ^= xor($Rss, $Rtt)",
1735 [(set (i64 DoubleRegs:$Rxx),
1736 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
1737 (i64 DoubleRegs:$Rtt))))],
1738 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
1743 let IClass = 0b1100;
1745 let Inst{27-23} = 0b10101;
1746 let Inst{20-16} = Rss;
1747 let Inst{12-8} = Rtt;
1748 let Inst{4-0} = Rxx;
1752 let isCodeGenOnly = 0 in
1753 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
1755 // Arithmetic/Convergent round
1756 let isCodeGenOnly = 0 in
1757 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
1759 let isCodeGenOnly = 0 in
1760 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
1762 let Defs = [USR_OVF], isCodeGenOnly = 0 in
1763 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
1765 // Add and accumulate.
1766 // Rd=add(Rs,add(Ru,#s6))
1767 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
1768 validSubTargets = HasV4SubT in
1769 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
1770 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1771 "$dst = add($src1, add($src2, #$src3))",
1772 [(set (i32 IntRegs:$dst),
1773 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1774 s6_16ExtPred:$src3)))]>,
1777 // Rd=add(Rs,sub(#s6,Ru))
1778 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1779 validSubTargets = HasV4SubT in
1780 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
1781 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1782 "$dst = add($src1, sub(#$src2, $src3))",
1783 [(set (i32 IntRegs:$dst),
1784 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1785 (i32 IntRegs:$src3))))]>,
1788 // Generates the same instruction as ADDr_SUBri_V4 but matches different
1790 // Rd=add(Rs,sub(#s6,Ru))
1791 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1792 validSubTargets = HasV4SubT in
1793 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
1794 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1795 "$dst = add($src1, sub(#$src2, $src3))",
1796 [(set (i32 IntRegs:$dst),
1797 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1798 (i32 IntRegs:$src3)))]>,
1802 // Add or subtract doublewords with carry.
1804 // Rdd=add(Rss,Rtt,Px):carry
1806 // Rdd=sub(Rss,Rtt,Px):carry
1809 // Logical doublewords.
1810 // Rdd=and(Rtt,~Rss)
1811 let validSubTargets = HasV4SubT in
1812 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1813 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1814 "$dst = and($src1, ~$src2)",
1815 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1816 (not (i64 DoubleRegs:$src2))))]>,
1820 let validSubTargets = HasV4SubT in
1821 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1822 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1823 "$dst = or($src1, ~$src2)",
1824 [(set (i64 DoubleRegs:$dst),
1825 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
1829 // Logical-logical doublewords.
1830 // Rxx^=xor(Rss,Rtt)
1831 let validSubTargets = HasV4SubT in
1832 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
1833 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1834 "$dst ^= xor($src2, $src3)",
1835 [(set (i64 DoubleRegs:$dst),
1836 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
1837 (i64 DoubleRegs:$src3))))],
1842 // Logical-logical words.
1843 // Rx=or(Ru,and(Rx,#s10))
1844 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1845 validSubTargets = HasV4SubT in
1846 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
1847 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1848 "$dst = or($src1, and($src2, #$src3))",
1849 [(set (i32 IntRegs:$dst),
1850 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1851 s10ExtPred:$src3)))],
1855 // Rx[&|^]=and(Rs,Rt)
1857 let validSubTargets = HasV4SubT in
1858 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1859 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1860 "$dst &= and($src2, $src3)",
1861 [(set (i32 IntRegs:$dst),
1862 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1863 (i32 IntRegs:$src3))))],
1868 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
1869 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1870 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1871 "$dst |= and($src2, $src3)",
1872 [(set (i32 IntRegs:$dst),
1873 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1874 (i32 IntRegs:$src3))))],
1876 Requires<[HasV4T]>, ImmRegRel;
1879 let validSubTargets = HasV4SubT in
1880 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1881 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1882 "$dst ^= and($src2, $src3)",
1883 [(set (i32 IntRegs:$dst),
1884 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1885 (i32 IntRegs:$src3))))],
1889 // Rx[&|^]=and(Rs,~Rt)
1891 let validSubTargets = HasV4SubT in
1892 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1893 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1894 "$dst &= and($src2, ~$src3)",
1895 [(set (i32 IntRegs:$dst),
1896 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1897 (not (i32 IntRegs:$src3)))))],
1902 let validSubTargets = HasV4SubT in
1903 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1904 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1905 "$dst |= and($src2, ~$src3)",
1906 [(set (i32 IntRegs:$dst),
1907 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1908 (not (i32 IntRegs:$src3)))))],
1913 let validSubTargets = HasV4SubT in
1914 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1915 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1916 "$dst ^= and($src2, ~$src3)",
1917 [(set (i32 IntRegs:$dst),
1918 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1919 (not (i32 IntRegs:$src3)))))],
1923 // Rx[&|^]=or(Rs,Rt)
1925 let validSubTargets = HasV4SubT in
1926 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1927 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1928 "$dst &= or($src2, $src3)",
1929 [(set (i32 IntRegs:$dst),
1930 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1931 (i32 IntRegs:$src3))))],
1936 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
1937 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1938 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1939 "$dst |= or($src2, $src3)",
1940 [(set (i32 IntRegs:$dst),
1941 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1942 (i32 IntRegs:$src3))))],
1944 Requires<[HasV4T]>, ImmRegRel;
1947 let validSubTargets = HasV4SubT in
1948 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1949 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1950 "$dst ^= or($src2, $src3)",
1951 [(set (i32 IntRegs:$dst),
1952 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1953 (i32 IntRegs:$src3))))],
1957 // Rx[&|^]=xor(Rs,Rt)
1959 let validSubTargets = HasV4SubT in
1960 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1961 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1962 "$dst &= xor($src2, $src3)",
1963 [(set (i32 IntRegs:$dst),
1964 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1965 (i32 IntRegs:$src3))))],
1970 let validSubTargets = HasV4SubT in
1971 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1972 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1973 "$dst |= xor($src2, $src3)",
1974 [(set (i32 IntRegs:$dst),
1975 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1976 (i32 IntRegs:$src3))))],
1981 let validSubTargets = HasV4SubT in
1982 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1983 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1984 "$dst ^= xor($src2, $src3)",
1985 [(set (i32 IntRegs:$dst),
1986 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1987 (i32 IntRegs:$src3))))],
1992 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1993 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
1994 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
1995 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1996 "$dst |= and($src2, #$src3)",
1997 [(set (i32 IntRegs:$dst),
1998 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1999 s10ExtPred:$src3)))],
2001 Requires<[HasV4T]>, ImmRegRel;
2004 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
2005 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
2006 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
2007 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
2008 "$dst |= or($src2, #$src3)",
2009 [(set (i32 IntRegs:$dst),
2010 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2011 s10ExtPred:$src3)))],
2013 Requires<[HasV4T]>, ImmRegRel;
2017 // Rd=modwrap(Rs,Rt)
2019 // Rd=cround(Rs,#u5)
2021 // Rd=round(Rs,#u5)[:sat]
2022 // Rd=round(Rs,Rt)[:sat]
2023 // Vector reduce add unsigned halfwords
2024 // Rd=vraddh(Rss,Rtt)
2026 // Rdd=vaddb(Rss,Rtt)
2027 // Vector conditional negate
2028 // Rdd=vcnegh(Rss,Rt)
2029 // Rxx+=vrcnegh(Rss,Rt)
2030 // Vector maximum bytes
2031 // Rdd=vmaxb(Rtt,Rss)
2032 // Vector reduce maximum halfwords
2033 // Rxx=vrmaxh(Rss,Ru)
2034 // Rxx=vrmaxuh(Rss,Ru)
2035 // Vector reduce maximum words
2036 // Rxx=vrmaxuw(Rss,Ru)
2037 // Rxx=vrmaxw(Rss,Ru)
2038 // Vector minimum bytes
2039 // Rdd=vminb(Rtt,Rss)
2040 // Vector reduce minimum halfwords
2041 // Rxx=vrminh(Rss,Ru)
2042 // Rxx=vrminuh(Rss,Ru)
2043 // Vector reduce minimum words
2044 // Rxx=vrminuw(Rss,Ru)
2045 // Rxx=vrminw(Rss,Ru)
2046 // Vector subtract bytes
2047 // Rdd=vsubb(Rss,Rtt)
2049 //===----------------------------------------------------------------------===//
2051 //===----------------------------------------------------------------------===//
2054 //===----------------------------------------------------------------------===//
2056 //===----------------------------------------------------------------------===//
2058 // Multiply and user lower result.
2059 // Rd=add(#u6,mpyi(Rs,#U6))
2060 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
2061 validSubTargets = HasV4SubT in
2062 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
2063 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
2064 "$dst = add(#$src1, mpyi($src2, #$src3))",
2065 [(set (i32 IntRegs:$dst),
2066 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2067 u6ExtPred:$src1))]>,
2070 // Rd=add(##,mpyi(Rs,#U6))
2071 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2072 (HexagonCONST32 tglobaladdr:$src1)),
2073 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
2076 // Rd=add(#u6,mpyi(Rs,Rt))
2077 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
2078 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
2079 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
2080 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
2081 "$dst = add(#$src1, mpyi($src2, $src3))",
2082 [(set (i32 IntRegs:$dst),
2083 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2084 u6ExtPred:$src1))]>,
2085 Requires<[HasV4T]>, ImmRegRel;
2087 // Rd=add(##,mpyi(Rs,Rt))
2088 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2089 (HexagonCONST32 tglobaladdr:$src1)),
2090 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
2093 // Rd=add(Ru,mpyi(#u6:2,Rs))
2094 let validSubTargets = HasV4SubT in
2095 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
2096 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
2097 "$dst = add($src1, mpyi(#$src2, $src3))",
2098 [(set (i32 IntRegs:$dst),
2099 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
2100 u6_2ImmPred:$src2)))]>,
2103 // Rd=add(Ru,mpyi(Rs,#u6))
2104 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
2105 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
2106 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
2107 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
2108 "$dst = add($src1, mpyi($src2, #$src3))",
2109 [(set (i32 IntRegs:$dst),
2110 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
2111 u6ExtPred:$src3)))]>,
2112 Requires<[HasV4T]>, ImmRegRel;
2114 // Rx=add(Ru,mpyi(Rx,Rs))
2115 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
2116 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
2117 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2118 "$dst = add($src1, mpyi($src2, $src3))",
2119 [(set (i32 IntRegs:$dst),
2120 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
2121 (i32 IntRegs:$src3))))],
2123 Requires<[HasV4T]>, ImmRegRel;
2126 // Polynomial multiply words
2128 // Rxx^=pmpyw(Rs,Rt)
2130 // Vector reduce multiply word by signed half (32x16)
2131 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2132 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2133 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
2134 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
2136 // Multiply and use upper result
2137 // Rd=mpy(Rs,Rt.H):<<1:sat
2138 // Rd=mpy(Rs,Rt.L):<<1:sat
2139 // Rd=mpy(Rs,Rt):<<1
2140 // Rd=mpy(Rs,Rt):<<1:sat
2142 // Rx+=mpy(Rs,Rt):<<1:sat
2143 // Rx-=mpy(Rs,Rt):<<1:sat
2145 // Vector multiply bytes
2146 // Rdd=vmpybsu(Rs,Rt)
2147 // Rdd=vmpybu(Rs,Rt)
2148 // Rxx+=vmpybsu(Rs,Rt)
2149 // Rxx+=vmpybu(Rs,Rt)
2151 // Vector polynomial multiply halfwords
2152 // Rdd=vpmpyh(Rs,Rt)
2153 // Rxx^=vpmpyh(Rs,Rt)
2155 //===----------------------------------------------------------------------===//
2157 //===----------------------------------------------------------------------===//
2160 //===----------------------------------------------------------------------===//
2162 //===----------------------------------------------------------------------===//
2164 // Shift by immediate and accumulate.
2165 // Rx=add(#u8,asl(Rx,#U5))
2166 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2167 validSubTargets = HasV4SubT in
2168 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2169 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2170 "$dst = add(#$src1, asl($src2, #$src3))",
2171 [(set (i32 IntRegs:$dst),
2172 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2177 // Rx=add(#u8,lsr(Rx,#U5))
2178 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2179 validSubTargets = HasV4SubT in
2180 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2181 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2182 "$dst = add(#$src1, lsr($src2, #$src3))",
2183 [(set (i32 IntRegs:$dst),
2184 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2189 // Rx=sub(#u8,asl(Rx,#U5))
2190 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2191 validSubTargets = HasV4SubT in
2192 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2193 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2194 "$dst = sub(#$src1, asl($src2, #$src3))",
2195 [(set (i32 IntRegs:$dst),
2196 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2201 // Rx=sub(#u8,lsr(Rx,#U5))
2202 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2203 validSubTargets = HasV4SubT in
2204 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2205 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2206 "$dst = sub(#$src1, lsr($src2, #$src3))",
2207 [(set (i32 IntRegs:$dst),
2208 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2214 //Shift by immediate and logical.
2215 //Rx=and(#u8,asl(Rx,#U5))
2216 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2217 validSubTargets = HasV4SubT in
2218 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2219 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2220 "$dst = and(#$src1, asl($src2, #$src3))",
2221 [(set (i32 IntRegs:$dst),
2222 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2227 //Rx=and(#u8,lsr(Rx,#U5))
2228 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2229 validSubTargets = HasV4SubT in
2230 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2231 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2232 "$dst = and(#$src1, lsr($src2, #$src3))",
2233 [(set (i32 IntRegs:$dst),
2234 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2239 //Rx=or(#u8,asl(Rx,#U5))
2240 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2241 AddedComplexity = 30, validSubTargets = HasV4SubT in
2242 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2243 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2244 "$dst = or(#$src1, asl($src2, #$src3))",
2245 [(set (i32 IntRegs:$dst),
2246 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2251 //Rx=or(#u8,lsr(Rx,#U5))
2252 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2253 AddedComplexity = 30, validSubTargets = HasV4SubT in
2254 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2255 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2256 "$dst = or(#$src1, lsr($src2, #$src3))",
2257 [(set (i32 IntRegs:$dst),
2258 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2264 //Shift by register.
2266 let validSubTargets = HasV4SubT in {
2267 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
2268 "$dst = lsl(#$src1, $src2)",
2269 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
2270 (i32 IntRegs:$src2)))]>,
2274 //Shift by register and logical.
2276 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2277 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2278 "$dst ^= asl($src2, $src3)",
2279 [(set (i64 DoubleRegs:$dst),
2280 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
2281 (i32 IntRegs:$src3))))],
2286 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2287 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2288 "$dst ^= asr($src2, $src3)",
2289 [(set (i64 DoubleRegs:$dst),
2290 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
2291 (i32 IntRegs:$src3))))],
2296 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2297 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2298 "$dst ^= lsl($src2, $src3)",
2299 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
2300 (shl (i64 DoubleRegs:$src2),
2301 (i32 IntRegs:$src3))))],
2306 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2307 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2308 "$dst ^= lsr($src2, $src3)",
2309 [(set (i64 DoubleRegs:$dst),
2310 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
2311 (i32 IntRegs:$src3))))],
2316 //===----------------------------------------------------------------------===//
2318 //===----------------------------------------------------------------------===//
2320 //===----------------------------------------------------------------------===//
2321 // MEMOP: Word, Half, Byte
2322 //===----------------------------------------------------------------------===//
2324 def MEMOPIMM : SDNodeXForm<imm, [{
2325 // Call the transformation function XformM5ToU5Imm to get the negative
2326 // immediate's positive counterpart.
2327 int32_t imm = N->getSExtValue();
2328 return XformM5ToU5Imm(imm);
2331 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2332 // -1 .. -31 represented as 65535..65515
2333 // assigning to a short restores our desired signed value.
2334 // Call the transformation function XformM5ToU5Imm to get the negative
2335 // immediate's positive counterpart.
2336 int16_t imm = N->getSExtValue();
2337 return XformM5ToU5Imm(imm);
2340 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2341 // -1 .. -31 represented as 255..235
2342 // assigning to a char restores our desired signed value.
2343 // Call the transformation function XformM5ToU5Imm to get the negative
2344 // immediate's positive counterpart.
2345 int8_t imm = N->getSExtValue();
2346 return XformM5ToU5Imm(imm);
2349 def SETMEMIMM : SDNodeXForm<imm, [{
2350 // Return the bit position we will set [0-31].
2352 int32_t imm = N->getSExtValue();
2353 return XformMskToBitPosU5Imm(imm);
2356 def CLRMEMIMM : SDNodeXForm<imm, [{
2357 // Return the bit position we will clear [0-31].
2359 // we bit negate the value first
2360 int32_t imm = ~(N->getSExtValue());
2361 return XformMskToBitPosU5Imm(imm);
2364 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2365 // Return the bit position we will set [0-15].
2367 int16_t imm = N->getSExtValue();
2368 return XformMskToBitPosU4Imm(imm);
2371 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2372 // Return the bit position we will clear [0-15].
2374 // we bit negate the value first
2375 int16_t imm = ~(N->getSExtValue());
2376 return XformMskToBitPosU4Imm(imm);
2379 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2380 // Return the bit position we will set [0-7].
2382 int8_t imm = N->getSExtValue();
2383 return XformMskToBitPosU3Imm(imm);
2386 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2387 // Return the bit position we will clear [0-7].
2389 // we bit negate the value first
2390 int8_t imm = ~(N->getSExtValue());
2391 return XformMskToBitPosU3Imm(imm);
2394 //===----------------------------------------------------------------------===//
2395 // Template class for MemOp instructions with the register value.
2396 //===----------------------------------------------------------------------===//
2397 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2398 string memOp, bits<2> memOpBits> :
2400 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2401 opc#"($base+#$offset)"#memOp#"$delta",
2403 Requires<[HasV4T, UseMEMOP]> {
2408 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2410 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2411 !if (!eq(opcBits, 0b01), offset{6-1},
2412 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2414 let IClass = 0b0011;
2415 let Inst{27-24} = 0b1110;
2416 let Inst{22-21} = opcBits;
2417 let Inst{20-16} = base;
2419 let Inst{12-7} = offsetBits;
2420 let Inst{6-5} = memOpBits;
2421 let Inst{4-0} = delta;
2424 //===----------------------------------------------------------------------===//
2425 // Template class for MemOp instructions with the immediate value.
2426 //===----------------------------------------------------------------------===//
2427 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2428 string memOp, bits<2> memOpBits> :
2430 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2431 opc#"($base+#$offset)"#memOp#"#$delta"
2432 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2434 Requires<[HasV4T, UseMEMOP]> {
2439 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2441 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2442 !if (!eq(opcBits, 0b01), offset{6-1},
2443 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2445 let IClass = 0b0011;
2446 let Inst{27-24} = 0b1111;
2447 let Inst{22-21} = opcBits;
2448 let Inst{20-16} = base;
2450 let Inst{12-7} = offsetBits;
2451 let Inst{6-5} = memOpBits;
2452 let Inst{4-0} = delta;
2455 // multiclass to define MemOp instructions with register operand.
2456 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2457 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2458 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2459 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2460 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2463 // multiclass to define MemOp instructions with immediate Operand.
2464 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2465 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2466 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2467 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
2468 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
2471 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2472 defm r : MemOp_rr <opc, opcBits, ImmOp>;
2473 defm i : MemOp_ri <opc, opcBits, ImmOp>;
2476 // Define MemOp instructions.
2477 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2478 validSubTargets =HasV4SubT in {
2479 let opExtentBits = 6, accessSize = ByteAccess in
2480 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
2482 let opExtentBits = 7, accessSize = HalfWordAccess in
2483 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
2485 let opExtentBits = 8, accessSize = WordAccess in
2486 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
2489 //===----------------------------------------------------------------------===//
2490 // Multiclass to define 'Def Pats' for ALU operations on the memory
2491 // Here value used for the ALU operation is an immediate value.
2492 // mem[bh](Rs+#0) += #U5
2493 // mem[bh](Rs+#u6) += #U5
2494 //===----------------------------------------------------------------------===//
2496 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2497 InstHexagon MI, SDNode OpNode> {
2498 let AddedComplexity = 180 in
2499 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2501 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2503 let AddedComplexity = 190 in
2504 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2506 (add IntRegs:$base, ExtPred:$offset)),
2507 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2510 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2511 InstHexagon addMI, InstHexagon subMI> {
2512 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2513 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2516 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2518 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2519 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
2521 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2522 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
2525 let Predicates = [HasV4T, UseMEMOP] in {
2526 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2527 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2528 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2531 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
2535 //===----------------------------------------------------------------------===//
2536 // multiclass to define 'Def Pats' for ALU operations on the memory.
2537 // Here value used for the ALU operation is a negative value.
2538 // mem[bh](Rs+#0) += #m5
2539 // mem[bh](Rs+#u6) += #m5
2540 //===----------------------------------------------------------------------===//
2542 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2543 PatLeaf immPred, ComplexPattern addrPred,
2544 SDNodeXForm xformFunc, InstHexagon MI> {
2545 let AddedComplexity = 190 in
2546 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2548 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2550 let AddedComplexity = 195 in
2551 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2553 (add IntRegs:$base, extPred:$offset)),
2554 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2557 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2559 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2560 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
2562 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2563 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
2566 let Predicates = [HasV4T, UseMEMOP] in {
2567 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2568 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2569 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2572 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2573 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
2576 //===----------------------------------------------------------------------===//
2577 // Multiclass to define 'def Pats' for bit operations on the memory.
2578 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2579 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2580 //===----------------------------------------------------------------------===//
2582 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2583 PatLeaf extPred, ComplexPattern addrPred,
2584 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2586 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2587 let AddedComplexity = 250 in
2588 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2590 (add IntRegs:$base, extPred:$offset)),
2591 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2593 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2594 let AddedComplexity = 225 in
2595 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2597 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2598 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2601 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2603 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2604 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
2606 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2607 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
2608 // Half Word - clrbit
2609 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2610 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
2611 // Half Word - setbit
2612 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2613 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
2616 let Predicates = [HasV4T, UseMEMOP] in {
2617 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2618 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2619 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2620 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2621 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2623 // memw(Rs+#0) = [clrbit|setbit](#U5)
2624 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2625 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2626 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2627 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2628 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2631 //===----------------------------------------------------------------------===//
2632 // Multiclass to define 'def Pats' for ALU operations on the memory
2633 // where addend is a register.
2634 // mem[bhw](Rs+#0) [+-&|]= Rt
2635 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2636 //===----------------------------------------------------------------------===//
2638 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2639 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2640 let AddedComplexity = 141 in
2641 // mem[bhw](Rs+#0) [+-&|]= Rt
2642 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2643 (i32 IntRegs:$addend)),
2644 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2645 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2647 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2648 let AddedComplexity = 150 in
2649 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2650 (i32 IntRegs:$orend)),
2651 (add IntRegs:$base, extPred:$offset)),
2652 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2655 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2656 ComplexPattern addrPred, PatLeaf extPred,
2657 InstHexagon addMI, InstHexagon subMI,
2658 InstHexagon andMI, InstHexagon orMI > {
2660 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2661 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2662 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2663 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2666 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2668 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2669 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2670 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2672 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2673 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2674 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2677 // Define 'def Pats' for MemOps with register addend.
2678 let Predicates = [HasV4T, UseMEMOP] in {
2680 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2681 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2682 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2684 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2685 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2688 //===----------------------------------------------------------------------===//
2690 //===----------------------------------------------------------------------===//
2692 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2693 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2694 // hardware. However, compiler can still implement these patterns through
2695 // appropriate patterns combinations based on current implemented patterns.
2696 // The implemented patterns are: EQ/GT/GTU.
2697 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2699 // Following instruction is not being extended as it results into the
2700 // incorrect code for negative numbers.
2701 // Pd=cmpb.eq(Rs,#u8)
2703 let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0,
2704 validSubTargets = HasV4SubT in
2705 class CMP_NOT_REG_IMM<string OpName, bits<2> op, Operand ImmOp,
2707 : ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2),
2708 "$dst = !cmp."#OpName#"($src1, #$src2)",
2710 "", ALU32_2op_tc_2early_SLOT0123> {
2715 let IClass = 0b0111;
2716 let Inst{27-24} = 0b0101;
2717 let Inst{23-22} = op;
2718 let Inst{20-16} = src1;
2719 let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9});
2720 let Inst{13-5} = src2{8-0};
2721 let Inst{4-2} = 0b100;
2722 let Inst{1-0} = dst;
2725 let opExtentBits = 10, isExtentSigned = 1 in {
2726 def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst),
2727 (setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>;
2729 def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst),
2730 (not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>;
2733 let opExtentBits = 9 in
2734 def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
2735 (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
2740 let isCompare = 1, validSubTargets = HasV4SubT in
2741 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2742 (ins IntRegs:$src1, IntRegs:$src2),
2743 "$dst = !cmp.eq($src1, $src2)",
2744 [(set (i1 PredRegs:$dst),
2745 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2749 let isCompare = 1, validSubTargets = HasV4SubT in
2750 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2751 (ins IntRegs:$src1, IntRegs:$src2),
2752 "$dst = !cmp.gt($src1, $src2)",
2753 [(set (i1 PredRegs:$dst),
2754 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2758 // p=!cmp.gtu(r1,r2)
2759 let isCompare = 1, validSubTargets = HasV4SubT in
2760 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2761 (ins IntRegs:$src1, IntRegs:$src2),
2762 "$dst = !cmp.gtu($src1, $src2)",
2763 [(set (i1 PredRegs:$dst),
2764 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2767 let isCompare = 1, validSubTargets = HasV4SubT in
2768 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2769 (ins IntRegs:$src1, u8Imm:$src2),
2770 "$dst = cmpb.eq($src1, #$src2)",
2771 [(set (i1 PredRegs:$dst),
2772 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2775 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2777 (J2_jumpf (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2781 // Pd=cmpb.eq(Rs,Rt)
2782 let isCompare = 1, validSubTargets = HasV4SubT in
2783 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2784 (ins IntRegs:$src1, IntRegs:$src2),
2785 "$dst = cmpb.eq($src1, $src2)",
2786 [(set (i1 PredRegs:$dst),
2787 (seteq (and (xor (i32 IntRegs:$src1),
2788 (i32 IntRegs:$src2)), 255), 0))]>,
2791 // Pd=cmpb.eq(Rs,Rt)
2792 let isCompare = 1, validSubTargets = HasV4SubT in
2793 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2794 (ins IntRegs:$src1, IntRegs:$src2),
2795 "$dst = cmpb.eq($src1, $src2)",
2796 [(set (i1 PredRegs:$dst),
2797 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2798 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2801 // Pd=cmpb.gt(Rs,Rt)
2802 let isCompare = 1, validSubTargets = HasV4SubT in
2803 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2804 (ins IntRegs:$src1, IntRegs:$src2),
2805 "$dst = cmpb.gt($src1, $src2)",
2806 [(set (i1 PredRegs:$dst),
2807 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2808 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2811 // Pd=cmpb.gtu(Rs,#u7)
2812 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2813 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2814 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2815 (ins IntRegs:$src1, u7Ext:$src2),
2816 "$dst = cmpb.gtu($src1, #$src2)",
2817 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2818 u7ExtPred:$src2))]>,
2819 Requires<[HasV4T]>, ImmRegRel;
2821 // SDNode for converting immediate C to C-1.
2822 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2823 // Return the byte immediate const-1 as an SDNode.
2824 int32_t imm = N->getSExtValue();
2825 return XformU7ToU7M1Imm(imm);
2829 // zext( seteq ( and(Rs, 255), u8))
2831 // Pd=cmpb.eq(Rs, #u8)
2832 // if (Pd.new) Rd=#1
2833 // if (!Pd.new) Rd=#0
2834 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2836 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2842 // zext( setne ( and(Rs, 255), u8))
2844 // Pd=cmpb.eq(Rs, #u8)
2845 // if (Pd.new) Rd=#0
2846 // if (!Pd.new) Rd=#1
2847 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2849 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2855 // zext( seteq (Rs, and(Rt, 255)))
2857 // Pd=cmpb.eq(Rs, Rt)
2858 // if (Pd.new) Rd=#1
2859 // if (!Pd.new) Rd=#0
2860 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2861 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2862 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2863 (i32 IntRegs:$Rt))),
2868 // zext( setne (Rs, and(Rt, 255)))
2870 // Pd=cmpb.eq(Rs, Rt)
2871 // if (Pd.new) Rd=#0
2872 // if (!Pd.new) Rd=#1
2873 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2874 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2875 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2876 (i32 IntRegs:$Rt))),
2881 // zext( setugt ( and(Rs, 255), u8))
2883 // Pd=cmpb.gtu(Rs, #u8)
2884 // if (Pd.new) Rd=#1
2885 // if (!Pd.new) Rd=#0
2886 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2888 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2894 // zext( setugt ( and(Rs, 254), u8))
2896 // Pd=cmpb.gtu(Rs, #u8)
2897 // if (Pd.new) Rd=#1
2898 // if (!Pd.new) Rd=#0
2899 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2901 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2907 // zext( setult ( Rs, Rt))
2909 // Pd=cmp.ltu(Rs, Rt)
2910 // if (Pd.new) Rd=#1
2911 // if (!Pd.new) Rd=#0
2912 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2913 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2914 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2915 (i32 IntRegs:$Rs))),
2920 // zext( setlt ( Rs, Rt))
2922 // Pd=cmp.lt(Rs, Rt)
2923 // if (Pd.new) Rd=#1
2924 // if (!Pd.new) Rd=#0
2925 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2926 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2927 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2928 (i32 IntRegs:$Rs))),
2933 // zext( setugt ( Rs, Rt))
2935 // Pd=cmp.gtu(Rs, Rt)
2936 // if (Pd.new) Rd=#1
2937 // if (!Pd.new) Rd=#0
2938 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2939 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2940 (i32 IntRegs:$Rt))),
2944 // This pattern interefers with coremark performance, not implementing at this
2947 // zext( setgt ( Rs, Rt))
2949 // Pd=cmp.gt(Rs, Rt)
2950 // if (Pd.new) Rd=#1
2951 // if (!Pd.new) Rd=#0
2954 // zext( setuge ( Rs, Rt))
2956 // Pd=cmp.ltu(Rs, Rt)
2957 // if (Pd.new) Rd=#0
2958 // if (!Pd.new) Rd=#1
2959 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2960 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2961 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2962 (i32 IntRegs:$Rs))),
2967 // zext( setge ( Rs, Rt))
2969 // Pd=cmp.lt(Rs, Rt)
2970 // if (Pd.new) Rd=#0
2971 // if (!Pd.new) Rd=#1
2972 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2973 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2974 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2975 (i32 IntRegs:$Rs))),
2980 // zext( setule ( Rs, Rt))
2982 // Pd=cmp.gtu(Rs, Rt)
2983 // if (Pd.new) Rd=#0
2984 // if (!Pd.new) Rd=#1
2985 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2986 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2987 (i32 IntRegs:$Rt))),
2992 // zext( setle ( Rs, Rt))
2994 // Pd=cmp.gt(Rs, Rt)
2995 // if (Pd.new) Rd=#0
2996 // if (!Pd.new) Rd=#1
2997 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2998 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
2999 (i32 IntRegs:$Rt))),
3004 // zext( setult ( and(Rs, 255), u8))
3005 // Use the isdigit transformation below
3007 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
3008 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3009 // The isdigit transformation relies on two 'clever' aspects:
3010 // 1) The data type is unsigned which allows us to eliminate a zero test after
3011 // biasing the expression by 48. We are depending on the representation of
3012 // the unsigned types, and semantics.
3013 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3016 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3017 // The code is transformed upstream of llvm into
3018 // retval = (c-48) < 10 ? 1 : 0;
3019 let AddedComplexity = 139 in
3020 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3021 u7StrictPosImmPred:$src2)))),
3022 (i32 (C2_muxii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
3023 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
3027 // Pd=cmpb.gtu(Rs,Rt)
3028 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
3029 InputType = "reg" in
3030 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
3031 (ins IntRegs:$src1, IntRegs:$src2),
3032 "$dst = cmpb.gtu($src1, $src2)",
3033 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
3034 (and (i32 IntRegs:$src2), 255)))]>,
3035 Requires<[HasV4T]>, ImmRegRel;
3037 // Following instruction is not being extended as it results into the incorrect
3038 // code for negative numbers.
3040 // Signed half compare(.eq) ri.
3041 // Pd=cmph.eq(Rs,#s8)
3042 let isCompare = 1, validSubTargets = HasV4SubT in
3043 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
3044 (ins IntRegs:$src1, s8Imm:$src2),
3045 "$dst = cmph.eq($src1, #$src2)",
3046 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
3047 s8ImmPred:$src2))]>,
3050 // Signed half compare(.eq) rr.
3051 // Case 1: xor + and, then compare:
3053 // r0=and(r0,#0xffff)
3055 // Pd=cmph.eq(Rs,Rt)
3056 let isCompare = 1, validSubTargets = HasV4SubT in
3057 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
3058 (ins IntRegs:$src1, IntRegs:$src2),
3059 "$dst = cmph.eq($src1, $src2)",
3060 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
3061 (i32 IntRegs:$src2)),
3065 // Signed half compare(.eq) rr.
3066 // Case 2: shift left 16 bits then compare:
3070 // Pd=cmph.eq(Rs,Rt)
3071 let isCompare = 1, validSubTargets = HasV4SubT in
3072 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
3073 (ins IntRegs:$src1, IntRegs:$src2),
3074 "$dst = cmph.eq($src1, $src2)",
3075 [(set (i1 PredRegs:$dst),
3076 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
3077 (shl (i32 IntRegs:$src2), (i32 16))))]>,
3080 /* Incorrect Pattern -- immediate should be right shifted before being
3081 used in the cmph.gt instruction.
3082 // Signed half compare(.gt) ri.
3083 // Pd=cmph.gt(Rs,#s8)
3085 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
3086 isCompare = 1, validSubTargets = HasV4SubT in
3087 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
3088 (ins IntRegs:$src1, s8Ext:$src2),
3089 "$dst = cmph.gt($src1, #$src2)",
3090 [(set (i1 PredRegs:$dst),
3091 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3092 s8ExtPred:$src2))]>,
3096 // Signed half compare(.gt) rr.
3097 // Pd=cmph.gt(Rs,Rt)
3098 let isCompare = 1, validSubTargets = HasV4SubT in
3099 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
3100 (ins IntRegs:$src1, IntRegs:$src2),
3101 "$dst = cmph.gt($src1, $src2)",
3102 [(set (i1 PredRegs:$dst),
3103 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3104 (shl (i32 IntRegs:$src2), (i32 16))))]>,
3107 // Unsigned half compare rr (.gtu).
3108 // Pd=cmph.gtu(Rs,Rt)
3109 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
3110 InputType = "reg" in
3111 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
3112 (ins IntRegs:$src1, IntRegs:$src2),
3113 "$dst = cmph.gtu($src1, $src2)",
3114 [(set (i1 PredRegs:$dst),
3115 (setugt (and (i32 IntRegs:$src1), 65535),
3116 (and (i32 IntRegs:$src2), 65535)))]>,
3117 Requires<[HasV4T]>, ImmRegRel;
3119 // Unsigned half compare ri (.gtu).
3120 // Pd=cmph.gtu(Rs,#u7)
3121 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
3122 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
3123 InputType = "imm" in
3124 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
3125 (ins IntRegs:$src1, u7Ext:$src2),
3126 "$dst = cmph.gtu($src1, #$src2)",
3127 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
3128 u7ExtPred:$src2))]>,
3129 Requires<[HasV4T]>, ImmRegRel;
3131 let validSubTargets = HasV4SubT in
3132 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3133 "$dst = !tstbit($src1, $src2)",
3134 [(set (i1 PredRegs:$dst),
3135 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
3138 let validSubTargets = HasV4SubT in
3139 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
3140 "$dst = !tstbit($src1, $src2)",
3141 [(set (i1 PredRegs:$dst),
3142 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
3145 //===----------------------------------------------------------------------===//
3147 //===----------------------------------------------------------------------===//
3149 //Deallocate frame and return.
3151 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
3152 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in {
3153 let validSubTargets = HasV4SubT in
3154 def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
3160 // Restore registers and dealloc return function call.
3161 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3162 Defs = [R29, R30, R31, PC] in {
3163 let validSubTargets = HasV4SubT in
3164 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
3165 (ins calltarget:$dst),
3171 // Restore registers and dealloc frame before a tail call.
3172 let isCall = 1, isBarrier = 1,
3173 Defs = [R29, R30, R31, PC] in {
3174 let validSubTargets = HasV4SubT in
3175 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3176 (ins calltarget:$dst),
3182 // Save registers function call.
3183 let isCall = 1, isBarrier = 1,
3184 Uses = [R29, R31] in {
3185 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3186 (ins calltarget:$dst),
3187 "call $dst // Save_calle_saved_registers",
3192 // if (Ps) dealloc_return
3193 let isReturn = 1, isTerminator = 1,
3194 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3195 isPredicated = 1 in {
3196 let validSubTargets = HasV4SubT in
3197 def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
3198 (ins PredRegs:$src1),
3199 "if ($src1) dealloc_return",
3204 // if (!Ps) dealloc_return
3205 let isReturn = 1, isTerminator = 1,
3206 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3207 isPredicated = 1, isPredicatedFalse = 1 in {
3208 let validSubTargets = HasV4SubT in
3209 def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3210 "if (!$src1) dealloc_return",
3215 // if (Ps.new) dealloc_return:nt
3216 let isReturn = 1, isTerminator = 1,
3217 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3218 isPredicated = 1 in {
3219 let validSubTargets = HasV4SubT in
3220 def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3221 "if ($src1.new) dealloc_return:nt",
3226 // if (!Ps.new) dealloc_return:nt
3227 let isReturn = 1, isTerminator = 1,
3228 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3229 isPredicated = 1, isPredicatedFalse = 1 in {
3230 let validSubTargets = HasV4SubT in
3231 def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3232 "if (!$src1.new) dealloc_return:nt",
3237 // if (Ps.new) dealloc_return:t
3238 let isReturn = 1, isTerminator = 1,
3239 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3240 isPredicated = 1 in {
3241 let validSubTargets = HasV4SubT in
3242 def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3243 "if ($src1.new) dealloc_return:t",
3248 // if (!Ps.new) dealloc_return:nt
3249 let isReturn = 1, isTerminator = 1,
3250 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3251 isPredicated = 1, isPredicatedFalse = 1 in {
3252 let validSubTargets = HasV4SubT in
3253 def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3254 "if (!$src1.new) dealloc_return:t",
3259 // Load/Store with absolute addressing mode
3262 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3264 let isPredicatedNew = isPredNew in
3265 def NAME#_V4 : STInst2<(outs),
3266 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3267 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3268 ") ")#mnemonic#"(##$absaddr) = $src2",
3273 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3274 let isPredicatedFalse = PredNot in {
3275 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3277 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3281 let isNVStorable = 1, isExtended = 1, hasSideEffects = 0 in
3282 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3283 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3284 let opExtendable = 0, isPredicable = 1 in
3285 def NAME#_V4 : STInst2<(outs),
3286 (ins u0AlwaysExt:$absaddr, RC:$src),
3287 mnemonic#"(##$absaddr) = $src",
3291 let opExtendable = 1, isPredicated = 1 in {
3292 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
3293 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
3298 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
3300 let isPredicatedNew = isPredNew in
3301 def NAME#_nv_V4 : NVInst_V4<(outs),
3302 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3303 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3304 ") ")#mnemonic#"(##$absaddr) = $src2.new",
3309 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
3310 let isPredicatedFalse = PredNot in {
3311 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
3313 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
3317 let mayStore = 1, isNVStore = 1, isExtended = 1, hasSideEffects = 0 in
3318 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
3319 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3320 let opExtendable = 0, isPredicable = 1 in
3321 def NAME#_nv_V4 : NVInst_V4<(outs),
3322 (ins u0AlwaysExt:$absaddr, RC:$src),
3323 mnemonic#"(##$absaddr) = $src.new",
3327 let opExtendable = 1, isPredicated = 1 in {
3328 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3329 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3334 let addrMode = Absolute in {
3335 let accessSize = ByteAccess in
3336 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
3337 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
3339 let accessSize = HalfWordAccess in
3340 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
3341 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
3343 let accessSize = WordAccess in
3344 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
3345 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
3347 let accessSize = DoubleWordAccess, isNVStorable = 0 in
3348 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
3351 let Predicates = [HasV4T], AddedComplexity = 30 in {
3352 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3353 (HexagonCONST32 tglobaladdr:$absaddr)),
3354 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3356 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3357 (HexagonCONST32 tglobaladdr:$absaddr)),
3358 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3360 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3361 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3363 def : Pat<(store (i64 DoubleRegs:$src1),
3364 (HexagonCONST32 tglobaladdr:$absaddr)),
3365 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3368 //===----------------------------------------------------------------------===//
3369 // multiclass for store instructions with GP-relative addressing mode.
3370 // mem[bhwd](#global)=Rt
3371 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
3372 //===----------------------------------------------------------------------===//
3373 let mayStore = 1, isNVStorable = 1 in
3374 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3375 let BaseOpcode = BaseOp, isPredicable = 1 in
3376 def NAME#_V4 : STInst2<(outs),
3377 (ins globaladdress:$global, RC:$src),
3378 mnemonic#"(#$global) = $src",
3381 // When GP-relative instructions are predicated, their addressing mode is
3382 // changed to absolute and they are always constant extended.
3383 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3384 isPredicated = 1 in {
3385 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
3386 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
3390 let mayStore = 1, isNVStore = 1 in
3391 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
3392 let BaseOpcode = BaseOp, isPredicable = 1 in
3393 def NAME#_nv_V4 : NVInst_V4<(outs),
3394 (ins u0AlwaysExt:$global, RC:$src),
3395 mnemonic#"(#$global) = $src.new",
3399 // When GP-relative instructions are predicated, their addressing mode is
3400 // changed to absolute and they are always constant extended.
3401 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3402 isPredicated = 1 in {
3403 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3404 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3408 let validSubTargets = HasV4SubT, hasSideEffects = 0 in {
3409 let isNVStorable = 0 in
3410 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
3412 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
3413 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel;
3414 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
3415 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel;
3416 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
3417 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel;
3420 // 64 bit atomic store
3421 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3422 (i64 DoubleRegs:$src1)),
3423 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3426 // Map from store(globaladdress) -> memd(#foo)
3427 let AddedComplexity = 100 in
3428 def : Pat <(store (i64 DoubleRegs:$src1),
3429 (HexagonCONST32_GP tglobaladdr:$global)),
3430 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3432 // 8 bit atomic store
3433 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3434 (i32 IntRegs:$src1)),
3435 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3437 // Map from store(globaladdress) -> memb(#foo)
3438 let AddedComplexity = 100 in
3439 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3440 (HexagonCONST32_GP tglobaladdr:$global)),
3441 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3443 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3444 // to "r0 = 1; memw(#foo) = r0"
3445 let AddedComplexity = 100 in
3446 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3447 (STb_GP_V4 tglobaladdr:$global, (A2_tfrsi 1))>;
3449 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3450 (i32 IntRegs:$src1)),
3451 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3453 // Map from store(globaladdress) -> memh(#foo)
3454 let AddedComplexity = 100 in
3455 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3456 (HexagonCONST32_GP tglobaladdr:$global)),
3457 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3459 // 32 bit atomic store
3460 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3461 (i32 IntRegs:$src1)),
3462 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3464 // Map from store(globaladdress) -> memw(#foo)
3465 let AddedComplexity = 100 in
3466 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3467 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3469 //===----------------------------------------------------------------------===//
3470 // Multiclass for the load instructions with absolute addressing mode.
3471 //===----------------------------------------------------------------------===//
3472 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3474 let isPredicatedNew = isPredNew in
3475 def NAME : LDInst2<(outs RC:$dst),
3476 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
3477 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3478 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
3483 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3484 let isPredicatedFalse = PredNot in {
3485 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3487 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3491 let isExtended = 1, hasSideEffects = 0 in
3492 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3493 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3494 let opExtendable = 1, isPredicable = 1 in
3495 def NAME#_V4 : LDInst2<(outs RC:$dst),
3496 (ins u0AlwaysExt:$absaddr),
3497 "$dst = "#mnemonic#"(##$absaddr)",
3501 let opExtendable = 2, isPredicated = 1 in {
3502 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3503 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3508 let addrMode = Absolute in {
3509 let accessSize = ByteAccess in {
3510 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
3511 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
3513 let accessSize = HalfWordAccess in {
3514 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
3515 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
3517 let accessSize = WordAccess in
3518 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
3520 let accessSize = DoubleWordAccess in
3521 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
3524 let Predicates = [HasV4T], AddedComplexity = 30 in {
3525 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3526 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
3528 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3529 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
3531 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3532 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
3534 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3535 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
3537 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3538 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
3541 //===----------------------------------------------------------------------===//
3542 // multiclass for load instructions with GP-relative addressing mode.
3543 // Rx=mem[bhwd](##global)
3544 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3545 //===----------------------------------------------------------------------===//
3546 let hasSideEffects = 0, validSubTargets = HasV4SubT in
3547 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3548 let BaseOpcode = BaseOp in {
3549 let isPredicable = 1 in
3550 def NAME#_V4 : LDInst2<(outs RC:$dst),
3551 (ins globaladdress:$global),
3552 "$dst = "#mnemonic#"(#$global)",
3555 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
3556 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3557 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3562 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel;
3563 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel;
3564 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel;
3565 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel;
3566 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel;
3567 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel;
3569 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3570 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3572 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3573 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3575 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3576 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3578 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3579 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3581 // Map from load(globaladdress) -> memw(#foo + 0)
3582 let AddedComplexity = 100 in
3583 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3584 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3586 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3587 let AddedComplexity = 100 in
3588 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3589 (i1 (C2_tfrrp (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
3591 // When the Interprocedural Global Variable optimizer realizes that a certain
3592 // global variable takes only two constant values, it shrinks the global to
3593 // a boolean. Catch those loads here in the following 3 patterns.
3594 let AddedComplexity = 100 in
3595 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3596 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3598 let AddedComplexity = 100 in
3599 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3600 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3602 // Map from load(globaladdress) -> memb(#foo)
3603 let AddedComplexity = 100 in
3604 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3605 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3607 // Map from load(globaladdress) -> memb(#foo)
3608 let AddedComplexity = 100 in
3609 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3610 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3612 let AddedComplexity = 100 in
3613 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3614 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3616 // Map from load(globaladdress) -> memub(#foo)
3617 let AddedComplexity = 100 in
3618 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3619 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3621 // Map from load(globaladdress) -> memh(#foo)
3622 let AddedComplexity = 100 in
3623 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3624 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3626 // Map from load(globaladdress) -> memh(#foo)
3627 let AddedComplexity = 100 in
3628 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3629 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3631 // Map from load(globaladdress) -> memuh(#foo)
3632 let AddedComplexity = 100 in
3633 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3634 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3636 // Map from load(globaladdress) -> memw(#foo)
3637 let AddedComplexity = 100 in
3638 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3639 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3642 // Transfer global address into a register
3643 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3644 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3645 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3647 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3650 // Transfer a block address into a register
3651 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3652 (TFRI_V4 tblockaddress:$src1)>,
3655 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3656 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3657 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3658 (ins PredRegs:$src1, s16Ext:$src2),
3659 "if($src1) $dst = #$src2",
3663 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3664 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3665 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3666 (ins PredRegs:$src1, s16Ext:$src2),
3667 "if(!$src1) $dst = #$src2",
3671 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3672 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3673 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3674 (ins PredRegs:$src1, s16Ext:$src2),
3675 "if($src1.new) $dst = #$src2",
3679 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3680 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3681 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3682 (ins PredRegs:$src1, s16Ext:$src2),
3683 "if(!$src1.new) $dst = #$src2",
3687 let AddedComplexity = 50, Predicates = [HasV4T] in
3688 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3689 (TFRI_V4 tglobaladdr:$src1)>,
3693 // Load - Indirect with long offset: These instructions take global address
3695 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3696 validSubTargets = HasV4SubT in
3697 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3698 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3699 "$dst=memd($src1<<#$src2+##$offset)",
3700 [(set (i64 DoubleRegs:$dst),
3701 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3702 (HexagonCONST32 tglobaladdr:$offset))))]>,
3705 let AddedComplexity = 40 in
3706 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3707 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3708 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3709 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3710 !strconcat("$dst = ",
3711 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3713 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3714 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3718 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3719 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3720 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3721 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3722 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3723 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3724 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3726 let AddedComplexity = 40 in
3727 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3728 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3729 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3732 let AddedComplexity = 40 in
3733 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3734 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3735 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3738 let Predicates = [HasV4T], AddedComplexity = 30 in {
3739 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3740 (STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3742 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3743 (STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3745 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3746 (STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3749 let Predicates = [HasV4T], AddedComplexity = 30 in {
3750 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3751 (LDriw_abs_V4 u0AlwaysExtPred:$src)>;
3753 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3754 (LDrib_abs_V4 u0AlwaysExtPred:$src)>;
3756 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3757 (LDriub_abs_V4 u0AlwaysExtPred:$src)>;
3759 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3760 (LDrih_abs_V4 u0AlwaysExtPred:$src)>;
3762 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3763 (LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
3766 // Indexed store word - global address.
3767 // memw(Rs+#u6:2)=#S8
3768 let AddedComplexity = 10 in
3769 def STriw_offset_ext_V4 : STInst<(outs),
3770 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3771 "memw($src1+#$src2) = ##$src3",
3772 [(store (HexagonCONST32 tglobaladdr:$src3),
3773 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3776 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3777 (i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
3780 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3781 (i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
3786 // We need a complexity of 120 here to override preceding handling of
3788 let Predicates = [HasV4T], AddedComplexity = 120 in {
3789 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3790 (i64 (A4_combineir 0, (LDrib_abs_V4 tglobaladdr:$addr)))>;
3792 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3793 (i64 (A4_combineir 0, (LDriub_abs_V4 tglobaladdr:$addr)))>;
3795 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3796 (i64 (A2_sxtw (LDrib_abs_V4 tglobaladdr:$addr)))>;
3798 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3799 (i64 (A4_combineir 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3801 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3802 (i64 (A4_combineir 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>;
3804 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3805 (i64 (A2_sxtw (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3808 // We need a complexity of 120 here to override preceding handling of
3810 let AddedComplexity = 120 in {
3811 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3812 (i64 (A4_combineir 0, (LDrih_abs_V4 tglobaladdr:$addr)))>,
3815 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3816 (i64 (A4_combineir 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>,
3819 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3820 (i64 (A2_sxtw (LDrih_abs_V4 tglobaladdr:$addr)))>,
3823 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3824 (i64 (A4_combineir 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3827 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3828 (i64 (A4_combineir 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>,
3831 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3832 (i64 (A2_sxtw (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3836 // We need a complexity of 120 here to override preceding handling of
3838 let AddedComplexity = 120 in {
3839 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3840 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3843 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3844 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3847 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3848 (i64 (A2_sxtw (LDriw_abs_V4 tglobaladdr:$addr)))>,
3851 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3852 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3855 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3856 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3859 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3860 (i64 (A2_sxtw (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3864 // Indexed store double word - global address.
3865 // memw(Rs+#u6:2)=#S8
3866 let AddedComplexity = 10 in
3867 def STrih_offset_ext_V4 : STInst<(outs),
3868 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3869 "memh($src1+#$src2) = ##$src3",
3870 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3871 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3873 // Map from store(globaladdress + x) -> memd(#foo + x)
3874 let AddedComplexity = 100 in
3875 def : Pat<(store (i64 DoubleRegs:$src1),
3876 FoldGlobalAddrGP:$addr),
3877 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3880 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3881 (i64 DoubleRegs:$src1)),
3882 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3885 // Map from store(globaladdress + x) -> memb(#foo + x)
3886 let AddedComplexity = 100 in
3887 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3888 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3891 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3892 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3895 // Map from store(globaladdress + x) -> memh(#foo + x)
3896 let AddedComplexity = 100 in
3897 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3898 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3901 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3902 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3905 // Map from store(globaladdress + x) -> memw(#foo + x)
3906 let AddedComplexity = 100 in
3907 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3908 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3911 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3912 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3915 // Map from load(globaladdress + x) -> memd(#foo + x)
3916 let AddedComplexity = 100 in
3917 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3918 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3921 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3922 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3925 // Map from load(globaladdress + x) -> memb(#foo + x)
3926 let AddedComplexity = 100 in
3927 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3928 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3931 // Map from load(globaladdress + x) -> memb(#foo + x)
3932 let AddedComplexity = 100 in
3933 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3934 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3937 //let AddedComplexity = 100 in
3938 let AddedComplexity = 100 in
3939 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3940 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3943 // Map from load(globaladdress + x) -> memh(#foo + x)
3944 let AddedComplexity = 100 in
3945 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3946 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3949 // Map from load(globaladdress + x) -> memuh(#foo + x)
3950 let AddedComplexity = 100 in
3951 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3952 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3955 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3956 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3959 // Map from load(globaladdress + x) -> memub(#foo + x)
3960 let AddedComplexity = 100 in
3961 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3962 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3965 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3966 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3969 // Map from load(globaladdress + x) -> memw(#foo + x)
3970 let AddedComplexity = 100 in
3971 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3972 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
3975 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3976 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,