1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let hasSideEffects = 0 in
15 class T_Immext<Operand ImmType>
16 : EXTENDERInst<(outs), (ins ImmType:$imm),
17 "immext(#$imm)", []> {
21 let Inst{27-16} = imm{31-20};
22 let Inst{13-0} = imm{19-6};
25 def A4_ext : T_Immext<u26_6Imm>;
26 let isCodeGenOnly = 1 in {
28 def A4_ext_b : T_Immext<brtarget>;
30 def A4_ext_c : T_Immext<calltarget>;
31 def A4_ext_g : T_Immext<globaladdress>;
34 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
35 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
37 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
38 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
40 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
41 (HexagonCONST32 node:$addr), [{
42 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
45 // Hexagon V4 Architecture spec defines 8 instruction classes:
46 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
50 // ========================================
51 // Loads (8/16/32/64 bit)
55 // ========================================
56 // Stores (8/16/32/64 bit)
59 // ALU32 Instructions:
60 // ========================================
61 // Arithmetic / Logical (32 bit)
64 // XTYPE Instructions (32/64 bit):
65 // ========================================
66 // Arithmetic, Logical, Bit Manipulation
67 // Multiply (Integer, Fractional, Complex)
68 // Permute / Vector Permute Operations
69 // Predicate Operations
70 // Shift / Shift with Add/Sub/Logical
72 // Vector Halfword (ALU, Shift, Multiply)
73 // Vector Word (ALU, Shift)
76 // ========================================
77 // Jump/Call PC-relative
80 // ========================================
83 // MEMOP Instructions:
84 // ========================================
85 // Operation on memory (8/16/32 bit)
88 // ========================================
93 // ========================================
94 // Control-Register Transfers
95 // Hardware Loop Setup
96 // Predicate Logicals & Reductions
98 // SYSTEM Instructions (not implemented in the compiler):
99 // ========================================
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
109 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
111 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
112 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
115 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
116 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
117 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
118 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
120 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
121 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
122 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
123 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
125 let isCodeGenOnly = 0 in {
126 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
127 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
128 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
131 // Pats for instruction selection.
133 // A class to embed the usual comparison patfrags within a zext to i32.
134 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
135 // names, or else the frag's "body" won't match the operands.
136 class CmpInReg<PatFrag Op>
137 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
139 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
140 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
142 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
143 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
144 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
146 let validSubTargets = HasV4SubT;
147 let InputType = "reg";
148 let CextOpcode = mnemonic;
150 let isCommutable = IsComm;
151 let hasSideEffects = 0;
158 let Inst{27-21} = 0b0111110;
159 let Inst{20-16} = Rs;
161 let Inst{7-5} = MinOp;
165 let isCodeGenOnly = 0 in {
166 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
167 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
168 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
169 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
170 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
171 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
174 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
175 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
176 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
177 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
179 let validSubTargets = HasV4SubT;
180 let InputType = "imm";
181 let CextOpcode = mnemonic;
183 let isCommutable = IsComm;
184 let hasSideEffects = 0;
185 let isExtendable = IsImmExt;
186 let opExtendable = !if (IsImmExt, 2, 0);
187 let isExtentSigned = IsImmSigned;
188 let opExtentBits = ImmBits;
195 let Inst{27-24} = 0b1101;
196 let Inst{22-21} = MajOp;
197 let Inst{20-16} = Rs;
198 let Inst{12-5} = Imm;
200 let Inst{3} = IsHalf;
204 let isCodeGenOnly = 0 in {
205 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
206 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
207 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
208 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
209 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
210 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
212 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
213 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
214 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
216 let validSubTargets = HasV4SubT;
217 let InputType = "imm";
218 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
219 let isExtendable = 1;
220 let opExtendable = 2;
221 let isExtentSigned = 1;
222 let opExtentBits = 8;
230 let Inst{27-24} = 0b0011;
232 let Inst{21} = IsNeg;
233 let Inst{20-16} = Rs;
239 let isCodeGenOnly = 0 in {
240 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
241 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
244 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
245 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
246 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
247 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
249 // Preserve the S2_tstbit_r generation
250 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
251 (i32 IntRegs:$src1))), 0)))),
252 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
255 //===----------------------------------------------------------------------===//
257 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 //===----------------------------------------------------------------------===//
264 // Combine a word and an immediate into a register pair.
265 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
267 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
268 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
274 let Inst{27-24} = 0b0011;
275 let Inst{22-21} = MajOp;
276 let Inst{20-16} = Rs;
282 let opExtendable = 2, isCodeGenOnly = 0 in
283 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
284 "$Rdd = combine($Rs, #$s8)">;
286 let opExtendable = 1, isCodeGenOnly = 0 in
287 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
288 "$Rdd = combine(#$s8, $Rs)">;
290 def HexagonWrapperCombineRI_V4 :
291 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
292 def HexagonWrapperCombineIR_V4 :
293 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
295 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
296 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
299 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
300 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
303 // A4_combineii: Set two small immediates.
304 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
305 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
306 "$Rdd = combine(#$s8, #$U6)"> {
312 let Inst{27-23} = 0b11001;
313 let Inst{20-16} = U6{5-1};
314 let Inst{13} = U6{0};
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
325 //===----------------------------------------------------------------------===//
326 //===----------------------------------------------------------------------===//
327 // Template class for load instructions with Absolute set addressing mode.
328 //===----------------------------------------------------------------------===//
329 let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
330 validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
331 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
332 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
333 (ins u0AlwaysExt:$addr),
334 "$dst1 = "#mnemonic#"($dst2=##$addr)",
338 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
339 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
340 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
341 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
342 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
343 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
345 //===----------------------------------------------------------------------===//
346 // Template classes for the non-predicated load instructions with
347 // base + register offset addressing mode
348 //===----------------------------------------------------------------------===//
349 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
350 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
351 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
352 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
360 let Inst{27-24} = 0b1010;
361 let Inst{23-21} = MajOp;
362 let Inst{20-16} = src1;
363 let Inst{12-8} = src2;
364 let Inst{13} = u2{1};
369 //===----------------------------------------------------------------------===//
370 // Template classes for the predicated load instructions with
371 // base + register offset addressing mode
372 //===----------------------------------------------------------------------===//
373 let isPredicated = 1 in
374 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
375 bit isNot, bit isPredNew>:
376 LDInst <(outs RC:$dst),
377 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
378 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
379 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
380 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
387 let isPredicatedFalse = isNot;
388 let isPredicatedNew = isPredNew;
392 let Inst{27-26} = 0b00;
393 let Inst{25} = isPredNew;
394 let Inst{24} = isNot;
395 let Inst{23-21} = MajOp;
396 let Inst{20-16} = src2;
397 let Inst{12-8} = src3;
398 let Inst{13} = u2{1};
400 let Inst{6-5} = src1;
404 //===----------------------------------------------------------------------===//
405 // multiclass for load instructions with base + register offset
407 //===----------------------------------------------------------------------===//
408 let hasSideEffects = 0, addrMode = BaseRegOffset in
409 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
411 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
412 InputType = "reg" in {
413 let isPredicable = 1 in
414 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
417 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
418 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
421 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
422 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
426 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
427 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
428 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
431 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
432 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
433 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
436 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
437 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
439 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
440 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
442 // 'def pats' for load instructions with base + register offset and non-zero
443 // immediate value. Immediate value is used to left-shift the second
445 let AddedComplexity = 40 in {
446 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
447 (shl IntRegs:$src2, u2ImmPred:$offset)))),
448 (L4_loadrb_rr IntRegs:$src1,
449 IntRegs:$src2, u2ImmPred:$offset)>,
452 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
453 (shl IntRegs:$src2, u2ImmPred:$offset)))),
454 (L4_loadrub_rr IntRegs:$src1,
455 IntRegs:$src2, u2ImmPred:$offset)>,
458 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
459 (shl IntRegs:$src2, u2ImmPred:$offset)))),
460 (L4_loadrub_rr IntRegs:$src1,
461 IntRegs:$src2, u2ImmPred:$offset)>,
464 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
465 (shl IntRegs:$src2, u2ImmPred:$offset)))),
466 (L4_loadrh_rr IntRegs:$src1,
467 IntRegs:$src2, u2ImmPred:$offset)>,
470 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
471 (shl IntRegs:$src2, u2ImmPred:$offset)))),
472 (L4_loadruh_rr IntRegs:$src1,
473 IntRegs:$src2, u2ImmPred:$offset)>,
476 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
477 (shl IntRegs:$src2, u2ImmPred:$offset)))),
478 (L4_loadruh_rr IntRegs:$src1,
479 IntRegs:$src2, u2ImmPred:$offset)>,
482 def : Pat <(i32 (load (add IntRegs:$src1,
483 (shl IntRegs:$src2, u2ImmPred:$offset)))),
484 (L4_loadri_rr IntRegs:$src1,
485 IntRegs:$src2, u2ImmPred:$offset)>,
488 def : Pat <(i64 (load (add IntRegs:$src1,
489 (shl IntRegs:$src2, u2ImmPred:$offset)))),
490 (L4_loadrd_rr IntRegs:$src1,
491 IntRegs:$src2, u2ImmPred:$offset)>,
496 // 'def pats' for load instruction base + register offset and
497 // zero immediate value.
498 let AddedComplexity = 10 in {
499 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
500 (L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>,
503 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
504 (L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>,
507 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
508 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
511 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
512 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
515 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
516 (L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
519 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
520 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
523 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
524 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
527 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
528 (L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>,
533 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
534 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
538 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
539 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
542 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
543 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
546 let AddedComplexity = 20 in
547 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
548 s11_0ExtPred:$offset))),
549 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
550 s11_0ExtPred:$offset)))>,
554 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
555 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
558 let AddedComplexity = 20 in
559 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
560 s11_0ExtPred:$offset))),
561 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
562 s11_0ExtPred:$offset)))>,
566 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
567 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
570 let AddedComplexity = 20 in
571 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
572 s11_1ExtPred:$offset))),
573 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
574 s11_1ExtPred:$offset)))>,
578 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
579 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
582 let AddedComplexity = 20 in
583 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
584 s11_1ExtPred:$offset))),
585 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
586 s11_1ExtPred:$offset)))>,
590 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
591 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
594 let AddedComplexity = 100 in
595 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
596 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
597 s11_2ExtPred:$offset)))>,
601 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
602 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
605 let AddedComplexity = 100 in
606 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
607 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
608 s11_2ExtPred:$offset)))>,
613 //===----------------------------------------------------------------------===//
615 //===----------------------------------------------------------------------===//
617 //===----------------------------------------------------------------------===//
619 //===----------------------------------------------------------------------===//
621 //===----------------------------------------------------------------------===//
622 // Template class for store instructions with Absolute set addressing mode.
623 //===----------------------------------------------------------------------===//
624 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
625 addrMode = AbsoluteSet in
626 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
627 STInst2<(outs IntRegs:$dst1),
628 (ins RC:$src1, u0AlwaysExt:$src2),
629 mnemonic#"($dst1=##$src2) = $src1",
633 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
634 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
635 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
636 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
638 //===----------------------------------------------------------------------===//
639 // Template classes for the non-predicated store instructions with
640 // base + register offset addressing mode
641 //===----------------------------------------------------------------------===//
642 let isPredicable = 1 in
643 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
644 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
645 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
646 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
655 let Inst{27-24} = 0b1011;
656 let Inst{23-21} = MajOp;
657 let Inst{20-16} = Rs;
659 let Inst{13} = u2{1};
664 //===----------------------------------------------------------------------===//
665 // Template classes for the predicated store instructions with
666 // base + register offset addressing mode
667 //===----------------------------------------------------------------------===//
668 let isPredicated = 1 in
669 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
670 bit isNot, bit isPredNew, bit isH>
672 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
674 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
675 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
676 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
683 let isPredicatedFalse = isNot;
684 let isPredicatedNew = isPredNew;
688 let Inst{27-26} = 0b01;
689 let Inst{25} = isPredNew;
690 let Inst{24} = isNot;
691 let Inst{23-21} = MajOp;
692 let Inst{20-16} = Rs;
694 let Inst{13} = u2{1};
700 //===----------------------------------------------------------------------===//
701 // Template classes for the new-value store instructions with
702 // base + register offset addressing mode
703 //===----------------------------------------------------------------------===//
704 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
705 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
706 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
707 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
708 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
717 let Inst{27-21} = 0b1011101;
718 let Inst{20-16} = Rs;
720 let Inst{13} = u2{1};
722 let Inst{4-3} = MajOp;
726 //===----------------------------------------------------------------------===//
727 // Template classes for the predicated new-value store instructions with
728 // base + register offset addressing mode
729 //===----------------------------------------------------------------------===//
730 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
731 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
733 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
734 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
735 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
736 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
743 let isPredicatedFalse = isNot;
744 let isPredicatedNew = isPredNew;
747 let Inst{27-26} = 0b01;
748 let Inst{25} = isPredNew;
749 let Inst{24} = isNot;
750 let Inst{23-21} = 0b101;
751 let Inst{20-16} = Rs;
753 let Inst{13} = u2{1};
756 let Inst{4-3} = MajOp;
760 //===----------------------------------------------------------------------===//
761 // multiclass for store instructions with base + register offset addressing
763 //===----------------------------------------------------------------------===//
764 let isNVStorable = 1 in
765 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
766 bits<3> MajOp, bit isH = 0> {
767 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
768 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
771 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
772 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
775 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
776 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
780 //===----------------------------------------------------------------------===//
781 // multiclass for new-value store instructions with base + register offset
783 //===----------------------------------------------------------------------===//
784 let mayStore = 1, isNVStore = 1 in
785 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
787 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
788 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
791 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
792 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
795 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
796 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
800 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
801 isCodeGenOnly = 0 in {
802 let accessSize = ByteAccess in
803 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
804 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
806 let accessSize = HalfWordAccess in
807 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
808 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
810 let accessSize = WordAccess in
811 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
812 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
814 let isNVStorable = 0, accessSize = DoubleWordAccess in
815 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
817 let isNVStorable = 0, accessSize = HalfWordAccess in
818 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
821 let Predicates = [HasV4T], AddedComplexity = 10 in {
822 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
823 (add IntRegs:$src1, (shl IntRegs:$src2,
825 (S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
826 u2ImmPred:$src3, IntRegs:$src4)>;
828 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
829 (add IntRegs:$src1, (shl IntRegs:$src2,
831 (S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
832 u2ImmPred:$src3, IntRegs:$src4)>;
834 def : Pat<(store (i32 IntRegs:$src4),
835 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
836 (S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
837 u2ImmPred:$src3, IntRegs:$src4)>;
839 def : Pat<(store (i64 DoubleRegs:$src4),
840 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
841 (S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
842 u2ImmPred:$src3, DoubleRegs:$src4)>;
845 let isExtended = 1, opExtendable = 2 in
846 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
848 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
849 mnemonic#"($src1<<#$src2+##$src3) = $src4",
850 [(stOp (VT RC:$src4),
851 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
852 u0AlwaysExtPred:$src3))]>,
855 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
856 class T_ST_LongOff_nv <string mnemonic> :
858 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
859 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
863 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
864 let BaseOpcode = BaseOp#"_shl" in {
865 let isNVStorable = 1 in
866 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
868 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
872 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
873 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
874 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
875 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
876 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
879 let AddedComplexity = 40 in
880 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
882 def : Pat<(stOp (VT RC:$src4),
883 (add (shl IntRegs:$src1, u2ImmPred:$src2),
884 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
885 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
887 def : Pat<(stOp (VT RC:$src4),
889 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
890 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
893 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
894 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
895 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
896 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
898 // memd(Rx++#s4:3)=Rtt
899 // memd(Rx++#s4:3:circ(Mu))=Rtt
900 // memd(Rx++I:circ(Mu))=Rtt
902 // memd(Rx++Mu:brev)=Rtt
903 // memd(gp+#u16:3)=Rtt
905 // Store doubleword conditionally.
906 // if ([!]Pv[.new]) memd(#u6)=Rtt
907 // TODO: needs to be implemented.
909 //===----------------------------------------------------------------------===//
911 //===----------------------------------------------------------------------===//
912 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
914 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
915 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
916 mnemonic#"($Rs+#$offset)=#$S8",
917 [], "", V4LDST_tc_st_SLOT01>,
918 ImmRegRel, PredNewRel {
924 string OffsetOpStr = !cast<string>(OffsetOp);
925 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
926 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
927 /* u6_0Imm */ offset{5-0}));
931 let Inst{27-25} = 0b110;
932 let Inst{22-21} = MajOp;
933 let Inst{20-16} = Rs;
934 let Inst{12-7} = offsetBits;
935 let Inst{13} = S8{7};
936 let Inst{6-0} = S8{6-0};
939 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
941 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
942 bit isPredNot, bit isPredNew >
944 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
945 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
946 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
947 [], "", V4LDST_tc_st_SLOT01>,
948 ImmRegRel, PredNewRel {
955 string OffsetOpStr = !cast<string>(OffsetOp);
956 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
957 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
958 /* u6_0Imm */ offset{5-0}));
959 let isPredicatedNew = isPredNew;
960 let isPredicatedFalse = isPredNot;
964 let Inst{27-25} = 0b100;
965 let Inst{24} = isPredNew;
966 let Inst{23} = isPredNot;
967 let Inst{22-21} = MajOp;
968 let Inst{20-16} = Rs;
969 let Inst{13} = S6{5};
970 let Inst{12-7} = offsetBits;
972 let Inst{4-0} = S6{4-0};
976 //===----------------------------------------------------------------------===//
977 // multiclass for store instructions with base + immediate offset
978 // addressing mode and immediate stored value.
979 // mem[bhw](Rx++#s4:3)=#s8
980 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
981 //===----------------------------------------------------------------------===//
983 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
985 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
987 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
990 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
992 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
993 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
995 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
996 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1000 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1001 InputType = "imm", isCodeGenOnly = 0 in {
1002 let accessSize = ByteAccess in
1003 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1005 let accessSize = HalfWordAccess in
1006 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1008 let accessSize = WordAccess in
1009 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1012 let Predicates = [HasV4T], AddedComplexity = 10 in {
1013 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1014 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1016 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1017 u6_1ImmPred:$src2)),
1018 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1020 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1021 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1024 let AddedComplexity = 6 in
1025 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1026 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1029 // memb(Rx++#s4:0:circ(Mu))=Rt
1030 // memb(Rx++I:circ(Mu))=Rt
1032 // memb(Rx++Mu:brev)=Rt
1033 // memb(gp+#u16:0)=Rt
1037 // TODO: needs to be implemented
1038 // memh(Re=#U6)=Rt.H
1039 // memh(Rs+#s11:1)=Rt.H
1040 let AddedComplexity = 6 in
1041 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1042 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1045 // memh(Rs+Ru<<#u2)=Rt.H
1046 // TODO: needs to be implemented.
1048 // memh(Ru<<#u2+#U6)=Rt.H
1049 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1050 // memh(Rx++#s4:1:circ(Mu))=Rt
1051 // memh(Rx++I:circ(Mu))=Rt.H
1052 // memh(Rx++I:circ(Mu))=Rt
1053 // memh(Rx++Mu)=Rt.H
1055 // memh(Rx++Mu:brev)=Rt.H
1056 // memh(Rx++Mu:brev)=Rt
1057 // memh(gp+#u16:1)=Rt
1058 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1059 // if ([!]Pv[.new]) memh(#u6)=Rt
1062 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1063 // TODO: needs to be implemented.
1065 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1066 // TODO: Needs to be implemented.
1070 // TODO: Needs to be implemented.
1073 let hasSideEffects = 0 in
1074 def STriw_pred_V4 : STInst2<(outs),
1075 (ins MEMri:$addr, PredRegs:$src1),
1076 "Error; should not emit",
1080 let AddedComplexity = 6 in
1081 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1082 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1085 // memw(Rx++#s4:2)=Rt
1086 // memw(Rx++#s4:2:circ(Mu))=Rt
1087 // memw(Rx++I:circ(Mu))=Rt
1089 // memw(Rx++Mu:brev)=Rt
1091 //===----------------------------------------------------------------------===
1093 //===----------------------------------------------------------------------===
1096 //===----------------------------------------------------------------------===//
1098 //===----------------------------------------------------------------------===//
1100 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1101 class T_store_io_nv <string mnemonic, RegisterClass RC,
1102 Operand ImmOp, bits<2>MajOp>
1103 : NVInst_V4 <(outs),
1104 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1105 mnemonic#"($src1+#$src2) = $src3.new",
1106 [],"",ST_tc_st_SLOT0> {
1108 bits<13> src2; // Actual address offset
1110 bits<11> offsetBits; // Represents offset encoding
1112 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1113 !if (!eq(mnemonic, "memh"), 12,
1114 !if (!eq(mnemonic, "memw"), 13, 0)));
1116 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1117 !if (!eq(mnemonic, "memh"), 1,
1118 !if (!eq(mnemonic, "memw"), 2, 0)));
1120 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1121 !if (!eq(mnemonic, "memh"), src2{11-1},
1122 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1124 let IClass = 0b1010;
1127 let Inst{26-25} = offsetBits{10-9};
1128 let Inst{24-21} = 0b1101;
1129 let Inst{20-16} = src1;
1130 let Inst{13} = offsetBits{8};
1131 let Inst{12-11} = MajOp;
1132 let Inst{10-8} = src3;
1133 let Inst{7-0} = offsetBits{7-0};
1136 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1137 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1138 bits<2>MajOp, bit PredNot, bit isPredNew>
1139 : NVInst_V4 <(outs),
1140 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1141 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1142 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1143 [],"",V2LDST_tc_st_SLOT0> {
1148 bits<6> offsetBits; // Represents offset encoding
1150 let isPredicatedNew = isPredNew;
1151 let isPredicatedFalse = PredNot;
1152 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1153 !if (!eq(mnemonic, "memh"), 7,
1154 !if (!eq(mnemonic, "memw"), 8, 0)));
1156 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1157 !if (!eq(mnemonic, "memh"), 1,
1158 !if (!eq(mnemonic, "memw"), 2, 0)));
1160 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1161 !if (!eq(mnemonic, "memh"), src3{6-1},
1162 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1164 let IClass = 0b0100;
1167 let Inst{26} = PredNot;
1168 let Inst{25} = isPredNew;
1169 let Inst{24-21} = 0b0101;
1170 let Inst{20-16} = src2;
1171 let Inst{13} = offsetBits{5};
1172 let Inst{12-11} = MajOp;
1173 let Inst{10-8} = src4;
1174 let Inst{7-3} = offsetBits{4-0};
1176 let Inst{1-0} = src1;
1179 // multiclass for new-value store instructions with base + immediate offset.
1181 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1183 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1184 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1186 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1187 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1189 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1190 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1192 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1194 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1199 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1200 let accessSize = ByteAccess in
1201 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1202 u6_0Ext, 0b00>, AddrModeRel;
1204 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1205 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1206 u6_1Ext, 0b01>, AddrModeRel;
1208 let accessSize = WordAccess, opExtentAlign = 2 in
1209 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1210 u6_2Ext, 0b10>, AddrModeRel;
1213 //===----------------------------------------------------------------------===//
1214 // Template class for non-predicated post increment .new stores
1215 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1216 //===----------------------------------------------------------------------===//
1217 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1218 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1219 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1220 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1221 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1222 mnemonic#"($src1++#$offset) = $src2.new",
1223 [], "$src1 = $_dst_">,
1230 string ImmOpStr = !cast<string>(ImmOp);
1231 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1232 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1233 /* s4_0Imm */ offset{3-0}));
1234 let IClass = 0b1010;
1236 let Inst{27-21} = 0b1011101;
1237 let Inst{20-16} = src1;
1239 let Inst{12-11} = MajOp;
1240 let Inst{10-8} = src2;
1242 let Inst{6-3} = offsetBits;
1246 //===----------------------------------------------------------------------===//
1247 // Template class for predicated post increment .new stores
1248 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1249 //===----------------------------------------------------------------------===//
1250 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1251 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1252 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1253 bits<2> MajOp, bit isPredNot, bit isPredNew >
1254 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1255 (ins PredRegs:$src1, IntRegs:$src2,
1256 ImmOp:$offset, IntRegs:$src3),
1257 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1258 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1259 [], "$src2 = $_dst_">,
1267 string ImmOpStr = !cast<string>(ImmOp);
1268 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1269 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1270 /* s4_0Imm */ offset{3-0}));
1271 let isPredicatedNew = isPredNew;
1272 let isPredicatedFalse = isPredNot;
1274 let IClass = 0b1010;
1276 let Inst{27-21} = 0b1011101;
1277 let Inst{20-16} = src2;
1279 let Inst{12-11} = MajOp;
1280 let Inst{10-8} = src3;
1281 let Inst{7} = isPredNew;
1282 let Inst{6-3} = offsetBits;
1283 let Inst{2} = isPredNot;
1284 let Inst{1-0} = src1;
1287 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1288 bits<2> MajOp, bit PredNot> {
1289 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1292 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1295 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1297 let BaseOpcode = "POST_"#BaseOp in {
1298 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1301 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1302 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1306 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1307 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1309 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1310 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1312 let accessSize = WordAccess, isCodeGenOnly = 0 in
1313 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1315 //===----------------------------------------------------------------------===//
1316 // Template class for post increment .new stores with register offset
1317 //===----------------------------------------------------------------------===//
1318 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1319 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1320 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1321 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1322 #mnemonic#"($src1++$src2) = $src3.new",
1323 [], "$src1 = $_dst_"> {
1327 let accessSize = AccessSz;
1329 let IClass = 0b1010;
1331 let Inst{27-21} = 0b1101101;
1332 let Inst{20-16} = src1;
1333 let Inst{13} = src2;
1334 let Inst{12-11} = MajOp;
1335 let Inst{10-8} = src3;
1339 let isCodeGenOnly = 0 in {
1340 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1341 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1342 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1345 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1346 // memb(Rx++I:circ(Mu))=Nt.new
1347 // memb(Rx++Mu)=Nt.new
1348 // memb(Rx++Mu:brev)=Nt.new
1349 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1350 // memh(Rx++I:circ(Mu))=Nt.new
1351 // memh(Rx++Mu)=Nt.new
1352 // memh(Rx++Mu:brev)=Nt.new
1354 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1355 // memw(Rx++I:circ(Mu))=Nt.new
1356 // memw(Rx++Mu)=Nt.new
1357 // memw(Rx++Mu:brev)=Nt.new
1359 //===----------------------------------------------------------------------===//
1361 //===----------------------------------------------------------------------===//
1363 //===----------------------------------------------------------------------===//
1365 //===----------------------------------------------------------------------===//
1367 //===----------------------------------------------------------------------===//
1368 // multiclass/template class for the new-value compare jumps with the register
1370 //===----------------------------------------------------------------------===//
1372 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
1373 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1374 bit isNegCond, bit isTak>
1376 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1377 "if ("#!if(isNegCond, "!","")#mnemonic#
1378 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1379 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1380 #!if(isTak, "t","nt")#" $offset",
1381 []>, Requires<[HasV4T]> {
1385 bits<3> Ns; // New-Value Operand
1386 bits<5> RegOp; // Non-New-Value Operand
1389 let isTaken = isTak;
1390 let isBrTaken = !if(isTaken, "true", "false");
1391 let isPredicatedFalse = isNegCond;
1393 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1394 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1396 let IClass = 0b0010;
1398 let Inst{25-23} = majOp;
1399 let Inst{22} = isNegCond;
1400 let Inst{18-16} = Ns;
1401 let Inst{13} = isTak;
1402 let Inst{12-8} = RegOp;
1403 let Inst{21-20} = offset{10-9};
1404 let Inst{7-1} = offset{8-2};
1408 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1410 // Branch not taken:
1411 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1413 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1416 // NvOpNum = 0 -> First Operand is a new-value Register
1417 // NvOpNum = 1 -> Second Operand is a new-value Register
1419 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1421 let BaseOpcode = BaseOp#_NVJ in {
1422 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1423 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1427 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1428 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1429 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1430 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1431 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1433 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1434 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
1435 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1436 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1437 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1438 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1439 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1442 //===----------------------------------------------------------------------===//
1443 // multiclass/template class for the new-value compare jumps instruction
1444 // with a register and an unsigned immediate (U5) operand.
1445 //===----------------------------------------------------------------------===//
1447 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
1448 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1451 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1452 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1453 #!if(isTak, "t","nt")#" $offset",
1454 []>, Requires<[HasV4T]> {
1456 let isTaken = isTak;
1457 let isPredicatedFalse = isNegCond;
1458 let isBrTaken = !if(isTaken, "true", "false");
1464 let IClass = 0b0010;
1466 let Inst{25-23} = majOp;
1467 let Inst{22} = isNegCond;
1468 let Inst{18-16} = src1;
1469 let Inst{13} = isTak;
1470 let Inst{12-8} = src2;
1471 let Inst{21-20} = offset{10-9};
1472 let Inst{7-1} = offset{8-2};
1475 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1476 // Branch not taken:
1477 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1479 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1482 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1483 let BaseOpcode = BaseOp#_NVJri in {
1484 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1485 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1489 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1490 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1491 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1493 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1494 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
1495 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1496 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1497 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1500 //===----------------------------------------------------------------------===//
1501 // multiclass/template class for the new-value compare jumps instruction
1502 // with a register and an hardcoded 0/-1 immediate value.
1503 //===----------------------------------------------------------------------===//
1505 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
1506 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1507 bit isNegCond, bit isTak>
1509 (ins IntRegs:$src1, brtarget:$offset),
1510 "if ("#!if(isNegCond, "!","")#mnemonic
1511 #"($src1.new, #"#ImmVal#")) jump:"
1512 #!if(isTak, "t","nt")#" $offset",
1513 []>, Requires<[HasV4T]> {
1515 let isTaken = isTak;
1516 let isPredicatedFalse = isNegCond;
1517 let isBrTaken = !if(isTaken, "true", "false");
1521 let IClass = 0b0010;
1523 let Inst{25-23} = majOp;
1524 let Inst{22} = isNegCond;
1525 let Inst{18-16} = src1;
1526 let Inst{13} = isTak;
1527 let Inst{21-20} = offset{10-9};
1528 let Inst{7-1} = offset{8-2};
1531 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1533 // Branch not taken:
1534 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1536 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1539 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1541 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1542 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True cond
1543 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False Cond
1547 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1548 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1549 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1551 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1552 Defs = [PC], hasSideEffects = 0 in {
1553 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1554 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1555 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1558 //===----------------------------------------------------------------------===//
1560 //===----------------------------------------------------------------------===//
1562 // Add and accumulate.
1563 // Rd=add(Rs,add(Ru,#s6))
1564 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
1565 validSubTargets = HasV4SubT in
1566 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
1567 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1568 "$dst = add($src1, add($src2, #$src3))",
1569 [(set (i32 IntRegs:$dst),
1570 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1571 s6_16ExtPred:$src3)))]>,
1574 // Rd=add(Rs,sub(#s6,Ru))
1575 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1576 validSubTargets = HasV4SubT in
1577 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
1578 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1579 "$dst = add($src1, sub(#$src2, $src3))",
1580 [(set (i32 IntRegs:$dst),
1581 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1582 (i32 IntRegs:$src3))))]>,
1585 // Generates the same instruction as ADDr_SUBri_V4 but matches different
1587 // Rd=add(Rs,sub(#s6,Ru))
1588 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1589 validSubTargets = HasV4SubT in
1590 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
1591 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1592 "$dst = add($src1, sub(#$src2, $src3))",
1593 [(set (i32 IntRegs:$dst),
1594 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1595 (i32 IntRegs:$src3)))]>,
1599 // Add or subtract doublewords with carry.
1601 // Rdd=add(Rss,Rtt,Px):carry
1603 // Rdd=sub(Rss,Rtt,Px):carry
1606 // Logical doublewords.
1607 // Rdd=and(Rtt,~Rss)
1608 let validSubTargets = HasV4SubT in
1609 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1610 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1611 "$dst = and($src1, ~$src2)",
1612 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1613 (not (i64 DoubleRegs:$src2))))]>,
1617 let validSubTargets = HasV4SubT in
1618 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1619 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1620 "$dst = or($src1, ~$src2)",
1621 [(set (i64 DoubleRegs:$dst),
1622 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
1626 // Logical-logical doublewords.
1627 // Rxx^=xor(Rss,Rtt)
1628 let validSubTargets = HasV4SubT in
1629 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
1630 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1631 "$dst ^= xor($src2, $src3)",
1632 [(set (i64 DoubleRegs:$dst),
1633 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
1634 (i64 DoubleRegs:$src3))))],
1639 // Logical-logical words.
1640 // Rx=or(Ru,and(Rx,#s10))
1641 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1642 validSubTargets = HasV4SubT in
1643 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
1644 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1645 "$dst = or($src1, and($src2, #$src3))",
1646 [(set (i32 IntRegs:$dst),
1647 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1648 s10ExtPred:$src3)))],
1652 // Rx[&|^]=and(Rs,Rt)
1654 let validSubTargets = HasV4SubT in
1655 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1656 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1657 "$dst &= and($src2, $src3)",
1658 [(set (i32 IntRegs:$dst),
1659 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1660 (i32 IntRegs:$src3))))],
1665 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
1666 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1667 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1668 "$dst |= and($src2, $src3)",
1669 [(set (i32 IntRegs:$dst),
1670 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1671 (i32 IntRegs:$src3))))],
1673 Requires<[HasV4T]>, ImmRegRel;
1676 let validSubTargets = HasV4SubT in
1677 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1678 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1679 "$dst ^= and($src2, $src3)",
1680 [(set (i32 IntRegs:$dst),
1681 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1682 (i32 IntRegs:$src3))))],
1686 // Rx[&|^]=and(Rs,~Rt)
1688 let validSubTargets = HasV4SubT in
1689 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1690 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1691 "$dst &= and($src2, ~$src3)",
1692 [(set (i32 IntRegs:$dst),
1693 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1694 (not (i32 IntRegs:$src3)))))],
1699 let validSubTargets = HasV4SubT in
1700 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1701 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1702 "$dst |= and($src2, ~$src3)",
1703 [(set (i32 IntRegs:$dst),
1704 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1705 (not (i32 IntRegs:$src3)))))],
1710 let validSubTargets = HasV4SubT in
1711 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1712 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1713 "$dst ^= and($src2, ~$src3)",
1714 [(set (i32 IntRegs:$dst),
1715 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1716 (not (i32 IntRegs:$src3)))))],
1720 // Rx[&|^]=or(Rs,Rt)
1722 let validSubTargets = HasV4SubT in
1723 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1724 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1725 "$dst &= or($src2, $src3)",
1726 [(set (i32 IntRegs:$dst),
1727 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1728 (i32 IntRegs:$src3))))],
1733 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
1734 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1735 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1736 "$dst |= or($src2, $src3)",
1737 [(set (i32 IntRegs:$dst),
1738 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1739 (i32 IntRegs:$src3))))],
1741 Requires<[HasV4T]>, ImmRegRel;
1744 let validSubTargets = HasV4SubT in
1745 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1746 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1747 "$dst ^= or($src2, $src3)",
1748 [(set (i32 IntRegs:$dst),
1749 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1750 (i32 IntRegs:$src3))))],
1754 // Rx[&|^]=xor(Rs,Rt)
1756 let validSubTargets = HasV4SubT in
1757 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1758 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1759 "$dst &= xor($src2, $src3)",
1760 [(set (i32 IntRegs:$dst),
1761 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1762 (i32 IntRegs:$src3))))],
1767 let validSubTargets = HasV4SubT in
1768 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1769 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1770 "$dst |= xor($src2, $src3)",
1771 [(set (i32 IntRegs:$dst),
1772 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1773 (i32 IntRegs:$src3))))],
1778 let validSubTargets = HasV4SubT in
1779 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1780 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1781 "$dst ^= xor($src2, $src3)",
1782 [(set (i32 IntRegs:$dst),
1783 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1784 (i32 IntRegs:$src3))))],
1789 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1790 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
1791 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
1792 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1793 "$dst |= and($src2, #$src3)",
1794 [(set (i32 IntRegs:$dst),
1795 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1796 s10ExtPred:$src3)))],
1798 Requires<[HasV4T]>, ImmRegRel;
1801 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1802 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
1803 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
1804 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1805 "$dst |= or($src2, #$src3)",
1806 [(set (i32 IntRegs:$dst),
1807 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1808 s10ExtPred:$src3)))],
1810 Requires<[HasV4T]>, ImmRegRel;
1814 // Rd=modwrap(Rs,Rt)
1816 // Rd=cround(Rs,#u5)
1818 // Rd=round(Rs,#u5)[:sat]
1819 // Rd=round(Rs,Rt)[:sat]
1820 // Vector reduce add unsigned halfwords
1821 // Rd=vraddh(Rss,Rtt)
1823 // Rdd=vaddb(Rss,Rtt)
1824 // Vector conditional negate
1825 // Rdd=vcnegh(Rss,Rt)
1826 // Rxx+=vrcnegh(Rss,Rt)
1827 // Vector maximum bytes
1828 // Rdd=vmaxb(Rtt,Rss)
1829 // Vector reduce maximum halfwords
1830 // Rxx=vrmaxh(Rss,Ru)
1831 // Rxx=vrmaxuh(Rss,Ru)
1832 // Vector reduce maximum words
1833 // Rxx=vrmaxuw(Rss,Ru)
1834 // Rxx=vrmaxw(Rss,Ru)
1835 // Vector minimum bytes
1836 // Rdd=vminb(Rtt,Rss)
1837 // Vector reduce minimum halfwords
1838 // Rxx=vrminh(Rss,Ru)
1839 // Rxx=vrminuh(Rss,Ru)
1840 // Vector reduce minimum words
1841 // Rxx=vrminuw(Rss,Ru)
1842 // Rxx=vrminw(Rss,Ru)
1843 // Vector subtract bytes
1844 // Rdd=vsubb(Rss,Rtt)
1846 //===----------------------------------------------------------------------===//
1848 //===----------------------------------------------------------------------===//
1851 //===----------------------------------------------------------------------===//
1853 //===----------------------------------------------------------------------===//
1855 // Multiply and user lower result.
1856 // Rd=add(#u6,mpyi(Rs,#U6))
1857 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1858 validSubTargets = HasV4SubT in
1859 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
1860 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1861 "$dst = add(#$src1, mpyi($src2, #$src3))",
1862 [(set (i32 IntRegs:$dst),
1863 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1864 u6ExtPred:$src1))]>,
1867 // Rd=add(##,mpyi(Rs,#U6))
1868 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1869 (HexagonCONST32 tglobaladdr:$src1)),
1870 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
1873 // Rd=add(#u6,mpyi(Rs,Rt))
1874 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1875 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1876 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
1877 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1878 "$dst = add(#$src1, mpyi($src2, $src3))",
1879 [(set (i32 IntRegs:$dst),
1880 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1881 u6ExtPred:$src1))]>,
1882 Requires<[HasV4T]>, ImmRegRel;
1884 // Rd=add(##,mpyi(Rs,Rt))
1885 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1886 (HexagonCONST32 tglobaladdr:$src1)),
1887 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
1890 // Rd=add(Ru,mpyi(#u6:2,Rs))
1891 let validSubTargets = HasV4SubT in
1892 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
1893 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1894 "$dst = add($src1, mpyi(#$src2, $src3))",
1895 [(set (i32 IntRegs:$dst),
1896 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1897 u6_2ImmPred:$src2)))]>,
1900 // Rd=add(Ru,mpyi(Rs,#u6))
1901 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
1902 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1903 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
1904 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1905 "$dst = add($src1, mpyi($src2, #$src3))",
1906 [(set (i32 IntRegs:$dst),
1907 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1908 u6ExtPred:$src3)))]>,
1909 Requires<[HasV4T]>, ImmRegRel;
1911 // Rx=add(Ru,mpyi(Rx,Rs))
1912 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
1913 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
1914 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1915 "$dst = add($src1, mpyi($src2, $src3))",
1916 [(set (i32 IntRegs:$dst),
1917 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1918 (i32 IntRegs:$src3))))],
1920 Requires<[HasV4T]>, ImmRegRel;
1923 // Polynomial multiply words
1925 // Rxx^=pmpyw(Rs,Rt)
1927 // Vector reduce multiply word by signed half (32x16)
1928 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
1929 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
1930 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
1931 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
1933 // Multiply and use upper result
1934 // Rd=mpy(Rs,Rt.H):<<1:sat
1935 // Rd=mpy(Rs,Rt.L):<<1:sat
1936 // Rd=mpy(Rs,Rt):<<1
1937 // Rd=mpy(Rs,Rt):<<1:sat
1939 // Rx+=mpy(Rs,Rt):<<1:sat
1940 // Rx-=mpy(Rs,Rt):<<1:sat
1942 // Vector multiply bytes
1943 // Rdd=vmpybsu(Rs,Rt)
1944 // Rdd=vmpybu(Rs,Rt)
1945 // Rxx+=vmpybsu(Rs,Rt)
1946 // Rxx+=vmpybu(Rs,Rt)
1948 // Vector polynomial multiply halfwords
1949 // Rdd=vpmpyh(Rs,Rt)
1950 // Rxx^=vpmpyh(Rs,Rt)
1952 //===----------------------------------------------------------------------===//
1954 //===----------------------------------------------------------------------===//
1957 //===----------------------------------------------------------------------===//
1959 //===----------------------------------------------------------------------===//
1961 // Shift by immediate and accumulate.
1962 // Rx=add(#u8,asl(Rx,#U5))
1963 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1964 validSubTargets = HasV4SubT in
1965 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1966 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1967 "$dst = add(#$src1, asl($src2, #$src3))",
1968 [(set (i32 IntRegs:$dst),
1969 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1974 // Rx=add(#u8,lsr(Rx,#U5))
1975 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1976 validSubTargets = HasV4SubT in
1977 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1978 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1979 "$dst = add(#$src1, lsr($src2, #$src3))",
1980 [(set (i32 IntRegs:$dst),
1981 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1986 // Rx=sub(#u8,asl(Rx,#U5))
1987 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1988 validSubTargets = HasV4SubT in
1989 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1990 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1991 "$dst = sub(#$src1, asl($src2, #$src3))",
1992 [(set (i32 IntRegs:$dst),
1993 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1998 // Rx=sub(#u8,lsr(Rx,#U5))
1999 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2000 validSubTargets = HasV4SubT in
2001 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2002 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2003 "$dst = sub(#$src1, lsr($src2, #$src3))",
2004 [(set (i32 IntRegs:$dst),
2005 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2011 //Shift by immediate and logical.
2012 //Rx=and(#u8,asl(Rx,#U5))
2013 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2014 validSubTargets = HasV4SubT in
2015 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2016 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2017 "$dst = and(#$src1, asl($src2, #$src3))",
2018 [(set (i32 IntRegs:$dst),
2019 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2024 //Rx=and(#u8,lsr(Rx,#U5))
2025 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2026 validSubTargets = HasV4SubT in
2027 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2028 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2029 "$dst = and(#$src1, lsr($src2, #$src3))",
2030 [(set (i32 IntRegs:$dst),
2031 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2036 //Rx=or(#u8,asl(Rx,#U5))
2037 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2038 AddedComplexity = 30, validSubTargets = HasV4SubT in
2039 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2040 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2041 "$dst = or(#$src1, asl($src2, #$src3))",
2042 [(set (i32 IntRegs:$dst),
2043 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2048 //Rx=or(#u8,lsr(Rx,#U5))
2049 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2050 AddedComplexity = 30, validSubTargets = HasV4SubT in
2051 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2052 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2053 "$dst = or(#$src1, lsr($src2, #$src3))",
2054 [(set (i32 IntRegs:$dst),
2055 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2061 //Shift by register.
2063 let validSubTargets = HasV4SubT in {
2064 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
2065 "$dst = lsl(#$src1, $src2)",
2066 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
2067 (i32 IntRegs:$src2)))]>,
2071 //Shift by register and logical.
2073 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2074 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2075 "$dst ^= asl($src2, $src3)",
2076 [(set (i64 DoubleRegs:$dst),
2077 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
2078 (i32 IntRegs:$src3))))],
2083 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2084 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2085 "$dst ^= asr($src2, $src3)",
2086 [(set (i64 DoubleRegs:$dst),
2087 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
2088 (i32 IntRegs:$src3))))],
2093 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2094 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2095 "$dst ^= lsl($src2, $src3)",
2096 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
2097 (shl (i64 DoubleRegs:$src2),
2098 (i32 IntRegs:$src3))))],
2103 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2104 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2105 "$dst ^= lsr($src2, $src3)",
2106 [(set (i64 DoubleRegs:$dst),
2107 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
2108 (i32 IntRegs:$src3))))],
2113 //===----------------------------------------------------------------------===//
2115 //===----------------------------------------------------------------------===//
2117 //===----------------------------------------------------------------------===//
2118 // MEMOP: Word, Half, Byte
2119 //===----------------------------------------------------------------------===//
2121 def MEMOPIMM : SDNodeXForm<imm, [{
2122 // Call the transformation function XformM5ToU5Imm to get the negative
2123 // immediate's positive counterpart.
2124 int32_t imm = N->getSExtValue();
2125 return XformM5ToU5Imm(imm);
2128 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2129 // -1 .. -31 represented as 65535..65515
2130 // assigning to a short restores our desired signed value.
2131 // Call the transformation function XformM5ToU5Imm to get the negative
2132 // immediate's positive counterpart.
2133 int16_t imm = N->getSExtValue();
2134 return XformM5ToU5Imm(imm);
2137 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2138 // -1 .. -31 represented as 255..235
2139 // assigning to a char restores our desired signed value.
2140 // Call the transformation function XformM5ToU5Imm to get the negative
2141 // immediate's positive counterpart.
2142 int8_t imm = N->getSExtValue();
2143 return XformM5ToU5Imm(imm);
2146 def SETMEMIMM : SDNodeXForm<imm, [{
2147 // Return the bit position we will set [0-31].
2149 int32_t imm = N->getSExtValue();
2150 return XformMskToBitPosU5Imm(imm);
2153 def CLRMEMIMM : SDNodeXForm<imm, [{
2154 // Return the bit position we will clear [0-31].
2156 // we bit negate the value first
2157 int32_t imm = ~(N->getSExtValue());
2158 return XformMskToBitPosU5Imm(imm);
2161 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2162 // Return the bit position we will set [0-15].
2164 int16_t imm = N->getSExtValue();
2165 return XformMskToBitPosU4Imm(imm);
2168 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2169 // Return the bit position we will clear [0-15].
2171 // we bit negate the value first
2172 int16_t imm = ~(N->getSExtValue());
2173 return XformMskToBitPosU4Imm(imm);
2176 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2177 // Return the bit position we will set [0-7].
2179 int8_t imm = N->getSExtValue();
2180 return XformMskToBitPosU3Imm(imm);
2183 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2184 // Return the bit position we will clear [0-7].
2186 // we bit negate the value first
2187 int8_t imm = ~(N->getSExtValue());
2188 return XformMskToBitPosU3Imm(imm);
2191 //===----------------------------------------------------------------------===//
2192 // Template class for MemOp instructions with the register value.
2193 //===----------------------------------------------------------------------===//
2194 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2195 string memOp, bits<2> memOpBits> :
2197 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2198 opc#"($base+#$offset)"#memOp#"$delta",
2200 Requires<[HasV4T, UseMEMOP]> {
2205 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2207 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2208 !if (!eq(opcBits, 0b01), offset{6-1},
2209 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2211 let IClass = 0b0011;
2212 let Inst{27-24} = 0b1110;
2213 let Inst{22-21} = opcBits;
2214 let Inst{20-16} = base;
2216 let Inst{12-7} = offsetBits;
2217 let Inst{6-5} = memOpBits;
2218 let Inst{4-0} = delta;
2221 //===----------------------------------------------------------------------===//
2222 // Template class for MemOp instructions with the immediate value.
2223 //===----------------------------------------------------------------------===//
2224 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2225 string memOp, bits<2> memOpBits> :
2227 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2228 opc#"($base+#$offset)"#memOp#"#$delta"
2229 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2231 Requires<[HasV4T, UseMEMOP]> {
2236 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2238 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2239 !if (!eq(opcBits, 0b01), offset{6-1},
2240 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2242 let IClass = 0b0011;
2243 let Inst{27-24} = 0b1111;
2244 let Inst{22-21} = opcBits;
2245 let Inst{20-16} = base;
2247 let Inst{12-7} = offsetBits;
2248 let Inst{6-5} = memOpBits;
2249 let Inst{4-0} = delta;
2252 // multiclass to define MemOp instructions with register operand.
2253 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2254 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2255 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2256 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2257 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2260 // multiclass to define MemOp instructions with immediate Operand.
2261 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2262 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2263 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2264 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
2265 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
2268 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2269 defm r : MemOp_rr <opc, opcBits, ImmOp>;
2270 defm i : MemOp_ri <opc, opcBits, ImmOp>;
2273 // Define MemOp instructions.
2274 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2275 validSubTargets =HasV4SubT in {
2276 let opExtentBits = 6, accessSize = ByteAccess in
2277 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
2279 let opExtentBits = 7, accessSize = HalfWordAccess in
2280 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
2282 let opExtentBits = 8, accessSize = WordAccess in
2283 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
2286 //===----------------------------------------------------------------------===//
2287 // Multiclass to define 'Def Pats' for ALU operations on the memory
2288 // Here value used for the ALU operation is an immediate value.
2289 // mem[bh](Rs+#0) += #U5
2290 // mem[bh](Rs+#u6) += #U5
2291 //===----------------------------------------------------------------------===//
2293 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2294 InstHexagon MI, SDNode OpNode> {
2295 let AddedComplexity = 180 in
2296 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2298 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2300 let AddedComplexity = 190 in
2301 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2303 (add IntRegs:$base, ExtPred:$offset)),
2304 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2307 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2308 InstHexagon addMI, InstHexagon subMI> {
2309 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2310 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2313 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2315 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2316 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
2318 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2319 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
2322 let Predicates = [HasV4T, UseMEMOP] in {
2323 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2324 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2325 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2328 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
2332 //===----------------------------------------------------------------------===//
2333 // multiclass to define 'Def Pats' for ALU operations on the memory.
2334 // Here value used for the ALU operation is a negative value.
2335 // mem[bh](Rs+#0) += #m5
2336 // mem[bh](Rs+#u6) += #m5
2337 //===----------------------------------------------------------------------===//
2339 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2340 PatLeaf immPred, ComplexPattern addrPred,
2341 SDNodeXForm xformFunc, InstHexagon MI> {
2342 let AddedComplexity = 190 in
2343 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2345 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2347 let AddedComplexity = 195 in
2348 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2350 (add IntRegs:$base, extPred:$offset)),
2351 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2354 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2356 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2357 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
2359 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2360 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
2363 let Predicates = [HasV4T, UseMEMOP] in {
2364 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2365 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2366 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2369 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2370 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
2373 //===----------------------------------------------------------------------===//
2374 // Multiclass to define 'def Pats' for bit operations on the memory.
2375 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2376 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2377 //===----------------------------------------------------------------------===//
2379 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2380 PatLeaf extPred, ComplexPattern addrPred,
2381 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2383 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2384 let AddedComplexity = 250 in
2385 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2387 (add IntRegs:$base, extPred:$offset)),
2388 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2390 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2391 let AddedComplexity = 225 in
2392 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2394 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2395 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2398 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2400 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2401 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
2403 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2404 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
2405 // Half Word - clrbit
2406 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2407 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
2408 // Half Word - setbit
2409 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2410 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
2413 let Predicates = [HasV4T, UseMEMOP] in {
2414 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2415 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2416 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2417 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2418 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2420 // memw(Rs+#0) = [clrbit|setbit](#U5)
2421 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2422 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2423 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2424 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2425 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2428 //===----------------------------------------------------------------------===//
2429 // Multiclass to define 'def Pats' for ALU operations on the memory
2430 // where addend is a register.
2431 // mem[bhw](Rs+#0) [+-&|]= Rt
2432 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2433 //===----------------------------------------------------------------------===//
2435 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2436 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2437 let AddedComplexity = 141 in
2438 // mem[bhw](Rs+#0) [+-&|]= Rt
2439 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2440 (i32 IntRegs:$addend)),
2441 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2442 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2444 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2445 let AddedComplexity = 150 in
2446 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2447 (i32 IntRegs:$orend)),
2448 (add IntRegs:$base, extPred:$offset)),
2449 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2452 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2453 ComplexPattern addrPred, PatLeaf extPred,
2454 InstHexagon addMI, InstHexagon subMI,
2455 InstHexagon andMI, InstHexagon orMI > {
2457 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2458 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2459 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2460 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2463 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2465 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2466 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2467 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2469 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2470 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2471 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2474 // Define 'def Pats' for MemOps with register addend.
2475 let Predicates = [HasV4T, UseMEMOP] in {
2477 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2478 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2479 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2481 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2482 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2485 //===----------------------------------------------------------------------===//
2487 //===----------------------------------------------------------------------===//
2489 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2490 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2491 // hardware. However, compiler can still implement these patterns through
2492 // appropriate patterns combinations based on current implemented patterns.
2493 // The implemented patterns are: EQ/GT/GTU.
2494 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2496 // Following instruction is not being extended as it results into the
2497 // incorrect code for negative numbers.
2498 // Pd=cmpb.eq(Rs,#u8)
2500 let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0,
2501 validSubTargets = HasV4SubT in
2502 class CMP_NOT_REG_IMM<string OpName, bits<2> op, Operand ImmOp,
2504 : ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2),
2505 "$dst = !cmp."#OpName#"($src1, #$src2)",
2507 "", ALU32_2op_tc_2early_SLOT0123> {
2512 let IClass = 0b0111;
2513 let Inst{27-24} = 0b0101;
2514 let Inst{23-22} = op;
2515 let Inst{20-16} = src1;
2516 let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9});
2517 let Inst{13-5} = src2{8-0};
2518 let Inst{4-2} = 0b100;
2519 let Inst{1-0} = dst;
2522 let opExtentBits = 10, isExtentSigned = 1 in {
2523 def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst),
2524 (setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>;
2526 def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst),
2527 (not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>;
2530 let opExtentBits = 9 in
2531 def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
2532 (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
2537 let isCompare = 1, validSubTargets = HasV4SubT in
2538 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2539 (ins IntRegs:$src1, IntRegs:$src2),
2540 "$dst = !cmp.eq($src1, $src2)",
2541 [(set (i1 PredRegs:$dst),
2542 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2546 let isCompare = 1, validSubTargets = HasV4SubT in
2547 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2548 (ins IntRegs:$src1, IntRegs:$src2),
2549 "$dst = !cmp.gt($src1, $src2)",
2550 [(set (i1 PredRegs:$dst),
2551 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2555 // p=!cmp.gtu(r1,r2)
2556 let isCompare = 1, validSubTargets = HasV4SubT in
2557 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2558 (ins IntRegs:$src1, IntRegs:$src2),
2559 "$dst = !cmp.gtu($src1, $src2)",
2560 [(set (i1 PredRegs:$dst),
2561 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2564 let isCompare = 1, validSubTargets = HasV4SubT in
2565 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2566 (ins IntRegs:$src1, u8Imm:$src2),
2567 "$dst = cmpb.eq($src1, #$src2)",
2568 [(set (i1 PredRegs:$dst),
2569 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2572 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2574 (J2_jumpf (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2578 // Pd=cmpb.eq(Rs,Rt)
2579 let isCompare = 1, validSubTargets = HasV4SubT in
2580 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2581 (ins IntRegs:$src1, IntRegs:$src2),
2582 "$dst = cmpb.eq($src1, $src2)",
2583 [(set (i1 PredRegs:$dst),
2584 (seteq (and (xor (i32 IntRegs:$src1),
2585 (i32 IntRegs:$src2)), 255), 0))]>,
2588 // Pd=cmpb.eq(Rs,Rt)
2589 let isCompare = 1, validSubTargets = HasV4SubT in
2590 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2591 (ins IntRegs:$src1, IntRegs:$src2),
2592 "$dst = cmpb.eq($src1, $src2)",
2593 [(set (i1 PredRegs:$dst),
2594 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2595 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2598 // Pd=cmpb.gt(Rs,Rt)
2599 let isCompare = 1, validSubTargets = HasV4SubT in
2600 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2601 (ins IntRegs:$src1, IntRegs:$src2),
2602 "$dst = cmpb.gt($src1, $src2)",
2603 [(set (i1 PredRegs:$dst),
2604 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2605 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2608 // Pd=cmpb.gtu(Rs,#u7)
2609 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2610 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2611 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2612 (ins IntRegs:$src1, u7Ext:$src2),
2613 "$dst = cmpb.gtu($src1, #$src2)",
2614 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2615 u7ExtPred:$src2))]>,
2616 Requires<[HasV4T]>, ImmRegRel;
2618 // SDNode for converting immediate C to C-1.
2619 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2620 // Return the byte immediate const-1 as an SDNode.
2621 int32_t imm = N->getSExtValue();
2622 return XformU7ToU7M1Imm(imm);
2626 // zext( seteq ( and(Rs, 255), u8))
2628 // Pd=cmpb.eq(Rs, #u8)
2629 // if (Pd.new) Rd=#1
2630 // if (!Pd.new) Rd=#0
2631 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2633 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2639 // zext( setne ( and(Rs, 255), u8))
2641 // Pd=cmpb.eq(Rs, #u8)
2642 // if (Pd.new) Rd=#0
2643 // if (!Pd.new) Rd=#1
2644 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2646 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2652 // zext( seteq (Rs, and(Rt, 255)))
2654 // Pd=cmpb.eq(Rs, Rt)
2655 // if (Pd.new) Rd=#1
2656 // if (!Pd.new) Rd=#0
2657 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2658 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2659 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2660 (i32 IntRegs:$Rt))),
2665 // zext( setne (Rs, and(Rt, 255)))
2667 // Pd=cmpb.eq(Rs, Rt)
2668 // if (Pd.new) Rd=#0
2669 // if (!Pd.new) Rd=#1
2670 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2671 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2672 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2673 (i32 IntRegs:$Rt))),
2678 // zext( setugt ( and(Rs, 255), u8))
2680 // Pd=cmpb.gtu(Rs, #u8)
2681 // if (Pd.new) Rd=#1
2682 // if (!Pd.new) Rd=#0
2683 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2685 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2691 // zext( setugt ( and(Rs, 254), u8))
2693 // Pd=cmpb.gtu(Rs, #u8)
2694 // if (Pd.new) Rd=#1
2695 // if (!Pd.new) Rd=#0
2696 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2698 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2704 // zext( setult ( Rs, Rt))
2706 // Pd=cmp.ltu(Rs, Rt)
2707 // if (Pd.new) Rd=#1
2708 // if (!Pd.new) Rd=#0
2709 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2710 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2711 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2712 (i32 IntRegs:$Rs))),
2717 // zext( setlt ( Rs, Rt))
2719 // Pd=cmp.lt(Rs, Rt)
2720 // if (Pd.new) Rd=#1
2721 // if (!Pd.new) Rd=#0
2722 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2723 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2724 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2725 (i32 IntRegs:$Rs))),
2730 // zext( setugt ( Rs, Rt))
2732 // Pd=cmp.gtu(Rs, Rt)
2733 // if (Pd.new) Rd=#1
2734 // if (!Pd.new) Rd=#0
2735 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2736 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2737 (i32 IntRegs:$Rt))),
2741 // This pattern interefers with coremark performance, not implementing at this
2744 // zext( setgt ( Rs, Rt))
2746 // Pd=cmp.gt(Rs, Rt)
2747 // if (Pd.new) Rd=#1
2748 // if (!Pd.new) Rd=#0
2751 // zext( setuge ( Rs, Rt))
2753 // Pd=cmp.ltu(Rs, Rt)
2754 // if (Pd.new) Rd=#0
2755 // if (!Pd.new) Rd=#1
2756 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2757 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2758 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2759 (i32 IntRegs:$Rs))),
2764 // zext( setge ( Rs, Rt))
2766 // Pd=cmp.lt(Rs, Rt)
2767 // if (Pd.new) Rd=#0
2768 // if (!Pd.new) Rd=#1
2769 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2770 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2771 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2772 (i32 IntRegs:$Rs))),
2777 // zext( setule ( Rs, Rt))
2779 // Pd=cmp.gtu(Rs, Rt)
2780 // if (Pd.new) Rd=#0
2781 // if (!Pd.new) Rd=#1
2782 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2783 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2784 (i32 IntRegs:$Rt))),
2789 // zext( setle ( Rs, Rt))
2791 // Pd=cmp.gt(Rs, Rt)
2792 // if (Pd.new) Rd=#0
2793 // if (!Pd.new) Rd=#1
2794 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2795 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
2796 (i32 IntRegs:$Rt))),
2801 // zext( setult ( and(Rs, 255), u8))
2802 // Use the isdigit transformation below
2804 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
2805 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
2806 // The isdigit transformation relies on two 'clever' aspects:
2807 // 1) The data type is unsigned which allows us to eliminate a zero test after
2808 // biasing the expression by 48. We are depending on the representation of
2809 // the unsigned types, and semantics.
2810 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
2813 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
2814 // The code is transformed upstream of llvm into
2815 // retval = (c-48) < 10 ? 1 : 0;
2816 let AddedComplexity = 139 in
2817 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
2818 u7StrictPosImmPred:$src2)))),
2819 (i32 (C2_muxii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
2820 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
2824 // Pd=cmpb.gtu(Rs,Rt)
2825 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
2826 InputType = "reg" in
2827 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
2828 (ins IntRegs:$src1, IntRegs:$src2),
2829 "$dst = cmpb.gtu($src1, $src2)",
2830 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2831 (and (i32 IntRegs:$src2), 255)))]>,
2832 Requires<[HasV4T]>, ImmRegRel;
2834 // Following instruction is not being extended as it results into the incorrect
2835 // code for negative numbers.
2837 // Signed half compare(.eq) ri.
2838 // Pd=cmph.eq(Rs,#s8)
2839 let isCompare = 1, validSubTargets = HasV4SubT in
2840 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
2841 (ins IntRegs:$src1, s8Imm:$src2),
2842 "$dst = cmph.eq($src1, #$src2)",
2843 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
2844 s8ImmPred:$src2))]>,
2847 // Signed half compare(.eq) rr.
2848 // Case 1: xor + and, then compare:
2850 // r0=and(r0,#0xffff)
2852 // Pd=cmph.eq(Rs,Rt)
2853 let isCompare = 1, validSubTargets = HasV4SubT in
2854 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
2855 (ins IntRegs:$src1, IntRegs:$src2),
2856 "$dst = cmph.eq($src1, $src2)",
2857 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
2858 (i32 IntRegs:$src2)),
2862 // Signed half compare(.eq) rr.
2863 // Case 2: shift left 16 bits then compare:
2867 // Pd=cmph.eq(Rs,Rt)
2868 let isCompare = 1, validSubTargets = HasV4SubT in
2869 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
2870 (ins IntRegs:$src1, IntRegs:$src2),
2871 "$dst = cmph.eq($src1, $src2)",
2872 [(set (i1 PredRegs:$dst),
2873 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
2874 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2877 /* Incorrect Pattern -- immediate should be right shifted before being
2878 used in the cmph.gt instruction.
2879 // Signed half compare(.gt) ri.
2880 // Pd=cmph.gt(Rs,#s8)
2882 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
2883 isCompare = 1, validSubTargets = HasV4SubT in
2884 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
2885 (ins IntRegs:$src1, s8Ext:$src2),
2886 "$dst = cmph.gt($src1, #$src2)",
2887 [(set (i1 PredRegs:$dst),
2888 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2889 s8ExtPred:$src2))]>,
2893 // Signed half compare(.gt) rr.
2894 // Pd=cmph.gt(Rs,Rt)
2895 let isCompare = 1, validSubTargets = HasV4SubT in
2896 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
2897 (ins IntRegs:$src1, IntRegs:$src2),
2898 "$dst = cmph.gt($src1, $src2)",
2899 [(set (i1 PredRegs:$dst),
2900 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2901 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2904 // Unsigned half compare rr (.gtu).
2905 // Pd=cmph.gtu(Rs,Rt)
2906 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2907 InputType = "reg" in
2908 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
2909 (ins IntRegs:$src1, IntRegs:$src2),
2910 "$dst = cmph.gtu($src1, $src2)",
2911 [(set (i1 PredRegs:$dst),
2912 (setugt (and (i32 IntRegs:$src1), 65535),
2913 (and (i32 IntRegs:$src2), 65535)))]>,
2914 Requires<[HasV4T]>, ImmRegRel;
2916 // Unsigned half compare ri (.gtu).
2917 // Pd=cmph.gtu(Rs,#u7)
2918 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2919 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2920 InputType = "imm" in
2921 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
2922 (ins IntRegs:$src1, u7Ext:$src2),
2923 "$dst = cmph.gtu($src1, #$src2)",
2924 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
2925 u7ExtPred:$src2))]>,
2926 Requires<[HasV4T]>, ImmRegRel;
2928 let validSubTargets = HasV4SubT in
2929 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2930 "$dst = !tstbit($src1, $src2)",
2931 [(set (i1 PredRegs:$dst),
2932 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
2935 let validSubTargets = HasV4SubT in
2936 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2937 "$dst = !tstbit($src1, $src2)",
2938 [(set (i1 PredRegs:$dst),
2939 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
2942 //===----------------------------------------------------------------------===//
2944 //===----------------------------------------------------------------------===//
2946 //Deallocate frame and return.
2948 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
2949 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in {
2950 let validSubTargets = HasV4SubT in
2951 def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
2957 // Restore registers and dealloc return function call.
2958 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2959 Defs = [R29, R30, R31, PC] in {
2960 let validSubTargets = HasV4SubT in
2961 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
2962 (ins calltarget:$dst),
2968 // Restore registers and dealloc frame before a tail call.
2969 let isCall = 1, isBarrier = 1,
2970 Defs = [R29, R30, R31, PC] in {
2971 let validSubTargets = HasV4SubT in
2972 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
2973 (ins calltarget:$dst),
2979 // Save registers function call.
2980 let isCall = 1, isBarrier = 1,
2981 Uses = [R29, R31] in {
2982 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
2983 (ins calltarget:$dst),
2984 "call $dst // Save_calle_saved_registers",
2989 // if (Ps) dealloc_return
2990 let isReturn = 1, isTerminator = 1,
2991 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
2992 isPredicated = 1 in {
2993 let validSubTargets = HasV4SubT in
2994 def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
2995 (ins PredRegs:$src1),
2996 "if ($src1) dealloc_return",
3001 // if (!Ps) dealloc_return
3002 let isReturn = 1, isTerminator = 1,
3003 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3004 isPredicated = 1, isPredicatedFalse = 1 in {
3005 let validSubTargets = HasV4SubT in
3006 def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3007 "if (!$src1) dealloc_return",
3012 // if (Ps.new) dealloc_return:nt
3013 let isReturn = 1, isTerminator = 1,
3014 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3015 isPredicated = 1 in {
3016 let validSubTargets = HasV4SubT in
3017 def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3018 "if ($src1.new) dealloc_return:nt",
3023 // if (!Ps.new) dealloc_return:nt
3024 let isReturn = 1, isTerminator = 1,
3025 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3026 isPredicated = 1, isPredicatedFalse = 1 in {
3027 let validSubTargets = HasV4SubT in
3028 def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3029 "if (!$src1.new) dealloc_return:nt",
3034 // if (Ps.new) dealloc_return:t
3035 let isReturn = 1, isTerminator = 1,
3036 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3037 isPredicated = 1 in {
3038 let validSubTargets = HasV4SubT in
3039 def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3040 "if ($src1.new) dealloc_return:t",
3045 // if (!Ps.new) dealloc_return:nt
3046 let isReturn = 1, isTerminator = 1,
3047 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3048 isPredicated = 1, isPredicatedFalse = 1 in {
3049 let validSubTargets = HasV4SubT in
3050 def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3051 "if (!$src1.new) dealloc_return:t",
3056 // Load/Store with absolute addressing mode
3059 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3061 let isPredicatedNew = isPredNew in
3062 def NAME#_V4 : STInst2<(outs),
3063 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3064 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3065 ") ")#mnemonic#"(##$absaddr) = $src2",
3070 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3071 let isPredicatedFalse = PredNot in {
3072 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3074 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3078 let isNVStorable = 1, isExtended = 1, hasSideEffects = 0 in
3079 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3080 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3081 let opExtendable = 0, isPredicable = 1 in
3082 def NAME#_V4 : STInst2<(outs),
3083 (ins u0AlwaysExt:$absaddr, RC:$src),
3084 mnemonic#"(##$absaddr) = $src",
3088 let opExtendable = 1, isPredicated = 1 in {
3089 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
3090 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
3095 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
3097 let isPredicatedNew = isPredNew in
3098 def NAME#_nv_V4 : NVInst_V4<(outs),
3099 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3100 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3101 ") ")#mnemonic#"(##$absaddr) = $src2.new",
3106 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
3107 let isPredicatedFalse = PredNot in {
3108 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
3110 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
3114 let mayStore = 1, isNVStore = 1, isExtended = 1, hasSideEffects = 0 in
3115 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
3116 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3117 let opExtendable = 0, isPredicable = 1 in
3118 def NAME#_nv_V4 : NVInst_V4<(outs),
3119 (ins u0AlwaysExt:$absaddr, RC:$src),
3120 mnemonic#"(##$absaddr) = $src.new",
3124 let opExtendable = 1, isPredicated = 1 in {
3125 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3126 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3131 let addrMode = Absolute in {
3132 let accessSize = ByteAccess in
3133 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
3134 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
3136 let accessSize = HalfWordAccess in
3137 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
3138 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
3140 let accessSize = WordAccess in
3141 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
3142 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
3144 let accessSize = DoubleWordAccess, isNVStorable = 0 in
3145 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
3148 let Predicates = [HasV4T], AddedComplexity = 30 in {
3149 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3150 (HexagonCONST32 tglobaladdr:$absaddr)),
3151 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3153 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3154 (HexagonCONST32 tglobaladdr:$absaddr)),
3155 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3157 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3158 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3160 def : Pat<(store (i64 DoubleRegs:$src1),
3161 (HexagonCONST32 tglobaladdr:$absaddr)),
3162 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3165 //===----------------------------------------------------------------------===//
3166 // multiclass for store instructions with GP-relative addressing mode.
3167 // mem[bhwd](#global)=Rt
3168 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
3169 //===----------------------------------------------------------------------===//
3170 let mayStore = 1, isNVStorable = 1 in
3171 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3172 let BaseOpcode = BaseOp, isPredicable = 1 in
3173 def NAME#_V4 : STInst2<(outs),
3174 (ins globaladdress:$global, RC:$src),
3175 mnemonic#"(#$global) = $src",
3178 // When GP-relative instructions are predicated, their addressing mode is
3179 // changed to absolute and they are always constant extended.
3180 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3181 isPredicated = 1 in {
3182 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
3183 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
3187 let mayStore = 1, isNVStore = 1 in
3188 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
3189 let BaseOpcode = BaseOp, isPredicable = 1 in
3190 def NAME#_nv_V4 : NVInst_V4<(outs),
3191 (ins u0AlwaysExt:$global, RC:$src),
3192 mnemonic#"(#$global) = $src.new",
3196 // When GP-relative instructions are predicated, their addressing mode is
3197 // changed to absolute and they are always constant extended.
3198 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3199 isPredicated = 1 in {
3200 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3201 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3205 let validSubTargets = HasV4SubT, hasSideEffects = 0 in {
3206 let isNVStorable = 0 in
3207 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
3209 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
3210 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel;
3211 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
3212 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel;
3213 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
3214 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel;
3217 // 64 bit atomic store
3218 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3219 (i64 DoubleRegs:$src1)),
3220 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3223 // Map from store(globaladdress) -> memd(#foo)
3224 let AddedComplexity = 100 in
3225 def : Pat <(store (i64 DoubleRegs:$src1),
3226 (HexagonCONST32_GP tglobaladdr:$global)),
3227 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3229 // 8 bit atomic store
3230 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3231 (i32 IntRegs:$src1)),
3232 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3234 // Map from store(globaladdress) -> memb(#foo)
3235 let AddedComplexity = 100 in
3236 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3237 (HexagonCONST32_GP tglobaladdr:$global)),
3238 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3240 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3241 // to "r0 = 1; memw(#foo) = r0"
3242 let AddedComplexity = 100 in
3243 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3244 (STb_GP_V4 tglobaladdr:$global, (A2_tfrsi 1))>;
3246 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3247 (i32 IntRegs:$src1)),
3248 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3250 // Map from store(globaladdress) -> memh(#foo)
3251 let AddedComplexity = 100 in
3252 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3253 (HexagonCONST32_GP tglobaladdr:$global)),
3254 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3256 // 32 bit atomic store
3257 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3258 (i32 IntRegs:$src1)),
3259 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3261 // Map from store(globaladdress) -> memw(#foo)
3262 let AddedComplexity = 100 in
3263 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3264 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3266 //===----------------------------------------------------------------------===//
3267 // Multiclass for the load instructions with absolute addressing mode.
3268 //===----------------------------------------------------------------------===//
3269 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3271 let isPredicatedNew = isPredNew in
3272 def NAME : LDInst2<(outs RC:$dst),
3273 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
3274 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3275 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
3280 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3281 let isPredicatedFalse = PredNot in {
3282 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3284 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3288 let isExtended = 1, hasSideEffects = 0 in
3289 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3290 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3291 let opExtendable = 1, isPredicable = 1 in
3292 def NAME#_V4 : LDInst2<(outs RC:$dst),
3293 (ins u0AlwaysExt:$absaddr),
3294 "$dst = "#mnemonic#"(##$absaddr)",
3298 let opExtendable = 2, isPredicated = 1 in {
3299 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3300 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3305 let addrMode = Absolute in {
3306 let accessSize = ByteAccess in {
3307 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
3308 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
3310 let accessSize = HalfWordAccess in {
3311 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
3312 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
3314 let accessSize = WordAccess in
3315 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
3317 let accessSize = DoubleWordAccess in
3318 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
3321 let Predicates = [HasV4T], AddedComplexity = 30 in {
3322 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3323 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
3325 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3326 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
3328 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3329 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
3331 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3332 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
3334 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3335 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
3338 //===----------------------------------------------------------------------===//
3339 // multiclass for load instructions with GP-relative addressing mode.
3340 // Rx=mem[bhwd](##global)
3341 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3342 //===----------------------------------------------------------------------===//
3343 let hasSideEffects = 0, validSubTargets = HasV4SubT in
3344 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3345 let BaseOpcode = BaseOp in {
3346 let isPredicable = 1 in
3347 def NAME#_V4 : LDInst2<(outs RC:$dst),
3348 (ins globaladdress:$global),
3349 "$dst = "#mnemonic#"(#$global)",
3352 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
3353 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3354 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3359 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel;
3360 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel;
3361 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel;
3362 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel;
3363 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel;
3364 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel;
3366 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3367 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3369 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3370 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3372 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3373 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3375 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3376 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3378 // Map from load(globaladdress) -> memw(#foo + 0)
3379 let AddedComplexity = 100 in
3380 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3381 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3383 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3384 let AddedComplexity = 100 in
3385 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3386 (i1 (C2_tfrrp (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
3388 // When the Interprocedural Global Variable optimizer realizes that a certain
3389 // global variable takes only two constant values, it shrinks the global to
3390 // a boolean. Catch those loads here in the following 3 patterns.
3391 let AddedComplexity = 100 in
3392 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3393 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3395 let AddedComplexity = 100 in
3396 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3397 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3399 // Map from load(globaladdress) -> memb(#foo)
3400 let AddedComplexity = 100 in
3401 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3402 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3404 // Map from load(globaladdress) -> memb(#foo)
3405 let AddedComplexity = 100 in
3406 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3407 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3409 let AddedComplexity = 100 in
3410 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3411 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3413 // Map from load(globaladdress) -> memub(#foo)
3414 let AddedComplexity = 100 in
3415 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3416 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3418 // Map from load(globaladdress) -> memh(#foo)
3419 let AddedComplexity = 100 in
3420 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3421 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3423 // Map from load(globaladdress) -> memh(#foo)
3424 let AddedComplexity = 100 in
3425 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3426 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3428 // Map from load(globaladdress) -> memuh(#foo)
3429 let AddedComplexity = 100 in
3430 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3431 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3433 // Map from load(globaladdress) -> memw(#foo)
3434 let AddedComplexity = 100 in
3435 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3436 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3439 // Transfer global address into a register
3440 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3441 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3442 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3444 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3447 // Transfer a block address into a register
3448 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3449 (TFRI_V4 tblockaddress:$src1)>,
3452 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3453 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3454 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3455 (ins PredRegs:$src1, s16Ext:$src2),
3456 "if($src1) $dst = #$src2",
3460 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3461 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3462 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3463 (ins PredRegs:$src1, s16Ext:$src2),
3464 "if(!$src1) $dst = #$src2",
3468 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3469 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3470 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3471 (ins PredRegs:$src1, s16Ext:$src2),
3472 "if($src1.new) $dst = #$src2",
3476 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3477 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3478 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3479 (ins PredRegs:$src1, s16Ext:$src2),
3480 "if(!$src1.new) $dst = #$src2",
3484 let AddedComplexity = 50, Predicates = [HasV4T] in
3485 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3486 (TFRI_V4 tglobaladdr:$src1)>,
3490 // Load - Indirect with long offset: These instructions take global address
3492 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3493 validSubTargets = HasV4SubT in
3494 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3495 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3496 "$dst=memd($src1<<#$src2+##$offset)",
3497 [(set (i64 DoubleRegs:$dst),
3498 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3499 (HexagonCONST32 tglobaladdr:$offset))))]>,
3502 let AddedComplexity = 40 in
3503 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3504 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3505 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3506 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3507 !strconcat("$dst = ",
3508 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3510 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3511 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3515 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3516 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3517 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3518 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3519 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3520 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3521 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3523 let AddedComplexity = 40 in
3524 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3525 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3526 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3529 let AddedComplexity = 40 in
3530 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3531 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3532 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3535 let Predicates = [HasV4T], AddedComplexity = 30 in {
3536 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3537 (STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3539 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3540 (STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3542 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3543 (STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3546 let Predicates = [HasV4T], AddedComplexity = 30 in {
3547 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3548 (LDriw_abs_V4 u0AlwaysExtPred:$src)>;
3550 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3551 (LDrib_abs_V4 u0AlwaysExtPred:$src)>;
3553 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3554 (LDriub_abs_V4 u0AlwaysExtPred:$src)>;
3556 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3557 (LDrih_abs_V4 u0AlwaysExtPred:$src)>;
3559 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3560 (LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
3563 // Indexed store word - global address.
3564 // memw(Rs+#u6:2)=#S8
3565 let AddedComplexity = 10 in
3566 def STriw_offset_ext_V4 : STInst<(outs),
3567 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3568 "memw($src1+#$src2) = ##$src3",
3569 [(store (HexagonCONST32 tglobaladdr:$src3),
3570 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3573 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3574 (i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
3577 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3578 (i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
3583 // We need a complexity of 120 here to override preceding handling of
3585 let Predicates = [HasV4T], AddedComplexity = 120 in {
3586 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3587 (i64 (A4_combineir 0, (LDrib_abs_V4 tglobaladdr:$addr)))>;
3589 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3590 (i64 (A4_combineir 0, (LDriub_abs_V4 tglobaladdr:$addr)))>;
3592 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3593 (i64 (A2_sxtw (LDrib_abs_V4 tglobaladdr:$addr)))>;
3595 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3596 (i64 (A4_combineir 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3598 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3599 (i64 (A4_combineir 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>;
3601 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3602 (i64 (A2_sxtw (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3605 // We need a complexity of 120 here to override preceding handling of
3607 let AddedComplexity = 120 in {
3608 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3609 (i64 (A4_combineir 0, (LDrih_abs_V4 tglobaladdr:$addr)))>,
3612 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3613 (i64 (A4_combineir 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>,
3616 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3617 (i64 (A2_sxtw (LDrih_abs_V4 tglobaladdr:$addr)))>,
3620 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3621 (i64 (A4_combineir 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3624 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3625 (i64 (A4_combineir 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>,
3628 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3629 (i64 (A2_sxtw (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3633 // We need a complexity of 120 here to override preceding handling of
3635 let AddedComplexity = 120 in {
3636 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3637 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3640 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3641 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3644 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3645 (i64 (A2_sxtw (LDriw_abs_V4 tglobaladdr:$addr)))>,
3648 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3649 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3652 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3653 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3656 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3657 (i64 (A2_sxtw (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3661 // Indexed store double word - global address.
3662 // memw(Rs+#u6:2)=#S8
3663 let AddedComplexity = 10 in
3664 def STrih_offset_ext_V4 : STInst<(outs),
3665 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3666 "memh($src1+#$src2) = ##$src3",
3667 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3668 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3670 // Map from store(globaladdress + x) -> memd(#foo + x)
3671 let AddedComplexity = 100 in
3672 def : Pat<(store (i64 DoubleRegs:$src1),
3673 FoldGlobalAddrGP:$addr),
3674 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3677 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3678 (i64 DoubleRegs:$src1)),
3679 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3682 // Map from store(globaladdress + x) -> memb(#foo + x)
3683 let AddedComplexity = 100 in
3684 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3685 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3688 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3689 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3692 // Map from store(globaladdress + x) -> memh(#foo + x)
3693 let AddedComplexity = 100 in
3694 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3695 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3698 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3699 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3702 // Map from store(globaladdress + x) -> memw(#foo + x)
3703 let AddedComplexity = 100 in
3704 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3705 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3708 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3709 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3712 // Map from load(globaladdress + x) -> memd(#foo + x)
3713 let AddedComplexity = 100 in
3714 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3715 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3718 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3719 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3722 // Map from load(globaladdress + x) -> memb(#foo + x)
3723 let AddedComplexity = 100 in
3724 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3725 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3728 // Map from load(globaladdress + x) -> memb(#foo + x)
3729 let AddedComplexity = 100 in
3730 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3731 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3734 //let AddedComplexity = 100 in
3735 let AddedComplexity = 100 in
3736 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3737 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3740 // Map from load(globaladdress + x) -> memh(#foo + x)
3741 let AddedComplexity = 100 in
3742 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3743 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3746 // Map from load(globaladdress + x) -> memuh(#foo + x)
3747 let AddedComplexity = 100 in
3748 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3749 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3752 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3753 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3756 // Map from load(globaladdress + x) -> memub(#foo + x)
3757 let AddedComplexity = 100 in
3758 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3759 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3762 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3763 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3766 // Map from load(globaladdress + x) -> memw(#foo + x)
3767 let AddedComplexity = 100 in
3768 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3769 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
3772 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3773 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,