1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let hasSideEffects = 0 in
15 class T_Immext<Operand ImmType>
16 : EXTENDERInst<(outs), (ins ImmType:$imm),
17 "immext(#$imm)", []> {
21 let Inst{27-16} = imm{31-20};
22 let Inst{13-0} = imm{19-6};
25 def A4_ext : T_Immext<u26_6Imm>;
26 let isCodeGenOnly = 1 in {
28 def A4_ext_b : T_Immext<brtarget>;
30 def A4_ext_c : T_Immext<calltarget>;
31 def A4_ext_g : T_Immext<globaladdress>;
34 def BITPOS32 : SDNodeXForm<imm, [{
35 // Return the bit position we will set [0-31].
37 int32_t imm = N->getSExtValue();
38 return XformMskToBitPosU5Imm(imm);
41 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
42 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
44 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
45 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
47 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
48 (HexagonCONST32 node:$addr), [{
49 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
52 // Hexagon V4 Architecture spec defines 8 instruction classes:
53 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
57 // ========================================
58 // Loads (8/16/32/64 bit)
62 // ========================================
63 // Stores (8/16/32/64 bit)
66 // ALU32 Instructions:
67 // ========================================
68 // Arithmetic / Logical (32 bit)
71 // XTYPE Instructions (32/64 bit):
72 // ========================================
73 // Arithmetic, Logical, Bit Manipulation
74 // Multiply (Integer, Fractional, Complex)
75 // Permute / Vector Permute Operations
76 // Predicate Operations
77 // Shift / Shift with Add/Sub/Logical
79 // Vector Halfword (ALU, Shift, Multiply)
80 // Vector Word (ALU, Shift)
83 // ========================================
84 // Jump/Call PC-relative
87 // ========================================
90 // MEMOP Instructions:
91 // ========================================
92 // Operation on memory (8/16/32 bit)
95 // ========================================
100 // ========================================
101 // Control-Register Transfers
102 // Hardware Loop Setup
103 // Predicate Logicals & Reductions
105 // SYSTEM Instructions (not implemented in the compiler):
106 // ========================================
112 //===----------------------------------------------------------------------===//
114 //===----------------------------------------------------------------------===//
116 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
118 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
119 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
122 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
123 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
124 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
125 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
127 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
128 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
129 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
130 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
132 let isCodeGenOnly = 0 in {
133 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
134 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
135 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
138 // Pats for instruction selection.
140 // A class to embed the usual comparison patfrags within a zext to i32.
141 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
142 // names, or else the frag's "body" won't match the operands.
143 class CmpInReg<PatFrag Op>
144 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
146 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
147 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
149 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
151 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
152 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
153 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
155 let validSubTargets = HasV4SubT;
156 let InputType = "reg";
157 let CextOpcode = mnemonic;
159 let isCommutable = IsComm;
160 let hasSideEffects = 0;
167 let Inst{27-21} = 0b0111110;
168 let Inst{20-16} = Rs;
170 let Inst{7-5} = MinOp;
174 let isCodeGenOnly = 0 in {
175 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
176 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
177 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
178 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
179 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
180 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
183 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
184 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
185 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
186 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
188 let validSubTargets = HasV4SubT;
189 let InputType = "imm";
190 let CextOpcode = mnemonic;
192 let isCommutable = IsComm;
193 let hasSideEffects = 0;
194 let isExtendable = IsImmExt;
195 let opExtendable = !if (IsImmExt, 2, 0);
196 let isExtentSigned = IsImmSigned;
197 let opExtentBits = ImmBits;
204 let Inst{27-24} = 0b1101;
205 let Inst{22-21} = MajOp;
206 let Inst{20-16} = Rs;
207 let Inst{12-5} = Imm;
209 let Inst{3} = IsHalf;
213 let isCodeGenOnly = 0 in {
214 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
215 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
216 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
217 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
218 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
219 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
221 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
222 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
223 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
225 let validSubTargets = HasV4SubT;
226 let InputType = "imm";
227 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
228 let isExtendable = 1;
229 let opExtendable = 2;
230 let isExtentSigned = 1;
231 let opExtentBits = 8;
239 let Inst{27-24} = 0b0011;
241 let Inst{21} = IsNeg;
242 let Inst{20-16} = Rs;
248 let isCodeGenOnly = 0 in {
249 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
250 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
253 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
254 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
255 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
256 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
258 // Preserve the S2_tstbit_r generation
259 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
260 (i32 IntRegs:$src1))), 0)))),
261 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
264 //===----------------------------------------------------------------------===//
266 //===----------------------------------------------------------------------===//
269 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 // Combine a word and an immediate into a register pair.
274 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
276 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
277 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
283 let Inst{27-24} = 0b0011;
284 let Inst{22-21} = MajOp;
285 let Inst{20-16} = Rs;
291 let opExtendable = 2, isCodeGenOnly = 0 in
292 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
293 "$Rdd = combine($Rs, #$s8)">;
295 let opExtendable = 1, isCodeGenOnly = 0 in
296 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
297 "$Rdd = combine(#$s8, $Rs)">;
299 def HexagonWrapperCombineRI_V4 :
300 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
301 def HexagonWrapperCombineIR_V4 :
302 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
304 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
305 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
308 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
309 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
312 // A4_combineii: Set two small immediates.
313 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
314 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
315 "$Rdd = combine(#$s8, #$U6)"> {
321 let Inst{27-23} = 0b11001;
322 let Inst{20-16} = U6{5-1};
323 let Inst{13} = U6{0};
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
335 //===----------------------------------------------------------------------===//
336 // Template class for load instructions with Absolute set addressing mode.
337 //===----------------------------------------------------------------------===//
338 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
339 hasSideEffects = 0 in
340 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
341 LDInst<(outs RC:$dst1, IntRegs:$dst2),
343 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
351 let Inst{27-25} = 0b101;
352 let Inst{24-21} = MajOp;
353 let Inst{13-12} = 0b01;
354 let Inst{4-0} = dst1;
355 let Inst{20-16} = dst2;
356 let Inst{11-8} = addr{5-2};
357 let Inst{6-5} = addr{1-0};
360 let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
361 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
362 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
365 let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
366 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
367 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
370 let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
371 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
373 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
374 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
376 //===----------------------------------------------------------------------===//
377 // Template classes for the non-predicated load instructions with
378 // base + register offset addressing mode
379 //===----------------------------------------------------------------------===//
380 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
381 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
382 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
383 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
391 let Inst{27-24} = 0b1010;
392 let Inst{23-21} = MajOp;
393 let Inst{20-16} = src1;
394 let Inst{12-8} = src2;
395 let Inst{13} = u2{1};
400 //===----------------------------------------------------------------------===//
401 // Template classes for the predicated load instructions with
402 // base + register offset addressing mode
403 //===----------------------------------------------------------------------===//
404 let isPredicated = 1 in
405 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
406 bit isNot, bit isPredNew>:
407 LDInst <(outs RC:$dst),
408 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
409 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
410 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
411 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
418 let isPredicatedFalse = isNot;
419 let isPredicatedNew = isPredNew;
423 let Inst{27-26} = 0b00;
424 let Inst{25} = isPredNew;
425 let Inst{24} = isNot;
426 let Inst{23-21} = MajOp;
427 let Inst{20-16} = src2;
428 let Inst{12-8} = src3;
429 let Inst{13} = u2{1};
431 let Inst{6-5} = src1;
435 //===----------------------------------------------------------------------===//
436 // multiclass for load instructions with base + register offset
438 //===----------------------------------------------------------------------===//
439 let hasSideEffects = 0, addrMode = BaseRegOffset in
440 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
442 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
443 InputType = "reg" in {
444 let isPredicable = 1 in
445 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
448 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
449 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
452 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
453 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
457 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
458 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
459 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
462 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
463 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
464 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
467 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
468 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
470 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
471 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
473 // 'def pats' for load instructions with base + register offset and non-zero
474 // immediate value. Immediate value is used to left-shift the second
476 let AddedComplexity = 40 in {
477 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
478 (shl IntRegs:$src2, u2ImmPred:$offset)))),
479 (L4_loadrb_rr IntRegs:$src1,
480 IntRegs:$src2, u2ImmPred:$offset)>,
483 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
484 (shl IntRegs:$src2, u2ImmPred:$offset)))),
485 (L4_loadrub_rr IntRegs:$src1,
486 IntRegs:$src2, u2ImmPred:$offset)>,
489 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
490 (shl IntRegs:$src2, u2ImmPred:$offset)))),
491 (L4_loadrub_rr IntRegs:$src1,
492 IntRegs:$src2, u2ImmPred:$offset)>,
495 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
496 (shl IntRegs:$src2, u2ImmPred:$offset)))),
497 (L4_loadrh_rr IntRegs:$src1,
498 IntRegs:$src2, u2ImmPred:$offset)>,
501 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
502 (shl IntRegs:$src2, u2ImmPred:$offset)))),
503 (L4_loadruh_rr IntRegs:$src1,
504 IntRegs:$src2, u2ImmPred:$offset)>,
507 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
508 (shl IntRegs:$src2, u2ImmPred:$offset)))),
509 (L4_loadruh_rr IntRegs:$src1,
510 IntRegs:$src2, u2ImmPred:$offset)>,
513 def : Pat <(i32 (load (add IntRegs:$src1,
514 (shl IntRegs:$src2, u2ImmPred:$offset)))),
515 (L4_loadri_rr IntRegs:$src1,
516 IntRegs:$src2, u2ImmPred:$offset)>,
519 def : Pat <(i64 (load (add IntRegs:$src1,
520 (shl IntRegs:$src2, u2ImmPred:$offset)))),
521 (L4_loadrd_rr IntRegs:$src1,
522 IntRegs:$src2, u2ImmPred:$offset)>,
526 // 'def pats' for load instruction base + register offset and
527 // zero immediate value.
528 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
529 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
530 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
532 let AddedComplexity = 20 in {
533 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
534 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
535 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
536 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
537 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
538 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
539 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
540 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
544 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
545 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
549 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
550 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
553 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
554 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
557 let AddedComplexity = 20 in
558 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
559 s11_0ExtPred:$offset))),
560 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
561 s11_0ExtPred:$offset)))>,
565 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
566 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
569 let AddedComplexity = 20 in
570 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
571 s11_0ExtPred:$offset))),
572 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
573 s11_0ExtPred:$offset)))>,
577 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
578 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
581 let AddedComplexity = 20 in
582 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
583 s11_1ExtPred:$offset))),
584 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
585 s11_1ExtPred:$offset)))>,
589 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
590 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
593 let AddedComplexity = 20 in
594 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
595 s11_1ExtPred:$offset))),
596 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
597 s11_1ExtPred:$offset)))>,
601 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
602 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
605 let AddedComplexity = 100 in
606 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
607 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
608 s11_2ExtPred:$offset)))>,
612 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
613 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
616 let AddedComplexity = 100 in
617 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
618 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
619 s11_2ExtPred:$offset)))>,
624 //===----------------------------------------------------------------------===//
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
630 //===----------------------------------------------------------------------===//
632 //===----------------------------------------------------------------------===//
633 // Template class for store instructions with Absolute set addressing mode.
634 //===----------------------------------------------------------------------===//
635 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
636 addrMode = AbsoluteSet in
637 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
638 STInst2<(outs IntRegs:$dst1),
639 (ins RC:$src1, u0AlwaysExt:$src2),
640 mnemonic#"($dst1=##$src2) = $src1",
644 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
645 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
646 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
647 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
649 //===----------------------------------------------------------------------===//
650 // Template classes for the non-predicated store instructions with
651 // base + register offset addressing mode
652 //===----------------------------------------------------------------------===//
653 let isPredicable = 1 in
654 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
655 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
656 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
657 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
666 let Inst{27-24} = 0b1011;
667 let Inst{23-21} = MajOp;
668 let Inst{20-16} = Rs;
670 let Inst{13} = u2{1};
675 //===----------------------------------------------------------------------===//
676 // Template classes for the predicated store instructions with
677 // base + register offset addressing mode
678 //===----------------------------------------------------------------------===//
679 let isPredicated = 1 in
680 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
681 bit isNot, bit isPredNew, bit isH>
683 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
685 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
686 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
687 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
694 let isPredicatedFalse = isNot;
695 let isPredicatedNew = isPredNew;
699 let Inst{27-26} = 0b01;
700 let Inst{25} = isPredNew;
701 let Inst{24} = isNot;
702 let Inst{23-21} = MajOp;
703 let Inst{20-16} = Rs;
705 let Inst{13} = u2{1};
711 //===----------------------------------------------------------------------===//
712 // Template classes for the new-value store instructions with
713 // base + register offset addressing mode
714 //===----------------------------------------------------------------------===//
715 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
716 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
717 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
718 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
719 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
728 let Inst{27-21} = 0b1011101;
729 let Inst{20-16} = Rs;
731 let Inst{13} = u2{1};
733 let Inst{4-3} = MajOp;
737 //===----------------------------------------------------------------------===//
738 // Template classes for the predicated new-value store instructions with
739 // base + register offset addressing mode
740 //===----------------------------------------------------------------------===//
741 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
742 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
744 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
745 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
746 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
747 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
754 let isPredicatedFalse = isNot;
755 let isPredicatedNew = isPredNew;
758 let Inst{27-26} = 0b01;
759 let Inst{25} = isPredNew;
760 let Inst{24} = isNot;
761 let Inst{23-21} = 0b101;
762 let Inst{20-16} = Rs;
764 let Inst{13} = u2{1};
767 let Inst{4-3} = MajOp;
771 //===----------------------------------------------------------------------===//
772 // multiclass for store instructions with base + register offset addressing
774 //===----------------------------------------------------------------------===//
775 let isNVStorable = 1 in
776 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
777 bits<3> MajOp, bit isH = 0> {
778 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
779 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
782 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
783 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
786 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
787 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
791 //===----------------------------------------------------------------------===//
792 // multiclass for new-value store instructions with base + register offset
794 //===----------------------------------------------------------------------===//
795 let mayStore = 1, isNVStore = 1 in
796 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
798 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
799 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
802 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
803 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
806 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
807 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
811 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
812 isCodeGenOnly = 0 in {
813 let accessSize = ByteAccess in
814 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
815 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
817 let accessSize = HalfWordAccess in
818 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
819 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
821 let accessSize = WordAccess in
822 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
823 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
825 let isNVStorable = 0, accessSize = DoubleWordAccess in
826 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
828 let isNVStorable = 0, accessSize = HalfWordAccess in
829 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
832 let Predicates = [HasV4T], AddedComplexity = 10 in {
833 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
834 (add IntRegs:$src1, (shl IntRegs:$src2,
836 (S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
837 u2ImmPred:$src3, IntRegs:$src4)>;
839 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
840 (add IntRegs:$src1, (shl IntRegs:$src2,
842 (S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
843 u2ImmPred:$src3, IntRegs:$src4)>;
845 def : Pat<(store (i32 IntRegs:$src4),
846 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
847 (S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
848 u2ImmPred:$src3, IntRegs:$src4)>;
850 def : Pat<(store (i64 DoubleRegs:$src4),
851 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
852 (S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
853 u2ImmPred:$src3, DoubleRegs:$src4)>;
856 let isExtended = 1, opExtendable = 2 in
857 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
859 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
860 mnemonic#"($src1<<#$src2+##$src3) = $src4",
861 [(stOp (VT RC:$src4),
862 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
863 u0AlwaysExtPred:$src3))]>,
866 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
867 class T_ST_LongOff_nv <string mnemonic> :
869 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
870 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
874 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
875 let BaseOpcode = BaseOp#"_shl" in {
876 let isNVStorable = 1 in
877 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
879 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
883 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
884 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
885 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
886 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
887 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
890 let AddedComplexity = 40 in
891 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
893 def : Pat<(stOp (VT RC:$src4),
894 (add (shl IntRegs:$src1, u2ImmPred:$src2),
895 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
896 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
898 def : Pat<(stOp (VT RC:$src4),
900 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
901 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
904 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
905 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
906 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
907 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
909 // memd(Rx++#s4:3)=Rtt
910 // memd(Rx++#s4:3:circ(Mu))=Rtt
911 // memd(Rx++I:circ(Mu))=Rtt
913 // memd(Rx++Mu:brev)=Rtt
914 // memd(gp+#u16:3)=Rtt
916 // Store doubleword conditionally.
917 // if ([!]Pv[.new]) memd(#u6)=Rtt
918 // TODO: needs to be implemented.
920 //===----------------------------------------------------------------------===//
922 //===----------------------------------------------------------------------===//
923 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
925 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
926 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
927 mnemonic#"($Rs+#$offset)=#$S8",
928 [], "", V4LDST_tc_st_SLOT01>,
929 ImmRegRel, PredNewRel {
935 string OffsetOpStr = !cast<string>(OffsetOp);
936 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
937 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
938 /* u6_0Imm */ offset{5-0}));
942 let Inst{27-25} = 0b110;
943 let Inst{22-21} = MajOp;
944 let Inst{20-16} = Rs;
945 let Inst{12-7} = offsetBits;
946 let Inst{13} = S8{7};
947 let Inst{6-0} = S8{6-0};
950 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
952 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
953 bit isPredNot, bit isPredNew >
955 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
956 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
957 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
958 [], "", V4LDST_tc_st_SLOT01>,
959 ImmRegRel, PredNewRel {
966 string OffsetOpStr = !cast<string>(OffsetOp);
967 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
968 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
969 /* u6_0Imm */ offset{5-0}));
970 let isPredicatedNew = isPredNew;
971 let isPredicatedFalse = isPredNot;
975 let Inst{27-25} = 0b100;
976 let Inst{24} = isPredNew;
977 let Inst{23} = isPredNot;
978 let Inst{22-21} = MajOp;
979 let Inst{20-16} = Rs;
980 let Inst{13} = S6{5};
981 let Inst{12-7} = offsetBits;
983 let Inst{4-0} = S6{4-0};
987 //===----------------------------------------------------------------------===//
988 // multiclass for store instructions with base + immediate offset
989 // addressing mode and immediate stored value.
990 // mem[bhw](Rx++#s4:3)=#s8
991 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
992 //===----------------------------------------------------------------------===//
994 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
996 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
998 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1001 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1003 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1004 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1006 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1007 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1011 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1012 InputType = "imm", isCodeGenOnly = 0 in {
1013 let accessSize = ByteAccess in
1014 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1016 let accessSize = HalfWordAccess in
1017 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1019 let accessSize = WordAccess in
1020 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1023 let Predicates = [HasV4T], AddedComplexity = 10 in {
1024 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1025 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1027 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1028 u6_1ImmPred:$src2)),
1029 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1031 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1032 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1035 let AddedComplexity = 6 in
1036 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1037 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1040 // memb(Rx++#s4:0:circ(Mu))=Rt
1041 // memb(Rx++I:circ(Mu))=Rt
1043 // memb(Rx++Mu:brev)=Rt
1044 // memb(gp+#u16:0)=Rt
1048 // TODO: needs to be implemented
1049 // memh(Re=#U6)=Rt.H
1050 // memh(Rs+#s11:1)=Rt.H
1051 let AddedComplexity = 6 in
1052 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1053 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1056 // memh(Rs+Ru<<#u2)=Rt.H
1057 // TODO: needs to be implemented.
1059 // memh(Ru<<#u2+#U6)=Rt.H
1060 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1061 // memh(Rx++#s4:1:circ(Mu))=Rt
1062 // memh(Rx++I:circ(Mu))=Rt.H
1063 // memh(Rx++I:circ(Mu))=Rt
1064 // memh(Rx++Mu)=Rt.H
1066 // memh(Rx++Mu:brev)=Rt.H
1067 // memh(Rx++Mu:brev)=Rt
1068 // memh(gp+#u16:1)=Rt
1069 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1070 // if ([!]Pv[.new]) memh(#u6)=Rt
1073 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1074 // TODO: needs to be implemented.
1076 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1077 // TODO: Needs to be implemented.
1081 // TODO: Needs to be implemented.
1084 let hasSideEffects = 0 in
1085 def STriw_pred_V4 : STInst2<(outs),
1086 (ins MEMri:$addr, PredRegs:$src1),
1087 "Error; should not emit",
1091 let AddedComplexity = 6 in
1092 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1093 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1096 // memw(Rx++#s4:2)=Rt
1097 // memw(Rx++#s4:2:circ(Mu))=Rt
1098 // memw(Rx++I:circ(Mu))=Rt
1100 // memw(Rx++Mu:brev)=Rt
1102 //===----------------------------------------------------------------------===
1104 //===----------------------------------------------------------------------===
1107 //===----------------------------------------------------------------------===//
1109 //===----------------------------------------------------------------------===//
1111 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1112 class T_store_io_nv <string mnemonic, RegisterClass RC,
1113 Operand ImmOp, bits<2>MajOp>
1114 : NVInst_V4 <(outs),
1115 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1116 mnemonic#"($src1+#$src2) = $src3.new",
1117 [],"",ST_tc_st_SLOT0> {
1119 bits<13> src2; // Actual address offset
1121 bits<11> offsetBits; // Represents offset encoding
1123 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1124 !if (!eq(mnemonic, "memh"), 12,
1125 !if (!eq(mnemonic, "memw"), 13, 0)));
1127 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1128 !if (!eq(mnemonic, "memh"), 1,
1129 !if (!eq(mnemonic, "memw"), 2, 0)));
1131 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1132 !if (!eq(mnemonic, "memh"), src2{11-1},
1133 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1135 let IClass = 0b1010;
1138 let Inst{26-25} = offsetBits{10-9};
1139 let Inst{24-21} = 0b1101;
1140 let Inst{20-16} = src1;
1141 let Inst{13} = offsetBits{8};
1142 let Inst{12-11} = MajOp;
1143 let Inst{10-8} = src3;
1144 let Inst{7-0} = offsetBits{7-0};
1147 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1148 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1149 bits<2>MajOp, bit PredNot, bit isPredNew>
1150 : NVInst_V4 <(outs),
1151 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1152 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1153 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1154 [],"",V2LDST_tc_st_SLOT0> {
1159 bits<6> offsetBits; // Represents offset encoding
1161 let isPredicatedNew = isPredNew;
1162 let isPredicatedFalse = PredNot;
1163 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1164 !if (!eq(mnemonic, "memh"), 7,
1165 !if (!eq(mnemonic, "memw"), 8, 0)));
1167 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1168 !if (!eq(mnemonic, "memh"), 1,
1169 !if (!eq(mnemonic, "memw"), 2, 0)));
1171 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1172 !if (!eq(mnemonic, "memh"), src3{6-1},
1173 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1175 let IClass = 0b0100;
1178 let Inst{26} = PredNot;
1179 let Inst{25} = isPredNew;
1180 let Inst{24-21} = 0b0101;
1181 let Inst{20-16} = src2;
1182 let Inst{13} = offsetBits{5};
1183 let Inst{12-11} = MajOp;
1184 let Inst{10-8} = src4;
1185 let Inst{7-3} = offsetBits{4-0};
1187 let Inst{1-0} = src1;
1190 // multiclass for new-value store instructions with base + immediate offset.
1192 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1194 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1195 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1197 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1198 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1200 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1201 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1203 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1205 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1210 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1211 let accessSize = ByteAccess in
1212 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1213 u6_0Ext, 0b00>, AddrModeRel;
1215 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1216 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1217 u6_1Ext, 0b01>, AddrModeRel;
1219 let accessSize = WordAccess, opExtentAlign = 2 in
1220 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1221 u6_2Ext, 0b10>, AddrModeRel;
1224 //===----------------------------------------------------------------------===//
1225 // Post increment loads with register offset.
1226 //===----------------------------------------------------------------------===//
1228 let hasNewValue = 1, isCodeGenOnly = 0 in
1229 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1231 let isCodeGenOnly = 0 in
1232 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1234 //===----------------------------------------------------------------------===//
1235 // Template class for non-predicated post increment .new stores
1236 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1237 //===----------------------------------------------------------------------===//
1238 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1239 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1240 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1241 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1242 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1243 mnemonic#"($src1++#$offset) = $src2.new",
1244 [], "$src1 = $_dst_">,
1251 string ImmOpStr = !cast<string>(ImmOp);
1252 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1253 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1254 /* s4_0Imm */ offset{3-0}));
1255 let IClass = 0b1010;
1257 let Inst{27-21} = 0b1011101;
1258 let Inst{20-16} = src1;
1260 let Inst{12-11} = MajOp;
1261 let Inst{10-8} = src2;
1263 let Inst{6-3} = offsetBits;
1267 //===----------------------------------------------------------------------===//
1268 // Template class for predicated post increment .new stores
1269 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1270 //===----------------------------------------------------------------------===//
1271 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1272 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1273 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1274 bits<2> MajOp, bit isPredNot, bit isPredNew >
1275 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1276 (ins PredRegs:$src1, IntRegs:$src2,
1277 ImmOp:$offset, IntRegs:$src3),
1278 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1279 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1280 [], "$src2 = $_dst_">,
1288 string ImmOpStr = !cast<string>(ImmOp);
1289 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1290 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1291 /* s4_0Imm */ offset{3-0}));
1292 let isPredicatedNew = isPredNew;
1293 let isPredicatedFalse = isPredNot;
1295 let IClass = 0b1010;
1297 let Inst{27-21} = 0b1011101;
1298 let Inst{20-16} = src2;
1300 let Inst{12-11} = MajOp;
1301 let Inst{10-8} = src3;
1302 let Inst{7} = isPredNew;
1303 let Inst{6-3} = offsetBits;
1304 let Inst{2} = isPredNot;
1305 let Inst{1-0} = src1;
1308 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1309 bits<2> MajOp, bit PredNot> {
1310 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1313 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1316 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1318 let BaseOpcode = "POST_"#BaseOp in {
1319 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1322 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1323 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1327 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1328 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1330 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1331 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1333 let accessSize = WordAccess, isCodeGenOnly = 0 in
1334 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1336 //===----------------------------------------------------------------------===//
1337 // Template class for post increment .new stores with register offset
1338 //===----------------------------------------------------------------------===//
1339 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1340 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1341 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1342 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1343 #mnemonic#"($src1++$src2) = $src3.new",
1344 [], "$src1 = $_dst_"> {
1348 let accessSize = AccessSz;
1350 let IClass = 0b1010;
1352 let Inst{27-21} = 0b1101101;
1353 let Inst{20-16} = src1;
1354 let Inst{13} = src2;
1355 let Inst{12-11} = MajOp;
1356 let Inst{10-8} = src3;
1360 let isCodeGenOnly = 0 in {
1361 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1362 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1363 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1366 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1367 // memb(Rx++I:circ(Mu))=Nt.new
1368 // memb(Rx++Mu)=Nt.new
1369 // memb(Rx++Mu:brev)=Nt.new
1370 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1371 // memh(Rx++I:circ(Mu))=Nt.new
1372 // memh(Rx++Mu)=Nt.new
1373 // memh(Rx++Mu:brev)=Nt.new
1375 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1376 // memw(Rx++I:circ(Mu))=Nt.new
1377 // memw(Rx++Mu)=Nt.new
1378 // memw(Rx++Mu:brev)=Nt.new
1380 //===----------------------------------------------------------------------===//
1382 //===----------------------------------------------------------------------===//
1384 //===----------------------------------------------------------------------===//
1386 //===----------------------------------------------------------------------===//
1388 //===----------------------------------------------------------------------===//
1389 // multiclass/template class for the new-value compare jumps with the register
1391 //===----------------------------------------------------------------------===//
1393 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1394 opExtentAlign = 2 in
1395 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1396 bit isNegCond, bit isTak>
1398 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1399 "if ("#!if(isNegCond, "!","")#mnemonic#
1400 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1401 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1402 #!if(isTak, "t","nt")#" $offset", []> {
1406 bits<3> Ns; // New-Value Operand
1407 bits<5> RegOp; // Non-New-Value Operand
1410 let isTaken = isTak;
1411 let isPredicatedFalse = isNegCond;
1412 let opNewValue{0} = NvOpNum;
1414 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1415 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1417 let IClass = 0b0010;
1419 let Inst{25-23} = majOp;
1420 let Inst{22} = isNegCond;
1421 let Inst{18-16} = Ns;
1422 let Inst{13} = isTak;
1423 let Inst{12-8} = RegOp;
1424 let Inst{21-20} = offset{10-9};
1425 let Inst{7-1} = offset{8-2};
1429 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1431 // Branch not taken:
1432 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1434 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1437 // NvOpNum = 0 -> First Operand is a new-value Register
1438 // NvOpNum = 1 -> Second Operand is a new-value Register
1440 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1442 let BaseOpcode = BaseOp#_NVJ in {
1443 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1444 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1448 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1449 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1450 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1451 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1452 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1454 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1455 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1456 isCodeGenOnly = 0 in {
1457 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1458 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1459 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1460 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1461 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1464 //===----------------------------------------------------------------------===//
1465 // multiclass/template class for the new-value compare jumps instruction
1466 // with a register and an unsigned immediate (U5) operand.
1467 //===----------------------------------------------------------------------===//
1469 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1470 opExtentAlign = 2 in
1471 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1474 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1475 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1476 #!if(isTak, "t","nt")#" $offset", []> {
1478 let isTaken = isTak;
1479 let isPredicatedFalse = isNegCond;
1480 let isTaken = isTak;
1486 let IClass = 0b0010;
1488 let Inst{25-23} = majOp;
1489 let Inst{22} = isNegCond;
1490 let Inst{18-16} = src1;
1491 let Inst{13} = isTak;
1492 let Inst{12-8} = src2;
1493 let Inst{21-20} = offset{10-9};
1494 let Inst{7-1} = offset{8-2};
1497 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1498 // Branch not taken:
1499 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1501 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1504 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1505 let BaseOpcode = BaseOp#_NVJri in {
1506 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1507 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1511 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1512 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1513 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1515 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1516 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1517 isCodeGenOnly = 0 in {
1518 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1519 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1520 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1523 //===----------------------------------------------------------------------===//
1524 // multiclass/template class for the new-value compare jumps instruction
1525 // with a register and an hardcoded 0/-1 immediate value.
1526 //===----------------------------------------------------------------------===//
1528 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1529 opExtentAlign = 2 in
1530 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1531 bit isNegCond, bit isTak>
1533 (ins IntRegs:$src1, brtarget:$offset),
1534 "if ("#!if(isNegCond, "!","")#mnemonic
1535 #"($src1.new, #"#ImmVal#")) jump:"
1536 #!if(isTak, "t","nt")#" $offset", []> {
1538 let isTaken = isTak;
1539 let isPredicatedFalse = isNegCond;
1540 let isTaken = isTak;
1544 let IClass = 0b0010;
1546 let Inst{25-23} = majOp;
1547 let Inst{22} = isNegCond;
1548 let Inst{18-16} = src1;
1549 let Inst{13} = isTak;
1550 let Inst{21-20} = offset{10-9};
1551 let Inst{7-1} = offset{8-2};
1554 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1556 // Branch not taken:
1557 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1559 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1562 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1564 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1565 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1566 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1570 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1571 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1572 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1574 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1575 Defs = [PC], hasSideEffects = 0, isCodeGenOnly = 0 in {
1576 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1577 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1578 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1581 // J4_hintjumpr: Hint indirect conditional jump.
1582 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1583 def J4_hintjumpr: JRInst <
1588 let IClass = 0b0101;
1589 let Inst{27-21} = 0b0010101;
1590 let Inst{20-16} = Rs;
1593 //===----------------------------------------------------------------------===//
1595 //===----------------------------------------------------------------------===//
1597 //===----------------------------------------------------------------------===//
1599 //===----------------------------------------------------------------------===//
1602 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1603 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0,
1604 Uses = [PC], validSubTargets = HasV4SubT, isCodeGenOnly = 0 in
1605 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1606 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1610 let IClass = 0b0110;
1611 let Inst{27-16} = 0b101001001001;
1612 let Inst{12-7} = u6;
1618 let hasSideEffects = 0 in
1619 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1620 : CRInst<(outs PredRegs:$Pd),
1621 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1622 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1623 !if (IsNeg,"!","") # "$Pu))",
1624 [], "", CR_tc_2early_SLOT23> {
1630 let IClass = 0b0110;
1631 let Inst{27-24} = 0b1011;
1632 let Inst{23} = IsNeg;
1633 let Inst{22-21} = OpBits;
1635 let Inst{17-16} = Ps;
1642 let isCodeGenOnly = 0 in {
1643 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1644 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1645 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1646 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1647 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1648 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1649 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1650 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1653 //===----------------------------------------------------------------------===//
1655 //===----------------------------------------------------------------------===//
1657 //===----------------------------------------------------------------------===//
1659 //===----------------------------------------------------------------------===//
1661 // Logical with-not instructions.
1662 let validSubTargets = HasV4SubT, isCodeGenOnly = 0 in {
1663 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1664 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1667 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1668 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1669 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1674 let IClass = 0b1101;
1675 let Inst{27-21} = 0b0101111;
1676 let Inst{20-16} = Rs;
1677 let Inst{12-8} = Rt;
1680 // Add and accumulate.
1681 // Rd=add(Rs,add(Ru,#s6))
1682 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1683 opExtendable = 3, isCodeGenOnly = 0 in
1684 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1685 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1686 "$Rd = add($Rs, add($Ru, #$s6))" ,
1687 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1688 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1689 "", ALU64_tc_2_SLOT23> {
1695 let IClass = 0b1101;
1697 let Inst{27-23} = 0b10110;
1698 let Inst{22-21} = s6{5-4};
1699 let Inst{20-16} = Rs;
1700 let Inst{13} = s6{3};
1701 let Inst{12-8} = Rd;
1702 let Inst{7-5} = s6{2-0};
1706 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1707 opExtentBits = 6, opExtendable = 2, isCodeGenOnly = 0 in
1708 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1709 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1710 "$Rd = add($Rs, sub(#$s6, $Ru))",
1711 [], "", ALU64_tc_2_SLOT23> {
1717 let IClass = 0b1101;
1719 let Inst{27-23} = 0b10111;
1720 let Inst{22-21} = s6{5-4};
1721 let Inst{20-16} = Rs;
1722 let Inst{13} = s6{3};
1723 let Inst{12-8} = Rd;
1724 let Inst{7-5} = s6{2-0};
1729 // Rdd=extract(Rss,#u6,#U6)
1730 // Rdd=extract(Rss,Rtt)
1731 // Rd=extract(Rs,Rtt)
1732 // Rd=extract(Rs,#u5,#U5)
1734 let isCodeGenOnly = 0 in {
1735 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1736 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1739 let hasNewValue = 1, isCodeGenOnly = 0 in {
1740 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1741 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1744 // Complex add/sub halfwords/words
1745 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
1746 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1747 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1748 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1749 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1752 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
1753 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1754 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
1757 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1758 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1759 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1762 // Logical xor with xor accumulation.
1763 // Rxx^=xor(Rss,Rtt)
1764 let hasSideEffects = 0, isCodeGenOnly = 0 in
1766 : SInst <(outs DoubleRegs:$Rxx),
1767 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1768 "$Rxx ^= xor($Rss, $Rtt)",
1769 [(set (i64 DoubleRegs:$Rxx),
1770 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
1771 (i64 DoubleRegs:$Rtt))))],
1772 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
1777 let IClass = 0b1100;
1779 let Inst{27-23} = 0b10101;
1780 let Inst{20-16} = Rss;
1781 let Inst{12-8} = Rtt;
1782 let Inst{4-0} = Rxx;
1785 // Rotate and reduce bytes
1786 // Rdd=vrcrotate(Rss,Rt,#u2)
1787 let hasSideEffects = 0, isCodeGenOnly = 0 in
1789 : SInst <(outs DoubleRegs:$Rdd),
1790 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
1791 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
1792 [], "", S_3op_tc_3x_SLOT23> {
1798 let IClass = 0b1100;
1800 let Inst{27-22} = 0b001111;
1801 let Inst{20-16} = Rss;
1802 let Inst{13} = u2{1};
1803 let Inst{12-8} = Rt;
1804 let Inst{7-6} = 0b11;
1805 let Inst{5} = u2{0};
1806 let Inst{4-0} = Rdd;
1809 // Rotate and reduce bytes with accumulation
1810 // Rxx+=vrcrotate(Rss,Rt,#u2)
1811 let hasSideEffects = 0, isCodeGenOnly = 0 in
1812 def S4_vrcrotate_acc
1813 : SInst <(outs DoubleRegs:$Rxx),
1814 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
1815 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
1816 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
1822 let IClass = 0b1100;
1824 let Inst{27-21} = 0b1011101;
1825 let Inst{20-16} = Rss;
1826 let Inst{13} = u2{1};
1827 let Inst{12-8} = Rt;
1828 let Inst{5} = u2{0};
1829 let Inst{4-0} = Rxx;
1833 // Vector reduce conditional negate halfwords
1834 let hasSideEffects = 0, isCodeGenOnly = 0 in
1836 : SInst <(outs DoubleRegs:$Rxx),
1837 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
1838 "$Rxx += vrcnegh($Rss, $Rt)", [],
1839 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
1844 let IClass = 0b1100;
1846 let Inst{27-21} = 0b1011001;
1847 let Inst{20-16} = Rss;
1849 let Inst{12-8} = Rt;
1850 let Inst{7-5} = 0b111;
1851 let Inst{4-0} = Rxx;
1855 let isCodeGenOnly = 0 in
1856 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
1858 // Arithmetic/Convergent round
1859 let isCodeGenOnly = 0 in
1860 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
1862 let isCodeGenOnly = 0 in
1863 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
1865 let Defs = [USR_OVF], isCodeGenOnly = 0 in
1866 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
1868 // Logical-logical words.
1869 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
1870 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
1871 opExtendable = 3, isCodeGenOnly = 0 in
1873 ALU64Inst<(outs IntRegs:$Rx),
1874 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
1875 "$Rx = or($Ru, and($_src_, #$s10))" ,
1876 [(set (i32 IntRegs:$Rx),
1877 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
1878 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
1883 let IClass = 0b1101;
1885 let Inst{27-22} = 0b101001;
1886 let Inst{20-16} = Rx;
1887 let Inst{21} = s10{9};
1888 let Inst{13-5} = s10{8-0};
1892 // Miscellaneous ALU64 instructions.
1894 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1895 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1896 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1901 let IClass = 0b1101;
1902 let Inst{27-21} = 0b0011111;
1903 let Inst{20-16} = Rs;
1904 let Inst{12-8} = Rt;
1905 let Inst{7-5} = 0b111;
1909 let hasSideEffects = 0, isCodeGenOnly = 0 in
1910 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
1911 (ins IntRegs:$Rs, IntRegs:$Rt),
1912 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1917 let IClass = 0b1101;
1918 let Inst{27-24} = 0b0100;
1920 let Inst{20-16} = Rs;
1921 let Inst{12-8} = Rt;
1925 let isCodeGenOnly = 0 in {
1926 // Rx[&|]=xor(Rs,Rt)
1927 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
1928 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
1930 // Rx[&|^]=or(Rs,Rt)
1931 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
1933 let CextOpcode = "ORr_ORr" in
1934 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
1935 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
1937 // Rx[&|^]=and(Rs,Rt)
1938 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
1940 let CextOpcode = "ORr_ANDr" in
1941 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
1942 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
1944 // Rx[&|^]=and(Rs,~Rt)
1945 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
1946 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
1947 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
1950 // Compound or-or and or-and
1951 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
1952 opExtentBits = 10, opExtendable = 3 in
1953 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
1954 : MInst_acc <(outs IntRegs:$Rx),
1955 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
1956 "$Rx |= "#mnemonic#"($Rs, #$s10)",
1957 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
1958 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
1959 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
1964 let IClass = 0b1101;
1966 let Inst{27-24} = 0b1010;
1967 let Inst{23-22} = MajOp;
1968 let Inst{20-16} = Rs;
1969 let Inst{21} = s10{9};
1970 let Inst{13-5} = s10{8-0};
1974 let CextOpcode = "ORr_ANDr", isCodeGenOnly = 0 in
1975 def S4_or_andi : T_CompOR <"and", 0b00, and>;
1977 let CextOpcode = "ORr_ORr", isCodeGenOnly = 0 in
1978 def S4_or_ori : T_CompOR <"or", 0b10, or>;
1981 // Rd=modwrap(Rs,Rt)
1983 // Rd=cround(Rs,#u5)
1985 // Rd=round(Rs,#u5)[:sat]
1986 // Rd=round(Rs,Rt)[:sat]
1987 // Vector reduce add unsigned halfwords
1988 // Rd=vraddh(Rss,Rtt)
1990 // Rdd=vaddb(Rss,Rtt)
1991 // Vector conditional negate
1992 // Rdd=vcnegh(Rss,Rt)
1993 // Rxx+=vrcnegh(Rss,Rt)
1994 // Vector maximum bytes
1995 // Rdd=vmaxb(Rtt,Rss)
1996 // Vector reduce maximum halfwords
1997 // Rxx=vrmaxh(Rss,Ru)
1998 // Rxx=vrmaxuh(Rss,Ru)
1999 // Vector reduce maximum words
2000 // Rxx=vrmaxuw(Rss,Ru)
2001 // Rxx=vrmaxw(Rss,Ru)
2002 // Vector minimum bytes
2003 // Rdd=vminb(Rtt,Rss)
2004 // Vector reduce minimum halfwords
2005 // Rxx=vrminh(Rss,Ru)
2006 // Rxx=vrminuh(Rss,Ru)
2007 // Vector reduce minimum words
2008 // Rxx=vrminuw(Rss,Ru)
2009 // Rxx=vrminw(Rss,Ru)
2010 // Vector subtract bytes
2011 // Rdd=vsubb(Rss,Rtt)
2013 //===----------------------------------------------------------------------===//
2015 //===----------------------------------------------------------------------===//
2017 //===----------------------------------------------------------------------===//
2019 //===----------------------------------------------------------------------===//
2022 let isCodeGenOnly = 0 in
2023 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2026 let isCodeGenOnly = 0 in {
2027 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2028 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2029 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2032 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
2033 (S2_ct0p (i64 DoubleRegs:$Rss))>;
2034 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
2035 (S2_ct1p (i64 DoubleRegs:$Rss))>;
2037 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2038 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2039 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2043 let IClass = 0b1000;
2044 let Inst{27-24} = 0b1100;
2045 let Inst{23-21} = 0b001;
2046 let Inst{20-16} = Rs;
2047 let Inst{13-8} = s6;
2048 let Inst{7-5} = 0b000;
2052 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2053 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2054 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2058 let IClass = 0b1000;
2059 let Inst{27-24} = 0b1000;
2060 let Inst{23-21} = 0b011;
2061 let Inst{20-16} = Rs;
2062 let Inst{13-8} = s6;
2063 let Inst{7-5} = 0b010;
2068 // Bit test/set/clear
2069 let isCodeGenOnly = 0 in {
2070 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2071 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2074 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2075 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2076 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2077 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2078 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2081 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2082 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2083 // if ([!]tstbit(...)) jump ...
2084 let AddedComplexity = 100 in
2085 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2086 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2088 let AddedComplexity = 100 in
2089 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2090 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2092 let isCodeGenOnly = 0 in {
2093 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2094 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2095 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2098 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2099 // represented as a compare against "value & 0xFF", which is an exact match
2100 // for cmpb (same for cmph). The patterns below do not contain any additional
2101 // complexity that would make them preferable, and if they were actually used
2102 // instead of cmpb/cmph, they would result in a compare against register that
2103 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2104 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2105 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2106 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2107 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2108 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2109 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2111 //===----------------------------------------------------------------------===//
2113 //===----------------------------------------------------------------------===//
2115 //===----------------------------------------------------------------------===//
2117 //===----------------------------------------------------------------------===//
2119 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2121 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1,
2122 isCodeGenOnly = 0 in
2123 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2124 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2125 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2126 [(set (i32 IntRegs:$Rd),
2127 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2128 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2134 let IClass = 0b1101;
2136 let Inst{27-24} = 0b1000;
2137 let Inst{23} = U6{5};
2138 let Inst{22-21} = u6{5-4};
2139 let Inst{20-16} = Rs;
2140 let Inst{13} = u6{3};
2141 let Inst{12-8} = Rd;
2142 let Inst{7-5} = u6{2-0};
2143 let Inst{4-0} = U6{4-0};
2146 // Rd=add(#u6,mpyi(Rs,Rt))
2147 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2148 isExtendable = 1, opExtentBits = 6, opExtendable = 1, isCodeGenOnly = 0 in
2149 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2150 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2151 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2152 [(set (i32 IntRegs:$Rd),
2153 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2154 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2160 let IClass = 0b1101;
2162 let Inst{27-23} = 0b01110;
2163 let Inst{22-21} = u6{5-4};
2164 let Inst{20-16} = Rs;
2165 let Inst{13} = u6{3};
2166 let Inst{12-8} = Rt;
2167 let Inst{7-5} = u6{2-0};
2171 let hasNewValue = 1 in
2172 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2173 : ALU64Inst <(outs IntRegs:$dst), ins,
2174 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2176 [(set (i32 IntRegs:$dst),
2177 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2178 "", ALU64_tc_3x_SLOT23> {
2184 let IClass = 0b1101;
2186 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2188 let Inst{27-24} = 0b1111;
2189 let Inst{23} = MajOp;
2190 let Inst{22-21} = ImmValue{5-4};
2191 let Inst{20-16} = src3;
2192 let Inst{13} = ImmValue{3};
2193 let Inst{12-8} = dst;
2194 let Inst{7-5} = ImmValue{2-0};
2195 let Inst{4-0} = src1;
2198 let isCodeGenOnly = 0 in
2199 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2200 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2202 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2203 CextOpcode = "ADD_MPY", InputType = "imm", isCodeGenOnly = 0 in
2204 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2205 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2207 // Rx=add(Ru,mpyi(Rx,Rs))
2208 let validSubTargets = HasV4SubT, CextOpcode = "ADD_MPY", InputType = "reg",
2209 hasNewValue = 1, isCodeGenOnly = 0 in
2210 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2211 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2212 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2213 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2214 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2215 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2220 let IClass = 0b1110;
2222 let Inst{27-21} = 0b0011000;
2223 let Inst{12-8} = Rx;
2225 let Inst{20-16} = Rs;
2228 // Rd=add(##,mpyi(Rs,#U6))
2229 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2230 (HexagonCONST32 tglobaladdr:$src1)),
2231 (i32 (M4_mpyri_addi tglobaladdr:$src1, IntRegs:$src2,
2234 // Rd=add(##,mpyi(Rs,Rt))
2235 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2236 (HexagonCONST32 tglobaladdr:$src1)),
2237 (i32 (M4_mpyrr_addi tglobaladdr:$src1, IntRegs:$src2,
2240 // Vector reduce multiply word by signed half (32x16)
2241 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2242 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2243 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
2244 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
2246 // Multiply and use upper result
2247 // Rd=mpy(Rs,Rt.H):<<1:sat
2248 // Rd=mpy(Rs,Rt.L):<<1:sat
2249 // Rd=mpy(Rs,Rt):<<1
2250 // Rd=mpy(Rs,Rt):<<1:sat
2252 // Rx+=mpy(Rs,Rt):<<1:sat
2253 // Rx-=mpy(Rs,Rt):<<1:sat
2255 // Vector multiply bytes
2256 // Rdd=vmpybsu(Rs,Rt)
2257 // Rdd=vmpybu(Rs,Rt)
2258 // Rxx+=vmpybsu(Rs,Rt)
2259 // Rxx+=vmpybu(Rs,Rt)
2261 // Vector polynomial multiply halfwords
2262 // Rdd=vpmpyh(Rs,Rt)
2263 // Rxx^=vpmpyh(Rs,Rt)
2265 // Polynomial multiply words
2267 let isCodeGenOnly = 0 in
2268 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2270 // Rxx^=pmpyw(Rs,Rt)
2271 let isCodeGenOnly = 0 in
2272 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2274 //===----------------------------------------------------------------------===//
2276 //===----------------------------------------------------------------------===//
2279 //===----------------------------------------------------------------------===//
2281 //===----------------------------------------------------------------------===//
2282 // Shift by immediate and accumulate/logical.
2283 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2284 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2285 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2286 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2287 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2288 hasNewValue = 1, opNewValue = 0, validSubTargets = HasV4SubT in
2289 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2290 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2291 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2292 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2293 [(set (i32 IntRegs:$Rd),
2294 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2295 "$Rd = $Rx", Itin> {
2302 let IClass = 0b1101;
2303 let Inst{27-24} = 0b1110;
2304 let Inst{23-21} = u8{7-5};
2305 let Inst{20-16} = Rd;
2306 let Inst{13} = u8{4};
2307 let Inst{12-8} = U5;
2308 let Inst{7-5} = u8{3-1};
2309 let Inst{4} = asl_lsr;
2310 let Inst{3} = u8{0};
2311 let Inst{2-1} = MajOp;
2314 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2315 InstrItinClass Itin> {
2316 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2317 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2320 let AddedComplexity = 200, isCodeGenOnly = 0 in {
2321 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2322 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2325 let AddedComplexity = 30, isCodeGenOnly = 0 in
2326 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2328 let isCodeGenOnly = 0 in
2329 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2331 // Vector conditional negate
2332 // Rdd=vcnegh(Rss,Rt)
2333 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in
2334 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2336 // Rd=[cround|round](Rs,Rt)
2337 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in {
2338 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2339 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2342 // Rd=round(Rs,Rt):sat
2343 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23,
2344 isCodeGenOnly = 0 in
2345 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2347 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2348 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2349 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2350 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2353 // Rdd=[add|sub](Rss,Rtt,Px):carry
2354 let isPredicateLate = 1, hasSideEffects = 0 in
2355 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2356 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2357 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2358 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2359 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2365 let IClass = 0b1100;
2367 let Inst{27-24} = 0b0010;
2368 let Inst{23-21} = MajOp;
2369 let Inst{20-16} = Rss;
2370 let Inst{12-8} = Rtt;
2372 let Inst{4-0} = Rdd;
2375 let isCodeGenOnly = 0 in {
2376 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2377 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2380 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2381 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2382 : SInst <(outs DoubleRegs:$Rxx),
2383 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2384 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2385 [] , "$dst2 = $Rxx"> {
2390 let IClass = 0b1100;
2392 let Inst{27-21} = 0b1011001;
2393 let Inst{20-16} = Rss;
2394 let Inst{13} = isUnsigned;
2395 let Inst{12-8} = Rxx;
2396 let Inst{7-5} = MinOp;
2400 // Vector reduce maximum halfwords
2401 // Rxx=vrmax[u]h(Rss,Ru)
2402 let isCodeGenOnly = 0 in {
2403 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2404 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2406 // Vector reduce maximum words
2407 // Rxx=vrmax[u]w(Rss,Ru)
2408 let isCodeGenOnly = 0 in {
2409 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2410 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2412 // Vector reduce minimum halfwords
2413 // Rxx=vrmin[u]h(Rss,Ru)
2414 let isCodeGenOnly = 0 in {
2415 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2416 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2419 // Vector reduce minimum words
2420 // Rxx=vrmin[u]w(Rss,Ru)
2421 let isCodeGenOnly = 0 in {
2422 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2423 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2426 // Shift an immediate left by register amount.
2427 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
2428 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2429 "$Rd = lsl(#$s6, $Rt)" ,
2430 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2431 (i32 IntRegs:$Rt)))],
2432 "", S_3op_tc_1_SLOT23> {
2437 let IClass = 0b1100;
2439 let Inst{27-22} = 0b011010;
2440 let Inst{20-16} = s6{5-1};
2441 let Inst{12-8} = Rt;
2442 let Inst{7-6} = 0b11;
2444 let Inst{5} = s6{0};
2447 //===----------------------------------------------------------------------===//
2449 //===----------------------------------------------------------------------===//
2451 //===----------------------------------------------------------------------===//
2452 // MEMOP: Word, Half, Byte
2453 //===----------------------------------------------------------------------===//
2455 def MEMOPIMM : SDNodeXForm<imm, [{
2456 // Call the transformation function XformM5ToU5Imm to get the negative
2457 // immediate's positive counterpart.
2458 int32_t imm = N->getSExtValue();
2459 return XformM5ToU5Imm(imm);
2462 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2463 // -1 .. -31 represented as 65535..65515
2464 // assigning to a short restores our desired signed value.
2465 // Call the transformation function XformM5ToU5Imm to get the negative
2466 // immediate's positive counterpart.
2467 int16_t imm = N->getSExtValue();
2468 return XformM5ToU5Imm(imm);
2471 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2472 // -1 .. -31 represented as 255..235
2473 // assigning to a char restores our desired signed value.
2474 // Call the transformation function XformM5ToU5Imm to get the negative
2475 // immediate's positive counterpart.
2476 int8_t imm = N->getSExtValue();
2477 return XformM5ToU5Imm(imm);
2480 def SETMEMIMM : SDNodeXForm<imm, [{
2481 // Return the bit position we will set [0-31].
2483 int32_t imm = N->getSExtValue();
2484 return XformMskToBitPosU5Imm(imm);
2487 def CLRMEMIMM : SDNodeXForm<imm, [{
2488 // Return the bit position we will clear [0-31].
2490 // we bit negate the value first
2491 int32_t imm = ~(N->getSExtValue());
2492 return XformMskToBitPosU5Imm(imm);
2495 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2496 // Return the bit position we will set [0-15].
2498 int16_t imm = N->getSExtValue();
2499 return XformMskToBitPosU4Imm(imm);
2502 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2503 // Return the bit position we will clear [0-15].
2505 // we bit negate the value first
2506 int16_t imm = ~(N->getSExtValue());
2507 return XformMskToBitPosU4Imm(imm);
2510 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2511 // Return the bit position we will set [0-7].
2513 int8_t imm = N->getSExtValue();
2514 return XformMskToBitPosU3Imm(imm);
2517 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2518 // Return the bit position we will clear [0-7].
2520 // we bit negate the value first
2521 int8_t imm = ~(N->getSExtValue());
2522 return XformMskToBitPosU3Imm(imm);
2525 //===----------------------------------------------------------------------===//
2526 // Template class for MemOp instructions with the register value.
2527 //===----------------------------------------------------------------------===//
2528 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2529 string memOp, bits<2> memOpBits> :
2531 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2532 opc#"($base+#$offset)"#memOp#"$delta",
2534 Requires<[UseMEMOP]> {
2539 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2541 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2542 !if (!eq(opcBits, 0b01), offset{6-1},
2543 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2545 let opExtentAlign = opcBits;
2546 let IClass = 0b0011;
2547 let Inst{27-24} = 0b1110;
2548 let Inst{22-21} = opcBits;
2549 let Inst{20-16} = base;
2551 let Inst{12-7} = offsetBits;
2552 let Inst{6-5} = memOpBits;
2553 let Inst{4-0} = delta;
2556 //===----------------------------------------------------------------------===//
2557 // Template class for MemOp instructions with the immediate value.
2558 //===----------------------------------------------------------------------===//
2559 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2560 string memOp, bits<2> memOpBits> :
2562 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2563 opc#"($base+#$offset)"#memOp#"#$delta"
2564 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2566 Requires<[UseMEMOP]> {
2571 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2573 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2574 !if (!eq(opcBits, 0b01), offset{6-1},
2575 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2577 let opExtentAlign = opcBits;
2578 let IClass = 0b0011;
2579 let Inst{27-24} = 0b1111;
2580 let Inst{22-21} = opcBits;
2581 let Inst{20-16} = base;
2583 let Inst{12-7} = offsetBits;
2584 let Inst{6-5} = memOpBits;
2585 let Inst{4-0} = delta;
2588 // multiclass to define MemOp instructions with register operand.
2589 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2590 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2591 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2592 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2593 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2596 // multiclass to define MemOp instructions with immediate Operand.
2597 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2598 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2599 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2600 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2601 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2604 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2605 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2606 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2609 // Define MemOp instructions.
2610 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2611 validSubTargets =HasV4SubT in {
2612 let opExtentBits = 6, accessSize = ByteAccess, isCodeGenOnly = 0 in
2613 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2615 let opExtentBits = 7, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
2616 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2618 let opExtentBits = 8, accessSize = WordAccess, isCodeGenOnly = 0 in
2619 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2622 //===----------------------------------------------------------------------===//
2623 // Multiclass to define 'Def Pats' for ALU operations on the memory
2624 // Here value used for the ALU operation is an immediate value.
2625 // mem[bh](Rs+#0) += #U5
2626 // mem[bh](Rs+#u6) += #U5
2627 //===----------------------------------------------------------------------===//
2629 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2630 InstHexagon MI, SDNode OpNode> {
2631 let AddedComplexity = 180 in
2632 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2634 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2636 let AddedComplexity = 190 in
2637 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2639 (add IntRegs:$base, ExtPred:$offset)),
2640 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2643 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2644 InstHexagon addMI, InstHexagon subMI> {
2645 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2646 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2649 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2651 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2652 L4_iadd_memoph_io, L4_isub_memoph_io>;
2654 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2655 L4_iadd_memopb_io, L4_isub_memopb_io>;
2658 let Predicates = [HasV4T, UseMEMOP] in {
2659 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2660 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2661 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2664 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
2668 //===----------------------------------------------------------------------===//
2669 // multiclass to define 'Def Pats' for ALU operations on the memory.
2670 // Here value used for the ALU operation is a negative value.
2671 // mem[bh](Rs+#0) += #m5
2672 // mem[bh](Rs+#u6) += #m5
2673 //===----------------------------------------------------------------------===//
2675 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2676 PatLeaf immPred, ComplexPattern addrPred,
2677 SDNodeXForm xformFunc, InstHexagon MI> {
2678 let AddedComplexity = 190 in
2679 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2681 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2683 let AddedComplexity = 195 in
2684 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2686 (add IntRegs:$base, extPred:$offset)),
2687 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2690 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2692 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2693 ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>;
2695 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2696 ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>;
2699 let Predicates = [HasV4T, UseMEMOP] in {
2700 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2701 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2702 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2705 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2706 ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>;
2709 //===----------------------------------------------------------------------===//
2710 // Multiclass to define 'def Pats' for bit operations on the memory.
2711 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2712 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2713 //===----------------------------------------------------------------------===//
2715 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2716 PatLeaf extPred, ComplexPattern addrPred,
2717 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2719 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2720 let AddedComplexity = 250 in
2721 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2723 (add IntRegs:$base, extPred:$offset)),
2724 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2726 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2727 let AddedComplexity = 225 in
2728 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2730 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2731 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2734 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2736 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2737 ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
2739 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2740 ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
2741 // Half Word - clrbit
2742 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2743 ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
2744 // Half Word - setbit
2745 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2746 ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
2749 let Predicates = [HasV4T, UseMEMOP] in {
2750 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2751 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2752 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2753 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2754 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2756 // memw(Rs+#0) = [clrbit|setbit](#U5)
2757 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2758 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2759 CLRMEMIMM, L4_iand_memopw_io, and>;
2760 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2761 SETMEMIMM, L4_ior_memopw_io, or>;
2764 //===----------------------------------------------------------------------===//
2765 // Multiclass to define 'def Pats' for ALU operations on the memory
2766 // where addend is a register.
2767 // mem[bhw](Rs+#0) [+-&|]= Rt
2768 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2769 //===----------------------------------------------------------------------===//
2771 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2772 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2773 let AddedComplexity = 141 in
2774 // mem[bhw](Rs+#0) [+-&|]= Rt
2775 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2776 (i32 IntRegs:$addend)),
2777 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2778 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2780 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2781 let AddedComplexity = 150 in
2782 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2783 (i32 IntRegs:$orend)),
2784 (add IntRegs:$base, extPred:$offset)),
2785 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2788 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2789 ComplexPattern addrPred, PatLeaf extPred,
2790 InstHexagon addMI, InstHexagon subMI,
2791 InstHexagon andMI, InstHexagon orMI > {
2793 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2794 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2795 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2796 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2799 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2801 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2802 L4_add_memoph_io, L4_sub_memoph_io,
2803 L4_and_memoph_io, L4_or_memoph_io>;
2805 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2806 L4_add_memopb_io, L4_sub_memopb_io,
2807 L4_and_memopb_io, L4_or_memopb_io>;
2810 // Define 'def Pats' for MemOps with register addend.
2811 let Predicates = [HasV4T, UseMEMOP] in {
2813 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2814 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2815 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2817 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
2818 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io >;
2821 //===----------------------------------------------------------------------===//
2823 //===----------------------------------------------------------------------===//
2825 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2826 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2827 // hardware. However, compiler can still implement these patterns through
2828 // appropriate patterns combinations based on current implemented patterns.
2829 // The implemented patterns are: EQ/GT/GTU.
2830 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2832 // Following instruction is not being extended as it results into the
2833 // incorrect code for negative numbers.
2834 // Pd=cmpb.eq(Rs,#u8)
2836 // p=!cmp.eq(r1,#s10)
2837 let isCodeGenOnly = 0 in {
2838 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
2839 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
2840 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
2843 def : T_CMP_pat <C4_cmpneqi, setne, s10ExtPred>;
2844 def : T_CMP_pat <C4_cmpltei, setle, s10ExtPred>;
2845 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
2847 // rs <= rt -> !(rs > rt).
2849 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2850 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
2851 // (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
2853 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2854 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2855 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
2857 // rs != rt -> !(rs == rt).
2858 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2859 (C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
2861 // SDNode for converting immediate C to C-1.
2862 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2863 // Return the byte immediate const-1 as an SDNode.
2864 int32_t imm = N->getSExtValue();
2865 return XformU7ToU7M1Imm(imm);
2869 // zext( seteq ( and(Rs, 255), u8))
2871 // Pd=cmpb.eq(Rs, #u8)
2872 // if (Pd.new) Rd=#1
2873 // if (!Pd.new) Rd=#0
2874 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2876 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
2882 // zext( setne ( and(Rs, 255), u8))
2884 // Pd=cmpb.eq(Rs, #u8)
2885 // if (Pd.new) Rd=#0
2886 // if (!Pd.new) Rd=#1
2887 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2889 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
2895 // zext( seteq (Rs, and(Rt, 255)))
2897 // Pd=cmpb.eq(Rs, Rt)
2898 // if (Pd.new) Rd=#1
2899 // if (!Pd.new) Rd=#0
2900 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2901 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2902 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
2903 (i32 IntRegs:$Rt))),
2908 // zext( setne (Rs, and(Rt, 255)))
2910 // Pd=cmpb.eq(Rs, Rt)
2911 // if (Pd.new) Rd=#0
2912 // if (!Pd.new) Rd=#1
2913 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2914 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2915 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
2916 (i32 IntRegs:$Rt))),
2921 // zext( setugt ( and(Rs, 255), u8))
2923 // Pd=cmpb.gtu(Rs, #u8)
2924 // if (Pd.new) Rd=#1
2925 // if (!Pd.new) Rd=#0
2926 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2928 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
2934 // zext( setugt ( and(Rs, 254), u8))
2936 // Pd=cmpb.gtu(Rs, #u8)
2937 // if (Pd.new) Rd=#1
2938 // if (!Pd.new) Rd=#0
2939 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2941 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
2947 // zext( setult ( Rs, Rt))
2949 // Pd=cmp.ltu(Rs, Rt)
2950 // if (Pd.new) Rd=#1
2951 // if (!Pd.new) Rd=#0
2952 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2953 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2954 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2955 (i32 IntRegs:$Rs))),
2960 // zext( setlt ( Rs, Rt))
2962 // Pd=cmp.lt(Rs, Rt)
2963 // if (Pd.new) Rd=#1
2964 // if (!Pd.new) Rd=#0
2965 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2966 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2967 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2968 (i32 IntRegs:$Rs))),
2973 // zext( setugt ( Rs, Rt))
2975 // Pd=cmp.gtu(Rs, Rt)
2976 // if (Pd.new) Rd=#1
2977 // if (!Pd.new) Rd=#0
2978 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2979 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2980 (i32 IntRegs:$Rt))),
2984 // This pattern interefers with coremark performance, not implementing at this
2987 // zext( setgt ( Rs, Rt))
2989 // Pd=cmp.gt(Rs, Rt)
2990 // if (Pd.new) Rd=#1
2991 // if (!Pd.new) Rd=#0
2994 // zext( setuge ( Rs, Rt))
2996 // Pd=cmp.ltu(Rs, Rt)
2997 // if (Pd.new) Rd=#0
2998 // if (!Pd.new) Rd=#1
2999 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
3000 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3001 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
3002 (i32 IntRegs:$Rs))),
3007 // zext( setge ( Rs, Rt))
3009 // Pd=cmp.lt(Rs, Rt)
3010 // if (Pd.new) Rd=#0
3011 // if (!Pd.new) Rd=#1
3012 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3013 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3014 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
3015 (i32 IntRegs:$Rs))),
3020 // zext( setule ( Rs, Rt))
3022 // Pd=cmp.gtu(Rs, Rt)
3023 // if (Pd.new) Rd=#0
3024 // if (!Pd.new) Rd=#1
3025 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3026 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
3027 (i32 IntRegs:$Rt))),
3032 // zext( setle ( Rs, Rt))
3034 // Pd=cmp.gt(Rs, Rt)
3035 // if (Pd.new) Rd=#0
3036 // if (!Pd.new) Rd=#1
3037 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3038 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
3039 (i32 IntRegs:$Rt))),
3044 // zext( setult ( and(Rs, 255), u8))
3045 // Use the isdigit transformation below
3047 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
3048 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3049 // The isdigit transformation relies on two 'clever' aspects:
3050 // 1) The data type is unsigned which allows us to eliminate a zero test after
3051 // biasing the expression by 48. We are depending on the representation of
3052 // the unsigned types, and semantics.
3053 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3056 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3057 // The code is transformed upstream of llvm into
3058 // retval = (c-48) < 10 ? 1 : 0;
3059 let AddedComplexity = 139 in
3060 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3061 u7StrictPosImmPred:$src2)))),
3062 (i32 (C2_muxii (i1 (A4_cmpbgtui (i32 IntRegs:$src1),
3063 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
3067 //===----------------------------------------------------------------------===//
3069 //===----------------------------------------------------------------------===//
3071 //===----------------------------------------------------------------------===//
3072 // Multiclass for DeallocReturn
3073 //===----------------------------------------------------------------------===//
3074 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3075 : LD0Inst<(outs), (ins PredRegs:$src),
3076 !if(isNot, "if (!$src", "if ($src")#
3077 !if(isPredNew, ".new) ", ") ")#mnemonic#
3078 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3079 [], "", LD_tc_3or4stall_SLOT0> {
3082 let BaseOpcode = "L4_RETURN";
3083 let isPredicatedFalse = isNot;
3084 let isPredicatedNew = isPredNew;
3085 let isTaken = isTak;
3086 let IClass = 0b1001;
3088 let Inst{27-16} = 0b011000011110;
3090 let Inst{13} = isNot;
3091 let Inst{12} = isTak;
3092 let Inst{11} = isPredNew;
3094 let Inst{9-8} = src;
3095 let Inst{4-0} = 0b11110;
3098 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3099 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3100 let isPredicated = 1 in {
3101 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3102 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3103 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3107 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3108 let isBarrier = 1, isPredicable = 1 in
3109 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3110 LD_tc_3or4stall_SLOT0> {
3111 let BaseOpcode = "L4_RETURN";
3112 let IClass = 0b1001;
3113 let Inst{27-16} = 0b011000011110;
3114 let Inst{13-10} = 0b0000;
3115 let Inst{4-0} = 0b11110;
3117 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3118 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3121 let isReturn = 1, isTerminator = 1,
3122 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3123 validSubTargets = HasV4SubT, isCodeGenOnly = 0 in
3124 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3126 // Restore registers and dealloc return function call.
3127 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3128 Defs = [R29, R30, R31, PC] in {
3129 let validSubTargets = HasV4SubT in
3130 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
3131 (ins calltarget:$dst),
3137 // Restore registers and dealloc frame before a tail call.
3138 let isCall = 1, isBarrier = 1,
3139 Defs = [R29, R30, R31, PC] in {
3140 let validSubTargets = HasV4SubT in
3141 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3142 (ins calltarget:$dst),
3148 // Save registers function call.
3149 let isCall = 1, isBarrier = 1,
3150 Uses = [R29, R31] in {
3151 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3152 (ins calltarget:$dst),
3153 "call $dst // Save_calle_saved_registers",
3158 //===----------------------------------------------------------------------===//
3159 // Template class for non predicated store instructions with
3160 // GP-Relative or absolute addressing.
3161 //===----------------------------------------------------------------------===//
3162 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3163 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3164 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3165 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3166 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3167 [], "", V2LDST_tc_st_SLOT01> {
3170 bits<16> offsetBits;
3172 string ImmOpStr = !cast<string>(ImmOp);
3173 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3174 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3175 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3176 /* u16_0Imm */ addr{15-0})));
3177 let IClass = 0b0100;
3179 let Inst{26-25} = offsetBits{15-14};
3181 let Inst{23-22} = MajOp;
3182 let Inst{21} = isHalf;
3183 let Inst{20-16} = offsetBits{13-9};
3184 let Inst{13} = offsetBits{8};
3185 let Inst{12-8} = src;
3186 let Inst{7-0} = offsetBits{7-0};
3189 //===----------------------------------------------------------------------===//
3190 // Template class for predicated store instructions with
3191 // GP-Relative or absolute addressing.
3192 //===----------------------------------------------------------------------===//
3193 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3195 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3196 bit isHalf, bit isNot, bit isNew>
3197 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3198 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3199 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3200 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3205 let isPredicatedNew = isNew;
3206 let isPredicatedFalse = isNot;
3208 let IClass = 0b1010;
3210 let Inst{27-24} = 0b1111;
3211 let Inst{23-22} = MajOp;
3212 let Inst{21} = isHalf;
3213 let Inst{17-16} = absaddr{5-4};
3214 let Inst{13} = isNew;
3215 let Inst{12-8} = src2;
3217 let Inst{6-3} = absaddr{3-0};
3218 let Inst{2} = isNot;
3219 let Inst{1-0} = src1;
3222 //===----------------------------------------------------------------------===//
3223 // Template class for predicated store instructions with absolute addressing.
3224 //===----------------------------------------------------------------------===//
3225 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3226 bits<2> MajOp, bit isHalf>
3227 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1, isHalf>,
3229 string ImmOpStr = !cast<string>(ImmOp);
3230 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3231 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3232 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3233 /* u16_0Imm */ 16)));
3235 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3236 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3237 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3238 /* u16_0Imm */ 0)));
3241 //===----------------------------------------------------------------------===//
3242 // Multiclass for store instructions with absolute addressing.
3243 //===----------------------------------------------------------------------===//
3244 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3245 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3246 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3247 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3248 let opExtendable = 0, isPredicable = 1 in
3249 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3252 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3253 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3256 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3257 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3261 //===----------------------------------------------------------------------===//
3262 // Template class for non predicated new-value store instructions with
3263 // GP-Relative or absolute addressing.
3264 //===----------------------------------------------------------------------===//
3265 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3266 isNewValue = 1, opNewValue = 1 in
3267 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3268 : NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
3269 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3270 [], "", V2LDST_tc_st_SLOT0> {
3273 bits<16> offsetBits;
3275 string ImmOpStr = !cast<string>(ImmOp);
3276 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3277 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3278 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3279 /* u16_0Imm */ addr{15-0})));
3280 let IClass = 0b0100;
3283 let Inst{26-25} = offsetBits{15-14};
3284 let Inst{24-21} = 0b0101;
3285 let Inst{20-16} = offsetBits{13-9};
3286 let Inst{13} = offsetBits{8};
3287 let Inst{12-11} = MajOp;
3288 let Inst{10-8} = src;
3289 let Inst{7-0} = offsetBits{7-0};
3292 //===----------------------------------------------------------------------===//
3293 // Template class for predicated new-value store instructions with
3294 // absolute addressing.
3295 //===----------------------------------------------------------------------===//
3296 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3297 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3298 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3299 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3300 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3301 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3302 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3307 let isPredicatedNew = isNew;
3308 let isPredicatedFalse = isNot;
3310 let IClass = 0b1010;
3312 let Inst{27-24} = 0b1111;
3313 let Inst{23-21} = 0b101;
3314 let Inst{17-16} = absaddr{5-4};
3315 let Inst{13} = isNew;
3316 let Inst{12-11} = MajOp;
3317 let Inst{10-8} = src2;
3319 let Inst{6-3} = absaddr{3-0};
3320 let Inst{2} = isNot;
3321 let Inst{1-0} = src1;
3324 //===----------------------------------------------------------------------===//
3325 // Template class for non-predicated new-value store instructions with
3326 // absolute addressing.
3327 //===----------------------------------------------------------------------===//
3328 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3329 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3331 string ImmOpStr = !cast<string>(ImmOp);
3332 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3333 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3334 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3335 /* u16_0Imm */ 16)));
3337 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3338 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3339 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3340 /* u16_0Imm */ 0)));
3343 //===----------------------------------------------------------------------===//
3344 // Multiclass for new-value store instructions with absolute addressing.
3345 //===----------------------------------------------------------------------===//
3346 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3347 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3349 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3350 let opExtendable = 0, isPredicable = 1 in
3351 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3354 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3355 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3358 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3359 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3363 //===----------------------------------------------------------------------===//
3364 // Stores with absolute addressing
3365 //===----------------------------------------------------------------------===//
3366 let accessSize = ByteAccess, isCodeGenOnly = 0 in
3367 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3368 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3370 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3371 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3372 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3374 let accessSize = WordAccess, isCodeGenOnly = 0 in
3375 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3376 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3378 let isNVStorable = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3379 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3381 let isNVStorable = 0, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3382 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3384 //===----------------------------------------------------------------------===//
3385 // GP-relative stores.
3386 // mem[bhwd](#global)=Rt
3387 // Once predicated, these instructions map to absolute addressing mode.
3388 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3389 //===----------------------------------------------------------------------===//
3391 let validSubTargets = HasV4SubT in
3392 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3393 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3394 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3395 // Set BaseOpcode same as absolute addressing instructions so that
3396 // non-predicated GP-Rel instructions can have relate with predicated
3397 // Absolute instruction.
3398 let BaseOpcode = BaseOp#_abs;
3401 let validSubTargets = HasV4SubT in
3402 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3403 bits<2> MajOp, bit isHalf = 0> {
3404 // Set BaseOpcode same as absolute addressing instructions so that
3405 // non-predicated GP-Rel instructions can have relate with predicated
3406 // Absolute instruction.
3407 let BaseOpcode = BaseOp#_abs in {
3408 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3409 globaladdress, 0, isHalf>;
3411 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3415 let accessSize = ByteAccess in
3416 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3418 let accessSize = HalfWordAccess in
3419 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3421 let accessSize = WordAccess in
3422 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3424 let isNVStorable = 0, accessSize = DoubleWordAccess in
3425 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3426 u16_3Imm, 0b11>, PredNewRel;
3428 let isNVStorable = 0, accessSize = HalfWordAccess in
3429 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3430 u16_1Imm, 0b01, 1>, PredNewRel;
3432 let Predicates = [HasV4T], AddedComplexity = 30 in {
3433 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3434 (HexagonCONST32 tglobaladdr:$absaddr)),
3435 (S2_storerbabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3437 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3438 (HexagonCONST32 tglobaladdr:$absaddr)),
3439 (S2_storerhabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3441 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3442 (S2_storeriabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3444 def : Pat<(store (i64 DoubleRegs:$src1),
3445 (HexagonCONST32 tglobaladdr:$absaddr)),
3446 (S2_storerdabs tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3449 // 64 bit atomic store
3450 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3451 (i64 DoubleRegs:$src1)),
3452 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3455 // Map from store(globaladdress) -> memd(#foo)
3456 let AddedComplexity = 100 in
3457 def : Pat <(store (i64 DoubleRegs:$src1),
3458 (HexagonCONST32_GP tglobaladdr:$global)),
3459 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3461 // 8 bit atomic store
3462 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3463 (i32 IntRegs:$src1)),
3464 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3466 // Map from store(globaladdress) -> memb(#foo)
3467 let AddedComplexity = 100 in
3468 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3469 (HexagonCONST32_GP tglobaladdr:$global)),
3470 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3472 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3473 // to "r0 = 1; memw(#foo) = r0"
3474 let AddedComplexity = 100 in
3475 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3476 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3478 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3479 (i32 IntRegs:$src1)),
3480 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3482 // Map from store(globaladdress) -> memh(#foo)
3483 let AddedComplexity = 100 in
3484 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3485 (HexagonCONST32_GP tglobaladdr:$global)),
3486 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3488 // 32 bit atomic store
3489 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3490 (i32 IntRegs:$src1)),
3491 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3493 // Map from store(globaladdress) -> memw(#foo)
3494 let AddedComplexity = 100 in
3495 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3496 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3498 //===----------------------------------------------------------------------===//
3499 // Template class for non predicated load instructions with
3500 // absolute addressing mode.
3501 //===----------------------------------------------------------------------===//
3502 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT in
3503 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3504 bits<3> MajOp, Operand AddrOp, bit isAbs>
3505 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3506 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3507 [], "", V2LDST_tc_ld_SLOT01> {
3510 bits<16> offsetBits;
3512 string ImmOpStr = !cast<string>(ImmOp);
3513 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3514 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3515 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3516 /* u16_0Imm */ addr{15-0})));
3518 let IClass = 0b0100;
3521 let Inst{26-25} = offsetBits{15-14};
3523 let Inst{23-21} = MajOp;
3524 let Inst{20-16} = offsetBits{13-9};
3525 let Inst{13-5} = offsetBits{8-0};
3526 let Inst{4-0} = dst;
3529 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3531 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1>, AddrModeRel {
3533 string ImmOpStr = !cast<string>(ImmOp);
3534 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3535 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3536 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3537 /* u16_0Imm */ 16)));
3539 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3540 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3541 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3542 /* u16_0Imm */ 0)));
3544 //===----------------------------------------------------------------------===//
3545 // Template class for predicated load instructions with
3546 // absolute addressing mode.
3547 //===----------------------------------------------------------------------===//
3548 let isPredicated = 1, hasNewValue = 1, opExtentBits = 6, opExtendable = 2 in
3549 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3550 bit isPredNot, bit isPredNew>
3551 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3552 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3553 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3558 let isPredicatedNew = isPredNew;
3559 let isPredicatedFalse = isPredNot;
3561 let IClass = 0b1001;
3563 let Inst{27-24} = 0b1111;
3564 let Inst{23-21} = MajOp;
3565 let Inst{20-16} = absaddr{5-1};
3567 let Inst{12} = isPredNew;
3568 let Inst{11} = isPredNot;
3569 let Inst{10-9} = src1;
3570 let Inst{8} = absaddr{0};
3572 let Inst{4-0} = dst;
3575 //===----------------------------------------------------------------------===//
3576 // Multiclass for the load instructions with absolute addressing mode.
3577 //===----------------------------------------------------------------------===//
3578 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3580 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3582 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3585 let addrMode = Absolute, isExtended = 1 in
3586 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3587 Operand ImmOp, bits<3> MajOp> {
3588 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3589 let opExtendable = 1, isPredicable = 1 in
3590 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3593 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3594 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3598 let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3599 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3600 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3603 let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3604 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3605 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3608 let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
3609 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3611 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3612 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3614 //===----------------------------------------------------------------------===//
3615 // multiclass for load instructions with GP-relative addressing mode.
3616 // Rx=mem[bhwd](##global)
3617 // Once predicated, these instructions map to absolute addressing mode.
3618 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3619 //===----------------------------------------------------------------------===//
3621 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3623 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3624 let BaseOpcode = BaseOp#_abs;
3627 let accessSize = ByteAccess, hasNewValue = 1 in {
3628 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3629 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3632 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3633 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3634 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3637 let accessSize = WordAccess, hasNewValue = 1 in
3638 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3640 let accessSize = DoubleWordAccess in
3641 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3643 let Predicates = [HasV4T], AddedComplexity = 30 in {
3644 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3645 (L4_loadri_abs tglobaladdr: $absaddr)>;
3647 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3648 (L4_loadrb_abs tglobaladdr:$absaddr)>;
3650 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3651 (L4_loadrub_abs tglobaladdr:$absaddr)>;
3653 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3654 (L4_loadrh_abs tglobaladdr:$absaddr)>;
3656 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3657 (L4_loadruh_abs tglobaladdr:$absaddr)>;
3660 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3661 (i64 (L2_loadrdgp tglobaladdr:$global))>;
3663 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3664 (i32 (L2_loadrigp tglobaladdr:$global))>;
3666 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3667 (i32 (L2_loadruhgp tglobaladdr:$global))>;
3669 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3670 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3672 // Map from load(globaladdress) -> memw(#foo + 0)
3673 let AddedComplexity = 100 in
3674 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3675 (i64 (L2_loadrdgp tglobaladdr:$global))>;
3677 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3678 let AddedComplexity = 100 in
3679 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3680 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3682 // When the Interprocedural Global Variable optimizer realizes that a certain
3683 // global variable takes only two constant values, it shrinks the global to
3684 // a boolean. Catch those loads here in the following 3 patterns.
3685 let AddedComplexity = 100 in
3686 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3687 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3689 let AddedComplexity = 100 in
3690 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3691 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3693 // Map from load(globaladdress) -> memb(#foo)
3694 let AddedComplexity = 100 in
3695 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3696 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3698 // Map from load(globaladdress) -> memb(#foo)
3699 let AddedComplexity = 100 in
3700 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3701 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3703 let AddedComplexity = 100 in
3704 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3705 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3707 // Map from load(globaladdress) -> memub(#foo)
3708 let AddedComplexity = 100 in
3709 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3710 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3712 // Map from load(globaladdress) -> memh(#foo)
3713 let AddedComplexity = 100 in
3714 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3715 (i32 (L2_loadrhgp tglobaladdr:$global))>;
3717 // Map from load(globaladdress) -> memh(#foo)
3718 let AddedComplexity = 100 in
3719 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3720 (i32 (L2_loadrhgp tglobaladdr:$global))>;
3722 // Map from load(globaladdress) -> memuh(#foo)
3723 let AddedComplexity = 100 in
3724 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3725 (i32 (L2_loadruhgp tglobaladdr:$global))>;
3727 // Map from load(globaladdress) -> memw(#foo)
3728 let AddedComplexity = 100 in
3729 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3730 (i32 (L2_loadrigp tglobaladdr:$global))>;
3733 // Transfer global address into a register
3734 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3735 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3736 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3738 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3741 // Transfer a block address into a register
3742 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3743 (TFRI_V4 tblockaddress:$src1)>,
3746 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3747 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3748 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3749 (ins PredRegs:$src1, s16Ext:$src2),
3750 "if($src1) $dst = #$src2",
3754 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3755 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3756 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3757 (ins PredRegs:$src1, s16Ext:$src2),
3758 "if(!$src1) $dst = #$src2",
3762 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3763 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3764 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3765 (ins PredRegs:$src1, s16Ext:$src2),
3766 "if($src1.new) $dst = #$src2",
3770 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3771 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3772 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3773 (ins PredRegs:$src1, s16Ext:$src2),
3774 "if(!$src1.new) $dst = #$src2",
3778 let AddedComplexity = 50, Predicates = [HasV4T] in
3779 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3780 (TFRI_V4 tglobaladdr:$src1)>,
3784 // Load - Indirect with long offset: These instructions take global address
3786 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3787 validSubTargets = HasV4SubT in
3788 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3789 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3790 "$dst=memd($src1<<#$src2+##$offset)",
3791 [(set (i64 DoubleRegs:$dst),
3792 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3793 (HexagonCONST32 tglobaladdr:$offset))))]>,
3796 let AddedComplexity = 40 in
3797 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3798 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3799 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3800 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3801 !strconcat("$dst = ",
3802 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3804 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3805 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3809 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3810 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3811 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3812 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3813 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3814 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3815 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3817 let AddedComplexity = 40 in
3818 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3819 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3820 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3823 let AddedComplexity = 40 in
3824 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3825 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3826 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3829 let Predicates = [HasV4T], AddedComplexity = 30 in {
3830 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3831 (S2_storerbabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3833 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3834 (S2_storerhabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3836 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3837 (S2_storeriabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3840 let Predicates = [HasV4T], AddedComplexity = 30 in {
3841 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3842 (L4_loadri_abs u0AlwaysExtPred:$src)>;
3844 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3845 (L4_loadrb_abs u0AlwaysExtPred:$src)>;
3847 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3848 (L4_loadrub_abs u0AlwaysExtPred:$src)>;
3850 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3851 (L4_loadrh_abs u0AlwaysExtPred:$src)>;
3853 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3854 (L4_loadruh_abs u0AlwaysExtPred:$src)>;
3857 // Indexed store word - global address.
3858 // memw(Rs+#u6:2)=#S8
3859 let AddedComplexity = 10 in
3860 def STriw_offset_ext_V4 : STInst<(outs),
3861 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3862 "memw($src1+#$src2) = ##$src3",
3863 [(store (HexagonCONST32 tglobaladdr:$src3),
3864 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3867 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3868 (i64 (A4_combineir (i32 0), (i32 (S2_cl0p DoubleRegs:$src1))))>,
3871 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3872 (i64 (A4_combineir (i32 0), (i32 (S2_ct0p DoubleRegs:$src1))))>,
3877 // We need a complexity of 120 here to override preceding handling of
3879 let Predicates = [HasV4T], AddedComplexity = 120 in {
3880 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3881 (i64 (A4_combineir 0, (L4_loadrb_abs tglobaladdr:$addr)))>;
3883 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3884 (i64 (A4_combineir 0, (L4_loadrub_abs tglobaladdr:$addr)))>;
3886 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3887 (i64 (A2_sxtw (L4_loadrb_abs tglobaladdr:$addr)))>;
3889 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3890 (i64 (A4_combineir 0, (L4_loadrb_abs FoldGlobalAddr:$addr)))>;
3892 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3893 (i64 (A4_combineir 0, (L4_loadrub_abs FoldGlobalAddr:$addr)))>;
3895 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3896 (i64 (A2_sxtw (L4_loadrb_abs FoldGlobalAddr:$addr)))>;
3899 // We need a complexity of 120 here to override preceding handling of
3901 let AddedComplexity = 120 in {
3902 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3903 (i64 (A4_combineir 0, (L4_loadrh_abs tglobaladdr:$addr)))>,
3906 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3907 (i64 (A4_combineir 0, (L4_loadruh_abs tglobaladdr:$addr)))>,
3910 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3911 (i64 (A2_sxtw (L4_loadrh_abs tglobaladdr:$addr)))>,
3914 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3915 (i64 (A4_combineir 0, (L4_loadrh_abs FoldGlobalAddr:$addr)))>,
3918 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3919 (i64 (A4_combineir 0, (L4_loadruh_abs FoldGlobalAddr:$addr)))>,
3922 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3923 (i64 (A2_sxtw (L4_loadrh_abs FoldGlobalAddr:$addr)))>,
3927 // We need a complexity of 120 here to override preceding handling of
3929 let AddedComplexity = 120 in {
3930 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3931 (i64 (A4_combineir 0, (L4_loadri_abs tglobaladdr:$addr)))>,
3934 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3935 (i64 (A4_combineir 0, (L4_loadri_abs tglobaladdr:$addr)))>,
3938 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3939 (i64 (A2_sxtw (L4_loadri_abs tglobaladdr:$addr)))>,
3942 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3943 (i64 (A4_combineir 0, (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3946 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3947 (i64 (A4_combineir 0, (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3950 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3951 (i64 (A2_sxtw (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3955 // Indexed store double word - global address.
3956 // memw(Rs+#u6:2)=#S8
3957 let AddedComplexity = 10 in
3958 def STrih_offset_ext_V4 : STInst<(outs),
3959 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3960 "memh($src1+#$src2) = ##$src3",
3961 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3962 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3964 // Map from store(globaladdress + x) -> memd(#foo + x)
3965 let AddedComplexity = 100 in
3966 def : Pat<(store (i64 DoubleRegs:$src1),
3967 FoldGlobalAddrGP:$addr),
3968 (S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3971 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3972 (i64 DoubleRegs:$src1)),
3973 (S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3976 // Map from store(globaladdress + x) -> memb(#foo + x)
3977 let AddedComplexity = 100 in
3978 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3979 (S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3982 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3983 (S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3986 // Map from store(globaladdress + x) -> memh(#foo + x)
3987 let AddedComplexity = 100 in
3988 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3989 (S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3992 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3993 (S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3996 // Map from store(globaladdress + x) -> memw(#foo + x)
3997 let AddedComplexity = 100 in
3998 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3999 (S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4002 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
4003 (S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4006 // Map from load(globaladdress + x) -> memd(#foo + x)
4007 let AddedComplexity = 100 in
4008 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
4009 (i64 (L4_loadrd_abs FoldGlobalAddrGP:$addr))>,
4012 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
4013 (i64 (L4_loadrd_abs FoldGlobalAddrGP:$addr))>,
4016 // Map from load(globaladdress + x) -> memb(#foo + x)
4017 let AddedComplexity = 100 in
4018 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
4019 (i32 (L4_loadrb_abs FoldGlobalAddrGP:$addr))>,
4022 // Map from load(globaladdress + x) -> memb(#foo + x)
4023 let AddedComplexity = 100 in
4024 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
4025 (i32 (L4_loadrb_abs FoldGlobalAddrGP:$addr))>,
4028 //let AddedComplexity = 100 in
4029 let AddedComplexity = 100 in
4030 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
4031 (i32 (L4_loadrh_abs FoldGlobalAddrGP:$addr))>,
4034 // Map from load(globaladdress + x) -> memh(#foo + x)
4035 let AddedComplexity = 100 in
4036 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
4037 (i32 (L4_loadrh_abs FoldGlobalAddrGP:$addr))>,
4040 // Map from load(globaladdress + x) -> memuh(#foo + x)
4041 let AddedComplexity = 100 in
4042 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
4043 (i32 (L4_loadruh_abs FoldGlobalAddrGP:$addr))>,
4046 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
4047 (i32 (L4_loadruh_abs FoldGlobalAddrGP:$addr))>,
4050 // Map from load(globaladdress + x) -> memub(#foo + x)
4051 let AddedComplexity = 100 in
4052 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
4053 (i32 (L4_loadrub_abs FoldGlobalAddrGP:$addr))>,
4056 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
4057 (i32 (L4_loadrub_abs FoldGlobalAddrGP:$addr))>,
4060 // Map from load(globaladdress + x) -> memw(#foo + x)
4061 let AddedComplexity = 100 in
4062 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
4063 (i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>,
4066 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
4067 (i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>,
4070 //===----------------------------------------------------------------------===//
4071 // :raw for of boundscheck:hi:lo insns
4072 //===----------------------------------------------------------------------===//
4074 // A4_boundscheck_lo: Detect if a register is within bounds.
4075 let hasSideEffects = 0, isCodeGenOnly = 0 in
4076 def A4_boundscheck_lo: ALU64Inst <
4077 (outs PredRegs:$Pd),
4078 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
4079 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
4084 let IClass = 0b1101;
4086 let Inst{27-23} = 0b00100;
4088 let Inst{7-5} = 0b100;
4090 let Inst{20-16} = Rss;
4091 let Inst{12-8} = Rtt;
4094 // A4_boundscheck_hi: Detect if a register is within bounds.
4095 let hasSideEffects = 0, isCodeGenOnly = 0 in
4096 def A4_boundscheck_hi: ALU64Inst <
4097 (outs PredRegs:$Pd),
4098 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
4099 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
4104 let IClass = 0b1101;
4106 let Inst{27-23} = 0b00100;
4108 let Inst{7-5} = 0b101;
4110 let Inst{20-16} = Rss;
4111 let Inst{12-8} = Rtt;
4114 let hasSideEffects = 0 in
4115 def A4_boundscheck : MInst <
4116 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
4117 "$Pd=boundscheck($Rs,$Rtt)">;
4119 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
4120 let isPredicateLate = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
4121 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
4122 (ins DoubleRegs:$Rs, IntRegs:$Rt),
4123 "$Pd = tlbmatch($Rs, $Rt)",
4124 [], "", ALU64_tc_2early_SLOT23> {
4129 let IClass = 0b1101;
4130 let Inst{27-23} = 0b00100;
4131 let Inst{20-16} = Rs;
4133 let Inst{12-8} = Rt;
4134 let Inst{7-5} = 0b011;
4138 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
4139 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
4140 // We don't really want either one here.
4141 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
4142 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
4145 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
4146 // really do a load.
4147 let hasSideEffects = 1, mayLoad = 0, isCodeGenOnly = 0 in
4148 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
4149 "dcfetch($Rs + #$u11_3)",
4150 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
4151 "", LD_tc_ld_SLOT0> {
4155 let IClass = 0b1001;
4156 let Inst{27-21} = 0b0100000;
4157 let Inst{20-16} = Rs;
4159 let Inst{10-0} = u11_3{13-3};
4162 //===----------------------------------------------------------------------===//
4163 // Compound instructions
4164 //===----------------------------------------------------------------------===//
4166 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4167 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4168 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4169 isTerminator = 1, validSubTargets = HasV4SubT in
4170 class CJInst_tstbit_R0<string px, bit np, string tnt>
4171 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4172 ""#px#" = tstbit($Rs, #0); if ("
4173 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4174 [], "", COMPOUND, TypeCOMPOUND> {
4179 let isPredicatedFalse = np;
4180 // tnt: Taken/Not Taken
4181 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4182 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4184 let IClass = 0b0001;
4185 let Inst{27-26} = 0b00;
4186 let Inst{25} = !if (!eq(px, "!p1"), 1,
4187 !if (!eq(px, "p1"), 1, 0));
4188 let Inst{24-23} = 0b11;
4190 let Inst{21-20} = r9_2{10-9};
4191 let Inst{19-16} = Rs;
4192 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4193 let Inst{9-8} = 0b11;
4194 let Inst{7-1} = r9_2{8-2};
4197 let Defs = [PC, P0], Uses = [P0], isCodeGenOnly = 0 in {
4198 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4199 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4200 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4201 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4204 let Defs = [PC, P1], Uses = [P1], isCodeGenOnly = 0 in {
4205 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4206 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4207 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4208 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4212 let isBranch = 1, hasSideEffects = 0,
4213 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4214 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4215 opExtendable = 2, isTerminator = 1, validSubTargets = HasV4SubT in
4216 class CJInst_RR<string px, string op, bit np, string tnt>
4217 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4218 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4219 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4220 [], "", COMPOUND, TypeCOMPOUND> {
4226 let isPredicatedFalse = np;
4227 // tnt: Taken/Not Taken
4228 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4229 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4231 let IClass = 0b0001;
4232 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4233 !if (!eq(op, "gt"), 0b01001,
4234 !if (!eq(op, "gtu"), 0b01010, 0)));
4236 let Inst{21-20} = r9_2{10-9};
4237 let Inst{19-16} = Rs;
4238 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4239 // px: Predicate reg 0/1
4240 let Inst{12} = !if (!eq(px, "!p1"), 1,
4241 !if (!eq(px, "p1"), 1, 0));
4242 let Inst{11-8} = Rt;
4243 let Inst{7-1} = r9_2{8-2};
4246 // P[10] taken/not taken.
4247 multiclass T_tnt_CJInst_RR<string op, bit np> {
4248 let Defs = [PC, P0], Uses = [P0] in {
4249 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4250 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4252 let Defs = [PC, P1], Uses = [P1] in {
4253 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4254 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4257 // Predicate / !Predicate
4258 multiclass T_pnp_CJInst_RR<string op>{
4259 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4260 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4262 // TypeCJ Instructions compare RR and jump
4263 let isCodeGenOnly = 0 in {
4264 defm eq : T_pnp_CJInst_RR<"eq">;
4265 defm gt : T_pnp_CJInst_RR<"gt">;
4266 defm gtu : T_pnp_CJInst_RR<"gtu">;
4269 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4270 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4271 opExtentAlign = 2, opExtendable = 2, isTerminator = 1,
4272 validSubTargets = HasV4SubT in
4273 class CJInst_RU5<string px, string op, bit np, string tnt>
4274 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4275 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4276 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4277 [], "", COMPOUND, TypeCOMPOUND> {
4283 let isPredicatedFalse = np;
4284 // tnt: Taken/Not Taken
4285 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4286 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4288 let IClass = 0b0001;
4289 let Inst{27-26} = 0b00;
4290 // px: Predicate reg 0/1
4291 let Inst{25} = !if (!eq(px, "!p1"), 1,
4292 !if (!eq(px, "p1"), 1, 0));
4293 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4294 !if (!eq(op, "gt"), 0b01,
4295 !if (!eq(op, "gtu"), 0b10, 0)));
4297 let Inst{21-20} = r9_2{10-9};
4298 let Inst{19-16} = Rs;
4299 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4300 let Inst{12-8} = U5;
4301 let Inst{7-1} = r9_2{8-2};
4303 // P[10] taken/not taken.
4304 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4305 let Defs = [PC, P0], Uses = [P0] in {
4306 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4307 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4309 let Defs = [PC, P1], Uses = [P1] in {
4310 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4311 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4314 // Predicate / !Predicate
4315 multiclass T_pnp_CJInst_RU5<string op>{
4316 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4317 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4319 // TypeCJ Instructions compare RI and jump
4320 let isCodeGenOnly = 0 in {
4321 defm eq : T_pnp_CJInst_RU5<"eq">;
4322 defm gt : T_pnp_CJInst_RU5<"gt">;
4323 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4326 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4327 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4328 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4329 isTerminator = 1, validSubTargets = HasV4SubT in
4330 class CJInst_Rn1<string px, string op, bit np, string tnt>
4331 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4332 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4333 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4334 [], "", COMPOUND, TypeCOMPOUND> {
4339 let isPredicatedFalse = np;
4340 // tnt: Taken/Not Taken
4341 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4342 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4344 let IClass = 0b0001;
4345 let Inst{27-26} = 0b00;
4346 let Inst{25} = !if (!eq(px, "!p1"), 1,
4347 !if (!eq(px, "p1"), 1, 0));
4349 let Inst{24-23} = 0b11;
4351 let Inst{21-20} = r9_2{10-9};
4352 let Inst{19-16} = Rs;
4353 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4354 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4355 !if (!eq(op, "gt"), 0b01, 0));
4356 let Inst{7-1} = r9_2{8-2};
4359 // P[10] taken/not taken.
4360 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4361 let Defs = [PC, P0], Uses = [P0] in {
4362 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4363 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4365 let Defs = [PC, P1], Uses = [P1] in {
4366 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4367 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4370 // Predicate / !Predicate
4371 multiclass T_pnp_CJInst_Rn1<string op>{
4372 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4373 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4375 // TypeCJ Instructions compare -1 and jump
4376 let isCodeGenOnly = 0 in {
4377 defm eq : T_pnp_CJInst_Rn1<"eq">;
4378 defm gt : T_pnp_CJInst_Rn1<"gt">;
4381 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4382 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4383 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4384 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4385 isCodeGenOnly = 0 in
4386 def J4_jumpseti: CJInst <
4388 (ins u6Imm:$U6, brtarget:$r9_2),
4389 "$Rd = #$U6 ; jump $r9_2"> {
4394 let IClass = 0b0001;
4395 let Inst{27-24} = 0b0110;
4396 let Inst{21-20} = r9_2{10-9};
4397 let Inst{19-16} = Rd;
4398 let Inst{13-8} = U6;
4399 let Inst{7-1} = r9_2{8-2};
4402 // J4_jumpsetr: Direct unconditional jump and transfer register.
4403 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4404 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4405 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4406 isCodeGenOnly = 0 in
4407 def J4_jumpsetr: CJInst <
4409 (ins IntRegs:$Rs, brtarget:$r9_2),
4410 "$Rd = $Rs ; jump $r9_2"> {
4415 let IClass = 0b0001;
4416 let Inst{27-24} = 0b0111;
4417 let Inst{21-20} = r9_2{10-9};
4418 let Inst{11-8} = Rd;
4419 let Inst{19-16} = Rs;
4420 let Inst{7-1} = r9_2{8-2};