1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let hasSideEffects = 0 in
15 class T_Immext<Operand ImmType>
16 : EXTENDERInst<(outs), (ins ImmType:$imm),
17 "immext(#$imm)", []> {
21 let Inst{27-16} = imm{31-20};
22 let Inst{13-0} = imm{19-6};
25 def A4_ext : T_Immext<u26_6Imm>;
26 let isCodeGenOnly = 1 in {
28 def A4_ext_b : T_Immext<brtarget>;
30 def A4_ext_c : T_Immext<calltarget>;
31 def A4_ext_g : T_Immext<globaladdress>;
34 def BITPOS32 : SDNodeXForm<imm, [{
35 // Return the bit position we will set [0-31].
37 int32_t imm = N->getSExtValue();
38 return XformMskToBitPosU5Imm(imm);
41 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
42 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
44 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
45 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
47 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
48 (HexagonCONST32 node:$addr), [{
49 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
52 // Hexagon V4 Architecture spec defines 8 instruction classes:
53 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
57 // ========================================
58 // Loads (8/16/32/64 bit)
62 // ========================================
63 // Stores (8/16/32/64 bit)
66 // ALU32 Instructions:
67 // ========================================
68 // Arithmetic / Logical (32 bit)
71 // XTYPE Instructions (32/64 bit):
72 // ========================================
73 // Arithmetic, Logical, Bit Manipulation
74 // Multiply (Integer, Fractional, Complex)
75 // Permute / Vector Permute Operations
76 // Predicate Operations
77 // Shift / Shift with Add/Sub/Logical
79 // Vector Halfword (ALU, Shift, Multiply)
80 // Vector Word (ALU, Shift)
83 // ========================================
84 // Jump/Call PC-relative
87 // ========================================
90 // MEMOP Instructions:
91 // ========================================
92 // Operation on memory (8/16/32 bit)
95 // ========================================
100 // ========================================
101 // Control-Register Transfers
102 // Hardware Loop Setup
103 // Predicate Logicals & Reductions
105 // SYSTEM Instructions (not implemented in the compiler):
106 // ========================================
112 //===----------------------------------------------------------------------===//
114 //===----------------------------------------------------------------------===//
116 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
118 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
119 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
122 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
123 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
124 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
125 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
127 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
128 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
129 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
130 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
132 let isCodeGenOnly = 0 in {
133 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
134 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
135 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
138 // Pats for instruction selection.
140 // A class to embed the usual comparison patfrags within a zext to i32.
141 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
142 // names, or else the frag's "body" won't match the operands.
143 class CmpInReg<PatFrag Op>
144 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
146 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
147 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
149 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
151 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
152 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
153 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
155 let validSubTargets = HasV4SubT;
156 let InputType = "reg";
157 let CextOpcode = mnemonic;
159 let isCommutable = IsComm;
160 let hasSideEffects = 0;
167 let Inst{27-21} = 0b0111110;
168 let Inst{20-16} = Rs;
170 let Inst{7-5} = MinOp;
174 let isCodeGenOnly = 0 in {
175 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
176 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
177 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
178 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
179 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
180 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
183 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
184 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
185 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
186 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
188 let validSubTargets = HasV4SubT;
189 let InputType = "imm";
190 let CextOpcode = mnemonic;
192 let isCommutable = IsComm;
193 let hasSideEffects = 0;
194 let isExtendable = IsImmExt;
195 let opExtendable = !if (IsImmExt, 2, 0);
196 let isExtentSigned = IsImmSigned;
197 let opExtentBits = ImmBits;
204 let Inst{27-24} = 0b1101;
205 let Inst{22-21} = MajOp;
206 let Inst{20-16} = Rs;
207 let Inst{12-5} = Imm;
209 let Inst{3} = IsHalf;
213 let isCodeGenOnly = 0 in {
214 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
215 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
216 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
217 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
218 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
219 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
221 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
222 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
223 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
225 let validSubTargets = HasV4SubT;
226 let InputType = "imm";
227 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
228 let isExtendable = 1;
229 let opExtendable = 2;
230 let isExtentSigned = 1;
231 let opExtentBits = 8;
239 let Inst{27-24} = 0b0011;
241 let Inst{21} = IsNeg;
242 let Inst{20-16} = Rs;
248 let isCodeGenOnly = 0 in {
249 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
250 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
253 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
254 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
255 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
256 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
258 // Preserve the S2_tstbit_r generation
259 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
260 (i32 IntRegs:$src1))), 0)))),
261 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
264 //===----------------------------------------------------------------------===//
266 //===----------------------------------------------------------------------===//
269 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 // Combine a word and an immediate into a register pair.
274 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
276 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
277 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
283 let Inst{27-24} = 0b0011;
284 let Inst{22-21} = MajOp;
285 let Inst{20-16} = Rs;
291 let opExtendable = 2, isCodeGenOnly = 0 in
292 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
293 "$Rdd = combine($Rs, #$s8)">;
295 let opExtendable = 1, isCodeGenOnly = 0 in
296 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
297 "$Rdd = combine(#$s8, $Rs)">;
299 def HexagonWrapperCombineRI_V4 :
300 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
301 def HexagonWrapperCombineIR_V4 :
302 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
304 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
305 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
308 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
309 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
312 // A4_combineii: Set two small immediates.
313 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
314 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
315 "$Rdd = combine(#$s8, #$U6)"> {
321 let Inst{27-23} = 0b11001;
322 let Inst{20-16} = U6{5-1};
323 let Inst{13} = U6{0};
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
335 //===----------------------------------------------------------------------===//
336 // Template class for load instructions with Absolute set addressing mode.
337 //===----------------------------------------------------------------------===//
338 let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
339 validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
340 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
341 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
342 (ins u0AlwaysExt:$addr),
343 "$dst1 = "#mnemonic#"($dst2=##$addr)",
347 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
348 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
349 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
350 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
351 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
352 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
354 //===----------------------------------------------------------------------===//
355 // Template classes for the non-predicated load instructions with
356 // base + register offset addressing mode
357 //===----------------------------------------------------------------------===//
358 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
359 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
360 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
361 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
369 let Inst{27-24} = 0b1010;
370 let Inst{23-21} = MajOp;
371 let Inst{20-16} = src1;
372 let Inst{12-8} = src2;
373 let Inst{13} = u2{1};
378 //===----------------------------------------------------------------------===//
379 // Template classes for the predicated load instructions with
380 // base + register offset addressing mode
381 //===----------------------------------------------------------------------===//
382 let isPredicated = 1 in
383 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
384 bit isNot, bit isPredNew>:
385 LDInst <(outs RC:$dst),
386 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
387 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
388 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
389 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
396 let isPredicatedFalse = isNot;
397 let isPredicatedNew = isPredNew;
401 let Inst{27-26} = 0b00;
402 let Inst{25} = isPredNew;
403 let Inst{24} = isNot;
404 let Inst{23-21} = MajOp;
405 let Inst{20-16} = src2;
406 let Inst{12-8} = src3;
407 let Inst{13} = u2{1};
409 let Inst{6-5} = src1;
413 //===----------------------------------------------------------------------===//
414 // multiclass for load instructions with base + register offset
416 //===----------------------------------------------------------------------===//
417 let hasSideEffects = 0, addrMode = BaseRegOffset in
418 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
420 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
421 InputType = "reg" in {
422 let isPredicable = 1 in
423 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
426 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
427 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
430 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
431 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
435 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
436 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
437 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
440 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
441 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
442 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
445 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
446 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
448 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
449 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
451 // 'def pats' for load instructions with base + register offset and non-zero
452 // immediate value. Immediate value is used to left-shift the second
454 let AddedComplexity = 40 in {
455 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
456 (shl IntRegs:$src2, u2ImmPred:$offset)))),
457 (L4_loadrb_rr IntRegs:$src1,
458 IntRegs:$src2, u2ImmPred:$offset)>,
461 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
462 (shl IntRegs:$src2, u2ImmPred:$offset)))),
463 (L4_loadrub_rr IntRegs:$src1,
464 IntRegs:$src2, u2ImmPred:$offset)>,
467 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
468 (shl IntRegs:$src2, u2ImmPred:$offset)))),
469 (L4_loadrub_rr IntRegs:$src1,
470 IntRegs:$src2, u2ImmPred:$offset)>,
473 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
474 (shl IntRegs:$src2, u2ImmPred:$offset)))),
475 (L4_loadrh_rr IntRegs:$src1,
476 IntRegs:$src2, u2ImmPred:$offset)>,
479 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
480 (shl IntRegs:$src2, u2ImmPred:$offset)))),
481 (L4_loadruh_rr IntRegs:$src1,
482 IntRegs:$src2, u2ImmPred:$offset)>,
485 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
486 (shl IntRegs:$src2, u2ImmPred:$offset)))),
487 (L4_loadruh_rr IntRegs:$src1,
488 IntRegs:$src2, u2ImmPred:$offset)>,
491 def : Pat <(i32 (load (add IntRegs:$src1,
492 (shl IntRegs:$src2, u2ImmPred:$offset)))),
493 (L4_loadri_rr IntRegs:$src1,
494 IntRegs:$src2, u2ImmPred:$offset)>,
497 def : Pat <(i64 (load (add IntRegs:$src1,
498 (shl IntRegs:$src2, u2ImmPred:$offset)))),
499 (L4_loadrd_rr IntRegs:$src1,
500 IntRegs:$src2, u2ImmPred:$offset)>,
505 // 'def pats' for load instruction base + register offset and
506 // zero immediate value.
507 let AddedComplexity = 10 in {
508 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
509 (L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>,
512 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
513 (L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>,
516 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
517 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
520 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
521 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
524 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
525 (L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
528 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
529 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
532 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
533 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
536 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
537 (L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>,
542 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
543 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
547 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
548 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
551 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
552 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
555 let AddedComplexity = 20 in
556 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
557 s11_0ExtPred:$offset))),
558 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
559 s11_0ExtPred:$offset)))>,
563 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
564 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
567 let AddedComplexity = 20 in
568 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
569 s11_0ExtPred:$offset))),
570 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
571 s11_0ExtPred:$offset)))>,
575 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
576 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
579 let AddedComplexity = 20 in
580 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
581 s11_1ExtPred:$offset))),
582 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
583 s11_1ExtPred:$offset)))>,
587 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
588 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
591 let AddedComplexity = 20 in
592 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
593 s11_1ExtPred:$offset))),
594 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
595 s11_1ExtPred:$offset)))>,
599 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
600 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
603 let AddedComplexity = 100 in
604 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
605 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
606 s11_2ExtPred:$offset)))>,
610 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
611 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
614 let AddedComplexity = 100 in
615 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
616 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
617 s11_2ExtPred:$offset)))>,
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
630 //===----------------------------------------------------------------------===//
631 // Template class for store instructions with Absolute set addressing mode.
632 //===----------------------------------------------------------------------===//
633 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
634 addrMode = AbsoluteSet in
635 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
636 STInst2<(outs IntRegs:$dst1),
637 (ins RC:$src1, u0AlwaysExt:$src2),
638 mnemonic#"($dst1=##$src2) = $src1",
642 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
643 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
644 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
645 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
647 //===----------------------------------------------------------------------===//
648 // Template classes for the non-predicated store instructions with
649 // base + register offset addressing mode
650 //===----------------------------------------------------------------------===//
651 let isPredicable = 1 in
652 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
653 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
654 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
655 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
664 let Inst{27-24} = 0b1011;
665 let Inst{23-21} = MajOp;
666 let Inst{20-16} = Rs;
668 let Inst{13} = u2{1};
673 //===----------------------------------------------------------------------===//
674 // Template classes for the predicated store instructions with
675 // base + register offset addressing mode
676 //===----------------------------------------------------------------------===//
677 let isPredicated = 1 in
678 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
679 bit isNot, bit isPredNew, bit isH>
681 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
683 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
684 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
685 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
692 let isPredicatedFalse = isNot;
693 let isPredicatedNew = isPredNew;
697 let Inst{27-26} = 0b01;
698 let Inst{25} = isPredNew;
699 let Inst{24} = isNot;
700 let Inst{23-21} = MajOp;
701 let Inst{20-16} = Rs;
703 let Inst{13} = u2{1};
709 //===----------------------------------------------------------------------===//
710 // Template classes for the new-value store instructions with
711 // base + register offset addressing mode
712 //===----------------------------------------------------------------------===//
713 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
714 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
715 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
716 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
717 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
726 let Inst{27-21} = 0b1011101;
727 let Inst{20-16} = Rs;
729 let Inst{13} = u2{1};
731 let Inst{4-3} = MajOp;
735 //===----------------------------------------------------------------------===//
736 // Template classes for the predicated new-value store instructions with
737 // base + register offset addressing mode
738 //===----------------------------------------------------------------------===//
739 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
740 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
742 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
743 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
744 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
745 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
752 let isPredicatedFalse = isNot;
753 let isPredicatedNew = isPredNew;
756 let Inst{27-26} = 0b01;
757 let Inst{25} = isPredNew;
758 let Inst{24} = isNot;
759 let Inst{23-21} = 0b101;
760 let Inst{20-16} = Rs;
762 let Inst{13} = u2{1};
765 let Inst{4-3} = MajOp;
769 //===----------------------------------------------------------------------===//
770 // multiclass for store instructions with base + register offset addressing
772 //===----------------------------------------------------------------------===//
773 let isNVStorable = 1 in
774 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
775 bits<3> MajOp, bit isH = 0> {
776 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
777 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
780 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
781 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
784 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
785 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
789 //===----------------------------------------------------------------------===//
790 // multiclass for new-value store instructions with base + register offset
792 //===----------------------------------------------------------------------===//
793 let mayStore = 1, isNVStore = 1 in
794 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
796 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
797 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
800 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
801 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
804 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
805 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
809 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
810 isCodeGenOnly = 0 in {
811 let accessSize = ByteAccess in
812 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
813 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
815 let accessSize = HalfWordAccess in
816 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
817 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
819 let accessSize = WordAccess in
820 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
821 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
823 let isNVStorable = 0, accessSize = DoubleWordAccess in
824 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
826 let isNVStorable = 0, accessSize = HalfWordAccess in
827 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
830 let Predicates = [HasV4T], AddedComplexity = 10 in {
831 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
832 (add IntRegs:$src1, (shl IntRegs:$src2,
834 (S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
835 u2ImmPred:$src3, IntRegs:$src4)>;
837 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
838 (add IntRegs:$src1, (shl IntRegs:$src2,
840 (S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
841 u2ImmPred:$src3, IntRegs:$src4)>;
843 def : Pat<(store (i32 IntRegs:$src4),
844 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
845 (S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
846 u2ImmPred:$src3, IntRegs:$src4)>;
848 def : Pat<(store (i64 DoubleRegs:$src4),
849 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
850 (S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
851 u2ImmPred:$src3, DoubleRegs:$src4)>;
854 let isExtended = 1, opExtendable = 2 in
855 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
857 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
858 mnemonic#"($src1<<#$src2+##$src3) = $src4",
859 [(stOp (VT RC:$src4),
860 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
861 u0AlwaysExtPred:$src3))]>,
864 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
865 class T_ST_LongOff_nv <string mnemonic> :
867 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
868 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
872 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
873 let BaseOpcode = BaseOp#"_shl" in {
874 let isNVStorable = 1 in
875 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
877 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
881 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
882 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
883 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
884 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
885 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
888 let AddedComplexity = 40 in
889 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
891 def : Pat<(stOp (VT RC:$src4),
892 (add (shl IntRegs:$src1, u2ImmPred:$src2),
893 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
894 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
896 def : Pat<(stOp (VT RC:$src4),
898 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
899 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
902 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
903 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
904 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
905 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
907 // memd(Rx++#s4:3)=Rtt
908 // memd(Rx++#s4:3:circ(Mu))=Rtt
909 // memd(Rx++I:circ(Mu))=Rtt
911 // memd(Rx++Mu:brev)=Rtt
912 // memd(gp+#u16:3)=Rtt
914 // Store doubleword conditionally.
915 // if ([!]Pv[.new]) memd(#u6)=Rtt
916 // TODO: needs to be implemented.
918 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
921 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
923 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
924 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
925 mnemonic#"($Rs+#$offset)=#$S8",
926 [], "", V4LDST_tc_st_SLOT01>,
927 ImmRegRel, PredNewRel {
933 string OffsetOpStr = !cast<string>(OffsetOp);
934 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
935 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
936 /* u6_0Imm */ offset{5-0}));
940 let Inst{27-25} = 0b110;
941 let Inst{22-21} = MajOp;
942 let Inst{20-16} = Rs;
943 let Inst{12-7} = offsetBits;
944 let Inst{13} = S8{7};
945 let Inst{6-0} = S8{6-0};
948 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
950 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
951 bit isPredNot, bit isPredNew >
953 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
954 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
955 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
956 [], "", V4LDST_tc_st_SLOT01>,
957 ImmRegRel, PredNewRel {
964 string OffsetOpStr = !cast<string>(OffsetOp);
965 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
966 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
967 /* u6_0Imm */ offset{5-0}));
968 let isPredicatedNew = isPredNew;
969 let isPredicatedFalse = isPredNot;
973 let Inst{27-25} = 0b100;
974 let Inst{24} = isPredNew;
975 let Inst{23} = isPredNot;
976 let Inst{22-21} = MajOp;
977 let Inst{20-16} = Rs;
978 let Inst{13} = S6{5};
979 let Inst{12-7} = offsetBits;
981 let Inst{4-0} = S6{4-0};
985 //===----------------------------------------------------------------------===//
986 // multiclass for store instructions with base + immediate offset
987 // addressing mode and immediate stored value.
988 // mem[bhw](Rx++#s4:3)=#s8
989 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
990 //===----------------------------------------------------------------------===//
992 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
994 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
996 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
999 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1001 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1002 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1004 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1005 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1009 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1010 InputType = "imm", isCodeGenOnly = 0 in {
1011 let accessSize = ByteAccess in
1012 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1014 let accessSize = HalfWordAccess in
1015 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1017 let accessSize = WordAccess in
1018 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1021 let Predicates = [HasV4T], AddedComplexity = 10 in {
1022 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1023 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1025 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1026 u6_1ImmPred:$src2)),
1027 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1029 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1030 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1033 let AddedComplexity = 6 in
1034 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1035 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1038 // memb(Rx++#s4:0:circ(Mu))=Rt
1039 // memb(Rx++I:circ(Mu))=Rt
1041 // memb(Rx++Mu:brev)=Rt
1042 // memb(gp+#u16:0)=Rt
1046 // TODO: needs to be implemented
1047 // memh(Re=#U6)=Rt.H
1048 // memh(Rs+#s11:1)=Rt.H
1049 let AddedComplexity = 6 in
1050 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1051 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1054 // memh(Rs+Ru<<#u2)=Rt.H
1055 // TODO: needs to be implemented.
1057 // memh(Ru<<#u2+#U6)=Rt.H
1058 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1059 // memh(Rx++#s4:1:circ(Mu))=Rt
1060 // memh(Rx++I:circ(Mu))=Rt.H
1061 // memh(Rx++I:circ(Mu))=Rt
1062 // memh(Rx++Mu)=Rt.H
1064 // memh(Rx++Mu:brev)=Rt.H
1065 // memh(Rx++Mu:brev)=Rt
1066 // memh(gp+#u16:1)=Rt
1067 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1068 // if ([!]Pv[.new]) memh(#u6)=Rt
1071 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1072 // TODO: needs to be implemented.
1074 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1075 // TODO: Needs to be implemented.
1079 // TODO: Needs to be implemented.
1082 let hasSideEffects = 0 in
1083 def STriw_pred_V4 : STInst2<(outs),
1084 (ins MEMri:$addr, PredRegs:$src1),
1085 "Error; should not emit",
1089 let AddedComplexity = 6 in
1090 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1091 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1094 // memw(Rx++#s4:2)=Rt
1095 // memw(Rx++#s4:2:circ(Mu))=Rt
1096 // memw(Rx++I:circ(Mu))=Rt
1098 // memw(Rx++Mu:brev)=Rt
1100 //===----------------------------------------------------------------------===
1102 //===----------------------------------------------------------------------===
1105 //===----------------------------------------------------------------------===//
1107 //===----------------------------------------------------------------------===//
1109 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1110 class T_store_io_nv <string mnemonic, RegisterClass RC,
1111 Operand ImmOp, bits<2>MajOp>
1112 : NVInst_V4 <(outs),
1113 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1114 mnemonic#"($src1+#$src2) = $src3.new",
1115 [],"",ST_tc_st_SLOT0> {
1117 bits<13> src2; // Actual address offset
1119 bits<11> offsetBits; // Represents offset encoding
1121 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1122 !if (!eq(mnemonic, "memh"), 12,
1123 !if (!eq(mnemonic, "memw"), 13, 0)));
1125 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1126 !if (!eq(mnemonic, "memh"), 1,
1127 !if (!eq(mnemonic, "memw"), 2, 0)));
1129 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1130 !if (!eq(mnemonic, "memh"), src2{11-1},
1131 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1133 let IClass = 0b1010;
1136 let Inst{26-25} = offsetBits{10-9};
1137 let Inst{24-21} = 0b1101;
1138 let Inst{20-16} = src1;
1139 let Inst{13} = offsetBits{8};
1140 let Inst{12-11} = MajOp;
1141 let Inst{10-8} = src3;
1142 let Inst{7-0} = offsetBits{7-0};
1145 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1146 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1147 bits<2>MajOp, bit PredNot, bit isPredNew>
1148 : NVInst_V4 <(outs),
1149 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1150 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1151 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1152 [],"",V2LDST_tc_st_SLOT0> {
1157 bits<6> offsetBits; // Represents offset encoding
1159 let isPredicatedNew = isPredNew;
1160 let isPredicatedFalse = PredNot;
1161 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1162 !if (!eq(mnemonic, "memh"), 7,
1163 !if (!eq(mnemonic, "memw"), 8, 0)));
1165 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1166 !if (!eq(mnemonic, "memh"), 1,
1167 !if (!eq(mnemonic, "memw"), 2, 0)));
1169 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1170 !if (!eq(mnemonic, "memh"), src3{6-1},
1171 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1173 let IClass = 0b0100;
1176 let Inst{26} = PredNot;
1177 let Inst{25} = isPredNew;
1178 let Inst{24-21} = 0b0101;
1179 let Inst{20-16} = src2;
1180 let Inst{13} = offsetBits{5};
1181 let Inst{12-11} = MajOp;
1182 let Inst{10-8} = src4;
1183 let Inst{7-3} = offsetBits{4-0};
1185 let Inst{1-0} = src1;
1188 // multiclass for new-value store instructions with base + immediate offset.
1190 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1192 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1193 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1195 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1196 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1198 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1199 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1201 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1203 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1208 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1209 let accessSize = ByteAccess in
1210 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1211 u6_0Ext, 0b00>, AddrModeRel;
1213 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1214 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1215 u6_1Ext, 0b01>, AddrModeRel;
1217 let accessSize = WordAccess, opExtentAlign = 2 in
1218 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1219 u6_2Ext, 0b10>, AddrModeRel;
1222 //===----------------------------------------------------------------------===//
1223 // Template class for non-predicated post increment .new stores
1224 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1225 //===----------------------------------------------------------------------===//
1226 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1227 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1228 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1229 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1230 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1231 mnemonic#"($src1++#$offset) = $src2.new",
1232 [], "$src1 = $_dst_">,
1239 string ImmOpStr = !cast<string>(ImmOp);
1240 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1241 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1242 /* s4_0Imm */ offset{3-0}));
1243 let IClass = 0b1010;
1245 let Inst{27-21} = 0b1011101;
1246 let Inst{20-16} = src1;
1248 let Inst{12-11} = MajOp;
1249 let Inst{10-8} = src2;
1251 let Inst{6-3} = offsetBits;
1255 //===----------------------------------------------------------------------===//
1256 // Template class for predicated post increment .new stores
1257 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1258 //===----------------------------------------------------------------------===//
1259 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1260 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1261 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1262 bits<2> MajOp, bit isPredNot, bit isPredNew >
1263 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1264 (ins PredRegs:$src1, IntRegs:$src2,
1265 ImmOp:$offset, IntRegs:$src3),
1266 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1267 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1268 [], "$src2 = $_dst_">,
1276 string ImmOpStr = !cast<string>(ImmOp);
1277 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1278 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1279 /* s4_0Imm */ offset{3-0}));
1280 let isPredicatedNew = isPredNew;
1281 let isPredicatedFalse = isPredNot;
1283 let IClass = 0b1010;
1285 let Inst{27-21} = 0b1011101;
1286 let Inst{20-16} = src2;
1288 let Inst{12-11} = MajOp;
1289 let Inst{10-8} = src3;
1290 let Inst{7} = isPredNew;
1291 let Inst{6-3} = offsetBits;
1292 let Inst{2} = isPredNot;
1293 let Inst{1-0} = src1;
1296 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1297 bits<2> MajOp, bit PredNot> {
1298 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1301 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1304 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1306 let BaseOpcode = "POST_"#BaseOp in {
1307 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1310 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1311 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1315 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1316 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1318 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1319 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1321 let accessSize = WordAccess, isCodeGenOnly = 0 in
1322 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1324 //===----------------------------------------------------------------------===//
1325 // Template class for post increment .new stores with register offset
1326 //===----------------------------------------------------------------------===//
1327 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1328 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1329 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1330 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1331 #mnemonic#"($src1++$src2) = $src3.new",
1332 [], "$src1 = $_dst_"> {
1336 let accessSize = AccessSz;
1338 let IClass = 0b1010;
1340 let Inst{27-21} = 0b1101101;
1341 let Inst{20-16} = src1;
1342 let Inst{13} = src2;
1343 let Inst{12-11} = MajOp;
1344 let Inst{10-8} = src3;
1348 let isCodeGenOnly = 0 in {
1349 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1350 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1351 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1354 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1355 // memb(Rx++I:circ(Mu))=Nt.new
1356 // memb(Rx++Mu)=Nt.new
1357 // memb(Rx++Mu:brev)=Nt.new
1358 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1359 // memh(Rx++I:circ(Mu))=Nt.new
1360 // memh(Rx++Mu)=Nt.new
1361 // memh(Rx++Mu:brev)=Nt.new
1363 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1364 // memw(Rx++I:circ(Mu))=Nt.new
1365 // memw(Rx++Mu)=Nt.new
1366 // memw(Rx++Mu:brev)=Nt.new
1368 //===----------------------------------------------------------------------===//
1370 //===----------------------------------------------------------------------===//
1372 //===----------------------------------------------------------------------===//
1374 //===----------------------------------------------------------------------===//
1376 //===----------------------------------------------------------------------===//
1377 // multiclass/template class for the new-value compare jumps with the register
1379 //===----------------------------------------------------------------------===//
1381 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1382 opExtentAlign = 2 in
1383 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1384 bit isNegCond, bit isTak>
1386 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1387 "if ("#!if(isNegCond, "!","")#mnemonic#
1388 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1389 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1390 #!if(isTak, "t","nt")#" $offset", []> {
1394 bits<3> Ns; // New-Value Operand
1395 bits<5> RegOp; // Non-New-Value Operand
1398 let isTaken = isTak;
1399 let isPredicatedFalse = isNegCond;
1400 let opNewValue{0} = NvOpNum;
1402 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1403 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1405 let IClass = 0b0010;
1407 let Inst{25-23} = majOp;
1408 let Inst{22} = isNegCond;
1409 let Inst{18-16} = Ns;
1410 let Inst{13} = isTak;
1411 let Inst{12-8} = RegOp;
1412 let Inst{21-20} = offset{10-9};
1413 let Inst{7-1} = offset{8-2};
1417 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1419 // Branch not taken:
1420 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1422 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1425 // NvOpNum = 0 -> First Operand is a new-value Register
1426 // NvOpNum = 1 -> Second Operand is a new-value Register
1428 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1430 let BaseOpcode = BaseOp#_NVJ in {
1431 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1432 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1436 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1437 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1438 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1439 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1440 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1442 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1443 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1444 isCodeGenOnly = 0 in {
1445 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1446 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1447 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1448 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1449 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1452 //===----------------------------------------------------------------------===//
1453 // multiclass/template class for the new-value compare jumps instruction
1454 // with a register and an unsigned immediate (U5) operand.
1455 //===----------------------------------------------------------------------===//
1457 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1458 opExtentAlign = 2 in
1459 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1462 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1463 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1464 #!if(isTak, "t","nt")#" $offset", []> {
1466 let isTaken = isTak;
1467 let isPredicatedFalse = isNegCond;
1468 let isTaken = isTak;
1474 let IClass = 0b0010;
1476 let Inst{25-23} = majOp;
1477 let Inst{22} = isNegCond;
1478 let Inst{18-16} = src1;
1479 let Inst{13} = isTak;
1480 let Inst{12-8} = src2;
1481 let Inst{21-20} = offset{10-9};
1482 let Inst{7-1} = offset{8-2};
1485 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1486 // Branch not taken:
1487 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1489 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1492 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1493 let BaseOpcode = BaseOp#_NVJri in {
1494 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1495 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1499 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1500 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1501 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1503 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1504 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1505 isCodeGenOnly = 0 in {
1506 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1507 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1508 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1511 //===----------------------------------------------------------------------===//
1512 // multiclass/template class for the new-value compare jumps instruction
1513 // with a register and an hardcoded 0/-1 immediate value.
1514 //===----------------------------------------------------------------------===//
1516 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1517 opExtentAlign = 2 in
1518 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1519 bit isNegCond, bit isTak>
1521 (ins IntRegs:$src1, brtarget:$offset),
1522 "if ("#!if(isNegCond, "!","")#mnemonic
1523 #"($src1.new, #"#ImmVal#")) jump:"
1524 #!if(isTak, "t","nt")#" $offset", []> {
1526 let isTaken = isTak;
1527 let isPredicatedFalse = isNegCond;
1528 let isTaken = isTak;
1532 let IClass = 0b0010;
1534 let Inst{25-23} = majOp;
1535 let Inst{22} = isNegCond;
1536 let Inst{18-16} = src1;
1537 let Inst{13} = isTak;
1538 let Inst{21-20} = offset{10-9};
1539 let Inst{7-1} = offset{8-2};
1542 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1544 // Branch not taken:
1545 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1547 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1550 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1552 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1553 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1554 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1558 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1559 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1560 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1562 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1563 Defs = [PC], hasSideEffects = 0, isCodeGenOnly = 0 in {
1564 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1565 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1566 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1569 // J4_hintjumpr: Hint indirect conditional jump.
1570 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1571 def J4_hintjumpr: JRInst <
1576 let IClass = 0b0101;
1577 let Inst{27-21} = 0b0010101;
1578 let Inst{20-16} = Rs;
1581 //===----------------------------------------------------------------------===//
1583 //===----------------------------------------------------------------------===//
1585 //===----------------------------------------------------------------------===//
1587 //===----------------------------------------------------------------------===//
1590 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1591 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0,
1592 Uses = [PC], validSubTargets = HasV4SubT in
1593 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1594 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1598 let IClass = 0b0110;
1599 let Inst{27-16} = 0b101001001001;
1600 let Inst{12-7} = u6;
1606 let hasSideEffects = 0 in
1607 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1608 : CRInst<(outs PredRegs:$Pd),
1609 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1610 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1611 !if (IsNeg,"!","") # "$Pu))",
1612 [], "", CR_tc_2early_SLOT23> {
1618 let IClass = 0b0110;
1619 let Inst{27-24} = 0b1011;
1620 let Inst{23} = IsNeg;
1621 let Inst{22-21} = OpBits;
1623 let Inst{17-16} = Ps;
1630 let isCodeGenOnly = 0 in {
1631 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1632 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1633 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1634 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1635 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1636 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1637 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1638 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1641 //===----------------------------------------------------------------------===//
1643 //===----------------------------------------------------------------------===//
1645 //===----------------------------------------------------------------------===//
1647 //===----------------------------------------------------------------------===//
1649 // Logical with-not instructions.
1650 let validSubTargets = HasV4SubT, isCodeGenOnly = 0 in {
1651 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1652 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1655 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1656 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1657 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1662 let IClass = 0b1101;
1663 let Inst{27-21} = 0b0101111;
1664 let Inst{20-16} = Rs;
1665 let Inst{12-8} = Rt;
1668 // Add and accumulate.
1669 // Rd=add(Rs,add(Ru,#s6))
1670 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1671 opExtendable = 3, isCodeGenOnly = 0 in
1672 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1673 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1674 "$Rd = add($Rs, add($Ru, #$s6))" ,
1675 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1676 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1677 "", ALU64_tc_2_SLOT23> {
1683 let IClass = 0b1101;
1685 let Inst{27-23} = 0b10110;
1686 let Inst{22-21} = s6{5-4};
1687 let Inst{20-16} = Rs;
1688 let Inst{13} = s6{3};
1689 let Inst{12-8} = Rd;
1690 let Inst{7-5} = s6{2-0};
1694 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1695 opExtentBits = 6, opExtendable = 2, isCodeGenOnly = 0 in
1696 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1697 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1698 "$Rd = add($Rs, sub(#$s6, $Ru))",
1699 [], "", ALU64_tc_2_SLOT23> {
1705 let IClass = 0b1101;
1707 let Inst{27-23} = 0b10111;
1708 let Inst{22-21} = s6{5-4};
1709 let Inst{20-16} = Rs;
1710 let Inst{13} = s6{3};
1711 let Inst{12-8} = Rd;
1712 let Inst{7-5} = s6{2-0};
1717 // Rdd=extract(Rss,#u6,#U6)
1718 // Rdd=extract(Rss,Rtt)
1719 // Rd=extract(Rs,Rtt)
1720 // Rd=extract(Rs,#u5,#U5)
1722 let isCodeGenOnly = 0 in {
1723 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1724 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1727 let hasNewValue = 1, isCodeGenOnly = 0 in {
1728 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1729 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1732 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1733 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1734 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1737 // Logical xor with xor accumulation.
1738 // Rxx^=xor(Rss,Rtt)
1739 let hasSideEffects = 0, isCodeGenOnly = 0 in
1741 : SInst <(outs DoubleRegs:$Rxx),
1742 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1743 "$Rxx ^= xor($Rss, $Rtt)",
1744 [(set (i64 DoubleRegs:$Rxx),
1745 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
1746 (i64 DoubleRegs:$Rtt))))],
1747 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
1752 let IClass = 0b1100;
1754 let Inst{27-23} = 0b10101;
1755 let Inst{20-16} = Rss;
1756 let Inst{12-8} = Rtt;
1757 let Inst{4-0} = Rxx;
1761 let isCodeGenOnly = 0 in
1762 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
1764 // Arithmetic/Convergent round
1765 let isCodeGenOnly = 0 in
1766 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
1768 let isCodeGenOnly = 0 in
1769 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
1771 let Defs = [USR_OVF], isCodeGenOnly = 0 in
1772 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
1774 // Logical-logical words.
1775 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
1776 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
1777 opExtendable = 3, isCodeGenOnly = 0 in
1779 ALU64Inst<(outs IntRegs:$Rx),
1780 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
1781 "$Rx = or($Ru, and($_src_, #$s10))" ,
1782 [(set (i32 IntRegs:$Rx),
1783 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
1784 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
1789 let IClass = 0b1101;
1791 let Inst{27-22} = 0b101001;
1792 let Inst{20-16} = Rx;
1793 let Inst{21} = s10{9};
1794 let Inst{13-5} = s10{8-0};
1798 // Miscellaneous ALU64 instructions.
1800 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1801 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1802 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1807 let IClass = 0b1101;
1808 let Inst{27-21} = 0b0011111;
1809 let Inst{20-16} = Rs;
1810 let Inst{12-8} = Rt;
1811 let Inst{7-5} = 0b111;
1815 let hasSideEffects = 0, isCodeGenOnly = 0 in
1816 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
1817 (ins IntRegs:$Rs, IntRegs:$Rt),
1818 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1823 let IClass = 0b1101;
1824 let Inst{27-24} = 0b0100;
1826 let Inst{20-16} = Rs;
1827 let Inst{12-8} = Rt;
1831 let isCodeGenOnly = 0 in {
1832 // Rx[&|]=xor(Rs,Rt)
1833 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
1834 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
1836 // Rx[&|^]=or(Rs,Rt)
1837 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
1839 let CextOpcode = "ORr_ORr" in
1840 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
1841 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
1843 // Rx[&|^]=and(Rs,Rt)
1844 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
1846 let CextOpcode = "ORr_ANDr" in
1847 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
1848 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
1850 // Rx[&|^]=and(Rs,~Rt)
1851 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
1852 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
1853 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
1856 // Compound or-or and or-and
1857 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
1858 opExtentBits = 10, opExtendable = 3 in
1859 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
1860 : MInst_acc <(outs IntRegs:$Rx),
1861 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
1862 "$Rx |= "#mnemonic#"($Rs, #$s10)",
1863 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
1864 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
1865 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
1870 let IClass = 0b1101;
1872 let Inst{27-24} = 0b1010;
1873 let Inst{23-22} = MajOp;
1874 let Inst{20-16} = Rs;
1875 let Inst{21} = s10{9};
1876 let Inst{13-5} = s10{8-0};
1880 let CextOpcode = "ORr_ANDr", isCodeGenOnly = 0 in
1881 def S4_or_andi : T_CompOR <"and", 0b00, and>;
1883 let CextOpcode = "ORr_ORr", isCodeGenOnly = 0 in
1884 def S4_or_ori : T_CompOR <"or", 0b10, or>;
1887 // Rd=modwrap(Rs,Rt)
1889 // Rd=cround(Rs,#u5)
1891 // Rd=round(Rs,#u5)[:sat]
1892 // Rd=round(Rs,Rt)[:sat]
1893 // Vector reduce add unsigned halfwords
1894 // Rd=vraddh(Rss,Rtt)
1896 // Rdd=vaddb(Rss,Rtt)
1897 // Vector conditional negate
1898 // Rdd=vcnegh(Rss,Rt)
1899 // Rxx+=vrcnegh(Rss,Rt)
1900 // Vector maximum bytes
1901 // Rdd=vmaxb(Rtt,Rss)
1902 // Vector reduce maximum halfwords
1903 // Rxx=vrmaxh(Rss,Ru)
1904 // Rxx=vrmaxuh(Rss,Ru)
1905 // Vector reduce maximum words
1906 // Rxx=vrmaxuw(Rss,Ru)
1907 // Rxx=vrmaxw(Rss,Ru)
1908 // Vector minimum bytes
1909 // Rdd=vminb(Rtt,Rss)
1910 // Vector reduce minimum halfwords
1911 // Rxx=vrminh(Rss,Ru)
1912 // Rxx=vrminuh(Rss,Ru)
1913 // Vector reduce minimum words
1914 // Rxx=vrminuw(Rss,Ru)
1915 // Rxx=vrminw(Rss,Ru)
1916 // Vector subtract bytes
1917 // Rdd=vsubb(Rss,Rtt)
1919 //===----------------------------------------------------------------------===//
1921 //===----------------------------------------------------------------------===//
1923 //===----------------------------------------------------------------------===//
1925 //===----------------------------------------------------------------------===//
1928 let isCodeGenOnly = 0 in
1929 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
1932 let isCodeGenOnly = 0 in {
1933 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
1934 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
1935 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
1938 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
1939 (S2_ct0p (i64 DoubleRegs:$Rss))>;
1940 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
1941 (S2_ct1p (i64 DoubleRegs:$Rss))>;
1943 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1944 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
1945 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
1949 let IClass = 0b1000;
1950 let Inst{27-24} = 0b1100;
1951 let Inst{23-21} = 0b001;
1952 let Inst{20-16} = Rs;
1953 let Inst{13-8} = s6;
1954 let Inst{7-5} = 0b000;
1958 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1959 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
1960 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
1964 let IClass = 0b1000;
1965 let Inst{27-24} = 0b1000;
1966 let Inst{23-21} = 0b011;
1967 let Inst{20-16} = Rs;
1968 let Inst{13-8} = s6;
1969 let Inst{7-5} = 0b010;
1974 // Bit test/set/clear
1975 let isCodeGenOnly = 0 in {
1976 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
1977 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
1980 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
1981 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
1982 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
1983 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
1984 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
1987 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
1988 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
1989 // if ([!]tstbit(...)) jump ...
1990 let AddedComplexity = 100 in
1991 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
1992 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
1994 let AddedComplexity = 100 in
1995 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
1996 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
1998 let isCodeGenOnly = 0 in {
1999 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2000 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2001 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2004 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2005 // represented as a compare against "value & 0xFF", which is an exact match
2006 // for cmpb (same for cmph). The patterns below do not contain any additional
2007 // complexity that would make them preferable, and if they were actually used
2008 // instead of cmpb/cmph, they would result in a compare against register that
2009 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2010 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2011 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2012 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2013 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2014 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2015 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2017 //===----------------------------------------------------------------------===//
2019 //===----------------------------------------------------------------------===//
2021 //===----------------------------------------------------------------------===//
2023 //===----------------------------------------------------------------------===//
2025 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2027 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1,
2028 isCodeGenOnly = 0 in
2029 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2030 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2031 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2032 [(set (i32 IntRegs:$Rd),
2033 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2034 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2040 let IClass = 0b1101;
2042 let Inst{27-24} = 0b1000;
2043 let Inst{23} = U6{5};
2044 let Inst{22-21} = u6{5-4};
2045 let Inst{20-16} = Rs;
2046 let Inst{13} = u6{3};
2047 let Inst{12-8} = Rd;
2048 let Inst{7-5} = u6{2-0};
2049 let Inst{4-0} = U6{4-0};
2052 // Rd=add(#u6,mpyi(Rs,Rt))
2053 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2054 isExtendable = 1, opExtentBits = 6, opExtendable = 1, isCodeGenOnly = 0 in
2055 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2056 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2057 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2058 [(set (i32 IntRegs:$Rd),
2059 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2060 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2066 let IClass = 0b1101;
2068 let Inst{27-23} = 0b01110;
2069 let Inst{22-21} = u6{5-4};
2070 let Inst{20-16} = Rs;
2071 let Inst{13} = u6{3};
2072 let Inst{12-8} = Rt;
2073 let Inst{7-5} = u6{2-0};
2077 let hasNewValue = 1 in
2078 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2079 : ALU64Inst <(outs IntRegs:$dst), ins,
2080 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2082 [(set (i32 IntRegs:$dst),
2083 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2084 "", ALU64_tc_3x_SLOT23> {
2090 let IClass = 0b1101;
2092 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2094 let Inst{27-24} = 0b1111;
2095 let Inst{23} = MajOp;
2096 let Inst{22-21} = ImmValue{5-4};
2097 let Inst{20-16} = src3;
2098 let Inst{13} = ImmValue{3};
2099 let Inst{12-8} = dst;
2100 let Inst{7-5} = ImmValue{2-0};
2101 let Inst{4-0} = src1;
2104 let isCodeGenOnly = 0 in
2105 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2106 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2108 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2109 CextOpcode = "ADD_MPY", InputType = "imm", isCodeGenOnly = 0 in
2110 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2111 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2113 // Rx=add(Ru,mpyi(Rx,Rs))
2114 let validSubTargets = HasV4SubT, CextOpcode = "ADD_MPY", InputType = "reg",
2115 hasNewValue = 1, isCodeGenOnly = 0 in
2116 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2117 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2118 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2119 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2120 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2121 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2126 let IClass = 0b1110;
2128 let Inst{27-21} = 0b0011000;
2129 let Inst{12-8} = Rx;
2131 let Inst{20-16} = Rs;
2134 // Rd=add(##,mpyi(Rs,#U6))
2135 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2136 (HexagonCONST32 tglobaladdr:$src1)),
2137 (i32 (M4_mpyri_addi tglobaladdr:$src1, IntRegs:$src2,
2140 // Rd=add(##,mpyi(Rs,Rt))
2141 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2142 (HexagonCONST32 tglobaladdr:$src1)),
2143 (i32 (M4_mpyrr_addi tglobaladdr:$src1, IntRegs:$src2,
2146 // Polynomial multiply words
2148 // Rxx^=pmpyw(Rs,Rt)
2150 // Vector reduce multiply word by signed half (32x16)
2151 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2152 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2153 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
2154 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
2156 // Multiply and use upper result
2157 // Rd=mpy(Rs,Rt.H):<<1:sat
2158 // Rd=mpy(Rs,Rt.L):<<1:sat
2159 // Rd=mpy(Rs,Rt):<<1
2160 // Rd=mpy(Rs,Rt):<<1:sat
2162 // Rx+=mpy(Rs,Rt):<<1:sat
2163 // Rx-=mpy(Rs,Rt):<<1:sat
2165 // Vector multiply bytes
2166 // Rdd=vmpybsu(Rs,Rt)
2167 // Rdd=vmpybu(Rs,Rt)
2168 // Rxx+=vmpybsu(Rs,Rt)
2169 // Rxx+=vmpybu(Rs,Rt)
2171 // Vector polynomial multiply halfwords
2172 // Rdd=vpmpyh(Rs,Rt)
2173 // Rxx^=vpmpyh(Rs,Rt)
2175 //===----------------------------------------------------------------------===//
2177 //===----------------------------------------------------------------------===//
2180 //===----------------------------------------------------------------------===//
2182 //===----------------------------------------------------------------------===//
2183 // Shift by immediate and accumulate/logical.
2184 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2185 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2186 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2187 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2188 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2189 hasNewValue = 1, opNewValue = 0, validSubTargets = HasV4SubT in
2190 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2191 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2192 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2193 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2194 [(set (i32 IntRegs:$Rd),
2195 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2196 "$Rd = $Rx", Itin> {
2203 let IClass = 0b1101;
2204 let Inst{27-24} = 0b1110;
2205 let Inst{23-21} = u8{7-5};
2206 let Inst{20-16} = Rd;
2207 let Inst{13} = u8{4};
2208 let Inst{12-8} = U5;
2209 let Inst{7-5} = u8{3-1};
2210 let Inst{4} = asl_lsr;
2211 let Inst{3} = u8{0};
2212 let Inst{2-1} = MajOp;
2215 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2216 InstrItinClass Itin> {
2217 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2218 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2221 let AddedComplexity = 200, isCodeGenOnly = 0 in {
2222 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2223 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2226 let AddedComplexity = 30, isCodeGenOnly = 0 in
2227 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2229 let isCodeGenOnly = 0 in
2230 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2233 // Rd=[cround|round](Rs,Rt)
2234 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in {
2235 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2236 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2239 // Rd=round(Rs,Rt):sat
2240 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23,
2241 isCodeGenOnly = 0 in
2242 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2244 // Rdd=[add|sub](Rss,Rtt,Px):carry
2245 let isPredicateLate = 1, hasSideEffects = 0 in
2246 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2247 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2248 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2249 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2250 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2256 let IClass = 0b1100;
2258 let Inst{27-24} = 0b0010;
2259 let Inst{23-21} = MajOp;
2260 let Inst{20-16} = Rss;
2261 let Inst{12-8} = Rtt;
2263 let Inst{4-0} = Rdd;
2266 let isCodeGenOnly = 0 in {
2267 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2268 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2271 // Shift an immediate left by register amount.
2272 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
2273 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2274 "$Rd = lsl(#$s6, $Rt)" ,
2275 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2276 (i32 IntRegs:$Rt)))],
2277 "", S_3op_tc_1_SLOT23> {
2282 let IClass = 0b1100;
2284 let Inst{27-22} = 0b011010;
2285 let Inst{20-16} = s6{5-1};
2286 let Inst{12-8} = Rt;
2287 let Inst{7-6} = 0b11;
2289 let Inst{5} = s6{0};
2292 //===----------------------------------------------------------------------===//
2294 //===----------------------------------------------------------------------===//
2296 //===----------------------------------------------------------------------===//
2297 // MEMOP: Word, Half, Byte
2298 //===----------------------------------------------------------------------===//
2300 def MEMOPIMM : SDNodeXForm<imm, [{
2301 // Call the transformation function XformM5ToU5Imm to get the negative
2302 // immediate's positive counterpart.
2303 int32_t imm = N->getSExtValue();
2304 return XformM5ToU5Imm(imm);
2307 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2308 // -1 .. -31 represented as 65535..65515
2309 // assigning to a short restores our desired signed value.
2310 // Call the transformation function XformM5ToU5Imm to get the negative
2311 // immediate's positive counterpart.
2312 int16_t imm = N->getSExtValue();
2313 return XformM5ToU5Imm(imm);
2316 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2317 // -1 .. -31 represented as 255..235
2318 // assigning to a char restores our desired signed value.
2319 // Call the transformation function XformM5ToU5Imm to get the negative
2320 // immediate's positive counterpart.
2321 int8_t imm = N->getSExtValue();
2322 return XformM5ToU5Imm(imm);
2325 def SETMEMIMM : SDNodeXForm<imm, [{
2326 // Return the bit position we will set [0-31].
2328 int32_t imm = N->getSExtValue();
2329 return XformMskToBitPosU5Imm(imm);
2332 def CLRMEMIMM : SDNodeXForm<imm, [{
2333 // Return the bit position we will clear [0-31].
2335 // we bit negate the value first
2336 int32_t imm = ~(N->getSExtValue());
2337 return XformMskToBitPosU5Imm(imm);
2340 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2341 // Return the bit position we will set [0-15].
2343 int16_t imm = N->getSExtValue();
2344 return XformMskToBitPosU4Imm(imm);
2347 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2348 // Return the bit position we will clear [0-15].
2350 // we bit negate the value first
2351 int16_t imm = ~(N->getSExtValue());
2352 return XformMskToBitPosU4Imm(imm);
2355 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2356 // Return the bit position we will set [0-7].
2358 int8_t imm = N->getSExtValue();
2359 return XformMskToBitPosU3Imm(imm);
2362 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2363 // Return the bit position we will clear [0-7].
2365 // we bit negate the value first
2366 int8_t imm = ~(N->getSExtValue());
2367 return XformMskToBitPosU3Imm(imm);
2370 //===----------------------------------------------------------------------===//
2371 // Template class for MemOp instructions with the register value.
2372 //===----------------------------------------------------------------------===//
2373 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2374 string memOp, bits<2> memOpBits> :
2376 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2377 opc#"($base+#$offset)"#memOp#"$delta",
2379 Requires<[UseMEMOP]> {
2384 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2386 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2387 !if (!eq(opcBits, 0b01), offset{6-1},
2388 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2390 let opExtentAlign = opcBits;
2391 let IClass = 0b0011;
2392 let Inst{27-24} = 0b1110;
2393 let Inst{22-21} = opcBits;
2394 let Inst{20-16} = base;
2396 let Inst{12-7} = offsetBits;
2397 let Inst{6-5} = memOpBits;
2398 let Inst{4-0} = delta;
2401 //===----------------------------------------------------------------------===//
2402 // Template class for MemOp instructions with the immediate value.
2403 //===----------------------------------------------------------------------===//
2404 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2405 string memOp, bits<2> memOpBits> :
2407 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2408 opc#"($base+#$offset)"#memOp#"#$delta"
2409 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2411 Requires<[UseMEMOP]> {
2416 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2418 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2419 !if (!eq(opcBits, 0b01), offset{6-1},
2420 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2422 let opExtentAlign = opcBits;
2423 let IClass = 0b0011;
2424 let Inst{27-24} = 0b1111;
2425 let Inst{22-21} = opcBits;
2426 let Inst{20-16} = base;
2428 let Inst{12-7} = offsetBits;
2429 let Inst{6-5} = memOpBits;
2430 let Inst{4-0} = delta;
2433 // multiclass to define MemOp instructions with register operand.
2434 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2435 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2436 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2437 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2438 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2441 // multiclass to define MemOp instructions with immediate Operand.
2442 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2443 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2444 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2445 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2446 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2449 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2450 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2451 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2454 // Define MemOp instructions.
2455 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2456 validSubTargets =HasV4SubT in {
2457 let opExtentBits = 6, accessSize = ByteAccess, isCodeGenOnly = 0 in
2458 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2460 let opExtentBits = 7, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
2461 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2463 let opExtentBits = 8, accessSize = WordAccess, isCodeGenOnly = 0 in
2464 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2467 //===----------------------------------------------------------------------===//
2468 // Multiclass to define 'Def Pats' for ALU operations on the memory
2469 // Here value used for the ALU operation is an immediate value.
2470 // mem[bh](Rs+#0) += #U5
2471 // mem[bh](Rs+#u6) += #U5
2472 //===----------------------------------------------------------------------===//
2474 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2475 InstHexagon MI, SDNode OpNode> {
2476 let AddedComplexity = 180 in
2477 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2479 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2481 let AddedComplexity = 190 in
2482 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2484 (add IntRegs:$base, ExtPred:$offset)),
2485 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2488 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2489 InstHexagon addMI, InstHexagon subMI> {
2490 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2491 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2494 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2496 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2497 L4_iadd_memoph_io, L4_isub_memoph_io>;
2499 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2500 L4_iadd_memopb_io, L4_isub_memopb_io>;
2503 let Predicates = [HasV4T, UseMEMOP] in {
2504 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2505 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2506 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2509 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
2513 //===----------------------------------------------------------------------===//
2514 // multiclass to define 'Def Pats' for ALU operations on the memory.
2515 // Here value used for the ALU operation is a negative value.
2516 // mem[bh](Rs+#0) += #m5
2517 // mem[bh](Rs+#u6) += #m5
2518 //===----------------------------------------------------------------------===//
2520 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2521 PatLeaf immPred, ComplexPattern addrPred,
2522 SDNodeXForm xformFunc, InstHexagon MI> {
2523 let AddedComplexity = 190 in
2524 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2526 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2528 let AddedComplexity = 195 in
2529 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2531 (add IntRegs:$base, extPred:$offset)),
2532 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2535 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2537 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2538 ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>;
2540 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2541 ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>;
2544 let Predicates = [HasV4T, UseMEMOP] in {
2545 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2546 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2547 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2550 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2551 ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>;
2554 //===----------------------------------------------------------------------===//
2555 // Multiclass to define 'def Pats' for bit operations on the memory.
2556 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2557 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2558 //===----------------------------------------------------------------------===//
2560 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2561 PatLeaf extPred, ComplexPattern addrPred,
2562 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2564 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2565 let AddedComplexity = 250 in
2566 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2568 (add IntRegs:$base, extPred:$offset)),
2569 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2571 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2572 let AddedComplexity = 225 in
2573 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2575 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2576 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2579 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2581 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2582 ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
2584 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2585 ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
2586 // Half Word - clrbit
2587 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2588 ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
2589 // Half Word - setbit
2590 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2591 ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
2594 let Predicates = [HasV4T, UseMEMOP] in {
2595 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2596 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2597 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2598 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2599 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2601 // memw(Rs+#0) = [clrbit|setbit](#U5)
2602 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2603 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2604 CLRMEMIMM, L4_iand_memopw_io, and>;
2605 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2606 SETMEMIMM, L4_ior_memopw_io, or>;
2609 //===----------------------------------------------------------------------===//
2610 // Multiclass to define 'def Pats' for ALU operations on the memory
2611 // where addend is a register.
2612 // mem[bhw](Rs+#0) [+-&|]= Rt
2613 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2614 //===----------------------------------------------------------------------===//
2616 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2617 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2618 let AddedComplexity = 141 in
2619 // mem[bhw](Rs+#0) [+-&|]= Rt
2620 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2621 (i32 IntRegs:$addend)),
2622 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2623 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2625 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2626 let AddedComplexity = 150 in
2627 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2628 (i32 IntRegs:$orend)),
2629 (add IntRegs:$base, extPred:$offset)),
2630 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2633 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2634 ComplexPattern addrPred, PatLeaf extPred,
2635 InstHexagon addMI, InstHexagon subMI,
2636 InstHexagon andMI, InstHexagon orMI > {
2638 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2639 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2640 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2641 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2644 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2646 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2647 L4_add_memoph_io, L4_sub_memoph_io,
2648 L4_and_memoph_io, L4_or_memoph_io>;
2650 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2651 L4_add_memopb_io, L4_sub_memopb_io,
2652 L4_and_memopb_io, L4_or_memopb_io>;
2655 // Define 'def Pats' for MemOps with register addend.
2656 let Predicates = [HasV4T, UseMEMOP] in {
2658 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2659 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2660 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2662 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
2663 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io >;
2666 //===----------------------------------------------------------------------===//
2668 //===----------------------------------------------------------------------===//
2670 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2671 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2672 // hardware. However, compiler can still implement these patterns through
2673 // appropriate patterns combinations based on current implemented patterns.
2674 // The implemented patterns are: EQ/GT/GTU.
2675 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2677 // Following instruction is not being extended as it results into the
2678 // incorrect code for negative numbers.
2679 // Pd=cmpb.eq(Rs,#u8)
2681 let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0,
2682 validSubTargets = HasV4SubT in
2683 class CMP_NOT_REG_IMM<string OpName, bits<2> op, Operand ImmOp,
2685 : ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2),
2686 "$dst = !cmp."#OpName#"($src1, #$src2)",
2688 "", ALU32_2op_tc_2early_SLOT0123> {
2693 let IClass = 0b0111;
2694 let Inst{27-24} = 0b0101;
2695 let Inst{23-22} = op;
2696 let Inst{20-16} = src1;
2697 let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9});
2698 let Inst{13-5} = src2{8-0};
2699 let Inst{4-2} = 0b100;
2700 let Inst{1-0} = dst;
2703 let opExtentBits = 10, isExtentSigned = 1 in {
2704 def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst),
2705 (setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>;
2707 def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst),
2708 (not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>;
2711 let opExtentBits = 9 in
2712 def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
2713 (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
2715 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2717 (J2_jumpf (A4_cmpbeqi (i32 IntRegs:$src1), u8ImmPred:$src2),
2721 // SDNode for converting immediate C to C-1.
2722 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2723 // Return the byte immediate const-1 as an SDNode.
2724 int32_t imm = N->getSExtValue();
2725 return XformU7ToU7M1Imm(imm);
2729 // zext( seteq ( and(Rs, 255), u8))
2731 // Pd=cmpb.eq(Rs, #u8)
2732 // if (Pd.new) Rd=#1
2733 // if (!Pd.new) Rd=#0
2734 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2736 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
2742 // zext( setne ( and(Rs, 255), u8))
2744 // Pd=cmpb.eq(Rs, #u8)
2745 // if (Pd.new) Rd=#0
2746 // if (!Pd.new) Rd=#1
2747 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2749 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
2755 // zext( seteq (Rs, and(Rt, 255)))
2757 // Pd=cmpb.eq(Rs, Rt)
2758 // if (Pd.new) Rd=#1
2759 // if (!Pd.new) Rd=#0
2760 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2761 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2762 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
2763 (i32 IntRegs:$Rt))),
2768 // zext( setne (Rs, and(Rt, 255)))
2770 // Pd=cmpb.eq(Rs, Rt)
2771 // if (Pd.new) Rd=#0
2772 // if (!Pd.new) Rd=#1
2773 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2774 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2775 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
2776 (i32 IntRegs:$Rt))),
2781 // zext( setugt ( and(Rs, 255), u8))
2783 // Pd=cmpb.gtu(Rs, #u8)
2784 // if (Pd.new) Rd=#1
2785 // if (!Pd.new) Rd=#0
2786 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2788 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
2794 // zext( setugt ( and(Rs, 254), u8))
2796 // Pd=cmpb.gtu(Rs, #u8)
2797 // if (Pd.new) Rd=#1
2798 // if (!Pd.new) Rd=#0
2799 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2801 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
2807 // zext( setult ( Rs, Rt))
2809 // Pd=cmp.ltu(Rs, Rt)
2810 // if (Pd.new) Rd=#1
2811 // if (!Pd.new) Rd=#0
2812 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2813 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2814 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2815 (i32 IntRegs:$Rs))),
2820 // zext( setlt ( Rs, Rt))
2822 // Pd=cmp.lt(Rs, Rt)
2823 // if (Pd.new) Rd=#1
2824 // if (!Pd.new) Rd=#0
2825 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2826 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2827 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2828 (i32 IntRegs:$Rs))),
2833 // zext( setugt ( Rs, Rt))
2835 // Pd=cmp.gtu(Rs, Rt)
2836 // if (Pd.new) Rd=#1
2837 // if (!Pd.new) Rd=#0
2838 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2839 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2840 (i32 IntRegs:$Rt))),
2844 // This pattern interefers with coremark performance, not implementing at this
2847 // zext( setgt ( Rs, Rt))
2849 // Pd=cmp.gt(Rs, Rt)
2850 // if (Pd.new) Rd=#1
2851 // if (!Pd.new) Rd=#0
2854 // zext( setuge ( Rs, Rt))
2856 // Pd=cmp.ltu(Rs, Rt)
2857 // if (Pd.new) Rd=#0
2858 // if (!Pd.new) Rd=#1
2859 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2860 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2861 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2862 (i32 IntRegs:$Rs))),
2867 // zext( setge ( Rs, Rt))
2869 // Pd=cmp.lt(Rs, Rt)
2870 // if (Pd.new) Rd=#0
2871 // if (!Pd.new) Rd=#1
2872 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2873 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2874 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2875 (i32 IntRegs:$Rs))),
2880 // zext( setule ( Rs, Rt))
2882 // Pd=cmp.gtu(Rs, Rt)
2883 // if (Pd.new) Rd=#0
2884 // if (!Pd.new) Rd=#1
2885 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2886 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2887 (i32 IntRegs:$Rt))),
2892 // zext( setle ( Rs, Rt))
2894 // Pd=cmp.gt(Rs, Rt)
2895 // if (Pd.new) Rd=#0
2896 // if (!Pd.new) Rd=#1
2897 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2898 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
2899 (i32 IntRegs:$Rt))),
2904 // zext( setult ( and(Rs, 255), u8))
2905 // Use the isdigit transformation below
2907 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
2908 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
2909 // The isdigit transformation relies on two 'clever' aspects:
2910 // 1) The data type is unsigned which allows us to eliminate a zero test after
2911 // biasing the expression by 48. We are depending on the representation of
2912 // the unsigned types, and semantics.
2913 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
2916 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
2917 // The code is transformed upstream of llvm into
2918 // retval = (c-48) < 10 ? 1 : 0;
2919 let AddedComplexity = 139 in
2920 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
2921 u7StrictPosImmPred:$src2)))),
2922 (i32 (C2_muxii (i1 (A4_cmpbgtui (i32 IntRegs:$src1),
2923 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
2927 //===----------------------------------------------------------------------===//
2929 //===----------------------------------------------------------------------===//
2931 //===----------------------------------------------------------------------===//
2932 // Multiclass for DeallocReturn
2933 //===----------------------------------------------------------------------===//
2934 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
2935 : LD0Inst<(outs), (ins PredRegs:$src),
2936 !if(isNot, "if (!$src", "if ($src")#
2937 !if(isPredNew, ".new) ", ") ")#mnemonic#
2938 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
2939 [], "", LD_tc_3or4stall_SLOT0> {
2942 let BaseOpcode = "L4_RETURN";
2943 let isPredicatedFalse = isNot;
2944 let isPredicatedNew = isPredNew;
2945 let isTaken = isTak;
2946 let IClass = 0b1001;
2948 let Inst{27-16} = 0b011000011110;
2950 let Inst{13} = isNot;
2951 let Inst{12} = isTak;
2952 let Inst{11} = isPredNew;
2954 let Inst{9-8} = src;
2955 let Inst{4-0} = 0b11110;
2958 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
2959 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
2960 let isPredicated = 1 in {
2961 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
2962 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
2963 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
2967 multiclass LD_MISC_L4_RETURN<string mnemonic> {
2968 let isBarrier = 1, isPredicable = 1 in
2969 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
2970 LD_tc_3or4stall_SLOT0> {
2971 let BaseOpcode = "L4_RETURN";
2972 let IClass = 0b1001;
2973 let Inst{27-16} = 0b011000011110;
2974 let Inst{13-10} = 0b0000;
2975 let Inst{4-0} = 0b11110;
2977 defm t : L4_RETURN_PRED<mnemonic, 0 >;
2978 defm f : L4_RETURN_PRED<mnemonic, 1 >;
2981 let isReturn = 1, isTerminator = 1,
2982 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
2983 validSubTargets = HasV4SubT, isCodeGenOnly = 0 in
2984 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
2986 // Restore registers and dealloc return function call.
2987 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2988 Defs = [R29, R30, R31, PC] in {
2989 let validSubTargets = HasV4SubT in
2990 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
2991 (ins calltarget:$dst),
2997 // Restore registers and dealloc frame before a tail call.
2998 let isCall = 1, isBarrier = 1,
2999 Defs = [R29, R30, R31, PC] in {
3000 let validSubTargets = HasV4SubT in
3001 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3002 (ins calltarget:$dst),
3008 // Save registers function call.
3009 let isCall = 1, isBarrier = 1,
3010 Uses = [R29, R31] in {
3011 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3012 (ins calltarget:$dst),
3013 "call $dst // Save_calle_saved_registers",
3018 //===----------------------------------------------------------------------===//
3019 // Template class for non predicated store instructions with
3020 // GP-Relative or absolute addressing.
3021 //===----------------------------------------------------------------------===//
3022 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3023 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3024 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3025 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3026 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3027 [], "", V2LDST_tc_st_SLOT01> {
3030 bits<16> offsetBits;
3032 string ImmOpStr = !cast<string>(ImmOp);
3033 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3034 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3035 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3036 /* u16_0Imm */ addr{15-0})));
3037 let IClass = 0b0100;
3039 let Inst{26-25} = offsetBits{15-14};
3041 let Inst{23-22} = MajOp;
3042 let Inst{21} = isHalf;
3043 let Inst{20-16} = offsetBits{13-9};
3044 let Inst{13} = offsetBits{8};
3045 let Inst{12-8} = src;
3046 let Inst{7-0} = offsetBits{7-0};
3049 //===----------------------------------------------------------------------===//
3050 // Template class for predicated store instructions with
3051 // GP-Relative or absolute addressing.
3052 //===----------------------------------------------------------------------===//
3053 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3055 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3056 bit isHalf, bit isNot, bit isNew>
3057 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3058 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3059 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3060 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3065 let isPredicatedNew = isNew;
3066 let isPredicatedFalse = isNot;
3068 let IClass = 0b1010;
3070 let Inst{27-24} = 0b1111;
3071 let Inst{23-22} = MajOp;
3072 let Inst{21} = isHalf;
3073 let Inst{17-16} = absaddr{5-4};
3074 let Inst{13} = isNew;
3075 let Inst{12-8} = src2;
3077 let Inst{6-3} = absaddr{3-0};
3078 let Inst{2} = isNot;
3079 let Inst{1-0} = src1;
3082 //===----------------------------------------------------------------------===//
3083 // Template class for predicated store instructions with absolute addressing.
3084 //===----------------------------------------------------------------------===//
3085 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3086 bits<2> MajOp, bit isHalf>
3087 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1, isHalf>,
3089 string ImmOpStr = !cast<string>(ImmOp);
3090 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3091 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3092 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3093 /* u16_0Imm */ 16)));
3095 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3096 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3097 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3098 /* u16_0Imm */ 0)));
3101 //===----------------------------------------------------------------------===//
3102 // Multiclass for store instructions with absolute addressing.
3103 //===----------------------------------------------------------------------===//
3104 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3105 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3106 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3107 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3108 let opExtendable = 0, isPredicable = 1 in
3109 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3112 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3113 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3116 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3117 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3121 //===----------------------------------------------------------------------===//
3122 // Template class for non predicated new-value store instructions with
3123 // GP-Relative or absolute addressing.
3124 //===----------------------------------------------------------------------===//
3125 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3126 isNewValue = 1, opNewValue = 1 in
3127 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3128 : NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
3129 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3130 [], "", V2LDST_tc_st_SLOT0> {
3133 bits<16> offsetBits;
3135 string ImmOpStr = !cast<string>(ImmOp);
3136 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3137 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3138 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3139 /* u16_0Imm */ addr{15-0})));
3140 let IClass = 0b0100;
3143 let Inst{26-25} = offsetBits{15-14};
3144 let Inst{24-21} = 0b0101;
3145 let Inst{20-16} = offsetBits{13-9};
3146 let Inst{13} = offsetBits{8};
3147 let Inst{12-11} = MajOp;
3148 let Inst{10-8} = src;
3149 let Inst{7-0} = offsetBits{7-0};
3152 //===----------------------------------------------------------------------===//
3153 // Template class for predicated new-value store instructions with
3154 // absolute addressing.
3155 //===----------------------------------------------------------------------===//
3156 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3157 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3158 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3159 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3160 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3161 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3162 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3167 let isPredicatedNew = isNew;
3168 let isPredicatedFalse = isNot;
3170 let IClass = 0b1010;
3172 let Inst{27-24} = 0b1111;
3173 let Inst{23-21} = 0b101;
3174 let Inst{17-16} = absaddr{5-4};
3175 let Inst{13} = isNew;
3176 let Inst{12-11} = MajOp;
3177 let Inst{10-8} = src2;
3179 let Inst{6-3} = absaddr{3-0};
3180 let Inst{2} = isNot;
3181 let Inst{1-0} = src1;
3184 //===----------------------------------------------------------------------===//
3185 // Template class for non-predicated new-value store instructions with
3186 // absolute addressing.
3187 //===----------------------------------------------------------------------===//
3188 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3189 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3191 string ImmOpStr = !cast<string>(ImmOp);
3192 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3193 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3194 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3195 /* u16_0Imm */ 16)));
3197 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3198 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3199 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3200 /* u16_0Imm */ 0)));
3203 //===----------------------------------------------------------------------===//
3204 // Multiclass for new-value store instructions with absolute addressing.
3205 //===----------------------------------------------------------------------===//
3206 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3207 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3209 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3210 let opExtendable = 0, isPredicable = 1 in
3211 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3214 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3215 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3218 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3219 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3223 //===----------------------------------------------------------------------===//
3224 // Stores with absolute addressing
3225 //===----------------------------------------------------------------------===//
3226 let accessSize = ByteAccess, isCodeGenOnly = 0 in
3227 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3228 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3230 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3231 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3232 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3234 let accessSize = WordAccess, isCodeGenOnly = 0 in
3235 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3236 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3238 let isNVStorable = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3239 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3241 let isNVStorable = 0, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3242 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3244 //===----------------------------------------------------------------------===//
3245 // GP-relative stores.
3246 // mem[bhwd](#global)=Rt
3247 // Once predicated, these instructions map to absolute addressing mode.
3248 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3249 //===----------------------------------------------------------------------===//
3251 let validSubTargets = HasV4SubT in
3252 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3253 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3254 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3255 // Set BaseOpcode same as absolute addressing instructions so that
3256 // non-predicated GP-Rel instructions can have relate with predicated
3257 // Absolute instruction.
3258 let BaseOpcode = BaseOp#_abs;
3261 let validSubTargets = HasV4SubT in
3262 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3263 bits<2> MajOp, bit isHalf = 0> {
3264 // Set BaseOpcode same as absolute addressing instructions so that
3265 // non-predicated GP-Rel instructions can have relate with predicated
3266 // Absolute instruction.
3267 let BaseOpcode = BaseOp#_abs in {
3268 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3269 globaladdress, 0, isHalf>;
3271 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3275 let accessSize = ByteAccess in
3276 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3278 let accessSize = HalfWordAccess in
3279 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3281 let accessSize = WordAccess in
3282 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3284 let isNVStorable = 0, accessSize = DoubleWordAccess in
3285 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3286 u16_3Imm, 0b11>, PredNewRel;
3288 let isNVStorable = 0, accessSize = HalfWordAccess in
3289 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3290 u16_1Imm, 0b01, 1>, PredNewRel;
3292 let Predicates = [HasV4T], AddedComplexity = 30 in {
3293 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3294 (HexagonCONST32 tglobaladdr:$absaddr)),
3295 (S2_storerbabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3297 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3298 (HexagonCONST32 tglobaladdr:$absaddr)),
3299 (S2_storerhabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3301 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3302 (S2_storeriabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3304 def : Pat<(store (i64 DoubleRegs:$src1),
3305 (HexagonCONST32 tglobaladdr:$absaddr)),
3306 (S2_storerdabs tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3309 // 64 bit atomic store
3310 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3311 (i64 DoubleRegs:$src1)),
3312 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3315 // Map from store(globaladdress) -> memd(#foo)
3316 let AddedComplexity = 100 in
3317 def : Pat <(store (i64 DoubleRegs:$src1),
3318 (HexagonCONST32_GP tglobaladdr:$global)),
3319 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3321 // 8 bit atomic store
3322 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3323 (i32 IntRegs:$src1)),
3324 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3326 // Map from store(globaladdress) -> memb(#foo)
3327 let AddedComplexity = 100 in
3328 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3329 (HexagonCONST32_GP tglobaladdr:$global)),
3330 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3332 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3333 // to "r0 = 1; memw(#foo) = r0"
3334 let AddedComplexity = 100 in
3335 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3336 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3338 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3339 (i32 IntRegs:$src1)),
3340 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3342 // Map from store(globaladdress) -> memh(#foo)
3343 let AddedComplexity = 100 in
3344 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3345 (HexagonCONST32_GP tglobaladdr:$global)),
3346 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3348 // 32 bit atomic store
3349 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3350 (i32 IntRegs:$src1)),
3351 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3353 // Map from store(globaladdress) -> memw(#foo)
3354 let AddedComplexity = 100 in
3355 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3356 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3358 //===----------------------------------------------------------------------===//
3359 // Template class for non predicated load instructions with
3360 // absolute addressing mode.
3361 //===----------------------------------------------------------------------===//
3362 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT in
3363 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3364 bits<3> MajOp, Operand AddrOp, bit isAbs>
3365 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3366 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3367 [], "", V2LDST_tc_ld_SLOT01> {
3370 bits<16> offsetBits;
3372 string ImmOpStr = !cast<string>(ImmOp);
3373 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3374 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3375 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3376 /* u16_0Imm */ addr{15-0})));
3378 let IClass = 0b0100;
3381 let Inst{26-25} = offsetBits{15-14};
3383 let Inst{23-21} = MajOp;
3384 let Inst{20-16} = offsetBits{13-9};
3385 let Inst{13-5} = offsetBits{8-0};
3386 let Inst{4-0} = dst;
3389 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3391 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1>, AddrModeRel {
3393 string ImmOpStr = !cast<string>(ImmOp);
3394 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3395 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3396 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3397 /* u16_0Imm */ 16)));
3399 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3400 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3401 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3402 /* u16_0Imm */ 0)));
3404 //===----------------------------------------------------------------------===//
3405 // Template class for predicated load instructions with
3406 // absolute addressing mode.
3407 //===----------------------------------------------------------------------===//
3408 let isPredicated = 1, hasNewValue = 1, opExtentBits = 6, opExtendable = 2 in
3409 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3410 bit isPredNot, bit isPredNew>
3411 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3412 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3413 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3418 let isPredicatedNew = isPredNew;
3419 let isPredicatedFalse = isPredNot;
3421 let IClass = 0b1001;
3423 let Inst{27-24} = 0b1111;
3424 let Inst{23-21} = MajOp;
3425 let Inst{20-16} = absaddr{5-1};
3427 let Inst{12} = isPredNew;
3428 let Inst{11} = isPredNot;
3429 let Inst{10-9} = src1;
3430 let Inst{8} = absaddr{0};
3432 let Inst{4-0} = dst;
3435 //===----------------------------------------------------------------------===//
3436 // Multiclass for the load instructions with absolute addressing mode.
3437 //===----------------------------------------------------------------------===//
3438 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3440 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3442 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3445 let addrMode = Absolute, isExtended = 1 in
3446 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3447 Operand ImmOp, bits<3> MajOp> {
3448 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3449 let opExtendable = 1, isPredicable = 1 in
3450 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3453 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3454 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3458 let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3459 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3460 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3463 let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3464 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3465 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3468 let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
3469 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3471 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3472 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3474 //===----------------------------------------------------------------------===//
3475 // multiclass for load instructions with GP-relative addressing mode.
3476 // Rx=mem[bhwd](##global)
3477 // Once predicated, these instructions map to absolute addressing mode.
3478 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3479 //===----------------------------------------------------------------------===//
3481 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3483 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3484 let BaseOpcode = BaseOp#_abs;
3487 let accessSize = ByteAccess, hasNewValue = 1 in {
3488 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3489 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3492 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3493 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3494 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3497 let accessSize = WordAccess, hasNewValue = 1 in
3498 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3500 let accessSize = DoubleWordAccess in
3501 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3503 let Predicates = [HasV4T], AddedComplexity = 30 in {
3504 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3505 (L4_loadri_abs tglobaladdr: $absaddr)>;
3507 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3508 (L4_loadrb_abs tglobaladdr:$absaddr)>;
3510 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3511 (L4_loadrub_abs tglobaladdr:$absaddr)>;
3513 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3514 (L4_loadrh_abs tglobaladdr:$absaddr)>;
3516 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3517 (L4_loadruh_abs tglobaladdr:$absaddr)>;
3520 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3521 (i64 (L2_loadrdgp tglobaladdr:$global))>;
3523 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3524 (i32 (L2_loadrigp tglobaladdr:$global))>;
3526 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3527 (i32 (L2_loadruhgp tglobaladdr:$global))>;
3529 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3530 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3532 // Map from load(globaladdress) -> memw(#foo + 0)
3533 let AddedComplexity = 100 in
3534 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3535 (i64 (L2_loadrdgp tglobaladdr:$global))>;
3537 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3538 let AddedComplexity = 100 in
3539 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3540 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3542 // When the Interprocedural Global Variable optimizer realizes that a certain
3543 // global variable takes only two constant values, it shrinks the global to
3544 // a boolean. Catch those loads here in the following 3 patterns.
3545 let AddedComplexity = 100 in
3546 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3547 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3549 let AddedComplexity = 100 in
3550 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3551 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3553 // Map from load(globaladdress) -> memb(#foo)
3554 let AddedComplexity = 100 in
3555 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3556 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3558 // Map from load(globaladdress) -> memb(#foo)
3559 let AddedComplexity = 100 in
3560 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3561 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3563 let AddedComplexity = 100 in
3564 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3565 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3567 // Map from load(globaladdress) -> memub(#foo)
3568 let AddedComplexity = 100 in
3569 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3570 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3572 // Map from load(globaladdress) -> memh(#foo)
3573 let AddedComplexity = 100 in
3574 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3575 (i32 (L2_loadrhgp tglobaladdr:$global))>;
3577 // Map from load(globaladdress) -> memh(#foo)
3578 let AddedComplexity = 100 in
3579 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3580 (i32 (L2_loadrhgp tglobaladdr:$global))>;
3582 // Map from load(globaladdress) -> memuh(#foo)
3583 let AddedComplexity = 100 in
3584 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3585 (i32 (L2_loadruhgp tglobaladdr:$global))>;
3587 // Map from load(globaladdress) -> memw(#foo)
3588 let AddedComplexity = 100 in
3589 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3590 (i32 (L2_loadrigp tglobaladdr:$global))>;
3593 // Transfer global address into a register
3594 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3595 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3596 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3598 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3601 // Transfer a block address into a register
3602 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3603 (TFRI_V4 tblockaddress:$src1)>,
3606 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3607 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3608 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3609 (ins PredRegs:$src1, s16Ext:$src2),
3610 "if($src1) $dst = #$src2",
3614 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3615 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3616 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3617 (ins PredRegs:$src1, s16Ext:$src2),
3618 "if(!$src1) $dst = #$src2",
3622 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3623 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3624 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3625 (ins PredRegs:$src1, s16Ext:$src2),
3626 "if($src1.new) $dst = #$src2",
3630 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3631 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3632 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3633 (ins PredRegs:$src1, s16Ext:$src2),
3634 "if(!$src1.new) $dst = #$src2",
3638 let AddedComplexity = 50, Predicates = [HasV4T] in
3639 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3640 (TFRI_V4 tglobaladdr:$src1)>,
3644 // Load - Indirect with long offset: These instructions take global address
3646 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3647 validSubTargets = HasV4SubT in
3648 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3649 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3650 "$dst=memd($src1<<#$src2+##$offset)",
3651 [(set (i64 DoubleRegs:$dst),
3652 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3653 (HexagonCONST32 tglobaladdr:$offset))))]>,
3656 let AddedComplexity = 40 in
3657 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3658 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3659 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3660 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3661 !strconcat("$dst = ",
3662 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3664 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3665 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3669 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3670 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3671 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3672 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3673 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3674 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3675 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3677 let AddedComplexity = 40 in
3678 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3679 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3680 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3683 let AddedComplexity = 40 in
3684 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3685 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3686 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3689 let Predicates = [HasV4T], AddedComplexity = 30 in {
3690 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3691 (S2_storerbabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3693 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3694 (S2_storerhabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3696 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3697 (S2_storeriabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3700 let Predicates = [HasV4T], AddedComplexity = 30 in {
3701 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3702 (L4_loadri_abs u0AlwaysExtPred:$src)>;
3704 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3705 (L4_loadrb_abs u0AlwaysExtPred:$src)>;
3707 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3708 (L4_loadrub_abs u0AlwaysExtPred:$src)>;
3710 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3711 (L4_loadrh_abs u0AlwaysExtPred:$src)>;
3713 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3714 (L4_loadruh_abs u0AlwaysExtPred:$src)>;
3717 // Indexed store word - global address.
3718 // memw(Rs+#u6:2)=#S8
3719 let AddedComplexity = 10 in
3720 def STriw_offset_ext_V4 : STInst<(outs),
3721 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3722 "memw($src1+#$src2) = ##$src3",
3723 [(store (HexagonCONST32 tglobaladdr:$src3),
3724 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3727 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3728 (i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
3731 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3732 (i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
3737 // We need a complexity of 120 here to override preceding handling of
3739 let Predicates = [HasV4T], AddedComplexity = 120 in {
3740 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3741 (i64 (A4_combineir 0, (L4_loadrb_abs tglobaladdr:$addr)))>;
3743 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3744 (i64 (A4_combineir 0, (L4_loadrub_abs tglobaladdr:$addr)))>;
3746 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3747 (i64 (A2_sxtw (L4_loadrb_abs tglobaladdr:$addr)))>;
3749 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3750 (i64 (A4_combineir 0, (L4_loadrb_abs FoldGlobalAddr:$addr)))>;
3752 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3753 (i64 (A4_combineir 0, (L4_loadrub_abs FoldGlobalAddr:$addr)))>;
3755 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3756 (i64 (A2_sxtw (L4_loadrb_abs FoldGlobalAddr:$addr)))>;
3759 // We need a complexity of 120 here to override preceding handling of
3761 let AddedComplexity = 120 in {
3762 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3763 (i64 (A4_combineir 0, (L4_loadrh_abs tglobaladdr:$addr)))>,
3766 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3767 (i64 (A4_combineir 0, (L4_loadruh_abs tglobaladdr:$addr)))>,
3770 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3771 (i64 (A2_sxtw (L4_loadrh_abs tglobaladdr:$addr)))>,
3774 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3775 (i64 (A4_combineir 0, (L4_loadrh_abs FoldGlobalAddr:$addr)))>,
3778 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3779 (i64 (A4_combineir 0, (L4_loadruh_abs FoldGlobalAddr:$addr)))>,
3782 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3783 (i64 (A2_sxtw (L4_loadrh_abs FoldGlobalAddr:$addr)))>,
3787 // We need a complexity of 120 here to override preceding handling of
3789 let AddedComplexity = 120 in {
3790 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3791 (i64 (A4_combineir 0, (L4_loadri_abs tglobaladdr:$addr)))>,
3794 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3795 (i64 (A4_combineir 0, (L4_loadri_abs tglobaladdr:$addr)))>,
3798 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3799 (i64 (A2_sxtw (L4_loadri_abs tglobaladdr:$addr)))>,
3802 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3803 (i64 (A4_combineir 0, (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3806 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3807 (i64 (A4_combineir 0, (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3810 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3811 (i64 (A2_sxtw (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3815 // Indexed store double word - global address.
3816 // memw(Rs+#u6:2)=#S8
3817 let AddedComplexity = 10 in
3818 def STrih_offset_ext_V4 : STInst<(outs),
3819 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3820 "memh($src1+#$src2) = ##$src3",
3821 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3822 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3824 // Map from store(globaladdress + x) -> memd(#foo + x)
3825 let AddedComplexity = 100 in
3826 def : Pat<(store (i64 DoubleRegs:$src1),
3827 FoldGlobalAddrGP:$addr),
3828 (S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3831 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3832 (i64 DoubleRegs:$src1)),
3833 (S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3836 // Map from store(globaladdress + x) -> memb(#foo + x)
3837 let AddedComplexity = 100 in
3838 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3839 (S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3842 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3843 (S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3846 // Map from store(globaladdress + x) -> memh(#foo + x)
3847 let AddedComplexity = 100 in
3848 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3849 (S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3852 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3853 (S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3856 // Map from store(globaladdress + x) -> memw(#foo + x)
3857 let AddedComplexity = 100 in
3858 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3859 (S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3862 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3863 (S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3866 // Map from load(globaladdress + x) -> memd(#foo + x)
3867 let AddedComplexity = 100 in
3868 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3869 (i64 (L4_loadrd_abs FoldGlobalAddrGP:$addr))>,
3872 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3873 (i64 (L4_loadrd_abs FoldGlobalAddrGP:$addr))>,
3876 // Map from load(globaladdress + x) -> memb(#foo + x)
3877 let AddedComplexity = 100 in
3878 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3879 (i32 (L4_loadrb_abs FoldGlobalAddrGP:$addr))>,
3882 // Map from load(globaladdress + x) -> memb(#foo + x)
3883 let AddedComplexity = 100 in
3884 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3885 (i32 (L4_loadrb_abs FoldGlobalAddrGP:$addr))>,
3888 //let AddedComplexity = 100 in
3889 let AddedComplexity = 100 in
3890 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3891 (i32 (L4_loadrh_abs FoldGlobalAddrGP:$addr))>,
3894 // Map from load(globaladdress + x) -> memh(#foo + x)
3895 let AddedComplexity = 100 in
3896 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3897 (i32 (L4_loadrh_abs FoldGlobalAddrGP:$addr))>,
3900 // Map from load(globaladdress + x) -> memuh(#foo + x)
3901 let AddedComplexity = 100 in
3902 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3903 (i32 (L4_loadruh_abs FoldGlobalAddrGP:$addr))>,
3906 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3907 (i32 (L4_loadruh_abs FoldGlobalAddrGP:$addr))>,
3910 // Map from load(globaladdress + x) -> memub(#foo + x)
3911 let AddedComplexity = 100 in
3912 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3913 (i32 (L4_loadrub_abs FoldGlobalAddrGP:$addr))>,
3916 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3917 (i32 (L4_loadrub_abs FoldGlobalAddrGP:$addr))>,
3920 // Map from load(globaladdress + x) -> memw(#foo + x)
3921 let AddedComplexity = 100 in
3922 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3923 (i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>,
3926 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3927 (i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>,
3930 //===----------------------------------------------------------------------===//
3931 // :raw for of boundscheck:hi:lo insns
3932 //===----------------------------------------------------------------------===//
3934 // A4_boundscheck_lo: Detect if a register is within bounds.
3935 let hasSideEffects = 0, isCodeGenOnly = 0 in
3936 def A4_boundscheck_lo: ALU64Inst <
3937 (outs PredRegs:$Pd),
3938 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3939 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
3944 let IClass = 0b1101;
3946 let Inst{27-23} = 0b00100;
3948 let Inst{7-5} = 0b100;
3950 let Inst{20-16} = Rss;
3951 let Inst{12-8} = Rtt;
3954 // A4_boundscheck_hi: Detect if a register is within bounds.
3955 let hasSideEffects = 0, isCodeGenOnly = 0 in
3956 def A4_boundscheck_hi: ALU64Inst <
3957 (outs PredRegs:$Pd),
3958 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3959 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
3964 let IClass = 0b1101;
3966 let Inst{27-23} = 0b00100;
3968 let Inst{7-5} = 0b101;
3970 let Inst{20-16} = Rss;
3971 let Inst{12-8} = Rtt;
3974 let hasSideEffects = 0 in
3975 def A4_boundscheck : MInst <
3976 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3977 "$Pd=boundscheck($Rs,$Rtt)">;
3979 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
3980 let isPredicateLate = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
3981 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
3982 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3983 "$Pd = tlbmatch($Rs, $Rt)",
3984 [], "", ALU64_tc_2early_SLOT23> {
3989 let IClass = 0b1101;
3990 let Inst{27-23} = 0b00100;
3991 let Inst{20-16} = Rs;
3993 let Inst{12-8} = Rt;
3994 let Inst{7-5} = 0b011;
3998 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
3999 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
4000 // We don't really want either one here.
4001 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
4002 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
4005 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
4006 // really do a load.
4007 let hasSideEffects = 1, mayLoad = 0, isCodeGenOnly = 0 in
4008 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
4009 "dcfetch($Rs + #$u11_3)",
4010 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
4011 "", LD_tc_ld_SLOT0> {
4015 let IClass = 0b1001;
4016 let Inst{27-21} = 0b0100000;
4017 let Inst{20-16} = Rs;
4019 let Inst{10-0} = u11_3{13-3};
4022 //===----------------------------------------------------------------------===//
4023 // Compound instructions
4024 //===----------------------------------------------------------------------===//
4026 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4027 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4028 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4029 isTerminator = 1, validSubTargets = HasV4SubT in
4030 class CJInst_tstbit_R0<string px, bit np, string tnt>
4031 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4032 ""#px#" = tstbit($Rs, #0); if ("
4033 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4034 [], "", COMPOUND, TypeCOMPOUND> {
4039 let isPredicatedFalse = np;
4040 // tnt: Taken/Not Taken
4041 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4042 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4044 let IClass = 0b0001;
4045 let Inst{27-26} = 0b00;
4046 let Inst{25} = !if (!eq(px, "!p1"), 1,
4047 !if (!eq(px, "p1"), 1, 0));
4048 let Inst{24-23} = 0b11;
4050 let Inst{21-20} = r9_2{10-9};
4051 let Inst{19-16} = Rs;
4052 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4053 let Inst{9-8} = 0b11;
4054 let Inst{7-1} = r9_2{8-2};
4057 let Defs = [PC, P0], Uses = [P0], isCodeGenOnly = 0 in {
4058 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4059 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4060 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4061 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4064 let Defs = [PC, P1], Uses = [P1], isCodeGenOnly = 0 in {
4065 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4066 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4067 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4068 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4072 let isBranch = 1, hasSideEffects = 0,
4073 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4074 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4075 opExtendable = 2, isTerminator = 1, validSubTargets = HasV4SubT in
4076 class CJInst_RR<string px, string op, bit np, string tnt>
4077 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4078 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4079 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4080 [], "", COMPOUND, TypeCOMPOUND> {
4086 let isPredicatedFalse = np;
4087 // tnt: Taken/Not Taken
4088 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4089 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4091 let IClass = 0b0001;
4092 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4093 !if (!eq(op, "gt"), 0b01001,
4094 !if (!eq(op, "gtu"), 0b01010, 0)));
4096 let Inst{21-20} = r9_2{10-9};
4097 let Inst{19-16} = Rs;
4098 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4099 // px: Predicate reg 0/1
4100 let Inst{12} = !if (!eq(px, "!p1"), 1,
4101 !if (!eq(px, "p1"), 1, 0));
4102 let Inst{11-8} = Rt;
4103 let Inst{7-1} = r9_2{8-2};
4106 // P[10] taken/not taken.
4107 multiclass T_tnt_CJInst_RR<string op, bit np> {
4108 let Defs = [PC, P0], Uses = [P0] in {
4109 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4110 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4112 let Defs = [PC, P1], Uses = [P1] in {
4113 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4114 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4117 // Predicate / !Predicate
4118 multiclass T_pnp_CJInst_RR<string op>{
4119 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4120 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4122 // TypeCJ Instructions compare RR and jump
4123 let isCodeGenOnly = 0 in {
4124 defm eq : T_pnp_CJInst_RR<"eq">;
4125 defm gt : T_pnp_CJInst_RR<"gt">;
4126 defm gtu : T_pnp_CJInst_RR<"gtu">;
4129 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4130 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4131 opExtentAlign = 2, opExtendable = 2, isTerminator = 1,
4132 validSubTargets = HasV4SubT in
4133 class CJInst_RU5<string px, string op, bit np, string tnt>
4134 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4135 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4136 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4137 [], "", COMPOUND, TypeCOMPOUND> {
4143 let isPredicatedFalse = np;
4144 // tnt: Taken/Not Taken
4145 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4146 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4148 let IClass = 0b0001;
4149 let Inst{27-26} = 0b00;
4150 // px: Predicate reg 0/1
4151 let Inst{25} = !if (!eq(px, "!p1"), 1,
4152 !if (!eq(px, "p1"), 1, 0));
4153 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4154 !if (!eq(op, "gt"), 0b01,
4155 !if (!eq(op, "gtu"), 0b10, 0)));
4157 let Inst{21-20} = r9_2{10-9};
4158 let Inst{19-16} = Rs;
4159 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4160 let Inst{12-8} = U5;
4161 let Inst{7-1} = r9_2{8-2};
4163 // P[10] taken/not taken.
4164 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4165 let Defs = [PC, P0], Uses = [P0] in {
4166 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4167 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4169 let Defs = [PC, P1], Uses = [P1] in {
4170 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4171 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4174 // Predicate / !Predicate
4175 multiclass T_pnp_CJInst_RU5<string op>{
4176 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4177 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4179 // TypeCJ Instructions compare RI and jump
4180 let isCodeGenOnly = 0 in {
4181 defm eq : T_pnp_CJInst_RU5<"eq">;
4182 defm gt : T_pnp_CJInst_RU5<"gt">;
4183 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4186 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4187 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4188 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4189 isTerminator = 1, validSubTargets = HasV4SubT in
4190 class CJInst_Rn1<string px, string op, bit np, string tnt>
4191 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4192 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4193 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4194 [], "", COMPOUND, TypeCOMPOUND> {
4199 let isPredicatedFalse = np;
4200 // tnt: Taken/Not Taken
4201 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4202 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4204 let IClass = 0b0001;
4205 let Inst{27-26} = 0b00;
4206 let Inst{25} = !if (!eq(px, "!p1"), 1,
4207 !if (!eq(px, "p1"), 1, 0));
4209 let Inst{24-23} = 0b11;
4211 let Inst{21-20} = r9_2{10-9};
4212 let Inst{19-16} = Rs;
4213 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4214 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4215 !if (!eq(op, "gt"), 0b01, 0));
4216 let Inst{7-1} = r9_2{8-2};
4219 // P[10] taken/not taken.
4220 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4221 let Defs = [PC, P0], Uses = [P0] in {
4222 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4223 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4225 let Defs = [PC, P1], Uses = [P1] in {
4226 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4227 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4230 // Predicate / !Predicate
4231 multiclass T_pnp_CJInst_Rn1<string op>{
4232 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4233 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4235 // TypeCJ Instructions compare -1 and jump
4236 let isCodeGenOnly = 0 in {
4237 defm eq : T_pnp_CJInst_Rn1<"eq">;
4238 defm gt : T_pnp_CJInst_Rn1<"gt">;
4241 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4242 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4243 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4244 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4245 isCodeGenOnly = 0 in
4246 def J4_jumpseti: CJInst <
4248 (ins u6Imm:$U6, brtarget:$r9_2),
4249 "$Rd = #$U6 ; jump $r9_2"> {
4254 let IClass = 0b0001;
4255 let Inst{27-24} = 0b0110;
4256 let Inst{21-20} = r9_2{10-9};
4257 let Inst{19-16} = Rd;
4258 let Inst{13-8} = U6;
4259 let Inst{7-1} = r9_2{8-2};
4262 // J4_jumpsetr: Direct unconditional jump and transfer register.
4263 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4264 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4265 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4266 isCodeGenOnly = 0 in
4267 def J4_jumpsetr: CJInst <
4269 (ins IntRegs:$Rs, brtarget:$r9_2),
4270 "$Rd = $Rs ; jump $r9_2"> {
4275 let IClass = 0b0001;
4276 let Inst{27-24} = 0b0111;
4277 let Inst{21-20} = r9_2{10-9};
4278 let Inst{11-8} = Rd;
4279 let Inst{19-16} = Rs;
4280 let Inst{7-1} = r9_2{8-2};