1 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
4 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
6 let isReMaterializable = 1, isMoveImm = 1 in
7 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
8 "$dst = CONST32(#$global)",
9 [(set (f32 IntRegs:$dst),
10 (HexagonFCONST32 tglobaladdr:$global))]>,
13 let isReMaterializable = 1, isMoveImm = 1 in
14 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
15 "$dst = CONST64(#$src1)",
16 [(set DoubleRegs:$dst, fpimm:$src1)]>,
19 let isReMaterializable = 1, isMoveImm = 1 in
20 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
21 "$dst = CONST32(#$src1)",
22 [(set IntRegs:$dst, fpimm:$src1)]>,
25 // Transfer immediate float.
26 // Only works with single precision fp value.
27 // For double precision, use CONST64_float_real, as 64bit transfer
28 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
29 // Make sure that complexity is more than the CONST32 pattern in
30 // HexagonInstrInfo.td patterns.
31 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
32 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
34 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
36 [(set IntRegs:$dst, fpimm:$src1)]>,
39 let isExtended = 1, opExtendable = 2, isPredicated = 1,
40 neverHasSideEffects = 1, validSubTargets = HasV5SubT in
41 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
42 (ins PredRegs:$src1, f32Ext:$src2),
43 "if ($src1) $dst = #$src2",
47 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
48 neverHasSideEffects = 1, validSubTargets = HasV5SubT in
49 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
50 (ins PredRegs:$src1, f32Ext:$src2),
51 "if (!$src1) $dst =#$src2",
55 // Convert single precision to double precision and vice-versa.
56 def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
57 "$dst = convert_sf2df($src)",
58 [(set DoubleRegs:$dst, (fextend IntRegs:$src))]>,
61 def CONVERT_df2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
62 "$dst = convert_df2sf($src)",
63 [(set IntRegs:$dst, (fround DoubleRegs:$src))]>,
68 def LDrid_f : LDInst<(outs DoubleRegs:$dst),
71 [(set DoubleRegs:$dst, (f64 (load ADDRriS11_3:$addr)))]>,
75 let AddedComplexity = 20 in
76 def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst),
77 (ins IntRegs:$src1, s11_3Imm:$offset),
78 "$dst = memd($src1+#$offset)",
79 [(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1,
80 s11_3ImmPred:$offset))))]>,
83 def LDriw_f : LDInst<(outs IntRegs:$dst),
84 (ins MEMri:$addr), "$dst = memw($addr)",
85 [(set IntRegs:$dst, (f32 (load ADDRriS11_2:$addr)))]>,
89 let AddedComplexity = 20 in
90 def LDriw_indexed_f : LDInst<(outs IntRegs:$dst),
91 (ins IntRegs:$src1, s11_2Imm:$offset),
92 "$dst = memw($src1+#$offset)",
93 [(set IntRegs:$dst, (f32 (load (add IntRegs:$src1,
94 s11_2ImmPred:$offset))))]>,
98 def STriw_f : STInst<(outs),
99 (ins MEMri:$addr, IntRegs:$src1),
100 "memw($addr) = $src1",
101 [(store (f32 IntRegs:$src1), ADDRriS11_2:$addr)]>,
104 let AddedComplexity = 10 in
105 def STriw_indexed_f : STInst<(outs),
106 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
107 "memw($src1+#$src2) = $src3",
108 [(store (f32 IntRegs:$src3),
109 (add IntRegs:$src1, s11_2ImmPred:$src2))]>,
112 def STrid_f : STInst<(outs),
113 (ins MEMri:$addr, DoubleRegs:$src1),
114 "memd($addr) = $src1",
115 [(store (f64 DoubleRegs:$src1), ADDRriS11_2:$addr)]>,
118 // Indexed store double word.
119 let AddedComplexity = 10 in
120 def STrid_indexed_f : STInst<(outs),
121 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
122 "memd($src1+#$src2) = $src3",
123 [(store (f64 DoubleRegs:$src3),
124 (add IntRegs:$src1, s11_3ImmPred:$src2))]>,
129 let isCommutable = 1 in
130 def fADD_rr : ALU64_rr<(outs IntRegs:$dst),
131 (ins IntRegs:$src1, IntRegs:$src2),
132 "$dst = sfadd($src1, $src2)",
133 [(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>,
136 let isCommutable = 1 in
137 def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
139 "$dst = dfadd($src1, $src2)",
140 [(set DoubleRegs:$dst, (fadd DoubleRegs:$src1,
141 DoubleRegs:$src2))]>,
144 def fSUB_rr : ALU64_rr<(outs IntRegs:$dst),
145 (ins IntRegs:$src1, IntRegs:$src2),
146 "$dst = sfsub($src1, $src2)",
147 [(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>,
150 def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
152 "$dst = dfsub($src1, $src2)",
153 [(set DoubleRegs:$dst, (fsub DoubleRegs:$src1,
154 DoubleRegs:$src2))]>,
157 let isCommutable = 1 in
158 def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
159 (ins IntRegs:$src1, IntRegs:$src2),
160 "$dst = sfmpy($src1, $src2)",
161 [(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>,
164 let isCommutable = 1 in
165 def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
167 "$dst = dfmpy($src1, $src2)",
168 [(set DoubleRegs:$dst, (fmul DoubleRegs:$src1,
169 DoubleRegs:$src2))]>,
173 let isCompare = 1 in {
174 multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
175 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
176 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
178 (OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
182 multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
183 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
184 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
186 (OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
191 defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>;
192 defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>;
193 defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>;
194 defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>;
195 defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>;
196 defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>;
198 defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>;
199 defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>;
200 defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>;
201 defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>;
202 defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>;
203 defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>;
206 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
207 (i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>,
210 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
211 (i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
214 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
215 (i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
218 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
219 (i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
220 (f64 DoubleRegs:$src1)))>,
224 def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
225 (i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1),
226 (f64 (CONST64_Float_Real fpimm:$src2))))>,
229 def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
230 (i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
234 def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
235 (i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>,
238 def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
239 (i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
242 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
243 (i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
246 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
247 (i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
248 (f64 DoubleRegs:$src1)))>,
252 // rs <= rt -> rt >= rs.
253 def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
254 (i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>,
257 def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
258 (i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
262 // Rss <= Rtt -> Rtt >= Rss.
263 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
264 (i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
267 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
268 (i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
272 // rs <= rt -> rt >= rs.
273 def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
274 (i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>,
277 def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
278 (i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
281 // Rss <= Rtt -> Rtt >= Rss.
282 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
283 (i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
286 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
287 (i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
292 def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
293 (i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
296 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
297 (i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
300 def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
301 (i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
304 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
305 (i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
308 def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
309 (i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
312 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
313 (i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1,
314 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
317 def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
318 (i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
321 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
322 (i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1,
323 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
326 // Convert Integer to Floating Point.
327 def CONVERT_d2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
328 "$dst = convert_d2sf($src)",
329 [(set (f32 IntRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
332 def CONVERT_ud2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
333 "$dst = convert_ud2sf($src)",
334 [(set (f32 IntRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
337 def CONVERT_uw2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
338 "$dst = convert_uw2sf($src)",
339 [(set (f32 IntRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
342 def CONVERT_w2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
343 "$dst = convert_w2sf($src)",
344 [(set (f32 IntRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
347 def CONVERT_d2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
348 "$dst = convert_d2df($src)",
349 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
352 def CONVERT_ud2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
353 "$dst = convert_ud2df($src)",
354 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
357 def CONVERT_uw2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
358 "$dst = convert_uw2df($src)",
359 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
362 def CONVERT_w2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
363 "$dst = convert_w2df($src)",
364 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
367 // Convert Floating Point to Integer - default.
368 def CONVERT_df2uw : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
369 "$dst = convert_df2uw($src):chop",
370 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
373 def CONVERT_df2w : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
374 "$dst = convert_df2w($src):chop",
375 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
378 def CONVERT_sf2uw : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
379 "$dst = convert_sf2uw($src):chop",
380 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
383 def CONVERT_sf2w : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
384 "$dst = convert_sf2w($src):chop",
385 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
388 def CONVERT_df2d : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
389 "$dst = convert_df2d($src):chop",
390 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
393 def CONVERT_df2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
394 "$dst = convert_df2ud($src):chop",
395 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
398 def CONVERT_sf2d : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
399 "$dst = convert_sf2d($src):chop",
400 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
403 def CONVERT_sf2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
404 "$dst = convert_sf2ud($src):chop",
405 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
408 // Convert Floating Point to Integer: non-chopped.
409 let AddedComplexity = 20 in
410 def CONVERT_df2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
411 "$dst = convert_df2uw($src)",
412 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
413 Requires<[HasV5T, IEEERndNearV5T]>;
415 let AddedComplexity = 20 in
416 def CONVERT_df2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
417 "$dst = convert_df2w($src)",
418 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
419 Requires<[HasV5T, IEEERndNearV5T]>;
421 let AddedComplexity = 20 in
422 def CONVERT_sf2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
423 "$dst = convert_sf2uw($src)",
424 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
425 Requires<[HasV5T, IEEERndNearV5T]>;
427 let AddedComplexity = 20 in
428 def CONVERT_sf2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
429 "$dst = convert_sf2w($src)",
430 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
431 Requires<[HasV5T, IEEERndNearV5T]>;
433 let AddedComplexity = 20 in
434 def CONVERT_df2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
435 "$dst = convert_df2d($src)",
436 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
437 Requires<[HasV5T, IEEERndNearV5T]>;
439 let AddedComplexity = 20 in
440 def CONVERT_df2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
441 "$dst = convert_df2ud($src)",
442 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
443 Requires<[HasV5T, IEEERndNearV5T]>;
445 let AddedComplexity = 20 in
446 def CONVERT_sf2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
447 "$dst = convert_sf2d($src)",
448 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
449 Requires<[HasV5T, IEEERndNearV5T]>;
451 let AddedComplexity = 20 in
452 def CONVERT_sf2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
453 "$dst = convert_sf2ud($src)",
454 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
455 Requires<[HasV5T, IEEERndNearV5T]>;
459 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
460 def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
461 (i32 (TFR IntRegs:$src))>,
464 def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
465 (f32 (TFR IntRegs:$src))>,
468 def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
469 (i64 (TFR64 DoubleRegs:$src))>,
472 def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
473 (f64 (TFR64 DoubleRegs:$src))>,
476 // Floating point fused multiply-add.
477 def FMADD_dp : ALU64_acc<(outs DoubleRegs:$dst),
478 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
479 "$dst += dfmpy($src2, $src3)",
480 [(set (f64 DoubleRegs:$dst),
481 (fma DoubleRegs:$src2, DoubleRegs:$src3, DoubleRegs:$src1))],
485 def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
486 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
487 "$dst += sfmpy($src2, $src3)",
488 [(set (f32 IntRegs:$dst),
489 (fma IntRegs:$src2, IntRegs:$src3, IntRegs:$src1))],
494 // Floating point max/min.
495 let AddedComplexity = 100 in
496 def FMAX_dp : ALU64_rr<(outs DoubleRegs:$dst),
497 (ins DoubleRegs:$src1, DoubleRegs:$src2),
498 "$dst = dfmax($src1, $src2)",
499 [(set DoubleRegs:$dst, (f64 (select (i1 (setolt DoubleRegs:$src2,
502 DoubleRegs:$src2)))]>,
505 let AddedComplexity = 100 in
506 def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
507 (ins IntRegs:$src1, IntRegs:$src2),
508 "$dst = sfmax($src1, $src2)",
509 [(set IntRegs:$dst, (f32 (select (i1 (setolt IntRegs:$src2,
515 let AddedComplexity = 100 in
516 def FMIN_dp : ALU64_rr<(outs DoubleRegs:$dst),
517 (ins DoubleRegs:$src1, DoubleRegs:$src2),
518 "$dst = dfmin($src1, $src2)",
519 [(set DoubleRegs:$dst, (f64 (select (i1 (setogt DoubleRegs:$src2,
522 DoubleRegs:$src2)))]>,
525 let AddedComplexity = 100 in
526 def FMIN_sp : ALU64_rr<(outs IntRegs:$dst),
527 (ins IntRegs:$src1, IntRegs:$src2),
528 "$dst = sfmin($src1, $src2)",
529 [(set IntRegs:$dst, (f32 (select (i1 (setogt IntRegs:$src2,
535 // Pseudo instruction to encode a set of conditional transfers.
536 // This instruction is used instead of a mux and trades-off codesize
537 // for performance. We conduct this transformation optimistically in
538 // the hope that these instructions get promoted to dot-new transfers.
539 let AddedComplexity = 100, isPredicated = 1 in
540 def TFR_condset_rr_f : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
543 "Error; should not emit",
544 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
549 let AddedComplexity = 100, isPredicated = 1 in
550 def TFR_condset_rr64_f : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
553 "Error; should not emit",
554 [(set DoubleRegs:$dst, (f64 (select PredRegs:$src1,
556 DoubleRegs:$src3)))]>,
561 let AddedComplexity = 100, isPredicated = 1 in
562 def TFR_condset_ri_f : ALU32_rr<(outs IntRegs:$dst),
563 (ins PredRegs:$src1, IntRegs:$src2, f32imm:$src3),
564 "Error; should not emit",
566 (f32 (select PredRegs:$src1, IntRegs:$src2, fpimm:$src3)))]>,
569 let AddedComplexity = 100, isPredicated = 1 in
570 def TFR_condset_ir_f : ALU32_rr<(outs IntRegs:$dst),
571 (ins PredRegs:$src1, f32imm:$src2, IntRegs:$src3),
572 "Error; should not emit",
574 (f32 (select PredRegs:$src1, fpimm:$src2, IntRegs:$src3)))]>,
577 let AddedComplexity = 100, isPredicated = 1 in
578 def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst),
579 (ins PredRegs:$src1, f32imm:$src2, f32imm:$src3),
580 "Error; should not emit",
581 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
587 def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
589 (f32 IntRegs:$src4)),
590 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
591 IntRegs:$src3)>, Requires<[HasV5T]>;
593 def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
594 (f64 DoubleRegs:$src3),
595 (f64 DoubleRegs:$src4)),
596 (TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1),
597 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
599 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
600 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, fpimm:$src3),
601 (TFR_condset_ii_f PredRegs:$src1, fpimm:$src3, fpimm:$src2)>;
603 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
604 // => r0 = TFR_condset_ri(p0, r1, #i)
605 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
606 (TFR_condset_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;
608 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
609 // => r0 = TFR_condset_ir(p0, #i, r1)
610 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
611 (TFR_condset_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;
613 def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
614 (i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>,
617 def : Pat <(fabs (f32 IntRegs:$src1)),
618 (CLRBIT_31 (f32 IntRegs:$src1), 31)>,
621 def : Pat <(fneg (f32 IntRegs:$src1)),
622 (TOGBIT_31 (f32 IntRegs:$src1), 31)>,
626 def : Pat <(fabs (f64 DoubleRegs:$src1)),
627 (CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
630 def : Pat <(fabs (f64 DoubleRegs:$src1)),
631 (CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,