1 //=- HexagonInstrInfoV60.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V60 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
16 let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
18 class VSTInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
19 string cstr = "", InstrItinClass itin = CVI_VM_ST,
20 IType type = TypeCVI_VM_ST>
21 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>, OpcodeHexagon;
26 let Predicates = [HasV60T, UseHVX] in
27 let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
28 class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
29 string cstr = "", InstrItinClass itin = CVI_VM_LD,
30 IType type = TypeCVI_VM_LD>
31 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
33 let Predicates = [HasV60T, UseHVX] in
34 let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
35 class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
36 string cstr = "", InstrItinClass itin = CVI_VM_ST,
37 IType type = TypeCVI_VM_ST>
38 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
40 //===----------------------------------------------------------------------===//
41 // Vector loads with base + immediate offset
42 //===----------------------------------------------------------------------===//
43 let addrMode = BaseImmOffset, accessSize = Vector64Access in
44 class T_vload_ai<string asmStr>
45 : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2),
48 let isCodeGenOnly = 1, addrMode = BaseImmOffset, accessSize = Vector128Access in
49 class T_vload_ai_128B<string asmStr>
50 : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2),
53 let isCVLoadable = 1, hasNewValue = 1 in {
54 def V6_vL32b_ai : T_vload_ai <"$dst = vmem($src1+#$src2)">,
56 def V6_vL32b_nt_ai : T_vload_ai <"$dst = vmem($src1+#$src2):nt">,
59 def V6_vL32b_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2)">,
61 def V6_vL32b_nt_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2):nt">,
62 V6_vL32b_nt_ai_128B_enc;
65 let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU, hasNewValue = 1 in {
66 def V6_vL32Ub_ai : T_vload_ai <"$dst = vmemu($src1+#$src2)">,
68 def V6_vL32Ub_ai_128B : T_vload_ai_128B <"$dst = vmemu($src1+#$src2)">,
69 V6_vL32Ub_ai_128B_enc;
72 let Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD, isCVLoad = 1,
74 def V6_vL32b_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2)">,
76 def V6_vL32b_nt_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2):nt">,
77 V6_vL32b_nt_cur_ai_enc;
79 def V6_vL32b_cur_ai_128B : T_vload_ai_128B
80 <"$dst.cur = vmem($src1+#$src2)">,
81 V6_vL32b_cur_ai_128B_enc;
82 def V6_vL32b_nt_cur_ai_128B : T_vload_ai_128B
83 <"$dst.cur = vmem($src1+#$src2):nt">,
84 V6_vL32b_nt_cur_ai_128B_enc;
88 let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD, hasNewValue = 1 in {
89 def V6_vL32b_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2)">,
91 def V6_vL32b_nt_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2):nt">,
92 V6_vL32b_nt_tmp_ai_enc;
94 def V6_vL32b_tmp_ai_128B : T_vload_ai_128B
95 <"$dst.tmp = vmem($src1+#$src2)">,
96 V6_vL32b_tmp_ai_128B_enc;
97 def V6_vL32b_nt_tmp_ai_128B : T_vload_ai_128B
98 <"$dst.tmp = vmem($src1+#$src2)">,
99 V6_vL32b_nt_tmp_ai_128B_enc;
102 //===----------------------------------------------------------------------===//
103 // Vector stores with base + immediate offset - unconditional
104 //===----------------------------------------------------------------------===//
105 let addrMode = BaseImmOffset, accessSize = Vector64Access in
106 class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp,
107 RegisterClass RC, bit isNT>
108 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
109 mnemonic#"($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3">, NewValueRel {
110 let BaseOpcode = baseOp;
113 let accessSize = Vector64Access in
114 class T_vstore_ai_64B <string mnemonic, string baseOp, bit isNT = 0>
115 : T_vstore_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isNT>;
117 let isCodeGenOnly = 1, accessSize = Vector128Access in
118 class T_vstore_ai_128B <string mnemonic, string baseOp, bit isNT = 0>
119 : T_vstore_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>;
121 let isNVStorable = 1 in {
122 def V6_vS32b_ai : T_vstore_ai_64B <"vmem", "vS32b_ai">,
124 def V6_vS32b_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai">,
125 V6_vS32b_ai_128B_enc;
128 let isNVStorable = 1, isNonTemporal = 1 in {
129 def V6_vS32b_nt_ai : T_vstore_ai_64B <"vmem", "vS32b_ai", 1>,
131 def V6_vS32b_nt_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai", 1>,
132 V6_vS32b_nt_ai_128B_enc;
135 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
136 def V6_vS32Ub_ai : T_vstore_ai_64B <"vmemu", "vs32Ub_ai">,
138 def V6_vS32Ub_ai_128B : T_vstore_ai_128B <"vmemu", "vs32Ub_ai">,
139 V6_vS32Ub_ai_128B_enc;
141 //===----------------------------------------------------------------------===//
142 // Vector stores with base + immediate offset - unconditional new
143 //===----------------------------------------------------------------------===//
144 let addrMode = BaseImmOffset, isNewValue = 1, opNewValue = 2, isNVStore = 1,
145 Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST in
146 class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
147 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
148 "vmem($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3.new">, NewValueRel {
149 let BaseOpcode = baseOp;
152 let accessSize = Vector64Access in
153 class T_vstore_new_ai_64B <string baseOp, bit isNT = 0>
154 : T_vstore_new_ai <baseOp, s4_6Imm, VectorRegs, isNT>;
156 let isCodeGenOnly = 1, accessSize = Vector128Access in
157 class T_vstore_new_ai_128B <string baseOp, bit isNT = 0>
158 : T_vstore_new_ai <baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>;
160 def V6_vS32b_new_ai : T_vstore_new_ai_64B <"vS32b_ai">, V6_vS32b_new_ai_enc;
161 def V6_vS32b_new_ai_128B : T_vstore_new_ai_128B <"vS32b_ai">,
162 V6_vS32b_new_ai_128B_enc;
164 let isNonTemporal = 1 in {
165 def V6_vS32b_nt_new_ai : T_vstore_new_ai_64B<"vS32b_ai", 1>,
166 V6_vS32b_nt_new_ai_enc;
167 def V6_vS32b_nt_new_ai_128B : T_vstore_new_ai_128B<"vS32b_ai", 1>,
168 V6_vS32b_nt_new_ai_128B_enc;
171 //===----------------------------------------------------------------------===//
172 // Vector stores with base + immediate offset - conditional
173 //===----------------------------------------------------------------------===//
174 let addrMode = BaseImmOffset, isPredicated = 1 in
175 class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp,
176 RegisterClass RC, bit isPredNot = 0, bit isNT = 0>
178 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
179 "if ("#!if(isPredNot, "!", "")#"$src1) "
180 #mnemonic#"($src2+#$src3)"#!if(isNT, ":nt", "")#" = $src4">, NewValueRel {
181 let isPredicatedFalse = isPredNot;
182 let BaseOpcode = baseOp;
185 let accessSize = Vector64Access in
186 class T_vstore_pred_ai_64B <string mnemonic, string baseOp,
187 bit isPredNot = 0, bit isNT = 0>
188 : T_vstore_pred_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>;
190 let isCodeGenOnly = 1, accessSize = Vector128Access in
191 class T_vstore_pred_ai_128B <string mnemonic, string baseOp,
192 bit isPredNot = 0, bit isNT = 0>
193 : T_vstore_pred_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B,
196 let isNVStorable = 1 in {
197 def V6_vS32b_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai">,
198 V6_vS32b_pred_ai_enc;
199 def V6_vS32b_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1>,
200 V6_vS32b_npred_ai_enc;
202 def V6_vS32b_pred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai">,
203 V6_vS32b_pred_ai_128B_enc;
204 def V6_vS32b_npred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai", 1>,
205 V6_vS32b_npred_ai_128B_enc;
207 let isNVStorable = 1, isNonTemporal = 1 in {
208 def V6_vS32b_nt_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 0, 1>,
209 V6_vS32b_nt_pred_ai_enc;
210 def V6_vS32b_nt_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1, 1>,
211 V6_vS32b_nt_npred_ai_enc;
213 def V6_vS32b_nt_pred_ai_128B : T_vstore_pred_ai_128B
214 <"vmem", "vS32b_ai", 0, 1>,
215 V6_vS32b_nt_pred_ai_128B_enc;
216 def V6_vS32b_nt_npred_ai_128B : T_vstore_pred_ai_128B
217 <"vmem", "vS32b_ai", 1, 1>,
218 V6_vS32b_nt_npred_ai_128B_enc;
221 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
222 def V6_vS32Ub_pred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai">,
223 V6_vS32Ub_pred_ai_enc;
224 def V6_vS32Ub_npred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai", 1>,
225 V6_vS32Ub_npred_ai_enc;
227 def V6_vS32Ub_pred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai">,
228 V6_vS32Ub_pred_ai_128B_enc;
229 def V6_vS32Ub_npred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai", 1>,
230 V6_vS32Ub_npred_ai_128B_enc;
233 //===----------------------------------------------------------------------===//
234 // Vector stores with base + immediate offset - byte-enabled aligned
235 //===----------------------------------------------------------------------===//
236 let addrMode = BaseImmOffset in
237 class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC,
238 bit isPredNot = 0, bit isNT = 0>
240 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
241 "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)"
242 #!if(isNT, ":nt", "")#" = $src4"> {
243 let isPredicatedFalse = isPredNot;
246 let accessSize = Vector64Access in
247 class T_vstore_qpred_ai_64B <bit isPredNot = 0, bit isNT = 0>
248 : T_vstore_qpred_ai <s4_6Imm, VectorRegs, isPredNot, isNT>;
250 let isCodeGenOnly = 1, accessSize = Vector128Access in
251 class T_vstore_qpred_ai_128B <bit isPredNot = 0, bit isNT = 0>
252 : T_vstore_qpred_ai <s4_7Imm, VectorRegs128B, isPredNot, isNT>;
254 def V6_vS32b_qpred_ai : T_vstore_qpred_ai_64B, V6_vS32b_qpred_ai_enc;
255 def V6_vS32b_nqpred_ai : T_vstore_qpred_ai_64B <1>,
256 V6_vS32b_nqpred_ai_enc;
257 def V6_vS32b_nt_qpred_ai : T_vstore_qpred_ai_64B <0, 1>,
258 V6_vS32b_nt_qpred_ai_enc;
259 def V6_vS32b_nt_nqpred_ai : T_vstore_qpred_ai_64B <1, 1>,
260 V6_vS32b_nt_nqpred_ai_enc;
262 def V6_vS32b_qpred_ai_128B : T_vstore_qpred_ai_128B, V6_vS32b_qpred_ai_128B_enc;
263 def V6_vS32b_nqpred_ai_128B : T_vstore_qpred_ai_128B<1>,
264 V6_vS32b_nqpred_ai_128B_enc;
265 def V6_vS32b_nt_qpred_ai_128B : T_vstore_qpred_ai_128B<0, 1>,
266 V6_vS32b_nt_qpred_ai_128B_enc;
267 def V6_vS32b_nt_nqpred_ai_128B : T_vstore_qpred_ai_128B<1, 1>,
268 V6_vS32b_nt_nqpred_ai_128B_enc;
271 //===----------------------------------------------------------------------===//
272 // Vector stores with base + immediate offset - conditional new
273 //===----------------------------------------------------------------------===//
274 let addrMode = BaseImmOffset, isPredicated = 1, isNewValue = 1, opNewValue = 3,
275 isNVStore = 1, Type = TypeCVI_VM_NEW_ST, Itinerary = CVI_VM_NEW_ST in
276 class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC,
277 bit isPredNot, bit isNT>
279 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
280 "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)"
281 #!if(isNT, ":nt", "")#" = $src4.new">, NewValueRel {
282 let isPredicatedFalse = isPredNot;
283 let BaseOpcode = baseOp;
286 let accessSize = Vector64Access in
287 class T_vstore_new_pred_ai_64B <string baseOp, bit isPredNot = 0, bit isNT = 0>
288 : T_vstore_new_pred_ai <baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>;
290 let isCodeGenOnly = 1, accessSize = Vector128Access in
291 class T_vstore_new_pred_ai_128B <string baseOp, bit isPredNot = 0, bit isNT = 0>
292 : T_vstore_new_pred_ai <baseOp#"128B", s4_7Imm, VectorRegs128B,
296 def V6_vS32b_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai">,
297 V6_vS32b_new_pred_ai_enc;
298 def V6_vS32b_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1>,
299 V6_vS32b_new_npred_ai_enc;
301 def V6_vS32b_new_pred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai">,
302 V6_vS32b_new_pred_ai_128B_enc;
303 def V6_vS32b_new_npred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai", 1>,
304 V6_vS32b_new_npred_ai_128B_enc;
305 let isNonTemporal = 1 in {
306 def V6_vS32b_nt_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 0, 1>,
307 V6_vS32b_nt_new_pred_ai_enc;
308 def V6_vS32b_nt_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1, 1>,
309 V6_vS32b_nt_new_npred_ai_enc;
311 def V6_vS32b_nt_new_pred_ai_128B : T_vstore_new_pred_ai_128B
313 V6_vS32b_nt_new_pred_ai_128B_enc;
314 def V6_vS32b_nt_new_npred_ai_128B : T_vstore_new_pred_ai_128B
316 V6_vS32b_nt_new_npred_ai_128B_enc;
319 //===----------------------------------------------------------------------===//
320 // Post increment vector loads with immediate offset.
321 //===----------------------------------------------------------------------===//
322 let addrMode = PostInc, hasNewValue = 1 in
323 class T_vload_pi<string asmStr, Operand ImmOp, RegisterClass RC>
324 : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
325 (ins IntRegs:$src1, ImmOp:$src2), asmStr, [],
328 let accessSize = Vector64Access in
329 class T_vload_pi_64B <string asmStr>
330 : T_vload_pi <asmStr, s3_6Imm, VectorRegs>;
332 let isCodeGenOnly = 1, accessSize = Vector128Access in
333 class T_vload_pi_128B <string asmStr>
334 : T_vload_pi <asmStr, s3_7Imm, VectorRegs128B>;
336 let isCVLoadable = 1 in {
337 def V6_vL32b_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2)">,
339 def V6_vL32b_nt_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2):nt">,
342 def V6_vL32b_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2)">,
343 V6_vL32b_pi_128B_enc;
344 def V6_vL32b_nt_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2):nt">,
345 V6_vL32b_nt_pi_128B_enc;
348 let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in {
349 def V6_vL32Ub_pi : T_vload_pi_64B <"$dst = vmemu($src1++#$src2)">,
352 def V6_vL32Ub_pi_128B : T_vload_pi_128B <"$dst = vmemu($src1++#$src2)">,
353 V6_vL32Ub_pi_128B_enc;
356 let isCVLoad = 1, Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD in {
357 def V6_vL32b_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2)">,
359 def V6_vL32b_nt_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2):nt">,
360 V6_vL32b_nt_cur_pi_enc;
362 def V6_vL32b_cur_pi_128B : T_vload_pi_128B
363 <"$dst.cur = vmem($src1++#$src2)">,
364 V6_vL32b_cur_pi_128B_enc;
365 def V6_vL32b_nt_cur_pi_128B : T_vload_pi_128B
366 <"$dst.cur = vmem($src1++#$src2):nt">,
367 V6_vL32b_nt_cur_pi_128B_enc;
370 let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in {
371 def V6_vL32b_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2)">,
373 def V6_vL32b_nt_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2):nt">,
374 V6_vL32b_nt_tmp_pi_enc;
376 def V6_vL32b_tmp_pi_128B : T_vload_pi_128B
377 <"$dst.tmp = vmem($src1++#$src2)">,
378 V6_vL32b_tmp_pi_128B_enc;
379 def V6_vL32b_nt_tmp_pi_128B : T_vload_pi_128B
380 <"$dst.tmp = vmem($src1++#$src2):nt">,
381 V6_vL32b_nt_tmp_pi_128B_enc;
384 //===----------------------------------------------------------------------===//
385 // Post increment vector stores with immediate offset.
386 //===----------------------------------------------------------------------===//
387 let addrMode = PostInc in
388 class T_vstore_pi <string mnemonic, string baseOp, Operand ImmOp,
389 RegisterClass RC, bit isNT>
390 : V6_STInst <(outs IntRegs:$_dst_),
391 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
392 mnemonic#"($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3", [],
393 "$src1 = $_dst_">, NewValueRel;
395 let accessSize = Vector64Access in
396 class T_vstore_pi_64B <string mnemonic, string baseOp, bit isNT = 0>
397 : T_vstore_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isNT>;
399 let isCodeGenOnly = 1, accessSize = Vector128Access in
400 class T_vstore_pi_128B <string mnemonic, string baseOp, bit isNT = 0>
401 : T_vstore_pi <mnemonic, baseOp, s3_7Imm, VectorRegs128B, isNT>;
403 let isNVStorable = 1 in {
404 def V6_vS32b_pi : T_vstore_pi_64B <"vmem", "vS32b_pi">, V6_vS32b_pi_enc;
405 def V6_vS32b_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi">,
406 V6_vS32b_pi_128B_enc;
409 let isNVStorable = 1 , isNonTemporal = 1 in {
410 def V6_vS32b_nt_pi : T_vstore_pi_64B <"vmem", "vS32b_pi", 1>,
412 def V6_vS32b_nt_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi", 1>,
413 V6_vS32b_nt_pi_128B_enc;
417 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
418 def V6_vS32Ub_pi : T_vstore_pi_64B <"vmemu", "vS32Ub_pi">,
420 def V6_vS32Ub_pi_128B : T_vstore_pi_128B <"vmemu", "vS32Ub_pi">,
421 V6_vS32Ub_pi_128B_enc;
424 //===----------------------------------------------------------------------===//
425 // Post increment unconditional .new vector stores with immediate offset.
426 //===----------------------------------------------------------------------===//
427 let addrMode = PostInc, isNVStore = 1 in
428 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1,
429 opNewValue = 3, isNVStore = 1 in
430 class T_vstore_new_pi <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
431 : V6_STInst <(outs IntRegs:$_dst_),
432 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
433 "vmem($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [],
434 "$src1 = $_dst_">, NewValueRel {
435 let BaseOpcode = baseOp;
438 let accessSize = Vector64Access in
439 class T_vstore_new_pi_64B <string baseOp, bit isNT = 0>
440 : T_vstore_new_pi <baseOp, s3_6Imm, VectorRegs, isNT>;
442 let isCodeGenOnly = 1, accessSize = Vector128Access in
443 class T_vstore_new_pi_128B <string baseOp, bit isNT = 0>
444 : T_vstore_new_pi <baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>;
447 def V6_vS32b_new_pi : T_vstore_new_pi_64B <"vS32b_pi">,
449 def V6_vS32b_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi">,
450 V6_vS32b_new_pi_128B_enc;
452 let isNonTemporal = 1 in {
453 def V6_vS32b_nt_new_pi : T_vstore_new_pi_64B <"vS32b_pi", 1>,
454 V6_vS32b_nt_new_pi_enc;
455 def V6_vS32b_nt_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi", 1>,
456 V6_vS32b_nt_new_pi_128B_enc;
459 //===----------------------------------------------------------------------===//
460 // Post increment conditional vector stores with immediate offset
461 //===----------------------------------------------------------------------===//
462 let isPredicated = 1, addrMode = PostInc in
463 class T_vstore_pred_pi <string mnemonic, string baseOp, Operand ImmOp,
464 RegisterClass RC, bit isPredNot, bit isNT>
465 : V6_STInst<(outs IntRegs:$_dst_),
466 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
467 "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++#$src3)"
468 #!if(isNT, ":nt", "")#" = $src4", [],
469 "$src2 = $_dst_">, NewValueRel {
470 let isPredicatedFalse = isPredNot;
471 let BaseOpcode = baseOp;
474 let accessSize = Vector64Access in
475 class T_vstore_pred_pi_64B <string mnemonic, string baseOp,
476 bit isPredNot = 0, bit isNT = 0>
477 : T_vstore_pred_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>;
479 let isCodeGenOnly = 1, accessSize = Vector128Access in
480 class T_vstore_pred_pi_128B <string mnemonic, string baseOp,
481 bit isPredNot = 0, bit isNT = 0>
482 : T_vstore_pred_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B,
485 let isNVStorable = 1 in {
486 def V6_vS32b_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi">,
487 V6_vS32b_pred_pi_enc;
488 def V6_vS32b_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1>,
489 V6_vS32b_npred_pi_enc;
491 def V6_vS32b_pred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi">,
492 V6_vS32b_pred_pi_128B_enc;
493 def V6_vS32b_npred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi", 1>,
494 V6_vS32b_npred_pi_128B_enc;
496 let isNVStorable = 1, isNonTemporal = 1 in {
497 def V6_vS32b_nt_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 0, 1>,
498 V6_vS32b_nt_pred_pi_enc;
499 def V6_vS32b_nt_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1, 1>,
500 V6_vS32b_nt_npred_pi_enc;
502 def V6_vS32b_nt_pred_pi_128B : T_vstore_pred_pi_128B
503 <"vmem", "vS32b_pi", 0, 1>,
504 V6_vS32b_nt_pred_pi_128B_enc;
505 def V6_vS32b_nt_npred_pi_128B : T_vstore_pred_pi_128B
506 <"vmem", "vS32b_pi", 1, 1>,
507 V6_vS32b_nt_npred_pi_128B_enc;
510 let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
511 def V6_vS32Ub_pred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi">,
512 V6_vS32Ub_pred_pi_enc;
513 def V6_vS32Ub_npred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi", 1>,
514 V6_vS32Ub_npred_pi_enc;
516 def V6_vS32Ub_pred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi">,
517 V6_vS32Ub_pred_pi_128B_enc;
518 def V6_vS32Ub_npred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi", 1>,
519 V6_vS32Ub_npred_pi_128B_enc;
522 //===----------------------------------------------------------------------===//
523 // Post increment vector stores with immediate offset - byte-enabled aligned
524 //===----------------------------------------------------------------------===//
525 let addrMode = PostInc in
526 class T_vstore_qpred_pi <Operand ImmOp, RegisterClass RC, bit isPredNot = 0,
528 : V6_STInst <(outs IntRegs:$_dst_),
529 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
530 "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)"
531 #!if(isNT, ":nt", "")#" = $src4", [],
534 let accessSize = Vector64Access in
535 class T_vstore_qpred_pi_64B <bit isPredNot = 0, bit isNT = 0>
536 : T_vstore_qpred_pi <s3_6Imm, VectorRegs, isPredNot, isNT>;
538 let isCodeGenOnly = 1, accessSize = Vector128Access in
539 class T_vstore_qpred_pi_128B <bit isPredNot = 0, bit isNT = 0>
540 : T_vstore_qpred_pi <s3_7Imm, VectorRegs128B, isPredNot, isNT>;
542 def V6_vS32b_qpred_pi : T_vstore_qpred_pi_64B, V6_vS32b_qpred_pi_enc;
543 def V6_vS32b_nqpred_pi : T_vstore_qpred_pi_64B <1>, V6_vS32b_nqpred_pi_enc;
545 def V6_vS32b_qpred_pi_128B : T_vstore_qpred_pi_128B,
546 V6_vS32b_qpred_pi_128B_enc;
547 def V6_vS32b_nqpred_pi_128B : T_vstore_qpred_pi_128B<1>,
548 V6_vS32b_nqpred_pi_128B_enc;
550 let isNonTemporal = 1 in {
551 def V6_vS32b_nt_qpred_pi : T_vstore_qpred_pi_64B <0, 1>,
552 V6_vS32b_nt_qpred_pi_enc;
553 def V6_vS32b_nt_nqpred_pi : T_vstore_qpred_pi_64B <1, 1>,
554 V6_vS32b_nt_nqpred_pi_enc;
556 def V6_vS32b_nt_qpred_pi_128B : T_vstore_qpred_pi_128B<0, 1>,
557 V6_vS32b_nt_qpred_pi_128B_enc;
558 def V6_vS32b_nt_nqpred_pi_128B : T_vstore_qpred_pi_128B<1, 1>,
559 V6_vS32b_nt_nqpred_pi_128B_enc;
562 //===----------------------------------------------------------------------===//
563 // Post increment conditional .new vector stores with immediate offset
564 //===----------------------------------------------------------------------===//
565 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1,
566 isNewValue = 1, opNewValue = 4, addrMode = PostInc, isNVStore = 1 in
567 class T_vstore_new_pred_pi <string baseOp, Operand ImmOp, RegisterClass RC,
568 bit isPredNot, bit isNT>
569 : V6_STInst <(outs IntRegs:$_dst_),
570 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
571 "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)"
572 #!if(isNT, ":nt", "")#" = $src4.new", [],
573 "$src2 = $_dst_"> , NewValueRel {
574 let isPredicatedFalse = isPredNot;
575 let BaseOpcode = baseOp;
578 let accessSize = Vector64Access in
579 class T_vstore_new_pred_pi_64B <string baseOp, bit isPredNot = 0, bit isNT = 0>
580 : T_vstore_new_pred_pi <baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>;
582 let isCodeGenOnly = 1, accessSize = Vector128Access in
583 class T_vstore_new_pred_pi_128B <string baseOp, bit isPredNot = 0, bit isNT = 0>
584 : T_vstore_new_pred_pi <baseOp#"128B", s3_7Imm, VectorRegs128B,
587 def V6_vS32b_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi">,
588 V6_vS32b_new_pred_pi_enc;
589 def V6_vS32b_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1>,
590 V6_vS32b_new_npred_pi_enc;
592 def V6_vS32b_new_pred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi">,
593 V6_vS32b_new_pred_pi_128B_enc;
594 def V6_vS32b_new_npred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi", 1>,
595 V6_vS32b_new_npred_pi_128B_enc;
596 let isNonTemporal = 1 in {
597 def V6_vS32b_nt_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 0, 1>,
598 V6_vS32b_nt_new_pred_pi_enc;
599 def V6_vS32b_nt_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1, 1>,
600 V6_vS32b_nt_new_npred_pi_enc;
602 def V6_vS32b_nt_new_pred_pi_128B : T_vstore_new_pred_pi_128B
604 V6_vS32b_nt_new_pred_pi_128B_enc;
605 def V6_vS32b_nt_new_npred_pi_128B : T_vstore_new_pred_pi_128B
607 V6_vS32b_nt_new_npred_pi_128B_enc;
610 //===----------------------------------------------------------------------===//
611 // Post increment vector loads with register offset
612 //===----------------------------------------------------------------------===//
613 let hasNewValue = 1 in
614 class T_vload_ppu<string asmStr>
615 : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_),
616 (ins IntRegs:$src1, ModRegs:$src2), asmStr, [],
617 "$src1 = $_dst_">, NewValueRel;
619 let isCVLoadable = 1 in {
620 def V6_vL32b_ppu : T_vload_ppu <"$dst = vmem($src1++$src2)">,
622 def V6_vL32b_nt_ppu : T_vload_ppu <"$dst = vmem($src1++$src2):nt">,
626 let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in
627 def V6_vL32Ub_ppu : T_vload_ppu <"$dst = vmemu($src1++$src2)">,
630 let isCVLoad = 1, Itinerary = CVI_VM_CUR_LD, Type = TypeCVI_VM_CUR_LD in {
631 def V6_vL32b_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2)">,
632 V6_vL32b_cur_ppu_enc;
633 def V6_vL32b_nt_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2):nt">,
634 V6_vL32b_nt_cur_ppu_enc;
637 let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in {
638 def V6_vL32b_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2)">,
639 V6_vL32b_tmp_ppu_enc;
640 def V6_vL32b_nt_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2):nt">,
641 V6_vL32b_nt_tmp_ppu_enc;
644 //===----------------------------------------------------------------------===//
645 // Post increment vector stores with register offset
646 //===----------------------------------------------------------------------===//
647 class T_vstore_ppu <string mnemonic, bit isNT = 0>
648 : V6_STInst <(outs IntRegs:$_dst_),
649 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
650 mnemonic#"($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3", [],
651 "$src1 = $_dst_">, NewValueRel;
653 let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in {
654 def V6_vS32b_ppu : T_vstore_ppu <"vmem">,
656 let isNonTemporal = 1, BaseOpcode = "vS32b_ppu" in
657 def V6_vS32b_nt_ppu : T_vstore_ppu <"vmem", 1>,
661 let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in
662 def V6_vS32Ub_ppu : T_vstore_ppu <"vmemu">, V6_vS32Ub_ppu_enc;
664 //===----------------------------------------------------------------------===//
665 // Post increment .new vector stores with register offset
666 //===----------------------------------------------------------------------===//
667 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1,
668 opNewValue = 3, isNVStore = 1 in
669 class T_vstore_new_ppu <bit isNT = 0>
670 : V6_STInst <(outs IntRegs:$_dst_),
671 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
672 "vmem($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [],
673 "$src1 = $_dst_">, NewValueRel;
675 let BaseOpcode = "vS32b_ppu" in
676 def V6_vS32b_new_ppu : T_vstore_new_ppu, V6_vS32b_new_ppu_enc;
678 let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in
679 def V6_vS32b_nt_new_ppu : T_vstore_new_ppu<1>, V6_vS32b_nt_new_ppu_enc;
681 //===----------------------------------------------------------------------===//
682 // Post increment conditional .new vector stores with register offset
683 //===----------------------------------------------------------------------===//
684 let isPredicated = 1 in
685 class T_vstore_pred_ppu <string mnemonic, bit isPredNot = 0, bit isNT = 0>
686 : V6_STInst<(outs IntRegs:$_dst_),
687 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
688 "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++$src3)"
689 #!if(isNT, ":nt", "")#" = $src4", [],
690 "$src2 = $_dst_">, NewValueRel {
691 let isPredicatedFalse = isPredNot;
694 let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in {
695 def V6_vS32b_pred_ppu : T_vstore_pred_ppu<"vmem">, V6_vS32b_pred_ppu_enc;
696 def V6_vS32b_npred_ppu: T_vstore_pred_ppu<"vmem", 1>, V6_vS32b_npred_ppu_enc;
699 let isNVStorable = 1, BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in {
700 def V6_vS32b_nt_pred_ppu : T_vstore_pred_ppu <"vmem", 0, 1>,
701 V6_vS32b_nt_pred_ppu_enc;
702 def V6_vS32b_nt_npred_ppu : T_vstore_pred_ppu <"vmem", 1, 1>,
703 V6_vS32b_nt_npred_ppu_enc;
706 let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU,
707 Type = TypeCVI_VM_STU in {
708 def V6_vS32Ub_pred_ppu : T_vstore_pred_ppu <"vmemu">,
709 V6_vS32Ub_pred_ppu_enc;
710 def V6_vS32Ub_npred_ppu : T_vstore_pred_ppu <"vmemu", 1>,
711 V6_vS32Ub_npred_ppu_enc;
714 //===----------------------------------------------------------------------===//
715 // Post increment vector stores with register offset - byte-enabled aligned
716 //===----------------------------------------------------------------------===//
717 class T_vstore_qpred_ppu <bit isPredNot = 0, bit isNT = 0>
718 : V6_STInst <(outs IntRegs:$_dst_),
719 (ins VecPredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
720 "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)"
721 #!if(isNT, ":nt", "")#" = $src4", [],
722 "$src2 = $_dst_">, NewValueRel;
724 def V6_vS32b_qpred_ppu : T_vstore_qpred_ppu, V6_vS32b_qpred_ppu_enc;
725 def V6_vS32b_nqpred_ppu : T_vstore_qpred_ppu<1>, V6_vS32b_nqpred_ppu_enc;
726 def V6_vS32b_nt_qpred_ppu : T_vstore_qpred_ppu<0, 1>,
727 V6_vS32b_nt_qpred_ppu_enc;
728 def V6_vS32b_nt_nqpred_ppu : T_vstore_qpred_ppu<1, 1>,
729 V6_vS32b_nt_nqpred_ppu_enc;
731 //===----------------------------------------------------------------------===//
732 // Post increment conditional .new vector stores with register offset
733 //===----------------------------------------------------------------------===//
734 let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1,
735 isNewValue = 1, opNewValue = 4, isNVStore = 1 in
736 class T_vstore_new_pred_ppu <bit isPredNot = 0, bit isNT = 0>
737 : V6_STInst <(outs IntRegs:$_dst_),
738 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
739 "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)"
740 #!if(isNT, ":nt", "")#" = $src4.new", [],
741 "$src2 = $_dst_">, NewValueRel {
742 let isPredicatedFalse = isPredNot;
745 let BaseOpcode = "vS32b_ppu" in {
746 def V6_vS32b_new_pred_ppu : T_vstore_new_pred_ppu,
747 V6_vS32b_new_pred_ppu_enc;
748 def V6_vS32b_new_npred_ppu : T_vstore_new_pred_ppu<1>,
749 V6_vS32b_new_npred_ppu_enc;
752 let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in {
753 def V6_vS32b_nt_new_pred_ppu : T_vstore_new_pred_ppu<0, 1>,
754 V6_vS32b_nt_new_pred_ppu_enc;
755 def V6_vS32b_nt_new_npred_ppu : T_vstore_new_pred_ppu<1, 1>,
756 V6_vS32b_nt_new_npred_ppu_enc;
759 let isPseudo = 1, validSubTargets = HasV60SubT in
760 class STrivv_template<string mnemonic, Operand ImmOp, RegisterClass RC>:
761 VSTInst<(outs), (ins IntRegs:$addr, ImmOp:$off, RC:$src),
762 #mnemonic#"($addr+#$off) = $src", []>;
764 def STrivv_indexed: STrivv_template<"vvmem", s4_6Imm, VecDblRegs>,
765 Requires<[HasV60T, UseHVXSgl]>;
766 def STrivv_indexed_128B: STrivv_template<"vvmem", s4_7Imm, VecDblRegs128B>,
767 Requires<[HasV60T, UseHVXDbl]>;
769 multiclass STrivv_pats <ValueType VTSgl, ValueType VTDbl> {
770 def : Pat<(store (VTSgl VecDblRegs:$src1), IntRegs:$addr),
771 (STrivv_indexed IntRegs:$addr, #0, (VTSgl VecDblRegs:$src1))>,
772 Requires<[UseHVXSgl]>;
774 def : Pat<(store (VTDbl VecDblRegs128B:$src1), IntRegs:$addr),
775 (STrivv_indexed_128B IntRegs:$addr, #0,
776 (VTDbl VecDblRegs128B:$src1))>,
777 Requires<[UseHVXDbl]>;
780 defm : STrivv_pats <v128i8, v256i8>;
781 defm : STrivv_pats <v64i16, v128i16>;
782 defm : STrivv_pats <v32i32, v64i32>;
783 defm : STrivv_pats <v16i64, v32i64>;
786 multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
788 def : Pat<(store (VTSgl VectorRegs:$src1), IntRegs:$addr),
789 (V6_vS32b_ai IntRegs:$addr, #0, (VTSgl VectorRegs:$src1))>,
790 Requires<[UseHVXSgl]>;
792 // 128B Aligned stores
793 def : Pat<(store (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
794 (V6_vS32b_ai_128B IntRegs:$addr, #0, (VTDbl VectorRegs128B:$src1))>,
795 Requires<[UseHVXDbl]>;
797 // Fold Add R+IFF into vector store.
798 let AddedComplexity = 10 in
799 def : Pat<(store (VTSgl VectorRegs:$src1),
800 (add IntRegs:$src2, s4_6ImmPred:$offset)),
801 (V6_vS32b_ai IntRegs:$src2, s4_6ImmPred:$offset,
802 (VTSgl VectorRegs:$src1))>,
803 Requires<[UseHVXSgl]>;
805 // Fold Add R+IFF into vector store 128B.
806 let AddedComplexity = 10 in
807 def : Pat<(store (VTDbl VectorRegs128B:$src1),
808 (add IntRegs:$src2, s4_7ImmPred:$offset)),
809 (V6_vS32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
810 (VTDbl VectorRegs128B:$src1))>,
811 Requires<[UseHVXDbl]>;
814 defm : vS32b_ai_pats <v64i8, v128i8>;
815 defm : vS32b_ai_pats <v32i16, v64i16>;
816 defm : vS32b_ai_pats <v16i32, v32i32>;
817 defm : vS32b_ai_pats <v8i64, v16i64>;
819 let isPseudo = 1, validSubTargets = HasV60SubT in
820 class LDrivv_template<string mnemonic, Operand ImmOp, RegisterClass RC>
821 : V6_LDInst <(outs RC:$dst), (ins IntRegs:$addr, ImmOp:$off),
822 "$dst="#mnemonic#"($addr+#$off)",
824 Requires<[HasV60T,UseHVXSgl]>;
826 def LDrivv_indexed: LDrivv_template<"vvmem", s4_6Imm, VecDblRegs>;
827 def LDrivv_indexed_128B: LDrivv_template<"vvmem", s4_7Imm, VecDblRegs128B>;
829 multiclass LDrivv_pats <ValueType VTSgl, ValueType VTDbl> {
830 def : Pat < (VTSgl (load IntRegs:$addr)),
831 (LDrivv_indexed IntRegs:$addr, #0) >,
832 Requires<[UseHVXSgl]>;
834 def : Pat < (VTDbl (load IntRegs:$addr)),
835 (LDrivv_indexed_128B IntRegs:$addr, #0) >,
836 Requires<[UseHVXDbl]>;
839 defm : LDrivv_pats <v128i8, v256i8>;
840 defm : LDrivv_pats <v64i16, v128i16>;
841 defm : LDrivv_pats <v32i32, v64i32>;
842 defm : LDrivv_pats <v16i64, v32i64>;
844 multiclass vL32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
846 def : Pat < (VTSgl (load IntRegs:$addr)),
847 (V6_vL32b_ai IntRegs:$addr, #0) >,
848 Requires<[UseHVXSgl]>;
851 def : Pat < (VTDbl (load IntRegs:$addr)),
852 (V6_vL32b_ai_128B IntRegs:$addr, #0) >,
853 Requires<[UseHVXDbl]>;
855 // Fold Add R+IFF into vector load.
856 let AddedComplexity = 10 in
857 def : Pat<(VTDbl (load (add IntRegs:$src2, s4_7ImmPred:$offset))),
858 (V6_vL32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
859 Requires<[UseHVXDbl]>;
861 let AddedComplexity = 10 in
862 def : Pat<(VTSgl (load (add IntRegs:$src2, s4_6ImmPred:$offset))),
863 (V6_vL32b_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
864 Requires<[UseHVXSgl]>;
867 defm : vL32b_ai_pats <v64i8, v128i8>;
868 defm : vL32b_ai_pats <v32i16, v64i16>;
869 defm : vL32b_ai_pats <v16i32, v32i32>;
870 defm : vL32b_ai_pats <v8i64, v16i64>;
872 // Store vector predicate pseudo.
873 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
874 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
875 def STriq_pred_V6 : STInst<(outs),
876 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs:$src1),
877 ".error \"should not emit\" ",
879 Requires<[HasV60T,UseHVXSgl]>;
881 def STriq_pred_vec_V6 : STInst<(outs),
882 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
883 ".error \"should not emit\" ",
885 Requires<[HasV60T,UseHVXSgl]>;
887 def STriq_pred_V6_128B : STInst<(outs),
888 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs128B:$src1),
889 ".error \"should not emit\" ",
891 Requires<[HasV60T,UseHVXDbl]>;
893 def STriq_pred_vec_V6_128B : STInst<(outs),
894 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
895 ".error \"should not emit\" ",
897 Requires<[HasV60T,UseHVXDbl]>;
900 // Load vector predicate pseudo.
901 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
902 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
903 def LDriq_pred_V6 : LDInst<(outs VecPredRegs:$dst),
904 (ins IntRegs:$base, s32Imm:$offset),
905 ".error \"should not emit\" ",
907 Requires<[HasV60T,UseHVXSgl]>;
908 def LDriq_pred_vec_V6 : LDInst<(outs VectorRegs:$dst),
909 (ins IntRegs:$base, s32Imm:$offset),
910 ".error \"should not emit\" ",
912 Requires<[HasV60T,UseHVXSgl]>;
913 def LDriq_pred_V6_128B : LDInst<(outs VecPredRegs128B:$dst),
914 (ins IntRegs:$base, s32Imm:$offset),
915 ".error \"should not emit\" ",
917 Requires<[HasV60T,UseHVXDbl]>;
918 def LDriq_pred_vec_V6_128B : LDInst<(outs VectorRegs128B:$dst),
919 (ins IntRegs:$base, s32Imm:$offset),
920 ".error \"should not emit\" ",
922 Requires<[HasV60T,UseHVXDbl]>;
925 // Store vector pseudo.
926 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
927 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
928 def STriv_pseudo_V6 : STInst<(outs),
929 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
930 ".error \"should not emit\" ",
932 Requires<[HasV60T,UseHVXSgl]>;
933 def STriv_pseudo_V6_128B : STInst<(outs),
934 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
935 ".error \"should not emit\" ",
937 Requires<[HasV60T,UseHVXDbl]>;
940 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
941 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
942 def STrivv_pseudo_V6 : STInst<(outs),
943 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs:$src1),
944 ".error \"should not emit\" ",
946 Requires<[HasV60T,UseHVXSgl]>;
947 def STrivv_pseudo_V6_128B : STInst<(outs),
948 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs128B:$src1),
949 ".error \"should not emit\" ",
951 Requires<[HasV60T,UseHVXDbl]>;
954 // Load vector pseudo.
955 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
956 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
957 def LDriv_pseudo_V6 : LDInst<(outs VectorRegs:$dst),
958 (ins IntRegs:$base, s32Imm:$offset),
959 ".error \"should not emit\" ",
961 Requires<[HasV60T,UseHVXSgl]>;
962 def LDriv_pseudo_V6_128B : LDInst<(outs VectorRegs128B:$dst),
963 (ins IntRegs:$base, s32Imm:$offset),
964 ".error \"should not emit\" ",
966 Requires<[HasV60T,UseHVXDbl]>;
969 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
970 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
971 def LDrivv_pseudo_V6 : LDInst<(outs VecDblRegs:$dst),
972 (ins IntRegs:$base, s32Imm:$offset),
973 ".error \"should not emit\" ",
975 Requires<[HasV60T,UseHVXSgl]>;
976 def LDrivv_pseudo_V6_128B : LDInst<(outs VecDblRegs128B:$dst),
977 (ins IntRegs:$base, s32Imm:$offset),
978 ".error \"should not emit\" ",
980 Requires<[HasV60T,UseHVXDbl]>;
983 class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
984 string cstr = "", InstrItinClass itin = CVI_VA_DV,
985 IType type = TypeCVI_VA_DV>
986 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
988 let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
989 def VSelectPseudo_V6 : VSELInst<(outs VectorRegs:$dst),
990 (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
991 ".error \"should not emit\" ",
993 Requires<[HasV60T,UseHVXSgl]>;
994 def VSelectDblPseudo_V6 : VSELInst<(outs VecDblRegs:$dst),
995 (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3),
996 ".error \"should not emit\" ",
998 Requires<[HasV60T,UseHVXSgl]>;
1001 def : Pat <(v16i32 (selectcc (i32 IntRegs:$lhs), (i32 IntRegs:$rhs),
1002 (v16i32 VectorRegs:$tval),
1003 (v16i32 VectorRegs:$fval), SETEQ)),
1004 (v16i32 (VSelectPseudo_V6 (i32 (C2_cmpeq (i32 IntRegs:$lhs),
1005 (i32 IntRegs:$rhs))),
1006 (v16i32 VectorRegs:$tval),
1007 (v16i32 VectorRegs:$fval)))>;
1010 let hasNewValue = 1 in
1011 class T_vmpy <string asmString, RegisterClass RCout, RegisterClass RCin>
1012 : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
1015 multiclass T_vmpy <string asmString, RegisterClass RCout,
1016 RegisterClass RCin> {
1017 def NAME : T_vmpy <asmString, RCout, RCin>;
1018 let isCodeGenOnly = 1 in
1019 def NAME#_128B : T_vmpy <asmString, !cast<RegisterClass>(RCout#"128B"),
1020 !cast<RegisterClass>(RCin#"128B")>;
1023 multiclass T_vmpy_VV <string asmString>:
1024 T_vmpy <asmString, VectorRegs, VectorRegs>;
1026 multiclass T_vmpy_WW <string asmString>:
1027 T_vmpy <asmString, VecDblRegs, VecDblRegs>;
1029 multiclass T_vmpy_VW <string asmString>:
1030 T_vmpy <asmString, VectorRegs, VecDblRegs>;
1032 multiclass T_vmpy_WV <string asmString>:
1033 T_vmpy <asmString, VecDblRegs, VectorRegs>;
1035 defm V6_vtmpyb :T_vmpy_WW<"$dst.h = vtmpy($src1.b,$src2.b)">, V6_vtmpyb_enc;
1036 defm V6_vtmpybus :T_vmpy_WW<"$dst.h = vtmpy($src1.ub,$src2.b)">, V6_vtmpybus_enc;
1037 defm V6_vdsaduh :T_vmpy_WW<"$dst.uw = vdsad($src1.uh,$src2.uh)">, V6_vdsaduh_enc;
1038 defm V6_vmpybus :T_vmpy_WV<"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybus_enc;
1039 defm V6_vmpabus :T_vmpy_WW<"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabus_enc;
1040 defm V6_vmpahb :T_vmpy_WW<"$dst.w = vmpa($src1.h,$src2.b)">, V6_vmpahb_enc;
1041 defm V6_vmpyh :T_vmpy_WV<"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyh_enc;
1042 defm V6_vmpyuh :T_vmpy_WV<"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuh_enc;
1043 defm V6_vmpyiwh :T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_enc;
1044 defm V6_vtmpyhb :T_vmpy_WW<"$dst.w = vtmpy($src1.h,$src2.b)">, V6_vtmpyhb_enc;
1045 defm V6_vmpyub :T_vmpy_WV<"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyub_enc;
1047 let Itinerary = CVI_VX_LONG, Type = TypeCVI_VX in
1048 defm V6_vmpyihb :T_vmpy_VV<"$dst.h = vmpyi($src1.h,$src2.b)">, V6_vmpyihb_enc;
1050 defm V6_vdmpybus_dv :
1051 T_vmpy_WW <"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_dv_enc;
1052 defm V6_vdmpyhsusat :
1053 T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.uh):sat">, V6_vdmpyhsusat_enc;
1054 defm V6_vdmpyhsuisat :
1055 T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.uh,#1):sat">, V6_vdmpyhsuisat_enc;
1057 T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhsat_enc;
1058 defm V6_vdmpyhisat :
1059 T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhisat_enc;
1060 defm V6_vdmpyhb_dv :
1061 T_vmpy_WW <"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_dv_enc;
1063 T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:sat">, V6_vmpyhss_enc;
1065 T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhsrs_enc;
1067 let Itinerary = CVI_VP, Type = TypeCVI_VP in
1068 defm V6_vror : T_vmpy_VV <"$dst = vror($src1,$src2)">, V6_vror_enc;
1070 let Itinerary = CVI_VX, Type = TypeCVI_VX in {
1071 defm V6_vdmpyhb : T_vmpy_VV<"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_enc;
1072 defm V6_vrmpybus : T_vmpy_VV<"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybus_enc;
1073 defm V6_vdmpybus : T_vmpy_VV<"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_enc;
1074 defm V6_vmpyiwb : T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.b)">, V6_vmpyiwb_enc;
1075 defm V6_vrmpyub : T_vmpy_VV<"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyub_enc;
1078 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1079 defm V6_vasrw : T_vmpy_VV <"$dst.w = vasr($src1.w,$src2)">, V6_vasrw_enc;
1080 defm V6_vasrh : T_vmpy_VV <"$dst.h = vasr($src1.h,$src2)">, V6_vasrh_enc;
1081 defm V6_vaslw : T_vmpy_VV <"$dst.w = vasl($src1.w,$src2)">, V6_vaslw_enc;
1082 defm V6_vaslh : T_vmpy_VV <"$dst.h = vasl($src1.h,$src2)">, V6_vaslh_enc;
1083 defm V6_vlsrw : T_vmpy_VV <"$dst.uw = vlsr($src1.uw,$src2)">, V6_vlsrw_enc;
1084 defm V6_vlsrh : T_vmpy_VV <"$dst.uh = vlsr($src1.uh,$src2)">, V6_vlsrh_enc;
1087 let hasNewValue = 1 in
1088 class T_HVX_alu <string asmString, InstrItinClass itin,
1089 RegisterClass RCout, RegisterClass RCin>
1090 : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2),
1092 let Itinerary = itin;
1093 let Type = !cast<IType>("Type"#itin);
1096 multiclass T_HVX_alu <string asmString, RegisterClass RCout,
1097 RegisterClass RCin, InstrItinClass itin> {
1098 def NAME : T_HVX_alu <asmString, itin, RCout, RCin>;
1099 let isCodeGenOnly = 1 in
1100 def NAME#_128B : T_HVX_alu <asmString, itin,
1101 !cast<RegisterClass>(RCout#"128B"),
1102 !cast<RegisterClass>(RCin#"128B")>;
1105 multiclass T_HVX_alu_VV <string asmString>:
1106 T_HVX_alu <asmString, VectorRegs, VectorRegs, CVI_VA>;
1108 multiclass T_HVX_alu_WW <string asmString>:
1109 T_HVX_alu <asmString, VecDblRegs, VecDblRegs, CVI_VA_DV>;
1111 multiclass T_HVX_alu_WV <string asmString>:
1112 T_HVX_alu <asmString, VecDblRegs, VectorRegs, CVI_VX_DV>;
1115 let Itinerary = CVI_VX, Type = TypeCVI_VX in {
1117 T_HVX_alu_VV <"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyubv_enc;
1119 T_HVX_alu_VV <"$dst.w = vrmpy($src1.b,$src2.b)">, V6_vrmpybv_enc;
1121 T_HVX_alu_VV <"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybusv_enc;
1122 defm V6_vabsdiffub :
1123 T_HVX_alu_VV <"$dst.ub = vabsdiff($src1.ub,$src2.ub)">, V6_vabsdiffub_enc;
1125 T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.h,$src2.h)">, V6_vabsdiffh_enc;
1126 defm V6_vabsdiffuh :
1127 T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.uh,$src2.uh)">, V6_vabsdiffuh_enc;
1129 T_HVX_alu_VV <"$dst.uw = vabsdiff($src1.w,$src2.w)">, V6_vabsdiffw_enc;
1132 let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
1133 defm V6_vdmpyhvsat :
1134 T_HVX_alu_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhvsat_enc;
1136 T_HVX_alu_VV<"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhvsrs_enc;
1138 T_HVX_alu_VV <"$dst.h = vmpyi($src1.h,$src2.h)">, V6_vmpyih_enc;
1142 T_HVX_alu_VV <"$dst = vand($src1,$src2)">, V6_vand_enc;
1144 T_HVX_alu_VV <"$dst = vor($src1,$src2)">, V6_vor_enc;
1146 T_HVX_alu_VV <"$dst = vxor($src1,$src2)">, V6_vxor_enc;
1148 T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_enc;
1150 T_HVX_alu_VV <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_enc;
1152 T_HVX_alu_VV <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_enc;
1154 T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_enc;
1156 T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_enc;
1158 T_HVX_alu_VV <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_enc;
1160 T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_enc;
1162 T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_enc;
1164 T_HVX_alu_VV <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_enc;
1166 T_HVX_alu_VV <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_enc;
1168 T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_enc;
1170 T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_enc;
1172 T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub)">, V6_vavgub_enc;
1174 T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh)">, V6_vavguh_enc;
1176 T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h)">, V6_vavgh_enc;
1178 T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w)">, V6_vavgw_enc;
1180 T_HVX_alu_VV <"$dst.b = vnavg($src1.ub,$src2.ub)">, V6_vnavgub_enc;
1182 T_HVX_alu_VV <"$dst.h = vnavg($src1.h,$src2.h)">, V6_vnavgh_enc;
1184 T_HVX_alu_VV <"$dst.w = vnavg($src1.w,$src2.w)">, V6_vnavgw_enc;
1186 T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub):rnd">, V6_vavgubrnd_enc;
1188 T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh):rnd">, V6_vavguhrnd_enc;
1190 T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h):rnd">, V6_vavghrnd_enc;
1192 T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w):rnd">, V6_vavgwrnd_enc;
1195 T_HVX_alu_WV <"$dst.h = vmpy($src1.b,$src2.b)">, V6_vmpybv_enc;
1197 T_HVX_alu_WV <"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyubv_enc;
1199 T_HVX_alu_WV <"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybusv_enc;
1201 T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyhv_enc;
1203 T_HVX_alu_WV <"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuhv_enc;
1205 T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.uh)">, V6_vmpyhus_enc;
1207 T_HVX_alu_WV <"$dst.h = vadd($src1.ub,$src2.ub)">, V6_vaddubh_enc;
1209 T_HVX_alu_WV <"$dst.w = vadd($src1.uh,$src2.uh)">, V6_vadduhw_enc;
1211 T_HVX_alu_WV <"$dst.w = vadd($src1.h,$src2.h)">, V6_vaddhw_enc;
1213 T_HVX_alu_WV <"$dst.h = vsub($src1.ub,$src2.ub)">, V6_vsububh_enc;
1215 T_HVX_alu_WV <"$dst.w = vsub($src1.uh,$src2.uh)">, V6_vsubuhw_enc;
1217 T_HVX_alu_WV <"$dst.w = vsub($src1.h,$src2.h)">, V6_vsubhw_enc;
1220 T_HVX_alu_WW <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_dv_enc;
1222 T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_dv_enc;
1224 T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_dv_enc;
1225 defm V6_vaddubsat_dv :
1226 T_HVX_alu_WW <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_dv_enc;
1227 defm V6_vadduhsat_dv :
1228 T_HVX_alu_WW <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_dv_enc;
1229 defm V6_vaddhsat_dv :
1230 T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_dv_enc;
1231 defm V6_vaddwsat_dv :
1232 T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_dv_enc;
1234 T_HVX_alu_WW <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_dv_enc;
1236 T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_dv_enc;
1238 T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_dv_enc;
1239 defm V6_vsububsat_dv :
1240 T_HVX_alu_WW <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_dv_enc;
1241 defm V6_vsubuhsat_dv :
1242 T_HVX_alu_WW <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_dv_enc;
1243 defm V6_vsubhsat_dv :
1244 T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_dv_enc;
1245 defm V6_vsubwsat_dv :
1246 T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_dv_enc;
1248 let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV in {
1250 T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabusv_enc;
1252 T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.ub)">, V6_vmpabuuv_enc;
1255 let isAccumulator = 1, hasNewValue = 1 in
1256 class T_HVX_vmpyacc <string asmString, InstrItinClass itin, RegisterClass RCout,
1257 RegisterClass RCin1, RegisterClass RCin2>
1258 : CVI_VA_Resource1 <(outs RCout:$dst),
1259 (ins RCout:$_src_, RCin1:$src1, RCin2:$src2), asmString,
1260 [], "$dst = $_src_" > {
1261 let Itinerary = itin;
1262 let Type = !cast<IType>("Type"#itin);
1265 multiclass T_HVX_vmpyacc_both <string asmString, RegisterClass RCout,
1266 RegisterClass RCin1, RegisterClass RCin2, InstrItinClass itin > {
1267 def NAME : T_HVX_vmpyacc <asmString, itin, RCout, RCin1, RCin2>;
1268 let isCodeGenOnly = 1 in
1269 def NAME#_128B : T_HVX_vmpyacc <asmString, itin,
1270 !cast<RegisterClass>(RCout#"128B"),
1271 !cast<RegisterClass>(RCin1#"128B"),
1272 !cast<RegisterClass>(RCin2#
1273 !if(!eq (!cast<string>(RCin2), "IntRegs"), "", "128B"))>;
1276 multiclass T_HVX_vmpyacc_VVR <string asmString>:
1277 T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, IntRegs, CVI_VX>;
1279 multiclass T_HVX_vmpyacc_VWR <string asmString>:
1280 T_HVX_vmpyacc_both <asmString, VectorRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1282 multiclass T_HVX_vmpyacc_WVR <string asmString>:
1283 T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, IntRegs, CVI_VX_DV>;
1285 multiclass T_HVX_vmpyacc_WWR <string asmString>:
1286 T_HVX_vmpyacc_both <asmString, VecDblRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1288 multiclass T_HVX_vmpyacc_VVV <string asmString>:
1289 T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, VectorRegs, CVI_VX_DV>;
1291 multiclass T_HVX_vmpyacc_WVV <string asmString>:
1292 T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, VectorRegs, CVI_VX_DV>;
1295 defm V6_vtmpyb_acc :
1296 T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.b,$src2.b)">,
1298 defm V6_vtmpybus_acc :
1299 T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.ub,$src2.b)">,
1300 V6_vtmpybus_acc_enc;
1301 defm V6_vtmpyhb_acc :
1302 T_HVX_vmpyacc_WWR <"$dst.w += vtmpy($src1.h,$src2.b)">,
1304 defm V6_vdmpyhb_acc :
1305 T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.b)">,
1307 defm V6_vrmpyub_acc :
1308 T_HVX_vmpyacc_VVR <"$dst.uw += vrmpy($src1.ub,$src2.ub)">,
1310 defm V6_vrmpybus_acc :
1311 T_HVX_vmpyacc_VVR <"$dst.w += vrmpy($src1.ub,$src2.b)">,
1312 V6_vrmpybus_acc_enc;
1313 defm V6_vdmpybus_acc :
1314 T_HVX_vmpyacc_VVR <"$dst.h += vdmpy($src1.ub,$src2.b)">,
1315 V6_vdmpybus_acc_enc;
1316 defm V6_vdmpybus_dv_acc :
1317 T_HVX_vmpyacc_WWR <"$dst.h += vdmpy($src1.ub,$src2.b)">,
1318 V6_vdmpybus_dv_acc_enc;
1319 defm V6_vdmpyhsuisat_acc :
1320 T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.uh,#1):sat">,
1321 V6_vdmpyhsuisat_acc_enc;
1322 defm V6_vdmpyhisat_acc :
1323 T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
1324 V6_vdmpyhisat_acc_enc;
1325 defm V6_vdmpyhb_dv_acc :
1326 T_HVX_vmpyacc_WWR <"$dst.w += vdmpy($src1.h,$src2.b)">,
1327 V6_vdmpyhb_dv_acc_enc;
1328 defm V6_vmpybus_acc :
1329 T_HVX_vmpyacc_WVR <"$dst.h += vmpy($src1.ub,$src2.b)">,
1331 defm V6_vmpabus_acc :
1332 T_HVX_vmpyacc_WWR <"$dst.h += vmpa($src1.ub,$src2.b)">,
1334 defm V6_vmpahb_acc :
1335 T_HVX_vmpyacc_WWR <"$dst.w += vmpa($src1.h,$src2.b)">,
1337 defm V6_vmpyhsat_acc :
1338 T_HVX_vmpyacc_WVR <"$dst.w += vmpy($src1.h,$src2.h):sat">,
1339 V6_vmpyhsat_acc_enc;
1340 defm V6_vmpyuh_acc :
1341 T_HVX_vmpyacc_WVR <"$dst.uw += vmpy($src1.uh,$src2.uh)">,
1343 defm V6_vmpyiwb_acc :
1344 T_HVX_vmpyacc_VVR <"$dst.w += vmpyi($src1.w,$src2.b)">,
1346 defm V6_vdsaduh_acc :
1347 T_HVX_vmpyacc_WWR <"$dst.uw += vdsad($src1.uh,$src2.uh)">,
1349 defm V6_vmpyihb_acc :
1350 T_HVX_vmpyacc_VVR <"$dst.h += vmpyi($src1.h,$src2.b)">,
1352 defm V6_vmpyub_acc :
1353 T_HVX_vmpyacc_WVR <"$dst.uh += vmpy($src1.ub,$src2.ub)">,
1356 let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
1357 defm V6_vdmpyhsusat_acc :
1358 T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.uh):sat">,
1359 V6_vdmpyhsusat_acc_enc;
1360 defm V6_vdmpyhsat_acc :
1361 T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
1362 V6_vdmpyhsat_acc_enc;
1363 defm V6_vmpyiwh_acc : T_HVX_vmpyacc_VVR
1364 <"$dst.w += vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_acc_enc;
1367 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1369 T_HVX_vmpyacc_VVR <"$dst.w += vasl($src1.w,$src2)">, V6_vaslw_acc_enc;
1371 T_HVX_vmpyacc_VVR <"$dst.w += vasr($src1.w,$src2)">, V6_vasrw_acc_enc;
1374 defm V6_vdmpyhvsat_acc :
1375 T_HVX_vmpyacc_VVV <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
1376 V6_vdmpyhvsat_acc_enc;
1377 defm V6_vmpybusv_acc :
1378 T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.ub,$src2.b)">,
1379 V6_vmpybusv_acc_enc;
1380 defm V6_vmpybv_acc :
1381 T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.b,$src2.b)">, V6_vmpybv_acc_enc;
1382 defm V6_vmpyhus_acc :
1383 T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.uh)">, V6_vmpyhus_acc_enc;
1384 defm V6_vmpyhv_acc :
1385 T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.h)">, V6_vmpyhv_acc_enc;
1386 defm V6_vmpyiewh_acc :
1387 T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.h)">,
1388 V6_vmpyiewh_acc_enc;
1389 defm V6_vmpyiewuh_acc :
1390 T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.uh)">,
1391 V6_vmpyiewuh_acc_enc;
1392 defm V6_vmpyih_acc :
1393 T_HVX_vmpyacc_VVV <"$dst.h += vmpyi($src1.h,$src2.h)">, V6_vmpyih_acc_enc;
1394 defm V6_vmpyowh_rnd_sacc :
1395 T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:rnd:sat:shift">,
1396 V6_vmpyowh_rnd_sacc_enc;
1397 defm V6_vmpyowh_sacc :
1398 T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:sat:shift">,
1399 V6_vmpyowh_sacc_enc;
1400 defm V6_vmpyubv_acc :
1401 T_HVX_vmpyacc_WVV <"$dst.uh += vmpy($src1.ub,$src2.ub)">,
1403 defm V6_vmpyuhv_acc :
1404 T_HVX_vmpyacc_WVV <"$dst.uw += vmpy($src1.uh,$src2.uh)">,
1406 defm V6_vrmpybusv_acc :
1407 T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.ub,$src2.b)">,
1408 V6_vrmpybusv_acc_enc;
1409 defm V6_vrmpybv_acc :
1410 T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.b,$src2.b)">, V6_vrmpybv_acc_enc;
1411 defm V6_vrmpyubv_acc :
1412 T_HVX_vmpyacc_VVV <"$dst.uw += vrmpy($src1.ub,$src2.ub)">,
1413 V6_vrmpyubv_acc_enc;
1416 class T_HVX_vcmp <string asmString, RegisterClass RCout, RegisterClass RCin>
1417 : CVI_VA_Resource1 <(outs RCout:$dst),
1418 (ins RCout:$_src_, RCin:$src1, RCin:$src2), asmString,
1419 [], "$dst = $_src_" > {
1420 let Itinerary = CVI_VA;
1421 let Type = TypeCVI_VA;
1424 multiclass T_HVX_vcmp <string asmString> {
1425 def NAME : T_HVX_vcmp <asmString, VecPredRegs, VectorRegs>;
1426 let isCodeGenOnly = 1 in
1427 def NAME#_128B : T_HVX_vcmp <asmString, VecPredRegs128B, VectorRegs128B>;
1431 T_HVX_vcmp <"$dst &= vcmp.eq($src1.b,$src2.b)">, V6_veqb_and_enc;
1433 T_HVX_vcmp <"$dst &= vcmp.eq($src1.h,$src2.h)">, V6_veqh_and_enc;
1435 T_HVX_vcmp <"$dst &= vcmp.eq($src1.w,$src2.w)">, V6_veqw_and_enc;
1437 T_HVX_vcmp <"$dst &= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_and_enc;
1439 T_HVX_vcmp <"$dst &= vcmp.gt($src1.h,$src2.h)">, V6_vgth_and_enc;
1441 T_HVX_vcmp <"$dst &= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_and_enc;
1443 T_HVX_vcmp <"$dst &= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_and_enc;
1445 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_and_enc;
1447 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_and_enc;
1449 T_HVX_vcmp <"$dst |= vcmp.eq($src1.b,$src2.b)">, V6_veqb_or_enc;
1451 T_HVX_vcmp <"$dst |= vcmp.eq($src1.h,$src2.h)">, V6_veqh_or_enc;
1453 T_HVX_vcmp <"$dst |= vcmp.eq($src1.w,$src2.w)">, V6_veqw_or_enc;
1455 T_HVX_vcmp <"$dst |= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_or_enc;
1457 T_HVX_vcmp <"$dst |= vcmp.gt($src1.h,$src2.h)">, V6_vgth_or_enc;
1459 T_HVX_vcmp <"$dst |= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_or_enc;
1461 T_HVX_vcmp <"$dst |= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_or_enc;
1463 T_HVX_vcmp <"$dst |= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_or_enc;
1465 T_HVX_vcmp <"$dst |= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_or_enc;
1467 T_HVX_vcmp <"$dst ^= vcmp.eq($src1.b,$src2.b)">, V6_veqb_xor_enc;
1469 T_HVX_vcmp <"$dst ^= vcmp.eq($src1.h,$src2.h)">, V6_veqh_xor_enc;
1471 T_HVX_vcmp <"$dst ^= vcmp.eq($src1.w,$src2.w)">, V6_veqw_xor_enc;
1473 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_xor_enc;
1475 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.h,$src2.h)">, V6_vgth_xor_enc;
1477 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_xor_enc;
1479 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_xor_enc;
1481 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_xor_enc;
1483 T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_xor_enc;
1486 T_HVX_alu_VV <"$dst.ub = vmin($src1.ub,$src2.ub)">, V6_vminub_enc;
1488 T_HVX_alu_VV <"$dst.uh = vmin($src1.uh,$src2.uh)">, V6_vminuh_enc;
1490 T_HVX_alu_VV <"$dst.h = vmin($src1.h,$src2.h)">, V6_vminh_enc;
1492 T_HVX_alu_VV <"$dst.w = vmin($src1.w,$src2.w)">, V6_vminw_enc;
1494 T_HVX_alu_VV <"$dst.ub = vmax($src1.ub,$src2.ub)">, V6_vmaxub_enc;
1496 T_HVX_alu_VV <"$dst.uh = vmax($src1.uh,$src2.uh)">, V6_vmaxuh_enc;
1498 T_HVX_alu_VV <"$dst.h = vmax($src1.h,$src2.h)">, V6_vmaxh_enc;
1500 T_HVX_alu_VV <"$dst.w = vmax($src1.w,$src2.w)">, V6_vmaxw_enc;
1502 T_HVX_alu_VV <"$dst.b = vshuffe($src1.b,$src2.b)">, V6_vshuffeb_enc;
1504 T_HVX_alu_VV <"$dst.b = vshuffo($src1.b,$src2.b)">, V6_vshuffob_enc;
1506 T_HVX_alu_VV <"$dst.h = vshuffe($src1.h,$src2.h)">, V6_vshufeh_enc;
1508 T_HVX_alu_VV <"$dst.h = vshuffo($src1.h,$src2.h)">, V6_vshufoh_enc;
1510 let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
1511 defm V6_vmpyowh_rnd :
1512 T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:rnd:sat">,
1515 T_HVX_alu_VV <"$dst.w = vmpyie($src1.w,$src2.uh)">, V6_vmpyiewuh_enc;
1517 T_HVX_alu_VV <"$dst.w = vmpye($src1.w,$src2.uh)">, V6_vmpyewuh_enc;
1519 T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:sat">, V6_vmpyowh_enc;
1521 T_HVX_alu_VV <"$dst.w = vmpyio($src1.w,$src2.h)">, V6_vmpyiowh_enc;
1523 let Itinerary = CVI_VX, Type = TypeCVI_VX in
1525 T_HVX_alu_VV <"$dst.w = vmpyieo($src1.h,$src2.h)">, V6_vmpyieoh_enc;
1527 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in {
1529 T_HVX_alu_WV <"$dst.h = vshuffoe($src1.h,$src2.h)">, V6_vshufoeh_enc;
1531 T_HVX_alu_WV <"$dst.b = vshuffoe($src1.b,$src2.b)">, V6_vshufoeb_enc;
1534 let isRegSequence = 1, Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in
1536 T_HVX_alu_WV <"$dst = vcombine($src1,$src2)">, V6_vcombine_enc;
1538 def SDTHexagonVCOMBINE: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>,
1539 SDTCisSubVecOfVec<1, 0>]>;
1541 def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>;
1543 def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs),
1544 (v16i32 VectorRegs:$Vt))),
1545 (V6_vcombine VectorRegs:$Vs, VectorRegs:$Vt)>,
1546 Requires<[UseHVXSgl]>;
1547 def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
1548 (v32i32 VecDblRegs:$Vt))),
1549 (V6_vcombine_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>,
1550 Requires<[UseHVXDbl]>;
1552 let Itinerary = CVI_VINLANESAT, Type = TypeCVI_VINLANESAT in {
1554 T_HVX_alu_VV <"$dst.ub = vsat($src1.h,$src2.h)">, V6_vsathub_enc;
1556 T_HVX_alu_VV <"$dst.h = vsat($src1.w,$src2.w)">, V6_vsatwh_enc;
1559 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1561 T_HVX_alu_VV <"$dst.h = vround($src1.w,$src2.w):sat">, V6_vroundwh_enc;
1563 T_HVX_alu_VV <"$dst.uh = vround($src1.w,$src2.w):sat">, V6_vroundwuh_enc;
1565 T_HVX_alu_VV <"$dst.b = vround($src1.h,$src2.h):sat">, V6_vroundhb_enc;
1567 T_HVX_alu_VV <"$dst.ub = vround($src1.h,$src2.h):sat">, V6_vroundhub_enc;
1569 T_HVX_alu_VV <"$dst.w = vasr($src1.w,$src2.w)">, V6_vasrwv_enc;
1571 T_HVX_alu_VV <"$dst.w = vlsr($src1.w,$src2.w)">, V6_vlsrwv_enc;
1573 T_HVX_alu_VV <"$dst.h = vlsr($src1.h,$src2.h)">, V6_vlsrhv_enc;
1575 T_HVX_alu_VV <"$dst.h = vasr($src1.h,$src2.h)">, V6_vasrhv_enc;
1577 T_HVX_alu_VV <"$dst.w = vasl($src1.w,$src2.w)">, V6_vaslwv_enc;
1579 T_HVX_alu_VV <"$dst.h = vasl($src1.h,$src2.h)">, V6_vaslhv_enc;
1583 T_HVX_alu_VV <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_enc;
1585 T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_enc;
1587 let Itinerary = CVI_VP, Type = TypeCVI_VP in {
1589 T_HVX_alu_VV <"$dst = vdelta($src1,$src2)">, V6_vdelta_enc;
1591 T_HVX_alu_VV <"$dst = vrdelta($src1,$src2)">, V6_vrdelta_enc;
1593 T_HVX_alu_VV <"$dst.b = vdeale($src1.b,$src2.b)">, V6_vdealb4w_enc;
1595 T_HVX_alu_VV <"$dst.b = vpacke($src1.h,$src2.h)">, V6_vpackeb_enc;
1597 T_HVX_alu_VV <"$dst.h = vpacke($src1.w,$src2.w)">, V6_vpackeh_enc;
1598 defm V6_vpackhub_sat :
1599 T_HVX_alu_VV <"$dst.ub = vpack($src1.h,$src2.h):sat">, V6_vpackhub_sat_enc;
1600 defm V6_vpackhb_sat :
1601 T_HVX_alu_VV <"$dst.b = vpack($src1.h,$src2.h):sat">, V6_vpackhb_sat_enc;
1602 defm V6_vpackwuh_sat :
1603 T_HVX_alu_VV <"$dst.uh = vpack($src1.w,$src2.w):sat">, V6_vpackwuh_sat_enc;
1604 defm V6_vpackwh_sat :
1605 T_HVX_alu_VV <"$dst.h = vpack($src1.w,$src2.w):sat">, V6_vpackwh_sat_enc;
1607 T_HVX_alu_VV <"$dst.b = vpacko($src1.h,$src2.h)">, V6_vpackob_enc;
1609 T_HVX_alu_VV <"$dst.h = vpacko($src1.w,$src2.w)">, V6_vpackoh_enc;
1612 let hasNewValue = 1, hasSideEffects = 0 in
1613 class T_HVX_condALU <string asmString, RegisterClass RC1, RegisterClass RC2>
1614 : CVI_VA_Resource1 <(outs RC2:$dst),
1615 (ins RC1:$src1, RC2:$_src_, RC2:$src2), asmString,
1616 [], "$dst = $_src_" > {
1617 let Itinerary = CVI_VA;
1618 let Type = TypeCVI_VA;
1621 multiclass T_HVX_condALU <string asmString> {
1622 def NAME : T_HVX_condALU <asmString, VecPredRegs, VectorRegs>;
1623 let isCodeGenOnly = 1 in
1624 def NAME#_128B : T_HVX_condALU <asmString, VecPredRegs128B, VectorRegs128B>;
1627 defm V6_vaddbq : T_HVX_condALU <"if ($src1) $dst.b += $src2.b">,
1629 defm V6_vaddhq : T_HVX_condALU <"if ($src1) $dst.h += $src2.h">,
1631 defm V6_vaddwq : T_HVX_condALU <"if ($src1) $dst.w += $src2.w">,
1633 defm V6_vsubbq : T_HVX_condALU <"if ($src1) $dst.b -= $src2.b">,
1635 defm V6_vsubhq : T_HVX_condALU <"if ($src1) $dst.h -= $src2.h">,
1637 defm V6_vsubwq : T_HVX_condALU <"if ($src1) $dst.w -= $src2.w">,
1639 defm V6_vaddbnq : T_HVX_condALU <"if (!$src1) $dst.b += $src2.b">,
1641 defm V6_vaddhnq : T_HVX_condALU <"if (!$src1) $dst.h += $src2.h">,
1643 defm V6_vaddwnq : T_HVX_condALU <"if (!$src1) $dst.w += $src2.w">,
1645 defm V6_vsubbnq : T_HVX_condALU <"if (!$src1) $dst.b -= $src2.b">,
1647 defm V6_vsubhnq : T_HVX_condALU <"if (!$src1) $dst.h -= $src2.h">,
1649 defm V6_vsubwnq : T_HVX_condALU <"if (!$src1) $dst.w -= $src2.w">,
1652 let hasNewValue = 1 in
1653 class T_HVX_alu_2op <string asmString, InstrItinClass itin,
1654 RegisterClass RCout, RegisterClass RCin>
1655 : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1),
1657 let Itinerary = itin;
1658 let Type = !cast<IType>("Type"#itin);
1661 multiclass T_HVX_alu_2op <string asmString, RegisterClass RCout,
1662 RegisterClass RCin, InstrItinClass itin> {
1663 def NAME : T_HVX_alu_2op <asmString, itin, RCout, RCin>;
1664 let isCodeGenOnly = 1 in
1665 def NAME#_128B : T_HVX_alu_2op <asmString, itin,
1666 !cast<RegisterClass>(RCout#"128B"),
1667 !cast<RegisterClass>(RCin#"128B")>;
1670 let hasNewValue = 1 in
1671 multiclass T_HVX_alu_2op_VV <string asmString>:
1672 T_HVX_alu_2op <asmString, VectorRegs, VectorRegs, CVI_VA>;
1674 multiclass T_HVX_alu_2op_WV <string asmString>:
1675 T_HVX_alu_2op <asmString, VecDblRegs, VectorRegs, CVI_VA_DV>;
1678 defm V6_vabsh : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h)">,
1680 defm V6_vabsw : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w)">,
1682 defm V6_vabsh_sat : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h):sat">,
1684 defm V6_vabsw_sat : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w):sat">,
1686 defm V6_vnot : T_HVX_alu_2op_VV <"$dst = vnot($src1)">,
1688 defm V6_vassign : T_HVX_alu_2op_VV <"$dst = $src1">,
1691 defm V6_vzb : T_HVX_alu_2op_WV <"$dst.uh = vzxt($src1.ub)">,
1693 defm V6_vzh : T_HVX_alu_2op_WV <"$dst.uw = vzxt($src1.uh)">,
1695 defm V6_vsb : T_HVX_alu_2op_WV <"$dst.h = vsxt($src1.b)">,
1697 defm V6_vsh : T_HVX_alu_2op_WV <"$dst.w = vsxt($src1.h)">,
1700 let Itinerary = CVI_VP, Type = TypeCVI_VP in {
1701 defm V6_vdealh : T_HVX_alu_2op_VV <"$dst.h = vdeal($src1.h)">,
1703 defm V6_vdealb : T_HVX_alu_2op_VV <"$dst.b = vdeal($src1.b)">,
1705 defm V6_vshuffh : T_HVX_alu_2op_VV <"$dst.h = vshuff($src1.h)">,
1707 defm V6_vshuffb : T_HVX_alu_2op_VV <"$dst.b = vshuff($src1.b)">,
1711 let Itinerary = CVI_VP_VS, Type = TypeCVI_VP_VS in {
1712 defm V6_vunpackub : T_HVX_alu_2op_WV <"$dst.uh = vunpack($src1.ub)">,
1714 defm V6_vunpackuh : T_HVX_alu_2op_WV <"$dst.uw = vunpack($src1.uh)">,
1716 defm V6_vunpackb : T_HVX_alu_2op_WV <"$dst.h = vunpack($src1.b)">,
1718 defm V6_vunpackh : T_HVX_alu_2op_WV <"$dst.w = vunpack($src1.h)">,
1722 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1723 defm V6_vcl0w : T_HVX_alu_2op_VV <"$dst.uw = vcl0($src1.uw)">,
1725 defm V6_vcl0h : T_HVX_alu_2op_VV <"$dst.uh = vcl0($src1.uh)">,
1727 defm V6_vnormamtw : T_HVX_alu_2op_VV <"$dst.w = vnormamt($src1.w)">,
1729 defm V6_vnormamth : T_HVX_alu_2op_VV <"$dst.h = vnormamt($src1.h)">,
1731 defm V6_vpopcounth : T_HVX_alu_2op_VV <"$dst.h = vpopcount($src1.h)">,
1735 let isAccumulator = 1, hasNewValue = 1, Itinerary = CVI_VX_DV_LONG,
1736 Type = TypeCVI_VX_DV in
1737 class T_HVX_vmpyacc2 <string asmString, RegisterClass RC>
1738 : CVI_VA_Resource1 <(outs RC:$dst),
1739 (ins RC:$_src_, RC:$src1, IntRegs:$src2, u1Imm:$src3),
1740 asmString, [], "$dst = $_src_" > ;
1743 multiclass T_HVX_vmpyacc2 <string asmString> {
1744 def NAME : T_HVX_vmpyacc2 <asmString, VecDblRegs>;
1746 let isCodeGenOnly = 1 in
1747 def NAME#_128B : T_HVX_vmpyacc2 <asmString, VecDblRegs128B>;
1750 defm V6_vrmpybusi_acc :
1751 T_HVX_vmpyacc2<"$dst.w += vrmpy($src1.ub,$src2.b,#$src3)">,
1752 V6_vrmpybusi_acc_enc;
1753 defm V6_vrsadubi_acc :
1754 T_HVX_vmpyacc2<"$dst.uw += vrsad($src1.ub,$src2.ub,#$src3)">,
1755 V6_vrsadubi_acc_enc;
1756 defm V6_vrmpyubi_acc :
1757 T_HVX_vmpyacc2<"$dst.uw += vrmpy($src1.ub,$src2.ub,#$src3)">,
1758 V6_vrmpyubi_acc_enc;
1761 let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV, hasNewValue = 1 in
1762 class T_HVX_vmpy2 <string asmString, RegisterClass RC>
1763 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1Imm:$src3),
1767 multiclass T_HVX_vmpy2 <string asmString> {
1768 def NAME : T_HVX_vmpy2 <asmString, VecDblRegs>;
1770 let isCodeGenOnly = 1 in
1771 def NAME#_128B : T_HVX_vmpy2 <asmString, VecDblRegs128B>;
1775 T_HVX_vmpy2 <"$dst.w = vrmpy($src1.ub,$src2.b,#$src3)">, V6_vrmpybusi_enc;
1777 T_HVX_vmpy2 <"$dst.uw = vrsad($src1.ub,$src2.ub,#$src3)">, V6_vrsadubi_enc;
1779 T_HVX_vmpy2 <"$dst.uw = vrmpy($src1.ub,$src2.ub,#$src3)">, V6_vrmpyubi_enc;
1782 let Itinerary = CVI_VP_VS_LONG_EARLY, Type = TypeCVI_VP_VS,
1783 hasSideEffects = 0, hasNewValue2 = 1, opNewValue2 = 1 in
1784 class T_HVX_perm <string asmString, RegisterClass RC>
1785 : CVI_VA_Resource1 <(outs RC:$_dst1_, RC:$_dst2_),
1786 (ins RC:$src1, RC:$src2, IntRegs:$src3),
1787 asmString, [], "$_dst1_ = $src1, $_dst2_ = $src2" >;
1789 multiclass T_HVX_perm <string asmString> {
1790 def NAME : T_HVX_perm <asmString, VectorRegs>;
1792 let isCodeGenOnly = 1 in
1793 def NAME#_128B : T_HVX_perm <asmString, VectorRegs128B>;
1796 let hasNewValue = 1, opNewValue = 0, hasNewValue2 = 1, opNewValue2 = 1 in {
1797 defm V6_vshuff : T_HVX_perm <"vshuff($src1,$src2,$src3)">, V6_vshuff_enc;
1798 defm V6_vdeal : T_HVX_perm <"vdeal($src1,$src2,$src3)">, V6_vdeal_enc;
1801 // Conditional vector move.
1802 let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1803 class T_HVX_cmov <bit isPredNot, RegisterClass RC>
1804 : CVI_VA_Resource1 <(outs RC:$dst), (ins PredRegs:$src1, RC:$src2),
1805 "if ("#!if(isPredNot, "!", "")#"$src1) $dst = $src2"> {
1806 let isPredicatedFalse = isPredNot;
1809 multiclass T_HVX_cmov <bit isPredNot = 0> {
1810 def NAME : T_HVX_cmov <isPredNot, VectorRegs>;
1812 let isCodeGenOnly = 1 in
1813 def NAME#_128B : T_HVX_cmov <isPredNot, VectorRegs128B>;
1816 defm V6_vcmov : T_HVX_cmov, V6_vcmov_enc;
1817 defm V6_vncmov : T_HVX_cmov<1>, V6_vncmov_enc;
1819 // Conditional vector combine.
1820 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, isPredicated = 1,
1821 hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1822 class T_HVX_ccombine <bit isPredNot, RegisterClass RCout, RegisterClass RCin>
1823 : CVI_VA_Resource1 < (outs RCout:$dst),
1824 (ins PredRegs:$src1, RCin:$src2, RCin:$src3),
1825 "if ("#!if(isPredNot, "!", "")#"$src1) $dst = vcombine($src2,$src3)"> {
1826 let isPredicatedFalse = isPredNot;
1829 multiclass T_HVX_ccombine <bit isPredNot = 0> {
1830 def NAME : T_HVX_ccombine <isPredNot, VecDblRegs, VectorRegs>;
1832 let isCodeGenOnly = 1 in
1833 def NAME#_128B : T_HVX_ccombine <isPredNot, VecDblRegs128B, VectorRegs128B>;
1836 defm V6_vccombine : T_HVX_ccombine, V6_vccombine_enc;
1837 defm V6_vnccombine : T_HVX_ccombine<1>, V6_vnccombine_enc;
1839 let hasNewValue = 1 in
1840 class T_HVX_shift <string asmString, RegisterClass RCout, RegisterClass RCin>
1841 : CVI_VX_DV_Resource1<(outs RCout:$dst),
1842 (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3),
1845 multiclass T_HVX_shift <string asmString, RegisterClass RCout,
1846 RegisterClass RCin> {
1847 def NAME : T_HVX_shift <asmString, RCout, RCin>;
1848 let isCodeGenOnly = 1 in
1849 def NAME#_128B : T_HVX_shift <asmString, !cast<RegisterClass>(RCout#"128B"),
1850 !cast<RegisterClass>(RCin#"128B")>;
1853 multiclass T_HVX_shift_VV <string asmString>:
1854 T_HVX_shift <asmString, VectorRegs, VectorRegs>;
1856 multiclass T_HVX_shift_WV <string asmString>:
1857 T_HVX_shift <asmString, VecDblRegs, VectorRegs>;
1859 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in {
1861 T_HVX_shift_VV <"$dst = valign($src1,$src2,$src3)">, V6_valignb_enc;
1863 T_HVX_shift_VV <"$dst = vlalign($src1,$src2,$src3)">, V6_vlalignb_enc;
1866 let Itinerary = CVI_VS, Type = TypeCVI_VS in {
1868 T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3)">, V6_vasrwh_enc;
1870 T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):sat">,
1872 defm V6_vasrwhrndsat :
1873 T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):rnd:sat">,
1874 V6_vasrwhrndsat_enc;
1875 defm V6_vasrwuhsat :
1876 T_HVX_shift_VV <"$dst.uh = vasr($src1.w,$src2.w,$src3):sat">,
1878 defm V6_vasrhubsat :
1879 T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):sat">,
1881 defm V6_vasrhubrndsat :
1882 T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):rnd:sat">,
1883 V6_vasrhubrndsat_enc;
1884 defm V6_vasrhbrndsat :
1885 T_HVX_shift_VV <"$dst.b = vasr($src1.h,$src2.h,$src3):rnd:sat">,
1886 V6_vasrhbrndsat_enc;
1889 // Assembler mapped -- alias?
1890 //defm V6_vtran2x2vdd : T_HVX_shift_VV <"">, V6_vtran2x2vdd_enc;
1891 let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in {
1893 T_HVX_shift_WV <"$dst = vshuff($src1,$src2,$src3)">, V6_vshuffvdd_enc;
1895 T_HVX_shift_WV <"$dst = vdeal($src1,$src2,$src3)">, V6_vdealvdd_enc;
1898 let hasNewValue = 1, Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in
1899 class T_HVX_unpack <string asmString, RegisterClass RCout, RegisterClass RCin>
1900 : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCout:$_src_, RCin:$src1),
1901 asmString, [], "$dst = $_src_">;
1903 multiclass T_HVX_unpack <string asmString> {
1904 def NAME : T_HVX_unpack <asmString, VecDblRegs, VectorRegs>;
1905 let isCodeGenOnly = 1 in
1906 def NAME#_128B : T_HVX_unpack <asmString, VecDblRegs128B, VectorRegs128B>;
1909 defm V6_vunpackob : T_HVX_unpack <"$dst.h |= vunpacko($src1.b)">, V6_vunpackob_enc;
1910 defm V6_vunpackoh : T_HVX_unpack <"$dst.w |= vunpacko($src1.h)">, V6_vunpackoh_enc;
1912 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1,
1913 hasSideEffects = 0 in
1914 class T_HVX_valign <string asmString, RegisterClass RC>
1915 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2, u3Imm:$src3),
1918 multiclass T_HVX_valign <string asmString> {
1919 def NAME : T_HVX_valign <asmString, VectorRegs>;
1921 let isCodeGenOnly = 1 in
1922 def NAME#_128B : T_HVX_valign <asmString, VectorRegs128B>;
1926 T_HVX_valign <"$dst = valign($src1,$src2,#$src3)">, V6_valignbi_enc;
1928 T_HVX_valign <"$dst = vlalign($src1,$src2,#$src3)">, V6_vlalignbi_enc;
1930 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in
1931 class T_HVX_predAlu <string asmString, RegisterClass RC>
1932 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2),
1935 multiclass T_HVX_predAlu <string asmString> {
1936 def NAME : T_HVX_predAlu <asmString, VecPredRegs>;
1938 let isCodeGenOnly = 1 in
1939 def NAME#_128B : T_HVX_predAlu <asmString, VecPredRegs128B>;
1942 defm V6_pred_and : T_HVX_predAlu <"$dst = and($src1,$src2)">, V6_pred_and_enc;
1943 defm V6_pred_or : T_HVX_predAlu <"$dst = or($src1,$src2)">, V6_pred_or_enc;
1944 defm V6_pred_xor : T_HVX_predAlu <"$dst = xor($src1,$src2)">, V6_pred_xor_enc;
1945 defm V6_pred_or_n : T_HVX_predAlu <"$dst = or($src1,!$src2)">, V6_pred_or_n_enc;
1946 defm V6_pred_and_n :
1947 T_HVX_predAlu <"$dst = and($src1,!$src2)">, V6_pred_and_n_enc;
1949 let Itinerary = CVI_VA, Type = TypeCVI_VA in
1950 class T_HVX_prednot <RegisterClass RC>
1951 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1),
1952 "$dst = not($src1)">, V6_pred_not_enc;
1954 def V6_pred_not : T_HVX_prednot <VecPredRegs>;
1955 let isCodeGenOnly = 1 in
1956 def V6_pred_not_128B : T_HVX_prednot <VecPredRegs128B>;
1958 let Itinerary = CVI_VA, Type = TypeCVI_VA in
1959 class T_HVX_vcmp2 <string asmString, RegisterClass RCout, RegisterClass RCin>
1960 : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2),
1963 multiclass T_HVX_vcmp2 <string asmString> {
1964 def NAME : T_HVX_vcmp2 <asmString, VecPredRegs, VectorRegs>;
1965 let isCodeGenOnly = 1 in
1966 def NAME#_128B : T_HVX_vcmp2 <asmString, VecPredRegs128B, VectorRegs128B>;
1969 defm V6_veqb : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.b,$src2.b)">, V6_veqb_enc;
1970 defm V6_veqh : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.h,$src2.h)">, V6_veqh_enc;
1971 defm V6_veqw : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.w,$src2.w)">, V6_veqw_enc;
1972 defm V6_vgtb : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.b,$src2.b)">, V6_vgtb_enc;
1973 defm V6_vgth : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.h,$src2.h)">, V6_vgth_enc;
1974 defm V6_vgtw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.w,$src2.w)">, V6_vgtw_enc;
1975 defm V6_vgtub : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_enc;
1976 defm V6_vgtuh : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_enc;
1977 defm V6_vgtuw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_enc;
1979 let isAccumulator = 1, hasNewValue = 1, hasSideEffects = 0 in
1980 class T_V6_vandqrt_acc <RegisterClass RCout, RegisterClass RCin>
1981 : CVI_VX_Resource_late<(outs RCout:$dst),
1982 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
1983 "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandqrt_acc_enc;
1985 def V6_vandqrt_acc : T_V6_vandqrt_acc <VectorRegs, VecPredRegs>;
1986 let isCodeGenOnly = 1 in
1987 def V6_vandqrt_acc_128B : T_V6_vandqrt_acc <VectorRegs128B, VecPredRegs128B>;
1989 let isAccumulator = 1 in
1990 class T_V6_vandvrt_acc <RegisterClass RCout, RegisterClass RCin>
1991 : CVI_VX_Resource_late<(outs RCout:$dst),
1992 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
1993 "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandvrt_acc_enc;
1995 def V6_vandvrt_acc : T_V6_vandvrt_acc <VecPredRegs, VectorRegs>;
1996 let isCodeGenOnly = 1 in
1997 def V6_vandvrt_acc_128B : T_V6_vandvrt_acc <VecPredRegs128B, VectorRegs128B>;
1999 let hasNewValue = 1, hasSideEffects = 0 in
2000 class T_V6_vandqrt <RegisterClass RCout, RegisterClass RCin>
2001 : CVI_VX_Resource_late<(outs RCout:$dst),
2002 (ins RCin:$src1, IntRegs:$src2),
2003 "$dst = vand($src1,$src2)" >, V6_vandqrt_enc;
2005 def V6_vandqrt : T_V6_vandqrt <VectorRegs, VecPredRegs>;
2006 let isCodeGenOnly = 1 in
2007 def V6_vandqrt_128B : T_V6_vandqrt <VectorRegs128B, VecPredRegs128B>;
2009 let hasNewValue = 1, hasSideEffects = 0 in
2010 class T_V6_lvsplatw <RegisterClass RC>
2011 : CVI_VX_Resource_late<(outs RC:$dst), (ins IntRegs:$src1),
2012 "$dst = vsplat($src1)" >, V6_lvsplatw_enc;
2014 def V6_lvsplatw : T_V6_lvsplatw <VectorRegs>;
2015 let isCodeGenOnly = 1 in
2016 def V6_lvsplatw_128B : T_V6_lvsplatw <VectorRegs128B>;
2019 let hasNewValue = 1 in
2020 class T_V6_vinsertwr <RegisterClass RC>
2021 : CVI_VX_Resource_late<(outs RC:$dst), (ins RC:$_src_, IntRegs:$src1),
2022 "$dst.w = vinsert($src1)", [], "$dst = $_src_">,
2025 def V6_vinsertwr : T_V6_vinsertwr <VectorRegs>;
2026 let isCodeGenOnly = 1 in
2027 def V6_vinsertwr_128B : T_V6_vinsertwr <VectorRegs128B>;
2030 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in
2031 class T_V6_pred_scalar2 <RegisterClass RC>
2032 : CVI_VA_Resource1<(outs RC:$dst), (ins IntRegs:$src1),
2033 "$dst = vsetq($src1)">, V6_pred_scalar2_enc;
2035 def V6_pred_scalar2 : T_V6_pred_scalar2 <VecPredRegs>;
2036 let isCodeGenOnly = 1 in
2037 def V6_pred_scalar2_128B : T_V6_pred_scalar2 <VecPredRegs128B>;
2039 class T_V6_vandvrt <RegisterClass RCout, RegisterClass RCin>
2040 : CVI_VX_Resource_late<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
2041 "$dst = vand($src1,$src2)">, V6_vandvrt_enc;
2043 def V6_vandvrt : T_V6_vandvrt <VecPredRegs, VectorRegs>;
2044 let isCodeGenOnly = 1 in
2045 def V6_vandvrt_128B : T_V6_vandvrt <VecPredRegs128B, VectorRegs128B>;
2047 let validSubTargets = HasV60SubT in
2048 class T_HVX_rol <string asmString, RegisterClass RC, Operand ImmOp >
2049 : SInst2 <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2), asmString>;
2051 class T_HVX_rol_R <string asmString>
2052 : T_HVX_rol <asmString, IntRegs, u5Imm>;
2053 class T_HVX_rol_P <string asmString>
2054 : T_HVX_rol <asmString, DoubleRegs, u6Imm>;
2056 def S6_rol_i_p : T_HVX_rol_P <"$dst = rol($src1,#$src2)">, S6_rol_i_p_enc;
2057 let hasNewValue = 1, opNewValue = 0 in
2058 def S6_rol_i_r : T_HVX_rol_R <"$dst = rol($src1,#$src2)">, S6_rol_i_r_enc;
2060 let validSubTargets = HasV60SubT in
2061 class T_HVX_rol_acc <string asmString, RegisterClass RC, Operand ImmOp>
2062 : SInst2 <(outs RC:$dst), (ins RC:$_src_, RC:$src1, ImmOp:$src2),
2063 asmString, [], "$dst = $_src_" >;
2065 class T_HVX_rol_acc_P <string asmString>
2066 : T_HVX_rol_acc <asmString, DoubleRegs, u6Imm>;
2068 class T_HVX_rol_acc_R <string asmString>
2069 : T_HVX_rol_acc <asmString, IntRegs, u5Imm>;
2071 def S6_rol_i_p_nac :
2072 T_HVX_rol_acc_P <"$dst -= rol($src1,#$src2)">, S6_rol_i_p_nac_enc;
2073 def S6_rol_i_p_acc :
2074 T_HVX_rol_acc_P <"$dst += rol($src1,#$src2)">, S6_rol_i_p_acc_enc;
2075 def S6_rol_i_p_and :
2076 T_HVX_rol_acc_P <"$dst &= rol($src1,#$src2)">, S6_rol_i_p_and_enc;
2078 T_HVX_rol_acc_P <"$dst |= rol($src1,#$src2)">, S6_rol_i_p_or_enc;
2079 def S6_rol_i_p_xacc :
2080 T_HVX_rol_acc_P<"$dst ^= rol($src1,#$src2)">, S6_rol_i_p_xacc_enc;
2082 let hasNewValue = 1, opNewValue = 0 in {
2083 def S6_rol_i_r_nac :
2084 T_HVX_rol_acc_R <"$dst -= rol($src1,#$src2)">, S6_rol_i_r_nac_enc;
2085 def S6_rol_i_r_acc :
2086 T_HVX_rol_acc_R <"$dst += rol($src1,#$src2)">, S6_rol_i_r_acc_enc;
2087 def S6_rol_i_r_and :
2088 T_HVX_rol_acc_R <"$dst &= rol($src1,#$src2)">, S6_rol_i_r_and_enc;
2090 T_HVX_rol_acc_R <"$dst |= rol($src1,#$src2)">, S6_rol_i_r_or_enc;
2091 def S6_rol_i_r_xacc :
2092 T_HVX_rol_acc_R <"$dst ^= rol($src1,#$src2)">, S6_rol_i_r_xacc_enc;
2095 let isSolo = 1, Itinerary = LD_tc_ld_SLOT0, Type = TypeLD in
2096 class T_V6_extractw <RegisterClass RC>
2097 : LD1Inst <(outs IntRegs:$dst), (ins RC:$src1, IntRegs:$src2),
2098 "$dst = vextract($src1,$src2)">, V6_extractw_enc;
2100 def V6_extractw : T_V6_extractw <VectorRegs>;
2101 let isCodeGenOnly = 1 in
2102 def V6_extractw_128B : T_V6_extractw <VectorRegs128B>;
2104 let Itinerary = ST_tc_st_SLOT0, validSubTargets = HasV55SubT in
2105 class T_sys0op <string asmString>
2106 : ST1Inst <(outs), (ins), asmString>;
2108 let isSolo = 1, validSubTargets = HasV55SubT in {
2109 def Y5_l2gunlock : T_sys0op <"l2gunlock">, Y5_l2gunlock_enc;
2110 def Y5_l2gclean : T_sys0op <"l2gclean">, Y5_l2gclean_enc;
2111 def Y5_l2gcleaninv : T_sys0op <"l2gcleaninv">, Y5_l2gcleaninv_enc;
2114 class T_sys1op <string asmString, RegisterClass RC>
2115 : ST1Inst <(outs), (ins RC:$src1), asmString>;
2117 class T_sys1op_R <string asmString> : T_sys1op <asmString, IntRegs>;
2118 class T_sys1op_P <string asmString> : T_sys1op <asmString, DoubleRegs>;
2120 let isSoloAX = 1, validSubTargets = HasV55SubT in
2121 def Y5_l2unlocka : T_sys1op_R <"l2unlocka($src1)">, Y5_l2unlocka_enc;
2123 let isSolo = 1, validSubTargets = HasV60SubT in {
2124 def Y6_l2gcleanpa : T_sys1op_P <"l2gclean($src1)">, Y6_l2gcleanpa_enc;
2125 def Y6_l2gcleaninvpa : T_sys1op_P <"l2gcleaninv($src1)">, Y6_l2gcleaninvpa_enc;
2128 let Itinerary = ST_tc_3stall_SLOT0, isPredicateLate = 1, isSoloAX = 1,
2129 validSubTargets = HasV55SubT in
2130 def Y5_l2locka : ST1Inst <(outs PredRegs:$dst), (ins IntRegs:$src1),
2131 "$dst = l2locka($src1)">, Y5_l2locka_enc;
2133 // not defined on etc side. why?
2134 // defm S2_cabacencbin : _VV <"Rdd=encbin(Rss,$src2,Pu)">, S2_cabacencbin_enc;
2136 let Defs = [USR_OVF], Itinerary = M_tc_3stall_SLOT23, isPredicateLate = 1,
2138 validSubTargets = HasV55SubT in
2139 def A5_ACS : MInst2 <(outs DoubleRegs:$dst1, PredRegs:$dst2),
2140 (ins DoubleRegs:$_src_, DoubleRegs:$src1, DoubleRegs:$src2),
2141 "$dst1,$dst2 = vacsh($src1,$src2)", [],
2142 "$dst1 = $_src_" >, Requires<[HasV55T]>, A5_ACS_enc;
2144 let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, hasNewValue = 1,
2145 hasSideEffects = 0 in
2146 class T_HVX_alu2 <string asmString, RegisterClass RCout, RegisterClass RCin1,
2147 RegisterClass RCin2>
2148 : CVI_VA_Resource1<(outs RCout:$dst),
2149 (ins RCin1:$src1, RCin2:$src2, RCin2:$src3), asmString>;
2151 multiclass T_HVX_alu2 <string asmString, RegisterClass RC > {
2152 def NAME : T_HVX_alu2 <asmString, RC, VecPredRegs, VectorRegs>;
2153 let isCodeGenOnly = 1 in
2154 def NAME#_128B : T_HVX_alu2 <asmString, !cast<RegisterClass>(RC#"128B"),
2155 VecPredRegs128B, VectorRegs128B>;
2158 multiclass T_HVX_alu2_V <string asmString> :
2159 T_HVX_alu2 <asmString, VectorRegs>;
2161 multiclass T_HVX_alu2_W <string asmString> :
2162 T_HVX_alu2 <asmString, VecDblRegs>;
2164 defm V6_vswap : T_HVX_alu2_W <"$dst = vswap($src1,$src2,$src3)">, V6_vswap_enc;
2166 let Itinerary = CVI_VA, Type = TypeCVI_VA, hasNewValue = 1,
2167 hasSideEffects = 0 in
2168 defm V6_vmux : T_HVX_alu2_V <"$dst = vmux($src1,$src2,$src3)">, V6_vmux_enc;
2170 class T_HVX_vlutb <string asmString, RegisterClass RCout, RegisterClass RCin>
2171 : CVI_VA_Resource1<(outs RCout:$dst),
2172 (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3), asmString>;
2174 multiclass T_HVX_vlutb <string asmString, RegisterClass RCout,
2175 RegisterClass RCin> {
2176 def NAME : T_HVX_vlutb <asmString, RCout, RCin>;
2177 let isCodeGenOnly = 1 in
2178 def NAME#_128B : T_HVX_vlutb <asmString, !cast<RegisterClass>(RCout#"128B"),
2179 !cast<RegisterClass>(RCin#"128B")>;
2182 multiclass T_HVX_vlutb_V <string asmString> :
2183 T_HVX_vlutb <asmString, VectorRegs, VectorRegs>;
2185 multiclass T_HVX_vlutb_W <string asmString> :
2186 T_HVX_vlutb <asmString, VecDblRegs, VectorRegs>;
2188 let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, isAccumulator = 1 in
2189 class T_HVX_vlutb_acc <string asmString, RegisterClass RCout,
2191 : CVI_VA_Resource1<(outs RCout:$dst),
2192 (ins RCout:$_src_, RCin:$src1, RCin:$src2, IntRegsLow8:$src3),
2193 asmString, [], "$dst = $_src_">;
2195 multiclass T_HVX_vlutb_acc <string asmString, RegisterClass RCout,
2196 RegisterClass RCin> {
2197 def NAME : T_HVX_vlutb_acc <asmString, RCout, RCin>;
2198 let isCodeGenOnly = 1 in
2199 def NAME#_128B : T_HVX_vlutb_acc<asmString,
2200 !cast<RegisterClass>(RCout#"128B"),
2201 !cast<RegisterClass>(RCin#"128B")>;
2204 multiclass T_HVX_vlutb_acc_V <string asmString> :
2205 T_HVX_vlutb_acc <asmString, VectorRegs, VectorRegs>;
2207 multiclass T_HVX_vlutb_acc_W <string asmString> :
2208 T_HVX_vlutb_acc <asmString, VecDblRegs, VectorRegs>;
2211 let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1 in
2213 T_HVX_vlutb_V <"$dst.b = vlut32($src1.b,$src2.b,$src3)">, V6_vlutvvb_enc;
2215 let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, hasNewValue = 1 in
2217 T_HVX_vlutb_W <"$dst.h = vlut16($src1.b,$src2.h,$src3)">, V6_vlutvwh_enc;
2219 let hasNewValue = 1 in {
2220 defm V6_vlutvvb_oracc:
2221 T_HVX_vlutb_acc_V <"$dst.b |= vlut32($src1.b,$src2.b,$src3)">,
2222 V6_vlutvvb_oracc_enc;
2223 defm V6_vlutvwh_oracc:
2224 T_HVX_vlutb_acc_W <"$dst.h |= vlut16($src1.b,$src2.h,$src3)">,
2225 V6_vlutvwh_oracc_enc;
2228 // It's a fake instruction and should not be defined?
2230 : SInst2<(outs DoubleRegs:$dst),
2231 (ins DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),
2232 "$dst = encbin($src1,$src2,$src3)">, S2_cabacencbin_enc;
2234 // Vhist instructions
2236 : CVI_HIST_Resource1 <(outs), (ins VecPredRegs:$src1),
2237 "vhist($src1)">, V6_vhistq_enc;
2240 : CVI_HIST_Resource1 <(outs), (ins),
2241 "vhist" >, V6_vhist_enc;