1 //===- HexagonIntrinsics.td - Instruction intrinsics -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is populated based on the following specs:
10 // Hexagon V2 Architecture
11 // Application-Level Specification
14 //===----------------------------------------------------------------------===//
20 class qi_ALU32_sisi<string opc, Intrinsic IntID>
21 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
22 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
23 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
25 class qi_ALU32_sis10<string opc, Intrinsic IntID>
26 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
27 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
28 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
30 class qi_ALU32_sis8<string opc, Intrinsic IntID>
31 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
33 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
35 class qi_ALU32_siu8<string opc, Intrinsic IntID>
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
37 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
38 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
40 class qi_ALU32_siu9<string opc, Intrinsic IntID>
41 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
42 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
43 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
45 class si_ALU32_qisisi<string opc, Intrinsic IntID>
46 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
48 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
49 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
52 class si_ALU32_qis8si<string opc, Intrinsic IntID>
53 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
55 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
56 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
59 class si_ALU32_qisis8<string opc, Intrinsic IntID>
60 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
62 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
63 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
66 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
67 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
68 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
69 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
71 class si_ALU32_sisi<string opc, Intrinsic IntID>
72 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
73 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
74 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
76 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
77 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
78 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
79 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
81 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
82 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
83 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
84 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
86 class si_ALU32_sis16<string opc, Intrinsic IntID>
87 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
88 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
89 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
91 class si_ALU32_sis10<string opc, Intrinsic IntID>
92 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
93 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
94 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
96 class si_ALU32_s10si<string opc, Intrinsic IntID>
97 : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
98 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
99 [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
101 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
102 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
103 !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
104 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
106 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
107 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
108 !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
109 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
111 class si_ALU32_s16<string opc, Intrinsic IntID>
112 : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
113 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
114 [(set IntRegs:$dst, (IntID imm:$src1))]>;
116 class di_ALU32_s8<string opc, Intrinsic IntID>
117 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
118 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
119 [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
121 class di_ALU64_di<string opc, Intrinsic IntID>
122 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
123 !strconcat("$dst = ", !strconcat(opc , "$src")),
124 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
126 class si_ALU32_si<string opc, Intrinsic IntID>
127 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
128 !strconcat("$dst = ", !strconcat(opc , "($src)")),
129 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
131 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
132 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
133 !strconcat("$dst = ", !strconcat(opc , "$src")),
134 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
140 class si_ALU64_si_sat<string opc, Intrinsic IntID>
141 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
142 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
143 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
145 class si_ALU64_didi<string opc, Intrinsic IntID>
146 : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
147 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
148 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
150 class di_ALU64_sidi<string opc, Intrinsic IntID>
151 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
152 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
153 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
155 class di_ALU64_didi<string opc, Intrinsic IntID>
156 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
157 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
158 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
159 DoubleRegs:$src2))]>;
161 class di_ALU64_qididi<string opc, Intrinsic IntID>
162 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
164 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
165 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
166 DoubleRegs:$src3))]>;
168 class di_ALU64_sisi<string opc, Intrinsic IntID>
169 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
170 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
171 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
173 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
174 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
175 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
176 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
177 DoubleRegs:$src2))]>;
179 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
180 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
181 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
182 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
183 DoubleRegs:$src2))]>;
185 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
186 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
187 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
188 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
189 DoubleRegs:$src2))]>;
191 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
192 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
193 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
194 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
195 DoubleRegs:$src2))]>;
197 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
198 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
199 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
200 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
201 DoubleRegs:$src2))]>;
203 class qi_ALU64_didi<string opc, Intrinsic IntID>
204 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
205 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
206 [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
208 class si_ALU64_sisi<string opc, Intrinsic IntID>
209 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
210 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
211 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
213 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
214 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
215 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
216 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
218 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
219 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
220 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
221 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
223 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
224 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
225 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
226 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
228 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
229 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
230 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
231 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
233 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
234 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
235 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
236 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
238 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
239 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
240 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
241 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
243 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
244 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
245 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
246 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
248 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
249 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
250 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
251 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
253 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
254 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
255 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
256 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
258 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
259 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
260 !strconcat("$dst = ", !strconcat(opc ,
261 "($src1.H, $src2.H):sat:<<16")),
262 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
264 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
265 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
266 !strconcat("$dst = ", !strconcat(opc ,
267 "($src1.L, $src2.H):sat:<<16")),
268 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
270 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
271 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
272 !strconcat("$dst = ", !strconcat(opc ,
273 "($src1.H, $src2.L):sat:<<16")),
274 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
276 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
277 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
278 !strconcat("$dst = ", !strconcat(opc ,
279 "($src1.L, $src2.L):sat:<<16")),
280 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
282 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
283 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
284 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
285 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
287 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
288 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
289 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
290 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
292 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
293 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
294 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
295 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
297 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
298 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
299 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
300 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
302 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
303 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
304 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
305 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
307 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
308 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
309 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
310 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
312 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
313 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
314 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
315 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
321 class qi_SInst_qi<string opc, Intrinsic IntID>
322 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
323 !strconcat("$dst = ", !strconcat(opc , "($src)")),
324 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
326 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
327 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
328 !strconcat("$dst = ", !strconcat(opc , "$src")),
329 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
331 class qi_SInst_qiqi<string opc, Intrinsic IntID>
332 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
333 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
334 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
336 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
337 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
338 !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
339 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
341 class di_SInst_di<string opc, Intrinsic IntID>
342 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
343 !strconcat("$dst = ", !strconcat(opc , "($src)")),
344 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
346 class di_SInst_di_sat<string opc, Intrinsic IntID>
347 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
348 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
349 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
351 class si_SInst_di<string opc, Intrinsic IntID>
352 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
353 !strconcat("$dst = ", !strconcat(opc , "($src)")),
354 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
356 class si_SInst_di_sat<string opc, Intrinsic IntID>
357 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
358 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
359 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
361 class di_SInst_disi<string opc, Intrinsic IntID>
362 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
363 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
364 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
366 class di_SInst_didi<string opc, Intrinsic IntID>
367 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
368 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
369 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
371 class di_SInst_si<string opc, Intrinsic IntID>
372 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
373 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
374 [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
376 class si_SInst_sisiu3<string opc, Intrinsic IntID>
377 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
378 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
379 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
382 class si_SInst_diu5<string opc, Intrinsic IntID>
383 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
384 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
385 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
387 class si_SInst_disi<string opc, Intrinsic IntID>
388 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
389 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
390 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
392 class si_SInst_sidi<string opc, Intrinsic IntID>
393 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
394 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
395 [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
397 class di_SInst_disisi<string opc, Intrinsic IntID>
398 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
400 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
401 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
404 class di_SInst_sisi<string opc, Intrinsic IntID>
405 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
406 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
407 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
409 class qi_SInst_siu5<string opc, Intrinsic IntID>
410 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
411 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
412 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
414 class qi_SInst_siu6<string opc, Intrinsic IntID>
415 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
416 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
417 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
419 class qi_SInst_sisi<string opc, Intrinsic IntID>
420 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
421 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
422 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
424 class si_SInst_si<string opc, Intrinsic IntID>
425 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
426 !strconcat("$dst = ", !strconcat(opc , "($src)")),
427 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
429 class si_SInst_si_sat<string opc, Intrinsic IntID>
430 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
431 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
432 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
434 class di_SInst_qi<string opc, Intrinsic IntID>
435 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
436 !strconcat("$dst = ", !strconcat(opc , "($src)")),
437 [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
439 class si_SInst_qi<string opc, Intrinsic IntID>
440 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
441 !strconcat("$dst = ", !strconcat(opc , "$src")),
442 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
444 class si_SInst_qiqi<string opc, Intrinsic IntID>
445 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
446 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
447 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
449 class qi_SInst_si<string opc, Intrinsic IntID>
450 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
451 !strconcat("$dst = ", !strconcat(opc , "$src")),
452 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
454 class si_SInst_sisi<string opc, Intrinsic IntID>
455 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
456 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
457 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
459 class di_SInst_diu6<string opc, Intrinsic IntID>
460 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
461 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
462 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
464 class si_SInst_siu5<string opc, Intrinsic IntID>
465 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
466 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
467 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
469 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
470 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
471 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
472 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
474 class si_SInst_siu5u5<string opc, Intrinsic IntID>
475 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
476 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
477 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
479 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
480 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
482 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
483 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
487 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
488 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
490 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
491 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
495 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
496 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
498 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
499 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
504 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
505 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
507 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
508 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
509 DoubleRegs:$src1, IntRegs:$src2))],
512 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
513 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
514 u5Imm:$src2, u5Imm:$src3),
515 !strconcat("$dst = ", !strconcat(opc ,
516 "($src1, #$src2, #$src3)")),
517 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
518 imm:$src2, imm:$src3))],
521 class si_SInst_sisidi<string opc, Intrinsic IntID>
522 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
524 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
525 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
529 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
530 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
531 u6Imm:$src2, u6Imm:$src3),
532 !strconcat("$dst = ", !strconcat(opc ,
533 "($src1, #$src2, #$src3)")),
534 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
535 imm:$src2, imm:$src3))],
538 class di_SInst_dididi<string opc, Intrinsic IntID>
539 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
541 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
542 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
547 class di_SInst_diu6u6<string opc, Intrinsic IntID>
548 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
550 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
551 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
554 class di_SInst_didisi<string opc, Intrinsic IntID>
555 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
557 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
558 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
561 class di_SInst_didiqi<string opc, Intrinsic IntID>
562 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
564 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
565 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
568 class di_SInst_didiu3<string opc, Intrinsic IntID>
569 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
571 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
572 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
575 class di_SInst_didisi_or<string opc, Intrinsic IntID>
576 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
578 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
579 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
583 class di_SInst_didisi_and<string opc, Intrinsic IntID>
584 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
586 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
587 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
591 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
592 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
594 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
595 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
599 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
600 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
602 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
603 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
607 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
608 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
610 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
611 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
615 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
616 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
618 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
619 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
623 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
624 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
626 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
627 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
632 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
633 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
635 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
636 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
640 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
641 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
643 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
644 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
648 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
649 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
651 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
652 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
656 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
657 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
659 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
660 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
664 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
665 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
667 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
668 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
672 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
673 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
675 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
676 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
677 DoubleRegs:$src1, imm:$src2))],
680 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
681 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
683 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
684 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
693 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
694 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
695 !strconcat("$dst = ", !strconcat(opc ,
696 "($src1.H, $src2.H):<<1:rnd")),
697 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
699 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
700 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
701 !strconcat("$dst = ", !strconcat(opc ,
702 "($src1.H, $src2.H):rnd")),
703 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
705 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
706 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
707 !strconcat("$dst = ", !strconcat(opc ,
708 "($src1.H, $src2.L):<<1:rnd")),
709 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
711 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
712 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
713 !strconcat("$dst = ", !strconcat(opc ,
714 "($src1.H, $src2.L):rnd")),
715 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
717 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
718 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
719 !strconcat("$dst = ", !strconcat(opc ,
720 "($src1.L, $src2.H):<<1:rnd")),
721 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
723 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
724 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
725 !strconcat("$dst = ", !strconcat(opc ,
726 "($src1.L, $src2.H):rnd")),
727 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
729 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
730 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
731 !strconcat("$dst = ", !strconcat(opc ,
732 "($src1.L, $src2.L):<<1:rnd")),
733 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
735 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
736 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
737 !strconcat("$dst = ", !strconcat(opc ,
738 "($src1.L, $src2.L):rnd")),
739 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
741 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
742 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
744 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
745 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
749 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
750 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
752 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
753 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
757 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
758 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
760 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
761 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
765 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
766 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
768 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
769 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
773 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
774 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
776 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
777 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
781 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
782 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
784 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
785 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
789 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
790 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
792 !strconcat("$dst -= ", !strconcat(opc ,
793 "($src1, $src2):<<1:sat")),
794 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
798 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
799 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
801 !strconcat("$dst += ", !strconcat(opc ,
802 "($src1, $src2*):<<1:sat")),
803 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
807 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
808 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
810 !strconcat("$dst -= ", !strconcat(opc ,
811 "($src1, $src2*):<<1:sat")),
812 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
816 class di_MInst_s8s8<string opc, Intrinsic IntID>
817 : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
818 !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
819 [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
821 class si_MInst_sisi<string opc, Intrinsic IntID>
822 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
823 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
824 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
826 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
827 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
828 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
829 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
831 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
832 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
833 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
834 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
836 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
837 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
838 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
839 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
841 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
842 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
843 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
844 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
846 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
847 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
848 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
849 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
851 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
852 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
853 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
854 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
856 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
857 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
858 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
859 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
861 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
862 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
863 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
864 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
867 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
868 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
869 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
870 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
872 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
873 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
874 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
875 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
877 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
878 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
879 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
880 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
882 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
883 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
884 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
885 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
887 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
888 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
889 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
890 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
892 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
893 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
894 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
895 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
897 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
898 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
899 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
900 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
902 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
903 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
904 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
905 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
907 class si_MInst_sisi_up<string opc, Intrinsic IntID>
908 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
909 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
910 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
912 class di_MInst_didi<string opc, Intrinsic IntID>
913 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
914 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
915 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
916 DoubleRegs:$src2))]>;
918 class di_MInst_didi_conj<string opc, Intrinsic IntID>
919 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
920 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
921 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
922 DoubleRegs:$src2))]>;
924 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
925 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
926 !strconcat("$dst = ", !strconcat(opc ,
927 "($src1, $src2*):<<1:sat")),
928 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
930 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
931 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
932 !strconcat("$dst = ", !strconcat(opc ,
933 "($src1, $src2):<<1:rnd:sat")),
934 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
935 DoubleRegs:$src2))]>;
937 class di_MInst_didi_sat<string opc, Intrinsic IntID>
938 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
939 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
940 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
941 DoubleRegs:$src2))]>;
943 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
944 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
945 !strconcat("$dst = ", !strconcat(opc ,
946 "($src1, $src2):rnd:sat")),
947 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
948 DoubleRegs:$src2))]>;
950 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
951 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
952 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
953 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
955 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
956 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
957 !strconcat("$dst = ", !strconcat(opc ,
958 "($src1, $src2):<<1:rnd:sat")),
959 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
961 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
962 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
963 !strconcat("$dst = ", !strconcat(opc ,
964 "($src1, $src2.L):<<1:rnd:sat")),
965 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
967 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
968 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
969 !strconcat("$dst = ", !strconcat(opc ,
970 "($src1, $src2.H):<<1:rnd:sat")),
971 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
973 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
974 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
975 !strconcat("$dst = ", !strconcat(opc ,
976 "($src1, $src2*):rnd:sat")),
977 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
979 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
980 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
981 !strconcat("$dst = ", !strconcat(opc ,
982 "($src1, $src2*):<<1:rnd:sat")),
983 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
985 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
986 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
987 !strconcat("$dst = ", !strconcat(opc ,
988 "($src1, $src2):rnd:sat")),
989 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
991 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
992 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
993 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
994 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
996 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
997 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
999 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1000 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1004 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1005 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1007 !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1008 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1012 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1013 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1015 !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1016 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1020 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1021 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1023 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1024 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1028 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1029 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1031 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1032 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1036 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1037 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1038 u4Imm:$src2, u5Imm:$src3),
1039 !strconcat("$dst = ", !strconcat(opc ,
1040 "($src1, #$src2, #$src3)")),
1041 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1042 imm:$src2, imm:$src3))],
1045 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1046 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1048 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1049 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1053 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1054 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1056 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1057 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1061 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1062 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1064 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1065 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1069 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1070 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1072 !strconcat("$dst += ", !strconcat(opc ,
1073 "($src1.L, $src2.H):sat")),
1074 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1078 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1079 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1081 !strconcat("$dst += ", !strconcat(opc ,
1082 "($src1.L, $src2.H):<<1:sat")),
1083 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1087 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1088 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1090 !strconcat("$dst += ", !strconcat(opc ,
1091 "($src1.H, $src2.H):sat")),
1092 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1096 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1097 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1099 !strconcat("$dst += ", !strconcat(opc ,
1100 "($src1.H, $src2.H):<<1:sat")),
1101 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1105 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1106 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1108 !strconcat("$dst += ", !strconcat(opc ,
1109 "($src1.H, $src2.H):<<1")),
1110 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1114 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1115 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1117 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1118 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1122 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1123 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1125 !strconcat("$dst -= ", !strconcat(opc ,
1126 "($src1.H, $src2.H):<<1:sat")),
1127 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1131 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1132 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1134 !strconcat("$dst -= ", !strconcat(opc ,
1135 "($src1.H, $src2.H):sat")),
1136 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1140 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1141 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1143 !strconcat("$dst -= ", !strconcat(opc ,
1144 "($src1.H, $src2.L):<<1:sat")),
1145 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1149 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1150 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1152 !strconcat("$dst -= ", !strconcat(opc ,
1153 "($src1.H, $src2.L):sat")),
1154 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1158 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1159 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1161 !strconcat("$dst -= ", !strconcat(opc ,
1162 "($src1.L, $src2.H):<<1:sat")),
1163 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1167 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1168 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1170 !strconcat("$dst -= ", !strconcat(opc ,
1171 "($src1.L, $src2.H):sat")),
1172 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1176 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1177 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1179 !strconcat("$dst -= ", !strconcat(opc ,
1180 "($src1.L, $src2.L):<<1:sat")),
1181 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1185 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1186 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1188 !strconcat("$dst -= ", !strconcat(opc ,
1189 "($src1.L, $src2.L):sat")),
1190 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1194 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1195 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1197 !strconcat("$dst -= ", !strconcat(opc ,
1198 "($src1.H, $src2.H):<<1")),
1199 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1203 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1204 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1206 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1207 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1211 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1212 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1214 !strconcat("$dst += ", !strconcat(opc ,
1215 "($src1.H, $src2.L):<<1")),
1216 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1220 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1221 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1223 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1224 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1228 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1229 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1231 !strconcat("$dst -= ", !strconcat(opc ,
1232 "($src1.H, $src2.L):<<1")),
1233 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1237 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1238 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1240 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1241 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1245 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1246 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1248 !strconcat("$dst += ", !strconcat(opc ,
1249 "($src1.L, $src2.H):<<1")),
1250 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1254 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1255 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1257 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1258 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1262 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1263 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1265 !strconcat("$dst -= ", !strconcat(opc ,
1266 "($src1.L, $src2.H):<<1")),
1267 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1271 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1272 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1274 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1275 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1279 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1280 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1282 !strconcat("$dst += ", !strconcat(opc ,
1283 "($src1.L, $src2.L):<<1")),
1284 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1288 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1289 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1291 !strconcat("$dst += ", !strconcat(opc ,
1292 "($src1.L, $src2.L):<<1:sat")),
1293 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1297 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1298 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1300 !strconcat("$dst += ", !strconcat(opc ,
1301 "($src1.H, $src2.L):<<1:sat")),
1302 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1306 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1307 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1309 !strconcat("$dst += ", !strconcat(opc ,
1310 "($src1.L, $src2.L):sat")),
1311 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1315 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1316 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1318 !strconcat("$dst += ", !strconcat(opc ,
1319 "($src1.H, $src2.L):sat")),
1320 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1324 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1325 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1327 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1328 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1332 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1333 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1335 !strconcat("$dst -= ", !strconcat(opc ,
1336 "($src1.L, $src2.L):<<1")),
1337 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1341 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1342 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1344 !strconcat("$dst -= ", !strconcat(opc ,
1345 "($src1.H, $src2.H):sat")),
1346 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1350 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1351 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1353 !strconcat("$dst -= ", !strconcat(opc ,
1354 "($src1.H, $src2.H):<<1:sat")),
1355 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1359 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1360 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1362 !strconcat("$dst -= ", !strconcat(opc ,
1363 "($src1.H, $src2.L):sat")),
1364 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1368 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1369 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1371 !strconcat("$dst -= ", !strconcat(opc ,
1372 "($src1.H, $src2.L):<<1:sat")),
1373 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1377 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1378 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1380 !strconcat("$dst -= ", !strconcat(opc ,
1381 "($src1.L, $src2.H):sat")),
1382 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1386 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1387 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1389 !strconcat("$dst -= ", !strconcat(opc ,
1390 "($src1.L, $src2.H):<<1:sat")),
1391 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1395 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1396 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1398 !strconcat("$dst -= ", !strconcat(opc ,
1399 "($src1.L, $src2.L):sat")),
1400 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1404 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1405 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1407 !strconcat("$dst -= ", !strconcat(opc ,
1408 "($src1.L, $src2.L):<<1:sat")),
1409 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1413 class di_ALU32_sisi<string opc, Intrinsic IntID>
1414 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1415 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1416 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1418 class di_MInst_sisi<string opc, Intrinsic IntID>
1419 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1420 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1421 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1423 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1424 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1425 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1426 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1428 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1429 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1430 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1431 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1433 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1434 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1435 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1436 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1438 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1439 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1440 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1441 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1442 DoubleRegs:$src2))]>;
1444 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1445 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1446 !strconcat("$dst = ", !strconcat(opc ,
1447 "($src1, $src2):<<1:rnd:sat")),
1448 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1450 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1451 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1452 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1453 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1455 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1456 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1457 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1458 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1460 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1461 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1462 !strconcat("$dst = ", !strconcat(opc ,
1463 "($src1.H, $src2.H):<<1:sat")),
1464 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1466 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1467 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1468 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1469 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1471 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1472 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1473 !strconcat("$dst = ", !strconcat(opc ,
1474 "($src1.H, $src2.L):<<1:sat")),
1475 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1477 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1478 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1479 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1480 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1482 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1483 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1484 !strconcat("$dst = ", !strconcat(opc ,
1485 "($src1.L, $src2.H):<<1:sat")),
1486 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1488 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1489 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1490 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1491 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1493 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1494 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1495 !strconcat("$dst = ", !strconcat(opc ,
1496 "($src1.L, $src2.L):<<1:sat")),
1497 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1499 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1500 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1501 !strconcat("$dst = ", !strconcat(opc ,
1502 "($src1.H, $src2.H):rnd:sat")),
1503 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1505 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1506 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1507 !strconcat("$dst = ", !strconcat(opc ,
1508 "($src1.H, $src2.H):rnd")),
1509 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1511 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1512 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1513 !strconcat("$dst = ", !strconcat(opc ,
1514 "($src1.H, $src2.H):<<1:rnd")),
1515 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1517 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1518 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1519 !strconcat("$dst = ",
1521 "($src1.H, $src2.H):<<1:rnd:sat")),
1522 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1524 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1525 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1526 !strconcat("$dst = ",
1527 !strconcat(opc , "($src1.H, $src2.L):rnd")),
1528 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1530 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1531 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1532 !strconcat("$dst = ",
1533 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1534 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1536 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1537 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1538 !strconcat("$dst = ",
1539 !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1540 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1542 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1543 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1544 !strconcat("$dst = ",
1545 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1546 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1548 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1549 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1550 !strconcat("$dst = ",
1551 !strconcat(opc , "($src1.L, $src2.H):rnd")),
1552 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1554 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1555 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1556 !strconcat("$dst = ",
1557 !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1558 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1560 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1561 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1562 !strconcat("$dst = ",
1563 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1564 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1566 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1567 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1568 !strconcat("$dst = ",
1569 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1570 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1572 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1573 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1574 !strconcat("$dst = ",
1575 !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1576 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1578 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1579 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1580 !strconcat("$dst = ",
1581 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1582 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1584 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1585 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1586 !strconcat("$dst = ",
1587 !strconcat(opc , "($src1.L, $src2.L):rnd")),
1588 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1590 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1591 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1592 !strconcat("$dst = ",
1593 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1594 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1596 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1597 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1598 DoubleRegs:$src1, DoubleRegs:$src2),
1599 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1600 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1602 DoubleRegs:$src2))],
1605 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1606 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1608 !strconcat("$dst += ",
1609 !strconcat(opc , "($src1, $src2):rnd:sat")),
1610 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1612 DoubleRegs:$src2))],
1615 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1616 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1619 !strconcat("$dst += ",
1620 !strconcat(opc , "($src1, $src2):<<1:sat")),
1621 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1623 DoubleRegs:$src2))],
1626 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1627 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1629 !strconcat("$dst += ",
1630 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1631 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1633 DoubleRegs:$src2))],
1636 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1637 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1639 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1640 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1642 DoubleRegs:$src2))],
1645 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1646 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1648 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1649 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1651 DoubleRegs:$src2))],
1654 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1655 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1657 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1658 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1662 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1663 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1665 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1666 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1670 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1671 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1673 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1674 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1678 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
1679 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1681 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1682 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1686 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
1687 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1689 !strconcat("$dst += ",
1690 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1691 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1695 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
1696 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1698 !strconcat("$dst += ",
1699 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1700 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1704 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
1705 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1707 !strconcat("$dst += ",
1708 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1709 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1713 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
1714 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1716 !strconcat("$dst += ",
1717 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1718 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1722 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
1723 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1725 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1726 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1730 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
1731 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1733 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1734 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1738 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
1739 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1741 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1742 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1746 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
1747 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1749 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1750 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1754 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
1755 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1757 !strconcat("$dst -= ",
1758 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1759 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1763 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
1764 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1766 !strconcat("$dst -= ",
1767 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1768 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1772 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
1773 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1775 !strconcat("$dst -= ",
1776 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1777 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1781 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
1782 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1784 !strconcat("$dst -= ",
1785 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1786 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1790 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
1791 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1793 !strconcat("$dst += ",
1794 !strconcat(opc , "($src1, $src2):<<1:sat")),
1795 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1799 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
1800 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1801 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1802 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1804 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
1805 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1807 !strconcat("$dst += ",
1808 !strconcat(opc , "($src1, $src2):<<1:sat")),
1809 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1814 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1815 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1816 !strconcat("$dst = ",
1817 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1818 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1820 class si_MInst_didi<string opc, Intrinsic IntID>
1821 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1822 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1823 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1826 /********************************************************************
1828 *********************************************************************/
1830 // ALU32 / ALU / Add.
1832 si_ALU32_sisi <"add", int_hexagon_A2_add>;
1833 def Hexagon_A2_addi:
1834 si_ALU32_sis16 <"add", int_hexagon_A2_addi>;
1836 // ALU32 / ALU / Logical operations.
1838 si_ALU32_sisi <"and", int_hexagon_A2_and>;
1839 def Hexagon_A2_andir:
1840 si_ALU32_sis10 <"and", int_hexagon_A2_andir>;
1842 si_ALU32_si <"not", int_hexagon_A2_not>;
1844 si_ALU32_sisi <"or", int_hexagon_A2_or>;
1845 def Hexagon_A2_orir:
1846 si_ALU32_sis10 <"or", int_hexagon_A2_orir>;
1848 si_ALU32_sisi <"xor", int_hexagon_A2_xor>;
1850 // ALU32 / ALU / Negate.
1852 si_ALU32_si <"neg", int_hexagon_A2_neg>;
1854 // ALU32 / ALU / Subtract.
1856 si_ALU32_sisi <"sub", int_hexagon_A2_sub>;
1857 def Hexagon_A2_subri:
1858 si_ALU32_s10si <"sub", int_hexagon_A2_subri>;
1860 // ALU32 / ALU / Transfer Immediate.
1861 def Hexagon_A2_tfril:
1862 si_lo_ALU32_siu16 <"", int_hexagon_A2_tfril>;
1863 def Hexagon_A2_tfrih:
1864 si_hi_ALU32_siu16 <"", int_hexagon_A2_tfrih>;
1865 def Hexagon_A2_tfrsi:
1866 si_ALU32_s16 <"", int_hexagon_A2_tfrsi>;
1867 def Hexagon_A2_tfrpi:
1868 di_ALU32_s8 <"", int_hexagon_A2_tfrpi>;
1870 // ALU32 / ALU / Transfer Register.
1872 si_ALU32_si_tfr <"", int_hexagon_A2_tfr>;
1874 /********************************************************************
1876 *********************************************************************/
1878 // ALU32 / PERM / Combine.
1879 def Hexagon_A2_combinew:
1880 di_ALU32_sisi <"combine", int_hexagon_A2_combinew>;
1881 def Hexagon_A2_combine_hh:
1882 si_MInst_sisi_hh <"combine", int_hexagon_A2_combine_hh>;
1883 def Hexagon_A2_combine_lh:
1884 si_MInst_sisi_lh <"combine", int_hexagon_A2_combine_lh>;
1885 def Hexagon_A2_combine_hl:
1886 si_MInst_sisi_hl <"combine", int_hexagon_A2_combine_hl>;
1887 def Hexagon_A2_combine_ll:
1888 si_MInst_sisi_ll <"combine", int_hexagon_A2_combine_ll>;
1889 def Hexagon_A2_combineii:
1890 di_MInst_s8s8 <"combine", int_hexagon_A2_combineii>;
1892 // ALU32 / PERM / Mux.
1894 si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
1895 def Hexagon_C2_muxri:
1896 si_ALU32_qis8si <"mux", int_hexagon_C2_muxri>;
1897 def Hexagon_C2_muxir:
1898 si_ALU32_qisis8 <"mux", int_hexagon_C2_muxir>;
1899 def Hexagon_C2_muxii:
1900 si_ALU32_qis8s8 <"mux", int_hexagon_C2_muxii>;
1902 // ALU32 / PERM / Shift halfword.
1903 def Hexagon_A2_aslh:
1904 si_ALU32_si <"aslh", int_hexagon_A2_aslh>;
1905 def Hexagon_A2_asrh:
1906 si_ALU32_si <"asrh", int_hexagon_A2_asrh>;
1907 def SI_to_SXTHI_asrh:
1908 si_ALU32_si <"asrh", int_hexagon_SI_to_SXTHI_asrh>;
1910 // ALU32 / PERM / Sign/zero extend.
1911 def Hexagon_A2_sxth:
1912 si_ALU32_si <"sxth", int_hexagon_A2_sxth>;
1913 def Hexagon_A2_sxtb:
1914 si_ALU32_si <"sxtb", int_hexagon_A2_sxtb>;
1915 def Hexagon_A2_zxth:
1916 si_ALU32_si <"zxth", int_hexagon_A2_zxth>;
1917 def Hexagon_A2_zxtb:
1918 si_ALU32_si <"zxtb", int_hexagon_A2_zxtb>;
1920 /********************************************************************
1922 *********************************************************************/
1924 // ALU32 / PRED / Compare.
1925 def Hexagon_C2_cmpeq:
1926 qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
1927 def Hexagon_C2_cmpeqi:
1928 qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
1929 def Hexagon_C2_cmpgei:
1930 qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
1931 def Hexagon_C2_cmpgeui:
1932 qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
1933 def Hexagon_C2_cmpgt:
1934 qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
1935 def Hexagon_C2_cmpgti:
1936 qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
1937 def Hexagon_C2_cmpgtu:
1938 qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
1939 def Hexagon_C2_cmpgtui:
1940 qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
1941 def Hexagon_C2_cmplt:
1942 qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
1943 def Hexagon_C2_cmpltu:
1944 qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
1946 /********************************************************************
1948 *********************************************************************/
1950 // ALU32 / VH / Vector add halfwords.
1951 // Rd32=vadd[u]h(Rs32,Rt32:sat]
1952 def Hexagon_A2_svaddh:
1953 si_ALU32_sisi <"vaddh", int_hexagon_A2_svaddh>;
1954 def Hexagon_A2_svaddhs:
1955 si_ALU32_sisi_sat <"vaddh", int_hexagon_A2_svaddhs>;
1956 def Hexagon_A2_svadduhs:
1957 si_ALU32_sisi_sat <"vadduh", int_hexagon_A2_svadduhs>;
1959 // ALU32 / VH / Vector average halfwords.
1960 def Hexagon_A2_svavgh:
1961 si_ALU32_sisi <"vavgh", int_hexagon_A2_svavgh>;
1962 def Hexagon_A2_svavghs:
1963 si_ALU32_sisi_rnd <"vavgh", int_hexagon_A2_svavghs>;
1964 def Hexagon_A2_svnavgh:
1965 si_ALU32_sisi <"vnavgh", int_hexagon_A2_svnavgh>;
1967 // ALU32 / VH / Vector subtract halfwords.
1968 def Hexagon_A2_svsubh:
1969 si_ALU32_sisi <"vsubh", int_hexagon_A2_svsubh>;
1970 def Hexagon_A2_svsubhs:
1971 si_ALU32_sisi_sat <"vsubh", int_hexagon_A2_svsubhs>;
1972 def Hexagon_A2_svsubuhs:
1973 si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
1975 /********************************************************************
1977 *********************************************************************/
1979 // ALU64 / ALU / Add.
1980 def Hexagon_A2_addp:
1981 di_ALU64_didi <"add", int_hexagon_A2_addp>;
1982 def Hexagon_A2_addsat:
1983 si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>;
1985 // ALU64 / ALU / Add halfword.
1986 // Even though the definition says hl, it should be lh -
1987 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
1988 def Hexagon_A2_addh_l16_hl:
1989 si_ALU64_sisi_l16_lh <"add", int_hexagon_A2_addh_l16_hl>;
1990 def Hexagon_A2_addh_l16_ll:
1991 si_ALU64_sisi_l16_ll <"add", int_hexagon_A2_addh_l16_ll>;
1993 def Hexagon_A2_addh_l16_sat_hl:
1994 si_ALU64_sisi_l16_sat_lh <"add", int_hexagon_A2_addh_l16_sat_hl>;
1995 def Hexagon_A2_addh_l16_sat_ll:
1996 si_ALU64_sisi_l16_sat_ll <"add", int_hexagon_A2_addh_l16_sat_ll>;
1998 def Hexagon_A2_addh_h16_hh:
1999 si_ALU64_sisi_h16_hh <"add", int_hexagon_A2_addh_h16_hh>;
2000 def Hexagon_A2_addh_h16_hl:
2001 si_ALU64_sisi_h16_hl <"add", int_hexagon_A2_addh_h16_hl>;
2002 def Hexagon_A2_addh_h16_lh:
2003 si_ALU64_sisi_h16_lh <"add", int_hexagon_A2_addh_h16_lh>;
2004 def Hexagon_A2_addh_h16_ll:
2005 si_ALU64_sisi_h16_ll <"add", int_hexagon_A2_addh_h16_ll>;
2007 def Hexagon_A2_addh_h16_sat_hh:
2008 si_ALU64_sisi_h16_sat_hh <"add", int_hexagon_A2_addh_h16_sat_hh>;
2009 def Hexagon_A2_addh_h16_sat_hl:
2010 si_ALU64_sisi_h16_sat_hl <"add", int_hexagon_A2_addh_h16_sat_hl>;
2011 def Hexagon_A2_addh_h16_sat_lh:
2012 si_ALU64_sisi_h16_sat_lh <"add", int_hexagon_A2_addh_h16_sat_lh>;
2013 def Hexagon_A2_addh_h16_sat_ll:
2014 si_ALU64_sisi_h16_sat_ll <"add", int_hexagon_A2_addh_h16_sat_ll>;
2016 // ALU64 / ALU / Compare.
2017 def Hexagon_C2_cmpeqp:
2018 qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
2019 def Hexagon_C2_cmpgtp:
2020 qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
2021 def Hexagon_C2_cmpgtup:
2022 qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
2024 // ALU64 / ALU / Logical operations.
2025 def Hexagon_A2_andp:
2026 di_ALU64_didi <"and", int_hexagon_A2_andp>;
2028 di_ALU64_didi <"or", int_hexagon_A2_orp>;
2029 def Hexagon_A2_xorp:
2030 di_ALU64_didi <"xor", int_hexagon_A2_xorp>;
2032 // ALU64 / ALU / Maximum.
2034 si_ALU64_sisi <"max", int_hexagon_A2_max>;
2035 def Hexagon_A2_maxu:
2036 si_ALU64_sisi <"maxu", int_hexagon_A2_maxu>;
2038 // ALU64 / ALU / Minimum.
2040 si_ALU64_sisi <"min", int_hexagon_A2_min>;
2041 def Hexagon_A2_minu:
2042 si_ALU64_sisi <"minu", int_hexagon_A2_minu>;
2044 // ALU64 / ALU / Subtract.
2045 def Hexagon_A2_subp:
2046 di_ALU64_didi <"sub", int_hexagon_A2_subp>;
2047 def Hexagon_A2_subsat:
2048 si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>;
2050 // ALU64 / ALU / Subtract halfword.
2051 // Even though the definition says hl, it should be lh -
2052 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2053 def Hexagon_A2_subh_l16_hl:
2054 si_ALU64_sisi_l16_lh <"sub", int_hexagon_A2_subh_l16_hl>;
2055 def Hexagon_A2_subh_l16_ll:
2056 si_ALU64_sisi_l16_ll <"sub", int_hexagon_A2_subh_l16_ll>;
2058 def Hexagon_A2_subh_l16_sat_hl:
2059 si_ALU64_sisi_l16_sat_lh <"sub", int_hexagon_A2_subh_l16_sat_hl>;
2060 def Hexagon_A2_subh_l16_sat_ll:
2061 si_ALU64_sisi_l16_sat_ll <"sub", int_hexagon_A2_subh_l16_sat_ll>;
2063 def Hexagon_A2_subh_h16_hh:
2064 si_ALU64_sisi_h16_hh <"sub", int_hexagon_A2_subh_h16_hh>;
2065 def Hexagon_A2_subh_h16_hl:
2066 si_ALU64_sisi_h16_hl <"sub", int_hexagon_A2_subh_h16_hl>;
2067 def Hexagon_A2_subh_h16_lh:
2068 si_ALU64_sisi_h16_lh <"sub", int_hexagon_A2_subh_h16_lh>;
2069 def Hexagon_A2_subh_h16_ll:
2070 si_ALU64_sisi_h16_ll <"sub", int_hexagon_A2_subh_h16_ll>;
2072 def Hexagon_A2_subh_h16_sat_hh:
2073 si_ALU64_sisi_h16_sat_hh <"sub", int_hexagon_A2_subh_h16_sat_hh>;
2074 def Hexagon_A2_subh_h16_sat_hl:
2075 si_ALU64_sisi_h16_sat_hl <"sub", int_hexagon_A2_subh_h16_sat_hl>;
2076 def Hexagon_A2_subh_h16_sat_lh:
2077 si_ALU64_sisi_h16_sat_lh <"sub", int_hexagon_A2_subh_h16_sat_lh>;
2078 def Hexagon_A2_subh_h16_sat_ll:
2079 si_ALU64_sisi_h16_sat_ll <"sub", int_hexagon_A2_subh_h16_sat_ll>;
2081 // ALU64 / ALU / Transfer register.
2082 def Hexagon_A2_tfrp:
2083 di_ALU64_di <"", int_hexagon_A2_tfrp>;
2085 /********************************************************************
2087 *********************************************************************/
2089 // ALU64 / BIT / Masked parity.
2090 def Hexagon_S2_parityp:
2091 si_ALU64_didi <"parity", int_hexagon_S2_parityp>;
2093 /********************************************************************
2095 *********************************************************************/
2097 // ALU64 / PERM / Vector pack high and low halfwords.
2098 def Hexagon_S2_packhl:
2099 di_ALU64_sisi <"packhl", int_hexagon_S2_packhl>;
2101 /********************************************************************
2103 *********************************************************************/
2105 // ALU64 / VB / Vector add unsigned bytes.
2106 def Hexagon_A2_vaddub:
2107 di_ALU64_didi <"vaddub", int_hexagon_A2_vaddub>;
2108 def Hexagon_A2_vaddubs:
2109 di_ALU64_didi_sat <"vaddub", int_hexagon_A2_vaddubs>;
2111 // ALU64 / VB / Vector average unsigned bytes.
2112 def Hexagon_A2_vavgub:
2113 di_ALU64_didi <"vavgub", int_hexagon_A2_vavgub>;
2114 def Hexagon_A2_vavgubr:
2115 di_ALU64_didi_rnd <"vavgub", int_hexagon_A2_vavgubr>;
2117 // ALU64 / VB / Vector compare unsigned bytes.
2118 def Hexagon_A2_vcmpbeq:
2119 qi_ALU64_didi <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2120 def Hexagon_A2_vcmpbgtu:
2121 qi_ALU64_didi <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2123 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2124 def Hexagon_A2_vmaxub:
2125 di_ALU64_didi <"vmaxub", int_hexagon_A2_vmaxub>;
2126 def Hexagon_A2_vminub:
2127 di_ALU64_didi <"vminub", int_hexagon_A2_vminub>;
2129 // ALU64 / VB / Vector subtract unsigned bytes.
2130 def Hexagon_A2_vsubub:
2131 di_ALU64_didi <"vsubub", int_hexagon_A2_vsubub>;
2132 def Hexagon_A2_vsububs:
2133 di_ALU64_didi_sat <"vsubub", int_hexagon_A2_vsububs>;
2135 // ALU64 / VB / Vector mux.
2136 def Hexagon_C2_vmux:
2137 di_ALU64_qididi <"vmux", int_hexagon_C2_vmux>;
2140 /********************************************************************
2142 *********************************************************************/
2144 // ALU64 / VH / Vector add halfwords.
2145 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2146 def Hexagon_A2_vaddh:
2147 di_ALU64_didi <"vaddh", int_hexagon_A2_vaddh>;
2148 def Hexagon_A2_vaddhs:
2149 di_ALU64_didi_sat <"vaddh", int_hexagon_A2_vaddhs>;
2150 def Hexagon_A2_vadduhs:
2151 di_ALU64_didi_sat <"vadduh", int_hexagon_A2_vadduhs>;
2153 // ALU64 / VH / Vector average halfwords.
2154 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2155 def Hexagon_A2_vavgh:
2156 di_ALU64_didi <"vavgh", int_hexagon_A2_vavgh>;
2157 def Hexagon_A2_vavghcr:
2158 di_ALU64_didi_crnd <"vavgh", int_hexagon_A2_vavghcr>;
2159 def Hexagon_A2_vavghr:
2160 di_ALU64_didi_rnd <"vavgh", int_hexagon_A2_vavghr>;
2161 def Hexagon_A2_vavguh:
2162 di_ALU64_didi <"vavguh", int_hexagon_A2_vavguh>;
2163 def Hexagon_A2_vavguhr:
2164 di_ALU64_didi_rnd <"vavguh", int_hexagon_A2_vavguhr>;
2165 def Hexagon_A2_vnavgh:
2166 di_ALU64_didi <"vnavgh", int_hexagon_A2_vnavgh>;
2167 def Hexagon_A2_vnavghcr:
2168 di_ALU64_didi_crnd_sat <"vnavgh", int_hexagon_A2_vnavghcr>;
2169 def Hexagon_A2_vnavghr:
2170 di_ALU64_didi_rnd_sat <"vnavgh", int_hexagon_A2_vnavghr>;
2172 // ALU64 / VH / Vector compare halfwords.
2173 def Hexagon_A2_vcmpheq:
2174 qi_ALU64_didi <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2175 def Hexagon_A2_vcmphgt:
2176 qi_ALU64_didi <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2177 def Hexagon_A2_vcmphgtu:
2178 qi_ALU64_didi <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2180 // ALU64 / VH / Vector maximum halfwords.
2181 def Hexagon_A2_vmaxh:
2182 di_ALU64_didi <"vmaxh", int_hexagon_A2_vmaxh>;
2183 def Hexagon_A2_vmaxuh:
2184 di_ALU64_didi <"vmaxuh", int_hexagon_A2_vmaxuh>;
2186 // ALU64 / VH / Vector minimum halfwords.
2187 def Hexagon_A2_vminh:
2188 di_ALU64_didi <"vminh", int_hexagon_A2_vminh>;
2189 def Hexagon_A2_vminuh:
2190 di_ALU64_didi <"vminuh", int_hexagon_A2_vminuh>;
2192 // ALU64 / VH / Vector subtract halfwords.
2193 def Hexagon_A2_vsubh:
2194 di_ALU64_didi <"vsubh", int_hexagon_A2_vsubh>;
2195 def Hexagon_A2_vsubhs:
2196 di_ALU64_didi_sat <"vsubh", int_hexagon_A2_vsubhs>;
2197 def Hexagon_A2_vsubuhs:
2198 di_ALU64_didi_sat <"vsubuh", int_hexagon_A2_vsubuhs>;
2201 /********************************************************************
2203 *********************************************************************/
2205 // ALU64 / VW / Vector add words.
2206 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2207 def Hexagon_A2_vaddw:
2208 di_ALU64_didi <"vaddw", int_hexagon_A2_vaddw>;
2209 def Hexagon_A2_vaddws:
2210 di_ALU64_didi_sat <"vaddw", int_hexagon_A2_vaddws>;
2212 // ALU64 / VW / Vector average words.
2213 def Hexagon_A2_vavguw:
2214 di_ALU64_didi <"vavguw", int_hexagon_A2_vavguw>;
2215 def Hexagon_A2_vavguwr:
2216 di_ALU64_didi_rnd <"vavguw", int_hexagon_A2_vavguwr>;
2217 def Hexagon_A2_vavgw:
2218 di_ALU64_didi <"vavgw", int_hexagon_A2_vavgw>;
2219 def Hexagon_A2_vavgwcr:
2220 di_ALU64_didi_crnd <"vavgw", int_hexagon_A2_vavgwcr>;
2221 def Hexagon_A2_vavgwr:
2222 di_ALU64_didi_rnd <"vavgw", int_hexagon_A2_vavgwr>;
2223 def Hexagon_A2_vnavgw:
2224 di_ALU64_didi <"vnavgw", int_hexagon_A2_vnavgw>;
2225 def Hexagon_A2_vnavgwcr:
2226 di_ALU64_didi_crnd_sat <"vnavgw", int_hexagon_A2_vnavgwcr>;
2227 def Hexagon_A2_vnavgwr:
2228 di_ALU64_didi_rnd_sat <"vnavgw", int_hexagon_A2_vnavgwr>;
2230 // ALU64 / VW / Vector compare words.
2231 def Hexagon_A2_vcmpweq:
2232 qi_ALU64_didi <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2233 def Hexagon_A2_vcmpwgt:
2234 qi_ALU64_didi <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2235 def Hexagon_A2_vcmpwgtu:
2236 qi_ALU64_didi <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2238 // ALU64 / VW / Vector maximum words.
2239 def Hexagon_A2_vmaxw:
2240 di_ALU64_didi <"vmaxw", int_hexagon_A2_vmaxw>;
2241 def Hexagon_A2_vmaxuw:
2242 di_ALU64_didi <"vmaxuw", int_hexagon_A2_vmaxuw>;
2244 // ALU64 / VW / Vector minimum words.
2245 def Hexagon_A2_vminw:
2246 di_ALU64_didi <"vminw", int_hexagon_A2_vminw>;
2247 def Hexagon_A2_vminuw:
2248 di_ALU64_didi <"vminuw", int_hexagon_A2_vminuw>;
2250 // ALU64 / VW / Vector subtract words.
2251 def Hexagon_A2_vsubw:
2252 di_ALU64_didi <"vsubw", int_hexagon_A2_vsubw>;
2253 def Hexagon_A2_vsubws:
2254 di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
2257 /********************************************************************
2259 *********************************************************************/
2261 // CR / Logical reductions on predicates.
2262 def Hexagon_C2_all8:
2263 qi_SInst_qi <"all8", int_hexagon_C2_all8>;
2264 def Hexagon_C2_any8:
2265 qi_SInst_qi <"any8", int_hexagon_C2_any8>;
2267 // CR / Logical operations on predicates.
2268 def Hexagon_C2_pxfer_map:
2269 qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
2271 qi_SInst_qiqi <"and", int_hexagon_C2_and>;
2272 def Hexagon_C2_andn:
2273 qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
2275 qi_SInst_qi <"not", int_hexagon_C2_not>;
2277 qi_SInst_qiqi <"or", int_hexagon_C2_or>;
2279 qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
2281 qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
2284 /********************************************************************
2286 *********************************************************************/
2288 // MTYPE / ALU / Add and accumulate.
2289 def Hexagon_M2_acci:
2290 si_MInst_sisisi_acc <"add", int_hexagon_M2_acci>;
2291 def Hexagon_M2_accii:
2292 si_MInst_sisis8_acc <"add", int_hexagon_M2_accii>;
2293 def Hexagon_M2_nacci:
2294 si_MInst_sisisi_nac <"add", int_hexagon_M2_nacci>;
2295 def Hexagon_M2_naccii:
2296 si_MInst_sisis8_nac <"add", int_hexagon_M2_naccii>;
2298 // MTYPE / ALU / Subtract and accumulate.
2299 def Hexagon_M2_subacc:
2300 si_MInst_sisisi_acc <"sub", int_hexagon_M2_subacc>;
2302 // MTYPE / ALU / Vector absolute difference.
2303 def Hexagon_M2_vabsdiffh:
2304 di_MInst_didi <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2305 def Hexagon_M2_vabsdiffw:
2306 di_MInst_didi <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2308 // MTYPE / ALU / XOR and xor with destination.
2309 def Hexagon_M2_xor_xacc:
2310 si_MInst_sisisi_xacc <"xor", int_hexagon_M2_xor_xacc>;
2313 /********************************************************************
2315 *********************************************************************/
2317 // MTYPE / COMPLEX / Complex multiply.
2318 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2319 def Hexagon_M2_cmpys_s1:
2320 di_MInst_sisi_s1_sat <"cmpy", int_hexagon_M2_cmpys_s1>;
2321 def Hexagon_M2_cmpys_s0:
2322 di_MInst_sisi_sat <"cmpy", int_hexagon_M2_cmpys_s0>;
2323 def Hexagon_M2_cmpysc_s1:
2324 di_MInst_sisi_s1_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s1>;
2325 def Hexagon_M2_cmpysc_s0:
2326 di_MInst_sisi_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s0>;
2328 def Hexagon_M2_cmacs_s1:
2329 di_MInst_disisi_acc_s1_sat <"cmpy", int_hexagon_M2_cmacs_s1>;
2330 def Hexagon_M2_cmacs_s0:
2331 di_MInst_disisi_acc_sat <"cmpy", int_hexagon_M2_cmacs_s0>;
2332 def Hexagon_M2_cmacsc_s1:
2333 di_MInst_disisi_acc_s1_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s1>;
2334 def Hexagon_M2_cmacsc_s0:
2335 di_MInst_disisi_acc_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s0>;
2337 def Hexagon_M2_cnacs_s1:
2338 di_MInst_disisi_nac_s1_sat <"cmpy", int_hexagon_M2_cnacs_s1>;
2339 def Hexagon_M2_cnacs_s0:
2340 di_MInst_disisi_nac_sat <"cmpy", int_hexagon_M2_cnacs_s0>;
2341 def Hexagon_M2_cnacsc_s1:
2342 di_MInst_disisi_nac_s1_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s1>;
2343 def Hexagon_M2_cnacsc_s0:
2344 di_MInst_disisi_nac_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s0>;
2346 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2347 def Hexagon_M2_cmpyr_s0:
2348 di_MInst_sisi <"cmpyr", int_hexagon_M2_cmpyr_s0>;
2349 def Hexagon_M2_cmacr_s0:
2350 di_MInst_disisi_acc <"cmpyr", int_hexagon_M2_cmacr_s0>;
2352 def Hexagon_M2_cmpyi_s0:
2353 di_MInst_sisi <"cmpyi", int_hexagon_M2_cmpyi_s0>;
2354 def Hexagon_M2_cmaci_s0:
2355 di_MInst_disisi_acc <"cmpyi", int_hexagon_M2_cmaci_s0>;
2357 // MTYPE / COMPLEX / Complex multiply with round and pack.
2358 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2359 def Hexagon_M2_cmpyrs_s0:
2360 si_MInst_sisi_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s0>;
2361 def Hexagon_M2_cmpyrs_s1:
2362 si_MInst_sisi_s1_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s1>;
2364 def Hexagon_M2_cmpyrsc_s0:
2365 si_MInst_sisi_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s0>;
2366 def Hexagon_M2_cmpyrsc_s1:
2367 si_MInst_sisi_s1_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s1>;
2369 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2370 def Hexagon_M2_vcmpy_s0_sat_i:
2371 di_MInst_didi_sat <"vcmpyi", int_hexagon_M2_vcmpy_s0_sat_i>;
2372 def Hexagon_M2_vcmpy_s1_sat_i:
2373 di_MInst_didi_s1_sat <"vcmpyi", int_hexagon_M2_vcmpy_s1_sat_i>;
2375 def Hexagon_M2_vcmpy_s0_sat_r:
2376 di_MInst_didi_sat <"vcmpyr", int_hexagon_M2_vcmpy_s0_sat_r>;
2377 def Hexagon_M2_vcmpy_s1_sat_r:
2378 di_MInst_didi_s1_sat <"vcmpyr", int_hexagon_M2_vcmpy_s1_sat_r>;
2380 def Hexagon_M2_vcmac_s0_sat_i:
2381 di_MInst_dididi_acc_sat <"vcmpyi", int_hexagon_M2_vcmac_s0_sat_i>;
2382 def Hexagon_M2_vcmac_s0_sat_r:
2383 di_MInst_dididi_acc_sat <"vcmpyr", int_hexagon_M2_vcmac_s0_sat_r>;
2385 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2386 def Hexagon_M2_vrcmpyi_s0:
2387 di_MInst_didi <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0>;
2388 def Hexagon_M2_vrcmpyr_s0:
2389 di_MInst_didi <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0>;
2391 def Hexagon_M2_vrcmpyi_s0c:
2392 di_MInst_didi_conj <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0c>;
2393 def Hexagon_M2_vrcmpyr_s0c:
2394 di_MInst_didi_conj <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0c>;
2396 def Hexagon_M2_vrcmaci_s0:
2397 di_MInst_dididi_acc <"vrcmpyi", int_hexagon_M2_vrcmaci_s0>;
2398 def Hexagon_M2_vrcmacr_s0:
2399 di_MInst_dididi_acc <"vrcmpyr", int_hexagon_M2_vrcmacr_s0>;
2401 def Hexagon_M2_vrcmaci_s0c:
2402 di_MInst_dididi_acc_conj <"vrcmpyi", int_hexagon_M2_vrcmaci_s0c>;
2403 def Hexagon_M2_vrcmacr_s0c:
2404 di_MInst_dididi_acc_conj <"vrcmpyr", int_hexagon_M2_vrcmacr_s0c>;
2407 /********************************************************************
2409 *********************************************************************/
2411 // MTYPE / MPYH / Multiply and use lower result.
2412 //def Hexagon_M2_mpysmi:
2413 // si_MInst_sim9 <"mpyi", int_hexagon_M2_mpysmi>;
2414 def Hexagon_M2_mpyi:
2415 si_MInst_sisi <"mpyi", int_hexagon_M2_mpyi>;
2416 def Hexagon_M2_mpyui:
2417 si_MInst_sisi <"mpyui", int_hexagon_M2_mpyui>;
2418 def Hexagon_M2_macsip:
2419 si_MInst_sisiu8_acc <"mpyi", int_hexagon_M2_macsip>;
2420 def Hexagon_M2_maci:
2421 si_MInst_sisisi_acc <"mpyi", int_hexagon_M2_maci>;
2422 def Hexagon_M2_macsin:
2423 si_MInst_sisiu8_nac <"mpyi", int_hexagon_M2_macsin>;
2425 // MTYPE / MPYH / Multiply word by half (32x16).
2426 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2427 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2428 def Hexagon_M2_mmpyl_rs1:
2429 di_MInst_didi_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs1>;
2430 def Hexagon_M2_mmpyl_s1:
2431 di_MInst_didi_s1_sat <"vmpyweh", int_hexagon_M2_mmpyl_s1>;
2432 def Hexagon_M2_mmpyl_rs0:
2433 di_MInst_didi_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs0>;
2434 def Hexagon_M2_mmpyl_s0:
2435 di_MInst_didi_sat <"vmpyweh", int_hexagon_M2_mmpyl_s0>;
2436 def Hexagon_M2_mmpyh_rs1:
2437 di_MInst_didi_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs1>;
2438 def Hexagon_M2_mmpyh_s1:
2439 di_MInst_didi_s1_sat <"vmpywoh", int_hexagon_M2_mmpyh_s1>;
2440 def Hexagon_M2_mmpyh_rs0:
2441 di_MInst_didi_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs0>;
2442 def Hexagon_M2_mmpyh_s0:
2443 di_MInst_didi_sat <"vmpywoh", int_hexagon_M2_mmpyh_s0>;
2444 def Hexagon_M2_mmacls_rs1:
2445 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs1>;
2446 def Hexagon_M2_mmacls_s1:
2447 di_MInst_dididi_acc_s1_sat <"vmpyweh", int_hexagon_M2_mmacls_s1>;
2448 def Hexagon_M2_mmacls_rs0:
2449 di_MInst_dididi_acc_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs0>;
2450 def Hexagon_M2_mmacls_s0:
2451 di_MInst_dididi_acc_sat <"vmpyweh", int_hexagon_M2_mmacls_s0>;
2452 def Hexagon_M2_mmachs_rs1:
2453 di_MInst_dididi_acc_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs1>;
2454 def Hexagon_M2_mmachs_s1:
2455 di_MInst_dididi_acc_s1_sat <"vmpywoh", int_hexagon_M2_mmachs_s1>;
2456 def Hexagon_M2_mmachs_rs0:
2457 di_MInst_dididi_acc_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs0>;
2458 def Hexagon_M2_mmachs_s0:
2459 di_MInst_dididi_acc_sat <"vmpywoh", int_hexagon_M2_mmachs_s0>;
2461 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2462 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2463 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2464 def Hexagon_M2_mmpyul_rs1:
2465 di_MInst_didi_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2466 def Hexagon_M2_mmpyul_s1:
2467 di_MInst_didi_s1_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2468 def Hexagon_M2_mmpyul_rs0:
2469 di_MInst_didi_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2470 def Hexagon_M2_mmpyul_s0:
2471 di_MInst_didi_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2472 def Hexagon_M2_mmpyuh_rs1:
2473 di_MInst_didi_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2474 def Hexagon_M2_mmpyuh_s1:
2475 di_MInst_didi_s1_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2476 def Hexagon_M2_mmpyuh_rs0:
2477 di_MInst_didi_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2478 def Hexagon_M2_mmpyuh_s0:
2479 di_MInst_didi_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2480 def Hexagon_M2_mmaculs_rs1:
2481 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2482 def Hexagon_M2_mmaculs_s1:
2483 di_MInst_dididi_acc_s1_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2484 def Hexagon_M2_mmaculs_rs0:
2485 di_MInst_dididi_acc_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2486 def Hexagon_M2_mmaculs_s0:
2487 di_MInst_dididi_acc_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2488 def Hexagon_M2_mmacuhs_rs1:
2489 di_MInst_dididi_acc_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2490 def Hexagon_M2_mmacuhs_s1:
2491 di_MInst_dididi_acc_s1_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2492 def Hexagon_M2_mmacuhs_rs0:
2493 di_MInst_dididi_acc_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2494 def Hexagon_M2_mmacuhs_s0:
2495 di_MInst_dididi_acc_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2497 // MTYPE / MPYH / Multiply and use upper result.
2498 def Hexagon_M2_hmmpyh_rs1:
2499 si_MInst_sisi_h_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyh_rs1>;
2500 def Hexagon_M2_hmmpyl_rs1:
2501 si_MInst_sisi_l_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyl_rs1>;
2502 def Hexagon_M2_mpy_up:
2503 si_MInst_sisi <"mpy", int_hexagon_M2_mpy_up>;
2504 def Hexagon_M2_dpmpyss_rnd_s0:
2505 si_MInst_sisi_rnd <"mpy", int_hexagon_M2_dpmpyss_rnd_s0>;
2506 def Hexagon_M2_mpyu_up:
2507 si_MInst_sisi <"mpyu", int_hexagon_M2_mpyu_up>;
2509 // MTYPE / MPYH / Multiply and use full result.
2510 def Hexagon_M2_dpmpyuu_s0:
2511 di_MInst_sisi <"mpyu", int_hexagon_M2_dpmpyuu_s0>;
2512 def Hexagon_M2_dpmpyuu_acc_s0:
2513 di_MInst_disisi_acc <"mpyu", int_hexagon_M2_dpmpyuu_acc_s0>;
2514 def Hexagon_M2_dpmpyuu_nac_s0:
2515 di_MInst_disisi_nac <"mpyu", int_hexagon_M2_dpmpyuu_nac_s0>;
2516 def Hexagon_M2_dpmpyss_s0:
2517 di_MInst_sisi <"mpy", int_hexagon_M2_dpmpyss_s0>;
2518 def Hexagon_M2_dpmpyss_acc_s0:
2519 di_MInst_disisi_acc <"mpy", int_hexagon_M2_dpmpyss_acc_s0>;
2520 def Hexagon_M2_dpmpyss_nac_s0:
2521 di_MInst_disisi_nac <"mpy", int_hexagon_M2_dpmpyss_nac_s0>;
2524 /********************************************************************
2526 *********************************************************************/
2528 // MTYPE / MPYS / Scalar 16x16 multiply signed.
2529 //Rd=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]|
2530 // [:<<0[:rnd|:sat|:rnd:sat]|:<<1[:rnd|:sat|:rnd:sat]]]
2531 def Hexagon_M2_mpy_hh_s0:
2532 si_MInst_sisi_hh <"mpy", int_hexagon_M2_mpy_hh_s0>;
2533 def Hexagon_M2_mpy_hh_s1:
2534 si_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpy_hh_s1>;
2535 def Hexagon_M2_mpy_rnd_hh_s1:
2536 si_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_rnd_hh_s1>;
2537 def Hexagon_M2_mpy_sat_rnd_hh_s1:
2538 si_MInst_sisi_sat_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s1>;
2539 def Hexagon_M2_mpy_sat_hh_s1:
2540 si_MInst_sisi_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_hh_s1>;
2541 def Hexagon_M2_mpy_rnd_hh_s0:
2542 si_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpy_rnd_hh_s0>;
2543 def Hexagon_M2_mpy_sat_rnd_hh_s0:
2544 si_MInst_sisi_sat_rnd_hh <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s0>;
2545 def Hexagon_M2_mpy_sat_hh_s0:
2546 si_MInst_sisi_sat_hh <"mpy", int_hexagon_M2_mpy_sat_hh_s0>;
2548 def Hexagon_M2_mpy_hl_s0:
2549 si_MInst_sisi_hl <"mpy", int_hexagon_M2_mpy_hl_s0>;
2550 def Hexagon_M2_mpy_hl_s1:
2551 si_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpy_hl_s1>;
2552 def Hexagon_M2_mpy_rnd_hl_s1:
2553 si_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_rnd_hl_s1>;
2554 def Hexagon_M2_mpy_sat_rnd_hl_s1:
2555 si_MInst_sisi_sat_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s1>;
2556 def Hexagon_M2_mpy_sat_hl_s1:
2557 si_MInst_sisi_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_hl_s1>;
2558 def Hexagon_M2_mpy_rnd_hl_s0:
2559 si_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpy_rnd_hl_s0>;
2560 def Hexagon_M2_mpy_sat_rnd_hl_s0:
2561 si_MInst_sisi_sat_rnd_hl <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s0>;
2562 def Hexagon_M2_mpy_sat_hl_s0:
2563 si_MInst_sisi_sat_hl <"mpy", int_hexagon_M2_mpy_sat_hl_s0>;
2565 def Hexagon_M2_mpy_lh_s0:
2566 si_MInst_sisi_lh <"mpy", int_hexagon_M2_mpy_lh_s0>;
2567 def Hexagon_M2_mpy_lh_s1:
2568 si_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpy_lh_s1>;
2569 def Hexagon_M2_mpy_rnd_lh_s1:
2570 si_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_rnd_lh_s1>;
2571 def Hexagon_M2_mpy_sat_rnd_lh_s1:
2572 si_MInst_sisi_sat_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s1>;
2573 def Hexagon_M2_mpy_sat_lh_s1:
2574 si_MInst_sisi_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_lh_s1>;
2575 def Hexagon_M2_mpy_rnd_lh_s0:
2576 si_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpy_rnd_lh_s0>;
2577 def Hexagon_M2_mpy_sat_rnd_lh_s0:
2578 si_MInst_sisi_sat_rnd_lh <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s0>;
2579 def Hexagon_M2_mpy_sat_lh_s0:
2580 si_MInst_sisi_sat_lh <"mpy", int_hexagon_M2_mpy_sat_lh_s0>;
2582 def Hexagon_M2_mpy_ll_s0:
2583 si_MInst_sisi_ll <"mpy", int_hexagon_M2_mpy_ll_s0>;
2584 def Hexagon_M2_mpy_ll_s1:
2585 si_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpy_ll_s1>;
2586 def Hexagon_M2_mpy_rnd_ll_s1:
2587 si_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_rnd_ll_s1>;
2588 def Hexagon_M2_mpy_sat_rnd_ll_s1:
2589 si_MInst_sisi_sat_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s1>;
2590 def Hexagon_M2_mpy_sat_ll_s1:
2591 si_MInst_sisi_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_ll_s1>;
2592 def Hexagon_M2_mpy_rnd_ll_s0:
2593 si_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpy_rnd_ll_s0>;
2594 def Hexagon_M2_mpy_sat_rnd_ll_s0:
2595 si_MInst_sisi_sat_rnd_ll <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s0>;
2596 def Hexagon_M2_mpy_sat_ll_s0:
2597 si_MInst_sisi_sat_ll <"mpy", int_hexagon_M2_mpy_sat_ll_s0>;
2599 //Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]]
2600 def Hexagon_M2_mpyd_hh_s0:
2601 di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>;
2602 def Hexagon_M2_mpyd_hh_s1:
2603 di_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpyd_hh_s1>;
2604 def Hexagon_M2_mpyd_rnd_hh_s1:
2605 di_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hh_s1>;
2606 def Hexagon_M2_mpyd_rnd_hh_s0:
2607 di_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpyd_rnd_hh_s0>;
2609 def Hexagon_M2_mpyd_hl_s0:
2610 di_MInst_sisi_hl <"mpy", int_hexagon_M2_mpyd_hl_s0>;
2611 def Hexagon_M2_mpyd_hl_s1:
2612 di_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpyd_hl_s1>;
2613 def Hexagon_M2_mpyd_rnd_hl_s1:
2614 di_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hl_s1>;
2615 def Hexagon_M2_mpyd_rnd_hl_s0:
2616 di_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpyd_rnd_hl_s0>;
2618 def Hexagon_M2_mpyd_lh_s0:
2619 di_MInst_sisi_lh <"mpy", int_hexagon_M2_mpyd_lh_s0>;
2620 def Hexagon_M2_mpyd_lh_s1:
2621 di_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpyd_lh_s1>;
2622 def Hexagon_M2_mpyd_rnd_lh_s1:
2623 di_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_lh_s1>;
2624 def Hexagon_M2_mpyd_rnd_lh_s0:
2625 di_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpyd_rnd_lh_s0>;
2627 def Hexagon_M2_mpyd_ll_s0:
2628 di_MInst_sisi_ll <"mpy", int_hexagon_M2_mpyd_ll_s0>;
2629 def Hexagon_M2_mpyd_ll_s1:
2630 di_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpyd_ll_s1>;
2631 def Hexagon_M2_mpyd_rnd_ll_s1:
2632 di_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpyd_rnd_ll_s1>;
2633 def Hexagon_M2_mpyd_rnd_ll_s0:
2634 di_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpyd_rnd_ll_s0>;
2636 //Rx+=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2637 def Hexagon_M2_mpy_acc_hh_s0:
2638 si_MInst_sisisi_acc_hh <"mpy", int_hexagon_M2_mpy_acc_hh_s0>;
2639 def Hexagon_M2_mpy_acc_hh_s1:
2640 si_MInst_sisisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_hh_s1>;
2641 def Hexagon_M2_mpy_acc_sat_hh_s1:
2642 si_MInst_sisisi_acc_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s1>;
2643 def Hexagon_M2_mpy_acc_sat_hh_s0:
2644 si_MInst_sisisi_acc_sat_hh <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s0>;
2646 def Hexagon_M2_mpy_acc_hl_s0:
2647 si_MInst_sisisi_acc_hl <"mpy", int_hexagon_M2_mpy_acc_hl_s0>;
2648 def Hexagon_M2_mpy_acc_hl_s1:
2649 si_MInst_sisisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_hl_s1>;
2650 def Hexagon_M2_mpy_acc_sat_hl_s1:
2651 si_MInst_sisisi_acc_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s1>;
2652 def Hexagon_M2_mpy_acc_sat_hl_s0:
2653 si_MInst_sisisi_acc_sat_hl <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s0>;
2655 def Hexagon_M2_mpy_acc_lh_s0:
2656 si_MInst_sisisi_acc_lh <"mpy", int_hexagon_M2_mpy_acc_lh_s0>;
2657 def Hexagon_M2_mpy_acc_lh_s1:
2658 si_MInst_sisisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_lh_s1>;
2659 def Hexagon_M2_mpy_acc_sat_lh_s1:
2660 si_MInst_sisisi_acc_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s1>;
2661 def Hexagon_M2_mpy_acc_sat_lh_s0:
2662 si_MInst_sisisi_acc_sat_lh <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s0>;
2664 def Hexagon_M2_mpy_acc_ll_s0:
2665 si_MInst_sisisi_acc_ll <"mpy", int_hexagon_M2_mpy_acc_ll_s0>;
2666 def Hexagon_M2_mpy_acc_ll_s1:
2667 si_MInst_sisisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_ll_s1>;
2668 def Hexagon_M2_mpy_acc_sat_ll_s1:
2669 si_MInst_sisisi_acc_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s1>;
2670 def Hexagon_M2_mpy_acc_sat_ll_s0:
2671 si_MInst_sisisi_acc_sat_ll <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s0>;
2673 //Rx-=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2674 def Hexagon_M2_mpy_nac_hh_s0:
2675 si_MInst_sisisi_nac_hh <"mpy", int_hexagon_M2_mpy_nac_hh_s0>;
2676 def Hexagon_M2_mpy_nac_hh_s1:
2677 si_MInst_sisisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_hh_s1>;
2678 def Hexagon_M2_mpy_nac_sat_hh_s1:
2679 si_MInst_sisisi_nac_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s1>;
2680 def Hexagon_M2_mpy_nac_sat_hh_s0:
2681 si_MInst_sisisi_nac_sat_hh <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s0>;
2683 def Hexagon_M2_mpy_nac_hl_s0:
2684 si_MInst_sisisi_nac_hl <"mpy", int_hexagon_M2_mpy_nac_hl_s0>;
2685 def Hexagon_M2_mpy_nac_hl_s1:
2686 si_MInst_sisisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_hl_s1>;
2687 def Hexagon_M2_mpy_nac_sat_hl_s1:
2688 si_MInst_sisisi_nac_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s1>;
2689 def Hexagon_M2_mpy_nac_sat_hl_s0:
2690 si_MInst_sisisi_nac_sat_hl <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s0>;
2692 def Hexagon_M2_mpy_nac_lh_s0:
2693 si_MInst_sisisi_nac_lh <"mpy", int_hexagon_M2_mpy_nac_lh_s0>;
2694 def Hexagon_M2_mpy_nac_lh_s1:
2695 si_MInst_sisisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_lh_s1>;
2696 def Hexagon_M2_mpy_nac_sat_lh_s1:
2697 si_MInst_sisisi_nac_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s1>;
2698 def Hexagon_M2_mpy_nac_sat_lh_s0:
2699 si_MInst_sisisi_nac_sat_lh <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s0>;
2701 def Hexagon_M2_mpy_nac_ll_s0:
2702 si_MInst_sisisi_nac_ll <"mpy", int_hexagon_M2_mpy_nac_ll_s0>;
2703 def Hexagon_M2_mpy_nac_ll_s1:
2704 si_MInst_sisisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_ll_s1>;
2705 def Hexagon_M2_mpy_nac_sat_ll_s1:
2706 si_MInst_sisisi_nac_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s1>;
2707 def Hexagon_M2_mpy_nac_sat_ll_s0:
2708 si_MInst_sisisi_nac_sat_ll <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s0>;
2710 //Rx+=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2711 def Hexagon_M2_mpyd_acc_hh_s0:
2712 di_MInst_disisi_acc_hh <"mpy", int_hexagon_M2_mpyd_acc_hh_s0>;
2713 def Hexagon_M2_mpyd_acc_hh_s1:
2714 di_MInst_disisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpyd_acc_hh_s1>;
2716 def Hexagon_M2_mpyd_acc_hl_s0:
2717 di_MInst_disisi_acc_hl <"mpy", int_hexagon_M2_mpyd_acc_hl_s0>;
2718 def Hexagon_M2_mpyd_acc_hl_s1:
2719 di_MInst_disisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpyd_acc_hl_s1>;
2721 def Hexagon_M2_mpyd_acc_lh_s0:
2722 di_MInst_disisi_acc_lh <"mpy", int_hexagon_M2_mpyd_acc_lh_s0>;
2723 def Hexagon_M2_mpyd_acc_lh_s1:
2724 di_MInst_disisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpyd_acc_lh_s1>;
2726 def Hexagon_M2_mpyd_acc_ll_s0:
2727 di_MInst_disisi_acc_ll <"mpy", int_hexagon_M2_mpyd_acc_ll_s0>;
2728 def Hexagon_M2_mpyd_acc_ll_s1:
2729 di_MInst_disisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpyd_acc_ll_s1>;
2731 //Rx-=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2732 def Hexagon_M2_mpyd_nac_hh_s0:
2733 di_MInst_disisi_nac_hh <"mpy", int_hexagon_M2_mpyd_nac_hh_s0>;
2734 def Hexagon_M2_mpyd_nac_hh_s1:
2735 di_MInst_disisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpyd_nac_hh_s1>;
2737 def Hexagon_M2_mpyd_nac_hl_s0:
2738 di_MInst_disisi_nac_hl <"mpy", int_hexagon_M2_mpyd_nac_hl_s0>;
2739 def Hexagon_M2_mpyd_nac_hl_s1:
2740 di_MInst_disisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpyd_nac_hl_s1>;
2742 def Hexagon_M2_mpyd_nac_lh_s0:
2743 di_MInst_disisi_nac_lh <"mpy", int_hexagon_M2_mpyd_nac_lh_s0>;
2744 def Hexagon_M2_mpyd_nac_lh_s1:
2745 di_MInst_disisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpyd_nac_lh_s1>;
2747 def Hexagon_M2_mpyd_nac_ll_s0:
2748 di_MInst_disisi_nac_ll <"mpy", int_hexagon_M2_mpyd_nac_ll_s0>;
2749 def Hexagon_M2_mpyd_nac_ll_s1:
2750 di_MInst_disisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpyd_nac_ll_s1>;
2752 // MTYPE / MPYS / Scalar 16x16 multiply unsigned.
2753 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2754 def Hexagon_M2_mpyu_hh_s0:
2755 si_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyu_hh_s0>;
2756 def Hexagon_M2_mpyu_hh_s1:
2757 si_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyu_hh_s1>;
2758 def Hexagon_M2_mpyu_hl_s0:
2759 si_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyu_hl_s0>;
2760 def Hexagon_M2_mpyu_hl_s1:
2761 si_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyu_hl_s1>;
2762 def Hexagon_M2_mpyu_lh_s0:
2763 si_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyu_lh_s0>;
2764 def Hexagon_M2_mpyu_lh_s1:
2765 si_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyu_lh_s1>;
2766 def Hexagon_M2_mpyu_ll_s0:
2767 si_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyu_ll_s0>;
2768 def Hexagon_M2_mpyu_ll_s1:
2769 si_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyu_ll_s1>;
2771 //Rdd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2772 def Hexagon_M2_mpyud_hh_s0:
2773 di_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyud_hh_s0>;
2774 def Hexagon_M2_mpyud_hh_s1:
2775 di_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyud_hh_s1>;
2776 def Hexagon_M2_mpyud_hl_s0:
2777 di_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyud_hl_s0>;
2778 def Hexagon_M2_mpyud_hl_s1:
2779 di_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyud_hl_s1>;
2780 def Hexagon_M2_mpyud_lh_s0:
2781 di_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyud_lh_s0>;
2782 def Hexagon_M2_mpyud_lh_s1:
2783 di_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyud_lh_s1>;
2784 def Hexagon_M2_mpyud_ll_s0:
2785 di_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyud_ll_s0>;
2786 def Hexagon_M2_mpyud_ll_s1:
2787 di_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyud_ll_s1>;
2789 //Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2790 def Hexagon_M2_mpyu_acc_hh_s0:
2791 si_MInst_sisisi_acc_hh <"mpyu", int_hexagon_M2_mpyu_acc_hh_s0>;
2792 def Hexagon_M2_mpyu_acc_hh_s1:
2793 si_MInst_sisisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hh_s1>;
2794 def Hexagon_M2_mpyu_acc_hl_s0:
2795 si_MInst_sisisi_acc_hl <"mpyu", int_hexagon_M2_mpyu_acc_hl_s0>;
2796 def Hexagon_M2_mpyu_acc_hl_s1:
2797 si_MInst_sisisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hl_s1>;
2798 def Hexagon_M2_mpyu_acc_lh_s0:
2799 si_MInst_sisisi_acc_lh <"mpyu", int_hexagon_M2_mpyu_acc_lh_s0>;
2800 def Hexagon_M2_mpyu_acc_lh_s1:
2801 si_MInst_sisisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_lh_s1>;
2802 def Hexagon_M2_mpyu_acc_ll_s0:
2803 si_MInst_sisisi_acc_ll <"mpyu", int_hexagon_M2_mpyu_acc_ll_s0>;
2804 def Hexagon_M2_mpyu_acc_ll_s1:
2805 si_MInst_sisisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyu_acc_ll_s1>;
2807 //Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2808 def Hexagon_M2_mpyu_nac_hh_s0:
2809 si_MInst_sisisi_nac_hh <"mpyu", int_hexagon_M2_mpyu_nac_hh_s0>;
2810 def Hexagon_M2_mpyu_nac_hh_s1:
2811 si_MInst_sisisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hh_s1>;
2812 def Hexagon_M2_mpyu_nac_hl_s0:
2813 si_MInst_sisisi_nac_hl <"mpyu", int_hexagon_M2_mpyu_nac_hl_s0>;
2814 def Hexagon_M2_mpyu_nac_hl_s1:
2815 si_MInst_sisisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hl_s1>;
2816 def Hexagon_M2_mpyu_nac_lh_s0:
2817 si_MInst_sisisi_nac_lh <"mpyu", int_hexagon_M2_mpyu_nac_lh_s0>;
2818 def Hexagon_M2_mpyu_nac_lh_s1:
2819 si_MInst_sisisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_lh_s1>;
2820 def Hexagon_M2_mpyu_nac_ll_s0:
2821 si_MInst_sisisi_nac_ll <"mpyu", int_hexagon_M2_mpyu_nac_ll_s0>;
2822 def Hexagon_M2_mpyu_nac_ll_s1:
2823 si_MInst_sisisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyu_nac_ll_s1>;
2825 //Rdd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2826 def Hexagon_M2_mpyud_acc_hh_s0:
2827 di_MInst_disisi_acc_hh <"mpyu", int_hexagon_M2_mpyud_acc_hh_s0>;
2828 def Hexagon_M2_mpyud_acc_hh_s1:
2829 di_MInst_disisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hh_s1>;
2830 def Hexagon_M2_mpyud_acc_hl_s0:
2831 di_MInst_disisi_acc_hl <"mpyu", int_hexagon_M2_mpyud_acc_hl_s0>;
2832 def Hexagon_M2_mpyud_acc_hl_s1:
2833 di_MInst_disisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hl_s1>;
2834 def Hexagon_M2_mpyud_acc_lh_s0:
2835 di_MInst_disisi_acc_lh <"mpyu", int_hexagon_M2_mpyud_acc_lh_s0>;
2836 def Hexagon_M2_mpyud_acc_lh_s1:
2837 di_MInst_disisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_lh_s1>;
2838 def Hexagon_M2_mpyud_acc_ll_s0:
2839 di_MInst_disisi_acc_ll <"mpyu", int_hexagon_M2_mpyud_acc_ll_s0>;
2840 def Hexagon_M2_mpyud_acc_ll_s1:
2841 di_MInst_disisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyud_acc_ll_s1>;
2843 //Rdd-=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2844 def Hexagon_M2_mpyud_nac_hh_s0:
2845 di_MInst_disisi_nac_hh <"mpyu", int_hexagon_M2_mpyud_nac_hh_s0>;
2846 def Hexagon_M2_mpyud_nac_hh_s1:
2847 di_MInst_disisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hh_s1>;
2848 def Hexagon_M2_mpyud_nac_hl_s0:
2849 di_MInst_disisi_nac_hl <"mpyu", int_hexagon_M2_mpyud_nac_hl_s0>;
2850 def Hexagon_M2_mpyud_nac_hl_s1:
2851 di_MInst_disisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hl_s1>;
2852 def Hexagon_M2_mpyud_nac_lh_s0:
2853 di_MInst_disisi_nac_lh <"mpyu", int_hexagon_M2_mpyud_nac_lh_s0>;
2854 def Hexagon_M2_mpyud_nac_lh_s1:
2855 di_MInst_disisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_lh_s1>;
2856 def Hexagon_M2_mpyud_nac_ll_s0:
2857 di_MInst_disisi_nac_ll <"mpyu", int_hexagon_M2_mpyud_nac_ll_s0>;
2858 def Hexagon_M2_mpyud_nac_ll_s1:
2859 di_MInst_disisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyud_nac_ll_s1>;
2862 /********************************************************************
2864 *********************************************************************/
2866 // MTYPE / VB / Vector reduce add unsigned bytes.
2867 def Hexagon_A2_vraddub:
2868 di_MInst_didi <"vraddub", int_hexagon_A2_vraddub>;
2869 def Hexagon_A2_vraddub_acc:
2870 di_MInst_dididi_acc <"vraddub", int_hexagon_A2_vraddub_acc>;
2872 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2873 def Hexagon_A2_vrsadub:
2874 di_MInst_didi <"vrsadub", int_hexagon_A2_vrsadub>;
2875 def Hexagon_A2_vrsadub_acc:
2876 di_MInst_dididi_acc <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2878 /********************************************************************
2880 *********************************************************************/
2882 // MTYPE / VH / Vector dual multiply.
2883 def Hexagon_M2_vdmpys_s1:
2884 di_MInst_didi_s1_sat <"vdmpy", int_hexagon_M2_vdmpys_s1>;
2885 def Hexagon_M2_vdmpys_s0:
2886 di_MInst_didi_sat <"vdmpy", int_hexagon_M2_vdmpys_s0>;
2887 def Hexagon_M2_vdmacs_s1:
2888 di_MInst_dididi_acc_s1_sat <"vdmpy", int_hexagon_M2_vdmacs_s1>;
2889 def Hexagon_M2_vdmacs_s0:
2890 di_MInst_dididi_acc_sat <"vdmpy", int_hexagon_M2_vdmacs_s0>;
2892 // MTYPE / VH / Vector dual multiply with round and pack.
2893 def Hexagon_M2_vdmpyrs_s0:
2894 si_MInst_didi_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s0>;
2895 def Hexagon_M2_vdmpyrs_s1:
2896 si_MInst_didi_s1_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s1>;
2898 // MTYPE / VH / Vector multiply even halfwords.
2899 def Hexagon_M2_vmpy2es_s1:
2900 di_MInst_didi_s1_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s1>;
2901 def Hexagon_M2_vmpy2es_s0:
2902 di_MInst_didi_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s0>;
2903 def Hexagon_M2_vmac2es:
2904 di_MInst_dididi_acc <"vmpyeh", int_hexagon_M2_vmac2es>;
2905 def Hexagon_M2_vmac2es_s1:
2906 di_MInst_dididi_acc_s1_sat <"vmpyeh", int_hexagon_M2_vmac2es_s1>;
2907 def Hexagon_M2_vmac2es_s0:
2908 di_MInst_dididi_acc_sat <"vmpyeh", int_hexagon_M2_vmac2es_s0>;
2910 // MTYPE / VH / Vector multiply halfwords.
2911 def Hexagon_M2_vmpy2s_s0:
2912 di_MInst_sisi_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0>;
2913 def Hexagon_M2_vmpy2s_s1:
2914 di_MInst_sisi_s1_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1>;
2915 def Hexagon_M2_vmac2:
2916 di_MInst_disisi_acc <"vmpyh", int_hexagon_M2_vmac2>;
2917 def Hexagon_M2_vmac2s_s0:
2918 di_MInst_disisi_acc_sat <"vmpyh", int_hexagon_M2_vmac2s_s0>;
2919 def Hexagon_M2_vmac2s_s1:
2920 di_MInst_disisi_acc_s1_sat <"vmpyh", int_hexagon_M2_vmac2s_s1>;
2922 // MTYPE / VH / Vector multiply halfwords with round and pack.
2923 def Hexagon_M2_vmpy2s_s0pack:
2924 si_MInst_sisi_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0pack>;
2925 def Hexagon_M2_vmpy2s_s1pack:
2926 si_MInst_sisi_s1_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1pack>;
2928 // MTYPE / VH / Vector reduce multiply halfwords.
2929 // Rxx32+=vrmpyh(Rss32,Rtt32)
2930 def Hexagon_M2_vrmpy_s0:
2931 di_MInst_didi <"vrmpyh", int_hexagon_M2_vrmpy_s0>;
2932 def Hexagon_M2_vrmac_s0:
2933 di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>;
2936 /********************************************************************
2938 *********************************************************************/
2940 // STYPE / ALU / Absolute value.
2942 si_SInst_si <"abs", int_hexagon_A2_abs>;
2943 def Hexagon_A2_absp:
2944 di_SInst_di <"abs", int_hexagon_A2_absp>;
2945 def Hexagon_A2_abssat:
2946 si_SInst_si_sat <"abs", int_hexagon_A2_abssat>;
2948 // STYPE / ALU / Negate.
2949 def Hexagon_A2_negp:
2950 di_SInst_di <"neg", int_hexagon_A2_negp>;
2951 def Hexagon_A2_negsat:
2952 si_SInst_si_sat <"neg", int_hexagon_A2_negsat>;
2954 // STYPE / ALU / Logical Not.
2955 def Hexagon_A2_notp:
2956 di_SInst_di <"not", int_hexagon_A2_notp>;
2958 // STYPE / ALU / Sign extend word to doubleword.
2959 def Hexagon_A2_sxtw:
2960 di_SInst_si <"sxtw", int_hexagon_A2_sxtw>;
2963 /********************************************************************
2965 *********************************************************************/
2967 // STYPE / BIT / Count leading.
2969 si_SInst_si <"cl0", int_hexagon_S2_cl0>;
2970 def Hexagon_S2_cl0p:
2971 si_SInst_di <"cl0", int_hexagon_S2_cl0p>;
2973 si_SInst_si <"cl1", int_hexagon_S2_cl1>;
2974 def Hexagon_S2_cl1p:
2975 si_SInst_di <"cl1", int_hexagon_S2_cl1p>;
2977 si_SInst_si <"clb", int_hexagon_S2_clb>;
2978 def Hexagon_S2_clbp:
2979 si_SInst_di <"clb", int_hexagon_S2_clbp>;
2980 def Hexagon_S2_clbnorm:
2981 si_SInst_si <"normamt", int_hexagon_S2_clbnorm>;
2983 // STYPE / BIT / Count trailing.
2985 si_SInst_si <"ct0", int_hexagon_S2_ct0>;
2987 si_SInst_si <"ct1", int_hexagon_S2_ct1>;
2989 // STYPE / BIT / Compare bit mask.
2990 def HEXAGON_C2_bitsclr:
2991 qi_SInst_sisi <"bitsclr", int_hexagon_C2_bitsclr>;
2992 def HEXAGON_C2_bitsclri:
2993 qi_SInst_siu6 <"bitsclr", int_hexagon_C2_bitsclri>;
2994 def HEXAGON_C2_bitsset:
2995 qi_SInst_sisi <"bitsset", int_hexagon_C2_bitsset>;
2997 // STYPE / BIT / Extract unsigned.
2998 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2999 def Hexagon_S2_extractu:
3000 si_SInst_siu5u5 <"extractu",int_hexagon_S2_extractu>;
3001 def Hexagon_S2_extractu_rp:
3002 si_SInst_sidi <"extractu",int_hexagon_S2_extractu_rp>;
3003 def Hexagon_S2_extractup:
3004 di_SInst_diu6u6 <"extractu",int_hexagon_S2_extractup>;
3005 def Hexagon_S2_extractup_rp:
3006 di_SInst_didi <"extractu",int_hexagon_S2_extractup_rp>;
3008 // STYPE / BIT / Insert bitfield.
3009 def HEXAGON_S2_insert:
3010 si_SInst_sisiu5u5 <"insert", int_hexagon_S2_insert>;
3011 def HEXAGON_S2_insert_rp:
3012 si_SInst_sisidi <"insert", int_hexagon_S2_insert_rp>;
3013 def HEXAGON_S2_insertp:
3014 di_SInst_didiu6u6 <"insert", int_hexagon_S2_insertp>;
3015 def HEXAGON_S2_insertp_rp:
3016 di_SInst_dididi <"insert", int_hexagon_S2_insertp_rp>;
3018 // STYPE / BIT / Innterleave/deinterleave.
3019 def HEXAGON_S2_interleave:
3020 di_SInst_di <"interleave", int_hexagon_S2_interleave>;
3021 def HEXAGON_S2_deinterleave:
3022 di_SInst_di <"deinterleave", int_hexagon_S2_deinterleave>;
3024 // STYPE / BIT / Linear feedback-shift Iteration.
3025 def HEXAGON_S2_lfsp:
3026 di_SInst_didi <"lfs", int_hexagon_S2_lfsp>;
3028 // STYPE / BIT / Bit reverse.
3029 def HEXAGON_S2_brev:
3030 si_SInst_si <"brev", int_hexagon_S2_brev>;
3032 // STYPE / BIT / Set/Clear/Toggle Bit.
3033 def Hexagon_S2_setbit_i:
3034 si_SInst_siu5 <"setbit", int_hexagon_S2_setbit_i>;
3035 def Hexagon_S2_togglebit_i:
3036 si_SInst_siu5 <"togglebit", int_hexagon_S2_togglebit_i>;
3037 def Hexagon_S2_clrbit_i:
3038 si_SInst_siu5 <"clrbit", int_hexagon_S2_clrbit_i>;
3039 def Hexagon_S2_setbit_r:
3040 si_SInst_sisi <"setbit", int_hexagon_S2_setbit_r>;
3041 def Hexagon_S2_togglebit_r:
3042 si_SInst_sisi <"togglebit", int_hexagon_S2_togglebit_r>;
3043 def Hexagon_S2_clrbit_r:
3044 si_SInst_sisi <"clrbit", int_hexagon_S2_clrbit_r>;
3046 // STYPE / BIT / Test Bit.
3047 def Hexagon_S2_tstbit_i:
3048 qi_SInst_siu5 <"tstbit", int_hexagon_S2_tstbit_i>;
3049 def Hexagon_S2_tstbit_r:
3050 qi_SInst_sisi <"tstbit", int_hexagon_S2_tstbit_r>;
3053 /********************************************************************
3055 *********************************************************************/
3057 // STYPE / COMPLEX / Vector Complex conjugate.
3058 def Hexagon_A2_vconj:
3059 di_SInst_di_sat <"vconj", int_hexagon_A2_vconj>;
3061 // STYPE / COMPLEX / Vector Complex rotate.
3062 def Hexagon_S2_vcrotate:
3063 di_SInst_disi <"vcrotate",int_hexagon_S2_vcrotate>;
3066 /********************************************************************
3068 *********************************************************************/
3070 // STYPE / PERM / Saturate.
3072 si_SInst_di <"sat", int_hexagon_A2_sat>;
3073 def Hexagon_A2_satb:
3074 si_SInst_si <"satb", int_hexagon_A2_satb>;
3075 def Hexagon_A2_sath:
3076 si_SInst_si <"sath", int_hexagon_A2_sath>;
3077 def Hexagon_A2_satub:
3078 si_SInst_si <"satub", int_hexagon_A2_satub>;
3079 def Hexagon_A2_satuh:
3080 si_SInst_si <"satuh", int_hexagon_A2_satuh>;
3082 // STYPE / PERM / Swizzle bytes.
3083 def Hexagon_A2_swiz:
3084 si_SInst_si <"swiz", int_hexagon_A2_swiz>;
3086 // STYPE / PERM / Vector align.
3087 // Need custom lowering
3088 def Hexagon_S2_valignib:
3089 di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
3090 def Hexagon_S2_valignrb:
3091 di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
3093 // STYPE / PERM / Vector round and pack.
3094 def Hexagon_S2_vrndpackwh:
3095 si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
3096 def Hexagon_S2_vrndpackwhs:
3097 si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
3099 // STYPE / PERM / Vector saturate and pack.
3100 def Hexagon_S2_svsathb:
3101 si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
3102 def Hexagon_S2_vsathb:
3103 si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
3104 def Hexagon_S2_svsathub:
3105 si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
3106 def Hexagon_S2_vsathub:
3107 si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
3108 def Hexagon_S2_vsatwh:
3109 si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
3110 def Hexagon_S2_vsatwuh:
3111 si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
3113 // STYPE / PERM / Vector saturate without pack.
3114 def Hexagon_S2_vsathb_nopack:
3115 di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
3116 def Hexagon_S2_vsathub_nopack:
3117 di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
3118 def Hexagon_S2_vsatwh_nopack:
3119 di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
3120 def Hexagon_S2_vsatwuh_nopack:
3121 di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3123 // STYPE / PERM / Vector shuffle.
3124 def Hexagon_S2_shuffeb:
3125 di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
3126 def Hexagon_S2_shuffeh:
3127 di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
3128 def Hexagon_S2_shuffob:
3129 di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
3130 def Hexagon_S2_shuffoh:
3131 di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
3133 // STYPE / PERM / Vector splat bytes.
3134 def Hexagon_S2_vsplatrb:
3135 si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
3137 // STYPE / PERM / Vector splat halfwords.
3138 def Hexagon_S2_vsplatrh:
3139 di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
3141 // STYPE / PERM / Vector splice.
3142 def HEXAGON_S2_vsplicerb:
3143 di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
3144 def HEXAGON_S2_vspliceib:
3145 di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
3147 // STYPE / PERM / Sign extend.
3148 def Hexagon_S2_vsxtbh:
3149 di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
3150 def Hexagon_S2_vsxthw:
3151 di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
3153 // STYPE / PERM / Truncate.
3154 def Hexagon_S2_vtrunehb:
3155 si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
3156 def Hexagon_S2_vtrunohb:
3157 si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
3158 def Hexagon_S2_vtrunewh:
3159 di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
3160 def Hexagon_S2_vtrunowh:
3161 di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
3163 // STYPE / PERM / Zero extend.
3164 def Hexagon_S2_vzxtbh:
3165 di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
3166 def Hexagon_S2_vzxthw:
3167 di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
3170 /********************************************************************
3172 *********************************************************************/
3174 // STYPE / PRED / Mask generate from predicate.
3175 def Hexagon_C2_mask:
3176 di_SInst_qi <"mask", int_hexagon_C2_mask>;
3178 // STYPE / PRED / Predicate transfer.
3179 def Hexagon_C2_tfrpr:
3180 si_SInst_qi <"", int_hexagon_C2_tfrpr>;
3181 def Hexagon_C2_tfrrp:
3182 qi_SInst_si <"", int_hexagon_C2_tfrrp>;
3184 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3185 def Hexagon_C2_vitpack:
3186 si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
3189 /********************************************************************
3191 *********************************************************************/
3193 // STYPE / SHIFT / Shift by immediate.
3194 def Hexagon_S2_asl_i_r:
3195 si_SInst_siu5 <"asl", int_hexagon_S2_asl_i_r>;
3196 def Hexagon_S2_asr_i_r:
3197 si_SInst_siu5 <"asr", int_hexagon_S2_asr_i_r>;
3198 def Hexagon_S2_lsr_i_r:
3199 si_SInst_siu5 <"lsr", int_hexagon_S2_lsr_i_r>;
3200 def Hexagon_S2_asl_i_p:
3201 di_SInst_diu6 <"asl", int_hexagon_S2_asl_i_p>;
3202 def Hexagon_S2_asr_i_p:
3203 di_SInst_diu6 <"asr", int_hexagon_S2_asr_i_p>;
3204 def Hexagon_S2_lsr_i_p:
3205 di_SInst_diu6 <"lsr", int_hexagon_S2_lsr_i_p>;
3207 // STYPE / SHIFT / Shift by immediate and accumulate.
3208 def Hexagon_S2_asl_i_r_acc:
3209 si_SInst_sisiu5_acc <"asl", int_hexagon_S2_asl_i_r_acc>;
3210 def Hexagon_S2_asr_i_r_acc:
3211 si_SInst_sisiu5_acc <"asr", int_hexagon_S2_asr_i_r_acc>;
3212 def Hexagon_S2_lsr_i_r_acc:
3213 si_SInst_sisiu5_acc <"lsr", int_hexagon_S2_lsr_i_r_acc>;
3214 def Hexagon_S2_asl_i_r_nac:
3215 si_SInst_sisiu5_nac <"asl", int_hexagon_S2_asl_i_r_nac>;
3216 def Hexagon_S2_asr_i_r_nac:
3217 si_SInst_sisiu5_nac <"asr", int_hexagon_S2_asr_i_r_nac>;
3218 def Hexagon_S2_lsr_i_r_nac:
3219 si_SInst_sisiu5_nac <"lsr", int_hexagon_S2_lsr_i_r_nac>;
3220 def Hexagon_S2_asl_i_p_acc:
3221 di_SInst_didiu6_acc <"asl", int_hexagon_S2_asl_i_p_acc>;
3222 def Hexagon_S2_asr_i_p_acc:
3223 di_SInst_didiu6_acc <"asr", int_hexagon_S2_asr_i_p_acc>;
3224 def Hexagon_S2_lsr_i_p_acc:
3225 di_SInst_didiu6_acc <"lsr", int_hexagon_S2_lsr_i_p_acc>;
3226 def Hexagon_S2_asl_i_p_nac:
3227 di_SInst_didiu6_nac <"asl", int_hexagon_S2_asl_i_p_nac>;
3228 def Hexagon_S2_asr_i_p_nac:
3229 di_SInst_didiu6_nac <"asr", int_hexagon_S2_asr_i_p_nac>;
3230 def Hexagon_S2_lsr_i_p_nac:
3231 di_SInst_didiu6_nac <"lsr", int_hexagon_S2_lsr_i_p_nac>;
3233 // STYPE / SHIFT / Shift by immediate and add.
3234 def Hexagon_S2_addasl_rrri:
3235 si_SInst_sisiu3 <"addasl", int_hexagon_S2_addasl_rrri>;
3237 // STYPE / SHIFT / Shift by immediate and logical.
3238 def Hexagon_S2_asl_i_r_and:
3239 si_SInst_sisiu5_and <"asl", int_hexagon_S2_asl_i_r_and>;
3240 def Hexagon_S2_asr_i_r_and:
3241 si_SInst_sisiu5_and <"asr", int_hexagon_S2_asr_i_r_and>;
3242 def Hexagon_S2_lsr_i_r_and:
3243 si_SInst_sisiu5_and <"lsr", int_hexagon_S2_lsr_i_r_and>;
3245 def Hexagon_S2_asl_i_r_xacc:
3246 si_SInst_sisiu5_xor <"asl", int_hexagon_S2_asl_i_r_xacc>;
3247 def Hexagon_S2_lsr_i_r_xacc:
3248 si_SInst_sisiu5_xor <"lsr", int_hexagon_S2_lsr_i_r_xacc>;
3250 def Hexagon_S2_asl_i_r_or:
3251 si_SInst_sisiu5_or <"asl", int_hexagon_S2_asl_i_r_or>;
3252 def Hexagon_S2_asr_i_r_or:
3253 si_SInst_sisiu5_or <"asr", int_hexagon_S2_asr_i_r_or>;
3254 def Hexagon_S2_lsr_i_r_or:
3255 si_SInst_sisiu5_or <"lsr", int_hexagon_S2_lsr_i_r_or>;
3257 def Hexagon_S2_asl_i_p_and:
3258 di_SInst_didiu6_and <"asl", int_hexagon_S2_asl_i_p_and>;
3259 def Hexagon_S2_asr_i_p_and:
3260 di_SInst_didiu6_and <"asr", int_hexagon_S2_asr_i_p_and>;
3261 def Hexagon_S2_lsr_i_p_and:
3262 di_SInst_didiu6_and <"lsr", int_hexagon_S2_lsr_i_p_and>;
3264 def Hexagon_S2_asl_i_p_xacc:
3265 di_SInst_didiu6_xor <"asl", int_hexagon_S2_asl_i_p_xacc>;
3266 def Hexagon_S2_lsr_i_p_xacc:
3267 di_SInst_didiu6_xor <"lsr", int_hexagon_S2_lsr_i_p_xacc>;
3269 def Hexagon_S2_asl_i_p_or:
3270 di_SInst_didiu6_or <"asl", int_hexagon_S2_asl_i_p_or>;
3271 def Hexagon_S2_asr_i_p_or:
3272 di_SInst_didiu6_or <"asr", int_hexagon_S2_asr_i_p_or>;
3273 def Hexagon_S2_lsr_i_p_or:
3274 di_SInst_didiu6_or <"lsr", int_hexagon_S2_lsr_i_p_or>;
3276 // STYPE / SHIFT / Shift right by immediate with rounding.
3277 def Hexagon_S2_asr_i_r_rnd:
3278 si_SInst_siu5_rnd <"asr", int_hexagon_S2_asr_i_r_rnd>;
3279 def Hexagon_S2_asr_i_r_rnd_goodsyntax:
3280 si_SInst_siu5 <"asrrnd", int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3282 // STYPE / SHIFT / Shift left by immediate with saturation.
3283 def Hexagon_S2_asl_i_r_sat:
3284 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_i_r_sat>;
3286 // STYPE / SHIFT / Shift by register.
3287 def Hexagon_S2_asl_r_r:
3288 si_SInst_sisi <"asl", int_hexagon_S2_asl_r_r>;
3289 def Hexagon_S2_asr_r_r:
3290 si_SInst_sisi <"asr", int_hexagon_S2_asr_r_r>;
3291 def Hexagon_S2_lsl_r_r:
3292 si_SInst_sisi <"lsl", int_hexagon_S2_lsl_r_r>;
3293 def Hexagon_S2_lsr_r_r:
3294 si_SInst_sisi <"lsr", int_hexagon_S2_lsr_r_r>;
3295 def Hexagon_S2_asl_r_p:
3296 di_SInst_disi <"asl", int_hexagon_S2_asl_r_p>;
3297 def Hexagon_S2_asr_r_p:
3298 di_SInst_disi <"asr", int_hexagon_S2_asr_r_p>;
3299 def Hexagon_S2_lsl_r_p:
3300 di_SInst_disi <"lsl", int_hexagon_S2_lsl_r_p>;
3301 def Hexagon_S2_lsr_r_p:
3302 di_SInst_disi <"lsr", int_hexagon_S2_lsr_r_p>;
3304 // STYPE / SHIFT / Shift by register and accumulate.
3305 def Hexagon_S2_asl_r_r_acc:
3306 si_SInst_sisisi_acc <"asl", int_hexagon_S2_asl_r_r_acc>;
3307 def Hexagon_S2_asr_r_r_acc:
3308 si_SInst_sisisi_acc <"asr", int_hexagon_S2_asr_r_r_acc>;
3309 def Hexagon_S2_lsl_r_r_acc:
3310 si_SInst_sisisi_acc <"lsl", int_hexagon_S2_lsl_r_r_acc>;
3311 def Hexagon_S2_lsr_r_r_acc:
3312 si_SInst_sisisi_acc <"lsr", int_hexagon_S2_lsr_r_r_acc>;
3313 def Hexagon_S2_asl_r_p_acc:
3314 di_SInst_didisi_acc <"asl", int_hexagon_S2_asl_r_p_acc>;
3315 def Hexagon_S2_asr_r_p_acc:
3316 di_SInst_didisi_acc <"asr", int_hexagon_S2_asr_r_p_acc>;
3317 def Hexagon_S2_lsl_r_p_acc:
3318 di_SInst_didisi_acc <"lsl", int_hexagon_S2_lsl_r_p_acc>;
3319 def Hexagon_S2_lsr_r_p_acc:
3320 di_SInst_didisi_acc <"lsr", int_hexagon_S2_lsr_r_p_acc>;
3322 def Hexagon_S2_asl_r_r_nac:
3323 si_SInst_sisisi_nac <"asl", int_hexagon_S2_asl_r_r_nac>;
3324 def Hexagon_S2_asr_r_r_nac:
3325 si_SInst_sisisi_nac <"asr", int_hexagon_S2_asr_r_r_nac>;
3326 def Hexagon_S2_lsl_r_r_nac:
3327 si_SInst_sisisi_nac <"lsl", int_hexagon_S2_lsl_r_r_nac>;
3328 def Hexagon_S2_lsr_r_r_nac:
3329 si_SInst_sisisi_nac <"lsr", int_hexagon_S2_lsr_r_r_nac>;
3330 def Hexagon_S2_asl_r_p_nac:
3331 di_SInst_didisi_nac <"asl", int_hexagon_S2_asl_r_p_nac>;
3332 def Hexagon_S2_asr_r_p_nac:
3333 di_SInst_didisi_nac <"asr", int_hexagon_S2_asr_r_p_nac>;
3334 def Hexagon_S2_lsl_r_p_nac:
3335 di_SInst_didisi_nac <"lsl", int_hexagon_S2_lsl_r_p_nac>;
3336 def Hexagon_S2_lsr_r_p_nac:
3337 di_SInst_didisi_nac <"lsr", int_hexagon_S2_lsr_r_p_nac>;
3339 // STYPE / SHIFT / Shift by register and logical.
3340 def Hexagon_S2_asl_r_r_and:
3341 si_SInst_sisisi_and <"asl", int_hexagon_S2_asl_r_r_and>;
3342 def Hexagon_S2_asr_r_r_and:
3343 si_SInst_sisisi_and <"asr", int_hexagon_S2_asr_r_r_and>;
3344 def Hexagon_S2_lsl_r_r_and:
3345 si_SInst_sisisi_and <"lsl", int_hexagon_S2_lsl_r_r_and>;
3346 def Hexagon_S2_lsr_r_r_and:
3347 si_SInst_sisisi_and <"lsr", int_hexagon_S2_lsr_r_r_and>;
3349 def Hexagon_S2_asl_r_r_or:
3350 si_SInst_sisisi_or <"asl", int_hexagon_S2_asl_r_r_or>;
3351 def Hexagon_S2_asr_r_r_or:
3352 si_SInst_sisisi_or <"asr", int_hexagon_S2_asr_r_r_or>;
3353 def Hexagon_S2_lsl_r_r_or:
3354 si_SInst_sisisi_or <"lsl", int_hexagon_S2_lsl_r_r_or>;
3355 def Hexagon_S2_lsr_r_r_or:
3356 si_SInst_sisisi_or <"lsr", int_hexagon_S2_lsr_r_r_or>;
3358 def Hexagon_S2_asl_r_p_and:
3359 di_SInst_didisi_and <"asl", int_hexagon_S2_asl_r_p_and>;
3360 def Hexagon_S2_asr_r_p_and:
3361 di_SInst_didisi_and <"asr", int_hexagon_S2_asr_r_p_and>;
3362 def Hexagon_S2_lsl_r_p_and:
3363 di_SInst_didisi_and <"lsl", int_hexagon_S2_lsl_r_p_and>;
3364 def Hexagon_S2_lsr_r_p_and:
3365 di_SInst_didisi_and <"lsr", int_hexagon_S2_lsr_r_p_and>;
3367 def Hexagon_S2_asl_r_p_or:
3368 di_SInst_didisi_or <"asl", int_hexagon_S2_asl_r_p_or>;
3369 def Hexagon_S2_asr_r_p_or:
3370 di_SInst_didisi_or <"asr", int_hexagon_S2_asr_r_p_or>;
3371 def Hexagon_S2_lsl_r_p_or:
3372 di_SInst_didisi_or <"lsl", int_hexagon_S2_lsl_r_p_or>;
3373 def Hexagon_S2_lsr_r_p_or:
3374 di_SInst_didisi_or <"lsr", int_hexagon_S2_lsr_r_p_or>;
3376 // STYPE / SHIFT / Shift by register with saturation.
3377 def Hexagon_S2_asl_r_r_sat:
3378 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_r_r_sat>;
3379 def Hexagon_S2_asr_r_r_sat:
3380 si_SInst_sisi_sat <"asr", int_hexagon_S2_asr_r_r_sat>;
3382 // STYPE / SHIFT / Table Index.
3383 def HEXAGON_S2_tableidxb_goodsyntax:
3384 si_MInst_sisiu4u5 <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3385 def HEXAGON_S2_tableidxd_goodsyntax:
3386 si_MInst_sisiu4u5 <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3387 def HEXAGON_S2_tableidxh_goodsyntax:
3388 si_MInst_sisiu4u5 <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3389 def HEXAGON_S2_tableidxw_goodsyntax:
3390 si_MInst_sisiu4u5 <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3393 /********************************************************************
3395 *********************************************************************/
3397 // STYPE / VH / Vector absolute value halfwords.
3398 // Rdd64=vabsh(Rss64)
3399 def Hexagon_A2_vabsh:
3400 di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
3401 def Hexagon_A2_vabshsat:
3402 di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
3404 // STYPE / VH / Vector shift halfwords by immediate.
3405 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3406 def Hexagon_S2_asl_i_vh:
3407 di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
3408 def Hexagon_S2_asr_i_vh:
3409 di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
3410 def Hexagon_S2_lsr_i_vh:
3411 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
3413 // STYPE / VH / Vector shift halfwords by register.
3414 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3415 def Hexagon_S2_asl_r_vh:
3416 di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
3417 def Hexagon_S2_asr_r_vh:
3418 di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
3419 def Hexagon_S2_lsl_r_vh:
3420 di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
3421 def Hexagon_S2_lsr_r_vh:
3422 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
3425 /********************************************************************
3427 *********************************************************************/
3429 // STYPE / VW / Vector absolute value words.
3430 def Hexagon_A2_vabsw:
3431 di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
3432 def Hexagon_A2_vabswsat:
3433 di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
3435 // STYPE / VW / Vector shift words by immediate.
3436 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3437 def Hexagon_S2_asl_i_vw:
3438 di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
3439 def Hexagon_S2_asr_i_vw:
3440 di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
3441 def Hexagon_S2_lsr_i_vw:
3442 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
3444 // STYPE / VW / Vector shift words by register.
3445 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3446 def Hexagon_S2_asl_r_vw:
3447 di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
3448 def Hexagon_S2_asr_r_vw:
3449 di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
3450 def Hexagon_S2_lsl_r_vw:
3451 di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
3452 def Hexagon_S2_lsr_r_vw:
3453 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
3455 // STYPE / VW / Vector shift words with truncate and pack.
3456 def Hexagon_S2_asr_r_svw_trun:
3457 si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
3458 def Hexagon_S2_asr_i_svw_trun:
3459 si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
3461 include "HexagonIntrinsicsV3.td"
3462 include "HexagonIntrinsicsV4.td"