1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is populated based on the following specs:
10 // Hexagon V2 Architecture
11 // Application-Level Specification
14 //===----------------------------------------------------------------------===//
20 class qi_ALU32_sisi<string opc, Intrinsic IntID>
21 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
22 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
23 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
25 class qi_ALU32_sis10<string opc, Intrinsic IntID>
26 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
27 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
28 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
30 class qi_ALU32_sis8<string opc, Intrinsic IntID>
31 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
33 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
35 class qi_ALU32_siu8<string opc, Intrinsic IntID>
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
37 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
38 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
40 class qi_ALU32_siu9<string opc, Intrinsic IntID>
41 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
42 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
43 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
45 class si_ALU32_qisisi<string opc, Intrinsic IntID>
46 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
48 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
49 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
52 class si_ALU32_qis8si<string opc, Intrinsic IntID>
53 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
55 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
56 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
59 class si_ALU32_qisis8<string opc, Intrinsic IntID>
60 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
62 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
63 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
66 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
67 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
68 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
69 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
71 class si_ALU32_sisi<string opc, Intrinsic IntID>
72 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
73 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
74 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
76 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
77 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
78 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
79 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
81 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
82 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
83 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
84 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
86 class si_ALU32_sis16<string opc, Intrinsic IntID>
87 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
88 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
89 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
91 class si_ALU32_sis10<string opc, Intrinsic IntID>
92 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
93 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
94 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
96 class si_ALU32_s10si<string opc, Intrinsic IntID>
97 : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
98 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
99 [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
101 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
102 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
103 !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
104 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
106 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
107 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
108 !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
109 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
111 class si_ALU32_s16<string opc, Intrinsic IntID>
112 : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
113 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
114 [(set IntRegs:$dst, (IntID imm:$src1))]>;
116 class di_ALU32_s8<string opc, Intrinsic IntID>
117 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
118 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
119 [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
121 class di_ALU64_di<string opc, Intrinsic IntID>
122 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
123 !strconcat("$dst = ", !strconcat(opc , "$src")),
124 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
126 class si_ALU32_si<string opc, Intrinsic IntID>
127 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
128 !strconcat("$dst = ", !strconcat(opc , "($src)")),
129 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
131 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
132 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
133 !strconcat("$dst = ", !strconcat(opc , "$src")),
134 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
140 class si_ALU64_si_sat<string opc, Intrinsic IntID>
141 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
142 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
143 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
145 class si_ALU64_didi<string opc, Intrinsic IntID>
146 : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
147 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
148 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
150 class di_ALU64_sidi<string opc, Intrinsic IntID>
151 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
152 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
153 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
155 class di_ALU64_didi<string opc, Intrinsic IntID>
156 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
157 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
158 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
159 DoubleRegs:$src2))]>;
161 class di_ALU64_qididi<string opc, Intrinsic IntID>
162 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
164 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
165 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
166 DoubleRegs:$src3))]>;
168 class di_ALU64_sisi<string opc, Intrinsic IntID>
169 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
170 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
171 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
173 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
174 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
175 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
176 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
177 DoubleRegs:$src2))]>;
179 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
180 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
181 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
182 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
183 DoubleRegs:$src2))]>;
185 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
186 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
187 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
188 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
189 DoubleRegs:$src2))]>;
191 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
192 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
193 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
194 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
195 DoubleRegs:$src2))]>;
197 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
198 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
199 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
200 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
201 DoubleRegs:$src2))]>;
203 class qi_ALU64_didi<string opc, Intrinsic IntID>
204 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
205 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
206 [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
208 class si_ALU64_sisi<string opc, Intrinsic IntID>
209 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
210 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
211 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
213 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
214 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
215 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
216 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
218 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
219 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
220 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
221 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
223 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
224 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
225 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
226 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
228 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
229 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
230 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
231 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
233 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
234 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
235 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
236 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
238 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
239 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
240 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
241 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
243 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
244 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
245 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
246 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
248 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
249 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
250 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
251 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
253 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
254 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
255 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
256 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
258 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
259 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
260 !strconcat("$dst = ", !strconcat(opc ,
261 "($src1.H, $src2.H):sat:<<16")),
262 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
264 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
265 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
266 !strconcat("$dst = ", !strconcat(opc ,
267 "($src1.L, $src2.H):sat:<<16")),
268 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
270 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
271 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
272 !strconcat("$dst = ", !strconcat(opc ,
273 "($src1.H, $src2.L):sat:<<16")),
274 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
276 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
277 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
278 !strconcat("$dst = ", !strconcat(opc ,
279 "($src1.L, $src2.L):sat:<<16")),
280 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
282 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
283 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
284 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
285 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
287 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
288 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
289 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
290 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
292 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
293 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
294 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
295 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
297 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
298 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
299 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
300 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
302 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
303 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
304 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
305 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
307 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
308 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
309 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
310 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
312 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
313 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
314 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
315 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
321 class qi_SInst_qi<string opc, Intrinsic IntID>
322 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
323 !strconcat("$dst = ", !strconcat(opc , "($src)")),
324 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
326 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
327 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
328 !strconcat("$dst = ", !strconcat(opc , "$src")),
329 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
331 class qi_SInst_qiqi<string opc, Intrinsic IntID>
332 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
333 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
334 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
336 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
337 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
338 !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
339 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
341 class di_SInst_di<string opc, Intrinsic IntID>
342 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
343 !strconcat("$dst = ", !strconcat(opc , "($src)")),
344 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
346 class di_SInst_di_sat<string opc, Intrinsic IntID>
347 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
348 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
349 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
351 class si_SInst_di<string opc, Intrinsic IntID>
352 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
353 !strconcat("$dst = ", !strconcat(opc , "($src)")),
354 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
356 class si_SInst_di_sat<string opc, Intrinsic IntID>
357 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
358 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
359 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
361 class di_SInst_disi<string opc, Intrinsic IntID>
362 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
363 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
364 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
366 class di_SInst_didi<string opc, Intrinsic IntID>
367 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
368 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
369 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
371 class di_SInst_si<string opc, Intrinsic IntID>
372 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
373 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
374 [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
376 class si_SInst_sisiu3<string opc, Intrinsic IntID>
377 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
378 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
379 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
382 class si_SInst_diu5<string opc, Intrinsic IntID>
383 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
384 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
385 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
387 class si_SInst_disi<string opc, Intrinsic IntID>
388 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
389 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
390 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
392 class si_SInst_sidi<string opc, Intrinsic IntID>
393 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
394 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
395 [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
397 class di_SInst_disisi<string opc, Intrinsic IntID>
398 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
400 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
401 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
404 class di_SInst_sisi<string opc, Intrinsic IntID>
405 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
406 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
407 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
409 class qi_SInst_siu5<string opc, Intrinsic IntID>
410 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
411 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
412 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
414 class qi_SInst_siu6<string opc, Intrinsic IntID>
415 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
416 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
417 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
419 class qi_SInst_sisi<string opc, Intrinsic IntID>
420 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
421 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
422 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
424 class si_SInst_si<string opc, Intrinsic IntID>
425 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
426 !strconcat("$dst = ", !strconcat(opc , "($src)")),
427 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
429 class si_SInst_si_sat<string opc, Intrinsic IntID>
430 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
431 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
432 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
434 class di_SInst_qi<string opc, Intrinsic IntID>
435 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
436 !strconcat("$dst = ", !strconcat(opc , "($src)")),
437 [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
439 class si_SInst_qi<string opc, Intrinsic IntID>
440 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
441 !strconcat("$dst = ", !strconcat(opc , "$src")),
442 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
444 class si_SInst_qiqi<string opc, Intrinsic IntID>
445 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
446 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
447 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
449 class qi_SInst_si<string opc, Intrinsic IntID>
450 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
451 !strconcat("$dst = ", !strconcat(opc , "$src")),
452 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
454 class si_SInst_sisi<string opc, Intrinsic IntID>
455 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
456 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
457 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
459 class di_SInst_diu6<string opc, Intrinsic IntID>
460 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
461 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
462 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
464 class si_SInst_siu5<string opc, Intrinsic IntID>
465 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
466 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
467 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
469 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
470 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
471 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
472 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
474 class si_SInst_siu5u5<string opc, Intrinsic IntID>
475 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
476 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
477 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
479 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
480 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
482 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
483 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
487 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
488 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
490 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
491 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
495 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
496 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
498 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
499 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
504 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
505 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
507 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
508 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
509 DoubleRegs:$src1, IntRegs:$src2))],
512 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
513 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
514 u5Imm:$src2, u5Imm:$src3),
515 !strconcat("$dst = ", !strconcat(opc ,
516 "($src1, #$src2, #$src3)")),
517 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
518 imm:$src2, imm:$src3))],
521 class si_SInst_sisidi<string opc, Intrinsic IntID>
522 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
524 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
525 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
529 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
530 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
531 u6Imm:$src2, u6Imm:$src3),
532 !strconcat("$dst = ", !strconcat(opc ,
533 "($src1, #$src2, #$src3)")),
534 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
535 imm:$src2, imm:$src3))],
538 class di_SInst_dididi<string opc, Intrinsic IntID>
539 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
541 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
542 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
547 class di_SInst_diu6u6<string opc, Intrinsic IntID>
548 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
550 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
551 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
554 class di_SInst_didiqi<string opc, Intrinsic IntID>
555 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
557 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
558 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
561 class di_SInst_didiu3<string opc, Intrinsic IntID>
562 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
564 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
565 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
568 class di_SInst_didisi_or<string opc, Intrinsic IntID>
569 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
571 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
572 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
576 class di_SInst_didisi_and<string opc, Intrinsic IntID>
577 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
579 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
580 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
584 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
585 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
587 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
588 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
592 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
593 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
595 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
596 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
600 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
601 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
603 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
604 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
608 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
609 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
611 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
612 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
616 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
617 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
619 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
620 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
625 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
626 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
628 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
629 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
633 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
634 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
636 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
637 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
641 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
642 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
644 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
645 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
649 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
650 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
652 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
653 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
657 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
658 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
660 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
661 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
665 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
666 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
668 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
669 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
670 DoubleRegs:$src1, imm:$src2))],
673 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
674 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
676 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
677 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
686 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
687 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
688 !strconcat("$dst = ", !strconcat(opc ,
689 "($src1.H, $src2.H):<<1:rnd")),
690 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
692 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
693 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
694 !strconcat("$dst = ", !strconcat(opc ,
695 "($src1.H, $src2.H):rnd")),
696 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
698 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
699 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
700 !strconcat("$dst = ", !strconcat(opc ,
701 "($src1.H, $src2.L):<<1:rnd")),
702 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
704 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
705 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
706 !strconcat("$dst = ", !strconcat(opc ,
707 "($src1.H, $src2.L):rnd")),
708 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
710 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
711 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
712 !strconcat("$dst = ", !strconcat(opc ,
713 "($src1.L, $src2.H):<<1:rnd")),
714 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
716 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
717 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
718 !strconcat("$dst = ", !strconcat(opc ,
719 "($src1.L, $src2.H):rnd")),
720 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
722 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
723 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
724 !strconcat("$dst = ", !strconcat(opc ,
725 "($src1.L, $src2.L):<<1:rnd")),
726 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
728 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
729 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
730 !strconcat("$dst = ", !strconcat(opc ,
731 "($src1.L, $src2.L):rnd")),
732 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
734 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
735 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
737 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
738 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
742 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
743 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
745 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
746 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
750 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
751 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
753 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
754 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
758 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
759 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
761 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
762 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
766 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
767 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
769 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
770 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
774 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
775 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
777 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
778 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
782 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
783 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
785 !strconcat("$dst -= ", !strconcat(opc ,
786 "($src1, $src2):<<1:sat")),
787 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
791 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
792 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
794 !strconcat("$dst += ", !strconcat(opc ,
795 "($src1, $src2*):<<1:sat")),
796 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
800 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
801 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
803 !strconcat("$dst -= ", !strconcat(opc ,
804 "($src1, $src2*):<<1:sat")),
805 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
809 class di_MInst_s8s8<string opc, Intrinsic IntID>
810 : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
811 !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
812 [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
814 class si_MInst_sis9<string opc, Intrinsic IntID>
815 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
816 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
817 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
819 class si_MInst_sisi<string opc, Intrinsic IntID>
820 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
821 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
822 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
824 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
825 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
826 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
827 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
829 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
830 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
831 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
832 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
834 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
835 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
836 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
837 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
839 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
840 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
841 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
842 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
844 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
845 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
846 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
847 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
849 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
850 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
851 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
852 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
854 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
855 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
856 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
857 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
859 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
860 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
861 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
862 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
865 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
866 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
867 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
868 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
870 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
871 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
872 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
873 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
875 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
876 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
877 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
878 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
880 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
881 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
882 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
883 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
885 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
886 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
887 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
888 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
890 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
891 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
892 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
893 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
895 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
896 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
897 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
898 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
900 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
901 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
902 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
903 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
905 class si_MInst_sisi_up<string opc, Intrinsic IntID>
906 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
907 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
908 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
910 class di_MInst_didi<string opc, Intrinsic IntID>
911 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
912 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
913 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
914 DoubleRegs:$src2))]>;
916 class di_MInst_didi_conj<string opc, Intrinsic IntID>
917 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
918 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
919 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
920 DoubleRegs:$src2))]>;
922 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
923 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
924 !strconcat("$dst = ", !strconcat(opc ,
925 "($src1, $src2*):<<1:sat")),
926 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
928 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
929 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
930 !strconcat("$dst = ", !strconcat(opc ,
931 "($src1, $src2):<<1:rnd:sat")),
932 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
933 DoubleRegs:$src2))]>;
935 class di_MInst_didi_sat<string opc, Intrinsic IntID>
936 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
937 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
938 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
939 DoubleRegs:$src2))]>;
941 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
942 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
943 !strconcat("$dst = ", !strconcat(opc ,
944 "($src1, $src2):rnd:sat")),
945 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
946 DoubleRegs:$src2))]>;
948 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
949 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
950 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
951 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
953 class si_SInst_didi_sat<string opc, Intrinsic IntID>
954 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
955 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
956 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
958 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
959 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
960 !strconcat("$dst = ", !strconcat(opc ,
961 "($src1, $src2):<<1:rnd:sat")),
962 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
964 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
965 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
966 !strconcat("$dst = ", !strconcat(opc ,
967 "($src1, $src2):<<1:rnd:sat")),
968 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
970 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
971 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
972 !strconcat("$dst = ", !strconcat(opc ,
973 "($src1, $src2.L):<<1:rnd:sat")),
974 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
976 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
977 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
978 !strconcat("$dst = ", !strconcat(opc ,
979 "($src1, $src2.H):<<1:rnd:sat")),
980 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
982 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
983 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
984 !strconcat("$dst = ", !strconcat(opc ,
985 "($src1, $src2*):rnd:sat")),
986 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
988 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
989 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
990 !strconcat("$dst = ", !strconcat(opc ,
991 "($src1, $src2*):<<1:rnd:sat")),
992 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
994 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
995 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
996 !strconcat("$dst = ", !strconcat(opc ,
997 "($src1, $src2):rnd:sat")),
998 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1000 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1001 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1002 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1003 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1005 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1006 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1008 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1009 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1013 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1014 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1016 !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1017 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1021 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1022 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1024 !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1025 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1029 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1030 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1032 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1033 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1037 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1038 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1040 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1041 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1045 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1046 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1047 u4Imm:$src2, u5Imm:$src3),
1048 !strconcat("$dst = ", !strconcat(opc ,
1049 "($src1, #$src2, #$src3)")),
1050 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1051 imm:$src2, imm:$src3))],
1054 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1055 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1057 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1058 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1062 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1063 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1065 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1066 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1070 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1071 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1073 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1074 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1078 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1079 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1081 !strconcat("$dst += ", !strconcat(opc ,
1082 "($src1.L, $src2.H):sat")),
1083 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1087 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1088 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1090 !strconcat("$dst += ", !strconcat(opc ,
1091 "($src1.L, $src2.H):<<1:sat")),
1092 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1096 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1097 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1099 !strconcat("$dst += ", !strconcat(opc ,
1100 "($src1.H, $src2.H):sat")),
1101 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1105 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1106 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1108 !strconcat("$dst += ", !strconcat(opc ,
1109 "($src1.H, $src2.H):<<1:sat")),
1110 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1114 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1115 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1117 !strconcat("$dst += ", !strconcat(opc ,
1118 "($src1.H, $src2.H):<<1")),
1119 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1123 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1124 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1126 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1127 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1131 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1132 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1134 !strconcat("$dst -= ", !strconcat(opc ,
1135 "($src1.H, $src2.H):<<1:sat")),
1136 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1140 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1141 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1143 !strconcat("$dst -= ", !strconcat(opc ,
1144 "($src1.H, $src2.H):sat")),
1145 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1149 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1150 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1152 !strconcat("$dst -= ", !strconcat(opc ,
1153 "($src1.H, $src2.L):<<1:sat")),
1154 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1158 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1159 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1161 !strconcat("$dst -= ", !strconcat(opc ,
1162 "($src1.H, $src2.L):sat")),
1163 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1167 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1168 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1170 !strconcat("$dst -= ", !strconcat(opc ,
1171 "($src1.L, $src2.H):<<1:sat")),
1172 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1176 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1177 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1179 !strconcat("$dst -= ", !strconcat(opc ,
1180 "($src1.L, $src2.H):sat")),
1181 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1185 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1186 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1188 !strconcat("$dst -= ", !strconcat(opc ,
1189 "($src1.L, $src2.L):<<1:sat")),
1190 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1194 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1195 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1197 !strconcat("$dst -= ", !strconcat(opc ,
1198 "($src1.L, $src2.L):sat")),
1199 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1203 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1204 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1206 !strconcat("$dst -= ", !strconcat(opc ,
1207 "($src1.H, $src2.H):<<1")),
1208 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1212 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1213 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1215 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1216 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1220 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1221 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1223 !strconcat("$dst += ", !strconcat(opc ,
1224 "($src1.H, $src2.L):<<1")),
1225 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1229 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1230 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1232 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1233 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1237 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1238 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1240 !strconcat("$dst -= ", !strconcat(opc ,
1241 "($src1.H, $src2.L):<<1")),
1242 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1246 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1247 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1249 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1250 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1254 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1255 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1257 !strconcat("$dst += ", !strconcat(opc ,
1258 "($src1.L, $src2.H):<<1")),
1259 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1263 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1264 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1266 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1267 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1271 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1272 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1274 !strconcat("$dst -= ", !strconcat(opc ,
1275 "($src1.L, $src2.H):<<1")),
1276 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1280 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1281 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1283 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1284 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1288 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1289 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1291 !strconcat("$dst += ", !strconcat(opc ,
1292 "($src1.L, $src2.L):<<1")),
1293 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1297 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1298 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1300 !strconcat("$dst += ", !strconcat(opc ,
1301 "($src1.L, $src2.L):<<1:sat")),
1302 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1306 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1307 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1309 !strconcat("$dst += ", !strconcat(opc ,
1310 "($src1.H, $src2.L):<<1:sat")),
1311 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1315 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1316 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1318 !strconcat("$dst += ", !strconcat(opc ,
1319 "($src1.L, $src2.L):sat")),
1320 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1324 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1325 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1327 !strconcat("$dst += ", !strconcat(opc ,
1328 "($src1.H, $src2.L):sat")),
1329 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1333 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1334 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1336 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1337 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1341 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1342 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1344 !strconcat("$dst -= ", !strconcat(opc ,
1345 "($src1.L, $src2.L):<<1")),
1346 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1350 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1351 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1353 !strconcat("$dst -= ", !strconcat(opc ,
1354 "($src1.H, $src2.H):sat")),
1355 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1359 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1360 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1362 !strconcat("$dst -= ", !strconcat(opc ,
1363 "($src1.H, $src2.H):<<1:sat")),
1364 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1368 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1369 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1371 !strconcat("$dst -= ", !strconcat(opc ,
1372 "($src1.H, $src2.L):sat")),
1373 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1377 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1378 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1380 !strconcat("$dst -= ", !strconcat(opc ,
1381 "($src1.H, $src2.L):<<1:sat")),
1382 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1386 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1387 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1389 !strconcat("$dst -= ", !strconcat(opc ,
1390 "($src1.L, $src2.H):sat")),
1391 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1395 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1396 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1398 !strconcat("$dst -= ", !strconcat(opc ,
1399 "($src1.L, $src2.H):<<1:sat")),
1400 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1404 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1405 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1407 !strconcat("$dst -= ", !strconcat(opc ,
1408 "($src1.L, $src2.L):sat")),
1409 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1413 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1414 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1416 !strconcat("$dst -= ", !strconcat(opc ,
1417 "($src1.L, $src2.L):<<1:sat")),
1418 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1422 class di_ALU32_sisi<string opc, Intrinsic IntID>
1423 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1424 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1425 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1427 class di_MInst_sisi<string opc, Intrinsic IntID>
1428 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1429 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1430 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1432 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1433 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1434 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1435 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1437 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1438 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1439 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1440 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1442 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1443 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1444 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1445 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1447 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1448 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1449 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1450 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1451 DoubleRegs:$src2))]>;
1453 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1454 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1455 !strconcat("$dst = ", !strconcat(opc ,
1456 "($src1, $src2):<<1:rnd:sat")),
1457 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1459 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1460 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1461 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1462 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1464 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1465 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1466 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1467 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1469 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1470 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1471 !strconcat("$dst = ", !strconcat(opc ,
1472 "($src1.H, $src2.H):<<1:sat")),
1473 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1475 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1476 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1477 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1478 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1480 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1481 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1482 !strconcat("$dst = ", !strconcat(opc ,
1483 "($src1.H, $src2.L):<<1:sat")),
1484 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1486 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1487 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1488 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1489 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1491 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1492 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1493 !strconcat("$dst = ", !strconcat(opc ,
1494 "($src1.L, $src2.H):<<1:sat")),
1495 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1497 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1498 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1499 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1500 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1502 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1503 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1504 !strconcat("$dst = ", !strconcat(opc ,
1505 "($src1.L, $src2.L):<<1:sat")),
1506 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1508 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1509 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1510 !strconcat("$dst = ", !strconcat(opc ,
1511 "($src1.H, $src2.H):rnd:sat")),
1512 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1514 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1515 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1516 !strconcat("$dst = ", !strconcat(opc ,
1517 "($src1.H, $src2.H):rnd")),
1518 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1520 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1521 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1522 !strconcat("$dst = ", !strconcat(opc ,
1523 "($src1.H, $src2.H):<<1:rnd")),
1524 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1526 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1527 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1528 !strconcat("$dst = ",
1530 "($src1.H, $src2.H):<<1:rnd:sat")),
1531 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1533 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1534 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1535 !strconcat("$dst = ",
1536 !strconcat(opc , "($src1.H, $src2.L):rnd")),
1537 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1539 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1540 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1541 !strconcat("$dst = ",
1542 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1543 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1545 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1546 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1547 !strconcat("$dst = ",
1548 !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1549 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1551 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1552 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1553 !strconcat("$dst = ",
1554 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1555 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1557 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1558 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1559 !strconcat("$dst = ",
1560 !strconcat(opc , "($src1.L, $src2.H):rnd")),
1561 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1563 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1564 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1565 !strconcat("$dst = ",
1566 !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1567 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1569 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1570 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1571 !strconcat("$dst = ",
1572 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1573 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1575 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1576 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1577 !strconcat("$dst = ",
1578 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1579 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1581 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1582 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1583 !strconcat("$dst = ",
1584 !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1585 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1587 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1588 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1589 !strconcat("$dst = ",
1590 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1591 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1593 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1594 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1595 !strconcat("$dst = ",
1596 !strconcat(opc , "($src1.L, $src2.L):rnd")),
1597 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1599 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1600 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1601 !strconcat("$dst = ",
1602 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1603 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1605 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1606 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1607 DoubleRegs:$src1, DoubleRegs:$src2),
1608 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1609 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1611 DoubleRegs:$src2))],
1614 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1615 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1617 !strconcat("$dst += ",
1618 !strconcat(opc , "($src1, $src2):rnd:sat")),
1619 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1621 DoubleRegs:$src2))],
1624 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1625 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1628 !strconcat("$dst += ",
1629 !strconcat(opc , "($src1, $src2):<<1")),
1630 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1632 DoubleRegs:$src2))],
1636 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1637 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1640 !strconcat("$dst += ",
1641 !strconcat(opc , "($src1, $src2):<<1:sat")),
1642 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1644 DoubleRegs:$src2))],
1647 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1648 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1650 !strconcat("$dst += ",
1651 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1652 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1654 DoubleRegs:$src2))],
1657 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1658 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1660 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1661 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1663 DoubleRegs:$src2))],
1666 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1667 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1669 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1670 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1672 DoubleRegs:$src2))],
1675 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1676 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1678 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1679 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1683 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1684 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1686 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1687 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1691 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1692 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1694 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1695 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1699 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
1700 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1702 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1703 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1707 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
1708 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1710 !strconcat("$dst += ",
1711 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1712 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1716 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
1717 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1719 !strconcat("$dst += ",
1720 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1721 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1725 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
1726 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1728 !strconcat("$dst += ",
1729 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1730 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1734 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
1735 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1737 !strconcat("$dst += ",
1738 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1739 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1743 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
1744 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1746 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1747 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1751 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
1752 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1754 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1755 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1759 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
1760 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1762 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1763 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1767 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
1768 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1770 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1771 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1775 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
1776 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1778 !strconcat("$dst -= ",
1779 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1780 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1784 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
1785 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1787 !strconcat("$dst -= ",
1788 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1789 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1793 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
1794 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1796 !strconcat("$dst -= ",
1797 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1798 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1802 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
1803 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1805 !strconcat("$dst -= ",
1806 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1807 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1811 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
1812 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1814 !strconcat("$dst += ",
1815 !strconcat(opc , "($src1, $src2):<<1:sat")),
1816 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1820 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
1821 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1822 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1823 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1825 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
1826 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1828 !strconcat("$dst += ",
1829 !strconcat(opc , "($src1, $src2):<<1:sat")),
1830 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1835 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1836 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1837 !strconcat("$dst = ",
1838 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1839 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1841 class si_MInst_didi<string opc, Intrinsic IntID>
1842 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1843 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1844 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1849 let mayLoad = 1, neverHasSideEffects = 1 in
1850 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
1851 : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
1852 (ins IntRegs:$src1, IntRegs:$src2, CRRegs:$src3, s4Imm:$offset),
1853 "$dst2 = memd($src1++#$offset:circ($src3))",
1857 /********************************************************************
1859 *********************************************************************/
1861 // ALU32 / ALU / Add.
1863 si_ALU32_sisi <"add", int_hexagon_A2_add>;
1864 def HEXAGON_A2_addi:
1865 si_ALU32_sis16 <"add", int_hexagon_A2_addi>;
1867 // ALU32 / ALU / Logical operations.
1869 si_ALU32_sisi <"and", int_hexagon_A2_and>;
1870 def HEXAGON_A2_andir:
1871 si_ALU32_sis10 <"and", int_hexagon_A2_andir>;
1873 si_ALU32_si <"not", int_hexagon_A2_not>;
1875 si_ALU32_sisi <"or", int_hexagon_A2_or>;
1876 def HEXAGON_A2_orir:
1877 si_ALU32_sis10 <"or", int_hexagon_A2_orir>;
1879 si_ALU32_sisi <"xor", int_hexagon_A2_xor>;
1881 // ALU32 / ALU / Negate.
1883 si_ALU32_si <"neg", int_hexagon_A2_neg>;
1885 // ALU32 / ALU / Subtract.
1887 si_ALU32_sisi <"sub", int_hexagon_A2_sub>;
1888 def HEXAGON_A2_subri:
1889 si_ALU32_s10si <"sub", int_hexagon_A2_subri>;
1891 // ALU32 / ALU / Transfer Immediate.
1892 def HEXAGON_A2_tfril:
1893 si_lo_ALU32_siu16 <"", int_hexagon_A2_tfril>;
1894 def HEXAGON_A2_tfrih:
1895 si_hi_ALU32_siu16 <"", int_hexagon_A2_tfrih>;
1896 def HEXAGON_A2_tfrsi:
1897 si_ALU32_s16 <"", int_hexagon_A2_tfrsi>;
1898 def HEXAGON_A2_tfrpi:
1899 di_ALU32_s8 <"", int_hexagon_A2_tfrpi>;
1901 // ALU32 / ALU / Transfer Register.
1903 si_ALU32_si_tfr <"", int_hexagon_A2_tfr>;
1905 /********************************************************************
1907 *********************************************************************/
1909 // ALU32 / PERM / Combine.
1910 def HEXAGON_A2_combinew:
1911 di_ALU32_sisi <"combine", int_hexagon_A2_combinew>;
1912 def HEXAGON_A2_combine_hh:
1913 si_MInst_sisi_hh <"combine", int_hexagon_A2_combine_hh>;
1914 def HEXAGON_A2_combine_lh:
1915 si_MInst_sisi_lh <"combine", int_hexagon_A2_combine_lh>;
1916 def HEXAGON_A2_combine_hl:
1917 si_MInst_sisi_hl <"combine", int_hexagon_A2_combine_hl>;
1918 def HEXAGON_A2_combine_ll:
1919 si_MInst_sisi_ll <"combine", int_hexagon_A2_combine_ll>;
1920 def HEXAGON_A2_combineii:
1921 di_MInst_s8s8 <"combine", int_hexagon_A2_combineii>;
1923 // ALU32 / PERM / Mux.
1925 si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
1926 def HEXAGON_C2_muxri:
1927 si_ALU32_qis8si <"mux", int_hexagon_C2_muxri>;
1928 def HEXAGON_C2_muxir:
1929 si_ALU32_qisis8 <"mux", int_hexagon_C2_muxir>;
1930 def HEXAGON_C2_muxii:
1931 si_ALU32_qis8s8 <"mux", int_hexagon_C2_muxii>;
1933 // ALU32 / PERM / Shift halfword.
1934 def HEXAGON_A2_aslh:
1935 si_ALU32_si <"aslh", int_hexagon_A2_aslh>;
1936 def HEXAGON_A2_asrh:
1937 si_ALU32_si <"asrh", int_hexagon_A2_asrh>;
1938 def SI_to_SXTHI_asrh:
1939 si_ALU32_si <"asrh", int_hexagon_SI_to_SXTHI_asrh>;
1941 // ALU32 / PERM / Sign/zero extend.
1942 def HEXAGON_A2_sxth:
1943 si_ALU32_si <"sxth", int_hexagon_A2_sxth>;
1944 def HEXAGON_A2_sxtb:
1945 si_ALU32_si <"sxtb", int_hexagon_A2_sxtb>;
1946 def HEXAGON_A2_zxth:
1947 si_ALU32_si <"zxth", int_hexagon_A2_zxth>;
1948 def HEXAGON_A2_zxtb:
1949 si_ALU32_si <"zxtb", int_hexagon_A2_zxtb>;
1951 /********************************************************************
1953 *********************************************************************/
1955 // ALU32 / PRED / Compare.
1956 def HEXAGON_C2_cmpeq:
1957 qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
1958 def HEXAGON_C2_cmpeqi:
1959 qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
1960 def HEXAGON_C2_cmpgei:
1961 qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
1962 def HEXAGON_C2_cmpgeui:
1963 qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
1964 def HEXAGON_C2_cmpgt:
1965 qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
1966 def HEXAGON_C2_cmpgti:
1967 qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
1968 def HEXAGON_C2_cmpgtu:
1969 qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
1970 def HEXAGON_C2_cmpgtui:
1971 qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
1972 def HEXAGON_C2_cmplt:
1973 qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
1974 def HEXAGON_C2_cmpltu:
1975 qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
1977 /********************************************************************
1979 *********************************************************************/
1981 // ALU32 / VH / Vector add halfwords.
1982 // Rd32=vadd[u]h(Rs32,Rt32:sat]
1983 def HEXAGON_A2_svaddh:
1984 si_ALU32_sisi <"vaddh", int_hexagon_A2_svaddh>;
1985 def HEXAGON_A2_svaddhs:
1986 si_ALU32_sisi_sat <"vaddh", int_hexagon_A2_svaddhs>;
1987 def HEXAGON_A2_svadduhs:
1988 si_ALU32_sisi_sat <"vadduh", int_hexagon_A2_svadduhs>;
1990 // ALU32 / VH / Vector average halfwords.
1991 def HEXAGON_A2_svavgh:
1992 si_ALU32_sisi <"vavgh", int_hexagon_A2_svavgh>;
1993 def HEXAGON_A2_svavghs:
1994 si_ALU32_sisi_rnd <"vavgh", int_hexagon_A2_svavghs>;
1995 def HEXAGON_A2_svnavgh:
1996 si_ALU32_sisi <"vnavgh", int_hexagon_A2_svnavgh>;
1998 // ALU32 / VH / Vector subtract halfwords.
1999 def HEXAGON_A2_svsubh:
2000 si_ALU32_sisi <"vsubh", int_hexagon_A2_svsubh>;
2001 def HEXAGON_A2_svsubhs:
2002 si_ALU32_sisi_sat <"vsubh", int_hexagon_A2_svsubhs>;
2003 def HEXAGON_A2_svsubuhs:
2004 si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
2006 /********************************************************************
2008 *********************************************************************/
2010 // ALU64 / ALU / Add.
2011 def HEXAGON_A2_addp:
2012 di_ALU64_didi <"add", int_hexagon_A2_addp>;
2013 def HEXAGON_A2_addsat:
2014 si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>;
2016 // ALU64 / ALU / Add halfword.
2017 // Even though the definition says hl, it should be lh -
2018 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2019 def HEXAGON_A2_addh_l16_hl:
2020 si_ALU64_sisi_l16_lh <"add", int_hexagon_A2_addh_l16_hl>;
2021 def HEXAGON_A2_addh_l16_ll:
2022 si_ALU64_sisi_l16_ll <"add", int_hexagon_A2_addh_l16_ll>;
2024 def HEXAGON_A2_addh_l16_sat_hl:
2025 si_ALU64_sisi_l16_sat_lh <"add", int_hexagon_A2_addh_l16_sat_hl>;
2026 def HEXAGON_A2_addh_l16_sat_ll:
2027 si_ALU64_sisi_l16_sat_ll <"add", int_hexagon_A2_addh_l16_sat_ll>;
2029 def HEXAGON_A2_addh_h16_hh:
2030 si_ALU64_sisi_h16_hh <"add", int_hexagon_A2_addh_h16_hh>;
2031 def HEXAGON_A2_addh_h16_hl:
2032 si_ALU64_sisi_h16_hl <"add", int_hexagon_A2_addh_h16_hl>;
2033 def HEXAGON_A2_addh_h16_lh:
2034 si_ALU64_sisi_h16_lh <"add", int_hexagon_A2_addh_h16_lh>;
2035 def HEXAGON_A2_addh_h16_ll:
2036 si_ALU64_sisi_h16_ll <"add", int_hexagon_A2_addh_h16_ll>;
2038 def HEXAGON_A2_addh_h16_sat_hh:
2039 si_ALU64_sisi_h16_sat_hh <"add", int_hexagon_A2_addh_h16_sat_hh>;
2040 def HEXAGON_A2_addh_h16_sat_hl:
2041 si_ALU64_sisi_h16_sat_hl <"add", int_hexagon_A2_addh_h16_sat_hl>;
2042 def HEXAGON_A2_addh_h16_sat_lh:
2043 si_ALU64_sisi_h16_sat_lh <"add", int_hexagon_A2_addh_h16_sat_lh>;
2044 def HEXAGON_A2_addh_h16_sat_ll:
2045 si_ALU64_sisi_h16_sat_ll <"add", int_hexagon_A2_addh_h16_sat_ll>;
2047 // ALU64 / ALU / Compare.
2048 def HEXAGON_C2_cmpeqp:
2049 qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
2050 def HEXAGON_C2_cmpgtp:
2051 qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
2052 def HEXAGON_C2_cmpgtup:
2053 qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
2055 // ALU64 / ALU / Logical operations.
2056 def HEXAGON_A2_andp:
2057 di_ALU64_didi <"and", int_hexagon_A2_andp>;
2059 di_ALU64_didi <"or", int_hexagon_A2_orp>;
2060 def HEXAGON_A2_xorp:
2061 di_ALU64_didi <"xor", int_hexagon_A2_xorp>;
2063 // ALU64 / ALU / Maximum.
2065 si_ALU64_sisi <"max", int_hexagon_A2_max>;
2066 def HEXAGON_A2_maxu:
2067 si_ALU64_sisi <"maxu", int_hexagon_A2_maxu>;
2069 // ALU64 / ALU / Minimum.
2071 si_ALU64_sisi <"min", int_hexagon_A2_min>;
2072 def HEXAGON_A2_minu:
2073 si_ALU64_sisi <"minu", int_hexagon_A2_minu>;
2075 // ALU64 / ALU / Subtract.
2076 def HEXAGON_A2_subp:
2077 di_ALU64_didi <"sub", int_hexagon_A2_subp>;
2078 def HEXAGON_A2_subsat:
2079 si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>;
2081 // ALU64 / ALU / Subtract halfword.
2082 // Even though the definition says hl, it should be lh -
2083 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2084 def HEXAGON_A2_subh_l16_hl:
2085 si_ALU64_sisi_l16_lh <"sub", int_hexagon_A2_subh_l16_hl>;
2086 def HEXAGON_A2_subh_l16_ll:
2087 si_ALU64_sisi_l16_ll <"sub", int_hexagon_A2_subh_l16_ll>;
2089 def HEXAGON_A2_subh_l16_sat_hl:
2090 si_ALU64_sisi_l16_sat_lh <"sub", int_hexagon_A2_subh_l16_sat_hl>;
2091 def HEXAGON_A2_subh_l16_sat_ll:
2092 si_ALU64_sisi_l16_sat_ll <"sub", int_hexagon_A2_subh_l16_sat_ll>;
2094 def HEXAGON_A2_subh_h16_hh:
2095 si_ALU64_sisi_h16_hh <"sub", int_hexagon_A2_subh_h16_hh>;
2096 def HEXAGON_A2_subh_h16_hl:
2097 si_ALU64_sisi_h16_hl <"sub", int_hexagon_A2_subh_h16_hl>;
2098 def HEXAGON_A2_subh_h16_lh:
2099 si_ALU64_sisi_h16_lh <"sub", int_hexagon_A2_subh_h16_lh>;
2100 def HEXAGON_A2_subh_h16_ll:
2101 si_ALU64_sisi_h16_ll <"sub", int_hexagon_A2_subh_h16_ll>;
2103 def HEXAGON_A2_subh_h16_sat_hh:
2104 si_ALU64_sisi_h16_sat_hh <"sub", int_hexagon_A2_subh_h16_sat_hh>;
2105 def HEXAGON_A2_subh_h16_sat_hl:
2106 si_ALU64_sisi_h16_sat_hl <"sub", int_hexagon_A2_subh_h16_sat_hl>;
2107 def HEXAGON_A2_subh_h16_sat_lh:
2108 si_ALU64_sisi_h16_sat_lh <"sub", int_hexagon_A2_subh_h16_sat_lh>;
2109 def HEXAGON_A2_subh_h16_sat_ll:
2110 si_ALU64_sisi_h16_sat_ll <"sub", int_hexagon_A2_subh_h16_sat_ll>;
2112 // ALU64 / ALU / Transfer register.
2113 def HEXAGON_A2_tfrp:
2114 di_ALU64_di <"", int_hexagon_A2_tfrp>;
2116 /********************************************************************
2118 *********************************************************************/
2120 // ALU64 / BIT / Masked parity.
2121 def HEXAGON_S2_parityp:
2122 si_ALU64_didi <"parity", int_hexagon_S2_parityp>;
2124 /********************************************************************
2126 *********************************************************************/
2128 // ALU64 / PERM / Vector pack high and low halfwords.
2129 def HEXAGON_S2_packhl:
2130 di_ALU64_sisi <"packhl", int_hexagon_S2_packhl>;
2132 /********************************************************************
2134 *********************************************************************/
2136 // ALU64 / VB / Vector add unsigned bytes.
2137 def HEXAGON_A2_vaddub:
2138 di_ALU64_didi <"vaddub", int_hexagon_A2_vaddub>;
2139 def HEXAGON_A2_vaddubs:
2140 di_ALU64_didi_sat <"vaddub", int_hexagon_A2_vaddubs>;
2142 // ALU64 / VB / Vector average unsigned bytes.
2143 def HEXAGON_A2_vavgub:
2144 di_ALU64_didi <"vavgub", int_hexagon_A2_vavgub>;
2145 def HEXAGON_A2_vavgubr:
2146 di_ALU64_didi_rnd <"vavgub", int_hexagon_A2_vavgubr>;
2148 // ALU64 / VB / Vector compare unsigned bytes.
2149 def HEXAGON_A2_vcmpbeq:
2150 qi_ALU64_didi <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2151 def HEXAGON_A2_vcmpbgtu:
2152 qi_ALU64_didi <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2154 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2155 def HEXAGON_A2_vmaxub:
2156 di_ALU64_didi <"vmaxub", int_hexagon_A2_vmaxub>;
2157 def HEXAGON_A2_vminub:
2158 di_ALU64_didi <"vminub", int_hexagon_A2_vminub>;
2160 // ALU64 / VB / Vector subtract unsigned bytes.
2161 def HEXAGON_A2_vsubub:
2162 di_ALU64_didi <"vsubub", int_hexagon_A2_vsubub>;
2163 def HEXAGON_A2_vsububs:
2164 di_ALU64_didi_sat <"vsubub", int_hexagon_A2_vsububs>;
2166 // ALU64 / VB / Vector mux.
2167 def HEXAGON_C2_vmux:
2168 di_ALU64_qididi <"vmux", int_hexagon_C2_vmux>;
2171 /********************************************************************
2173 *********************************************************************/
2175 // ALU64 / VH / Vector add halfwords.
2176 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2177 def HEXAGON_A2_vaddh:
2178 di_ALU64_didi <"vaddh", int_hexagon_A2_vaddh>;
2179 def HEXAGON_A2_vaddhs:
2180 di_ALU64_didi_sat <"vaddh", int_hexagon_A2_vaddhs>;
2181 def HEXAGON_A2_vadduhs:
2182 di_ALU64_didi_sat <"vadduh", int_hexagon_A2_vadduhs>;
2184 // ALU64 / VH / Vector average halfwords.
2185 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2186 def HEXAGON_A2_vavgh:
2187 di_ALU64_didi <"vavgh", int_hexagon_A2_vavgh>;
2188 def HEXAGON_A2_vavghcr:
2189 di_ALU64_didi_crnd <"vavgh", int_hexagon_A2_vavghcr>;
2190 def HEXAGON_A2_vavghr:
2191 di_ALU64_didi_rnd <"vavgh", int_hexagon_A2_vavghr>;
2192 def HEXAGON_A2_vavguh:
2193 di_ALU64_didi <"vavguh", int_hexagon_A2_vavguh>;
2194 def HEXAGON_A2_vavguhr:
2195 di_ALU64_didi_rnd <"vavguh", int_hexagon_A2_vavguhr>;
2196 def HEXAGON_A2_vnavgh:
2197 di_ALU64_didi <"vnavgh", int_hexagon_A2_vnavgh>;
2198 def HEXAGON_A2_vnavghcr:
2199 di_ALU64_didi_crnd_sat <"vnavgh", int_hexagon_A2_vnavghcr>;
2200 def HEXAGON_A2_vnavghr:
2201 di_ALU64_didi_rnd_sat <"vnavgh", int_hexagon_A2_vnavghr>;
2203 // ALU64 / VH / Vector compare halfwords.
2204 def HEXAGON_A2_vcmpheq:
2205 qi_ALU64_didi <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2206 def HEXAGON_A2_vcmphgt:
2207 qi_ALU64_didi <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2208 def HEXAGON_A2_vcmphgtu:
2209 qi_ALU64_didi <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2211 // ALU64 / VH / Vector maximum halfwords.
2212 def HEXAGON_A2_vmaxh:
2213 di_ALU64_didi <"vmaxh", int_hexagon_A2_vmaxh>;
2214 def HEXAGON_A2_vmaxuh:
2215 di_ALU64_didi <"vmaxuh", int_hexagon_A2_vmaxuh>;
2217 // ALU64 / VH / Vector minimum halfwords.
2218 def HEXAGON_A2_vminh:
2219 di_ALU64_didi <"vminh", int_hexagon_A2_vminh>;
2220 def HEXAGON_A2_vminuh:
2221 di_ALU64_didi <"vminuh", int_hexagon_A2_vminuh>;
2223 // ALU64 / VH / Vector subtract halfwords.
2224 def HEXAGON_A2_vsubh:
2225 di_ALU64_didi <"vsubh", int_hexagon_A2_vsubh>;
2226 def HEXAGON_A2_vsubhs:
2227 di_ALU64_didi_sat <"vsubh", int_hexagon_A2_vsubhs>;
2228 def HEXAGON_A2_vsubuhs:
2229 di_ALU64_didi_sat <"vsubuh", int_hexagon_A2_vsubuhs>;
2232 /********************************************************************
2234 *********************************************************************/
2236 // ALU64 / VW / Vector add words.
2237 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2238 def HEXAGON_A2_vaddw:
2239 di_ALU64_didi <"vaddw", int_hexagon_A2_vaddw>;
2240 def HEXAGON_A2_vaddws:
2241 di_ALU64_didi_sat <"vaddw", int_hexagon_A2_vaddws>;
2243 // ALU64 / VW / Vector average words.
2244 def HEXAGON_A2_vavguw:
2245 di_ALU64_didi <"vavguw", int_hexagon_A2_vavguw>;
2246 def HEXAGON_A2_vavguwr:
2247 di_ALU64_didi_rnd <"vavguw", int_hexagon_A2_vavguwr>;
2248 def HEXAGON_A2_vavgw:
2249 di_ALU64_didi <"vavgw", int_hexagon_A2_vavgw>;
2250 def HEXAGON_A2_vavgwcr:
2251 di_ALU64_didi_crnd <"vavgw", int_hexagon_A2_vavgwcr>;
2252 def HEXAGON_A2_vavgwr:
2253 di_ALU64_didi_rnd <"vavgw", int_hexagon_A2_vavgwr>;
2254 def HEXAGON_A2_vnavgw:
2255 di_ALU64_didi <"vnavgw", int_hexagon_A2_vnavgw>;
2256 def HEXAGON_A2_vnavgwcr:
2257 di_ALU64_didi_crnd_sat <"vnavgw", int_hexagon_A2_vnavgwcr>;
2258 def HEXAGON_A2_vnavgwr:
2259 di_ALU64_didi_rnd_sat <"vnavgw", int_hexagon_A2_vnavgwr>;
2261 // ALU64 / VW / Vector compare words.
2262 def HEXAGON_A2_vcmpweq:
2263 qi_ALU64_didi <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2264 def HEXAGON_A2_vcmpwgt:
2265 qi_ALU64_didi <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2266 def HEXAGON_A2_vcmpwgtu:
2267 qi_ALU64_didi <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2269 // ALU64 / VW / Vector maximum words.
2270 def HEXAGON_A2_vmaxw:
2271 di_ALU64_didi <"vmaxw", int_hexagon_A2_vmaxw>;
2272 def HEXAGON_A2_vmaxuw:
2273 di_ALU64_didi <"vmaxuw", int_hexagon_A2_vmaxuw>;
2275 // ALU64 / VW / Vector minimum words.
2276 def HEXAGON_A2_vminw:
2277 di_ALU64_didi <"vminw", int_hexagon_A2_vminw>;
2278 def HEXAGON_A2_vminuw:
2279 di_ALU64_didi <"vminuw", int_hexagon_A2_vminuw>;
2281 // ALU64 / VW / Vector subtract words.
2282 def HEXAGON_A2_vsubw:
2283 di_ALU64_didi <"vsubw", int_hexagon_A2_vsubw>;
2284 def HEXAGON_A2_vsubws:
2285 di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
2288 /********************************************************************
2290 *********************************************************************/
2292 // CR / Logical reductions on predicates.
2293 def HEXAGON_C2_all8:
2294 qi_SInst_qi <"all8", int_hexagon_C2_all8>;
2295 def HEXAGON_C2_any8:
2296 qi_SInst_qi <"any8", int_hexagon_C2_any8>;
2298 // CR / Logical operations on predicates.
2299 def HEXAGON_C2_pxfer_map:
2300 qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
2302 qi_SInst_qiqi <"and", int_hexagon_C2_and>;
2303 def HEXAGON_C2_andn:
2304 qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
2306 qi_SInst_qi <"not", int_hexagon_C2_not>;
2308 qi_SInst_qiqi <"or", int_hexagon_C2_or>;
2310 qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
2312 qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
2315 /********************************************************************
2317 *********************************************************************/
2319 // MTYPE / ALU / Add and accumulate.
2320 def HEXAGON_M2_acci:
2321 si_MInst_sisisi_acc <"add", int_hexagon_M2_acci>;
2322 def HEXAGON_M2_accii:
2323 si_MInst_sisis8_acc <"add", int_hexagon_M2_accii>;
2324 def HEXAGON_M2_nacci:
2325 si_MInst_sisisi_nac <"add", int_hexagon_M2_nacci>;
2326 def HEXAGON_M2_naccii:
2327 si_MInst_sisis8_nac <"add", int_hexagon_M2_naccii>;
2329 // MTYPE / ALU / Subtract and accumulate.
2330 def HEXAGON_M2_subacc:
2331 si_MInst_sisisi_acc <"sub", int_hexagon_M2_subacc>;
2333 // MTYPE / ALU / Vector absolute difference.
2334 def HEXAGON_M2_vabsdiffh:
2335 di_MInst_didi <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2336 def HEXAGON_M2_vabsdiffw:
2337 di_MInst_didi <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2339 // MTYPE / ALU / XOR and xor with destination.
2340 def HEXAGON_M2_xor_xacc:
2341 si_MInst_sisisi_xacc <"xor", int_hexagon_M2_xor_xacc>;
2344 /********************************************************************
2346 *********************************************************************/
2348 // MTYPE / COMPLEX / Complex multiply.
2349 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2350 def HEXAGON_M2_cmpys_s1:
2351 di_MInst_sisi_s1_sat <"cmpy", int_hexagon_M2_cmpys_s1>;
2352 def HEXAGON_M2_cmpys_s0:
2353 di_MInst_sisi_sat <"cmpy", int_hexagon_M2_cmpys_s0>;
2354 def HEXAGON_M2_cmpysc_s1:
2355 di_MInst_sisi_s1_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s1>;
2356 def HEXAGON_M2_cmpysc_s0:
2357 di_MInst_sisi_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s0>;
2359 def HEXAGON_M2_cmacs_s1:
2360 di_MInst_disisi_acc_s1_sat <"cmpy", int_hexagon_M2_cmacs_s1>;
2361 def HEXAGON_M2_cmacs_s0:
2362 di_MInst_disisi_acc_sat <"cmpy", int_hexagon_M2_cmacs_s0>;
2363 def HEXAGON_M2_cmacsc_s1:
2364 di_MInst_disisi_acc_s1_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s1>;
2365 def HEXAGON_M2_cmacsc_s0:
2366 di_MInst_disisi_acc_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s0>;
2368 def HEXAGON_M2_cnacs_s1:
2369 di_MInst_disisi_nac_s1_sat <"cmpy", int_hexagon_M2_cnacs_s1>;
2370 def HEXAGON_M2_cnacs_s0:
2371 di_MInst_disisi_nac_sat <"cmpy", int_hexagon_M2_cnacs_s0>;
2372 def HEXAGON_M2_cnacsc_s1:
2373 di_MInst_disisi_nac_s1_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s1>;
2374 def HEXAGON_M2_cnacsc_s0:
2375 di_MInst_disisi_nac_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s0>;
2377 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2378 def HEXAGON_M2_cmpyr_s0:
2379 di_MInst_sisi <"cmpyr", int_hexagon_M2_cmpyr_s0>;
2380 def HEXAGON_M2_cmacr_s0:
2381 di_MInst_disisi_acc <"cmpyr", int_hexagon_M2_cmacr_s0>;
2383 def HEXAGON_M2_cmpyi_s0:
2384 di_MInst_sisi <"cmpyi", int_hexagon_M2_cmpyi_s0>;
2385 def HEXAGON_M2_cmaci_s0:
2386 di_MInst_disisi_acc <"cmpyi", int_hexagon_M2_cmaci_s0>;
2388 // MTYPE / COMPLEX / Complex multiply with round and pack.
2389 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2390 def HEXAGON_M2_cmpyrs_s0:
2391 si_MInst_sisi_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s0>;
2392 def HEXAGON_M2_cmpyrs_s1:
2393 si_MInst_sisi_s1_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s1>;
2395 def HEXAGON_M2_cmpyrsc_s0:
2396 si_MInst_sisi_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s0>;
2397 def HEXAGON_M2_cmpyrsc_s1:
2398 si_MInst_sisi_s1_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s1>;
2400 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2401 def HEXAGON_M2_vcmpy_s0_sat_i:
2402 di_MInst_didi_sat <"vcmpyi", int_hexagon_M2_vcmpy_s0_sat_i>;
2403 def HEXAGON_M2_vcmpy_s1_sat_i:
2404 di_MInst_didi_s1_sat <"vcmpyi", int_hexagon_M2_vcmpy_s1_sat_i>;
2406 def HEXAGON_M2_vcmpy_s0_sat_r:
2407 di_MInst_didi_sat <"vcmpyr", int_hexagon_M2_vcmpy_s0_sat_r>;
2408 def HEXAGON_M2_vcmpy_s1_sat_r:
2409 di_MInst_didi_s1_sat <"vcmpyr", int_hexagon_M2_vcmpy_s1_sat_r>;
2411 def HEXAGON_M2_vcmac_s0_sat_i:
2412 di_MInst_dididi_acc_sat <"vcmpyi", int_hexagon_M2_vcmac_s0_sat_i>;
2413 def HEXAGON_M2_vcmac_s0_sat_r:
2414 di_MInst_dididi_acc_sat <"vcmpyr", int_hexagon_M2_vcmac_s0_sat_r>;
2416 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2417 def HEXAGON_M2_vrcmpyi_s0:
2418 di_MInst_didi <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0>;
2419 def HEXAGON_M2_vrcmpyr_s0:
2420 di_MInst_didi <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0>;
2422 def HEXAGON_M2_vrcmpyi_s0c:
2423 di_MInst_didi_conj <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0c>;
2424 def HEXAGON_M2_vrcmpyr_s0c:
2425 di_MInst_didi_conj <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0c>;
2427 def HEXAGON_M2_vrcmaci_s0:
2428 di_MInst_dididi_acc <"vrcmpyi", int_hexagon_M2_vrcmaci_s0>;
2429 def HEXAGON_M2_vrcmacr_s0:
2430 di_MInst_dididi_acc <"vrcmpyr", int_hexagon_M2_vrcmacr_s0>;
2432 def HEXAGON_M2_vrcmaci_s0c:
2433 di_MInst_dididi_acc_conj <"vrcmpyi", int_hexagon_M2_vrcmaci_s0c>;
2434 def HEXAGON_M2_vrcmacr_s0c:
2435 di_MInst_dididi_acc_conj <"vrcmpyr", int_hexagon_M2_vrcmacr_s0c>;
2438 /********************************************************************
2440 *********************************************************************/
2442 // MTYPE / MPYH / Multiply and use lower result.
2443 //def HEXAGON_M2_mpysmi:
2444 //FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
2445 // not si_MInst_sis9 - but for now, we will use s9.
2446 // def Hexagon_M2_mpysmi:
2447 // si_MInst_sim9 <"mpyi", int_hexagon_M2_mpysmi>;
2448 def Hexagon_M2_mpysmi:
2449 si_MInst_sis9 <"mpyi", int_hexagon_M2_mpysmi>;
2450 def HEXAGON_M2_mpyi:
2451 si_MInst_sisi <"mpyi", int_hexagon_M2_mpyi>;
2452 def HEXAGON_M2_mpyui:
2453 si_MInst_sisi <"mpyui", int_hexagon_M2_mpyui>;
2454 def HEXAGON_M2_macsip:
2455 si_MInst_sisiu8_acc <"mpyi", int_hexagon_M2_macsip>;
2456 def HEXAGON_M2_maci:
2457 si_MInst_sisisi_acc <"mpyi", int_hexagon_M2_maci>;
2458 def HEXAGON_M2_macsin:
2459 si_MInst_sisiu8_nac <"mpyi", int_hexagon_M2_macsin>;
2461 // MTYPE / MPYH / Multiply word by half (32x16).
2462 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2463 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2464 def HEXAGON_M2_mmpyl_rs1:
2465 di_MInst_didi_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs1>;
2466 def HEXAGON_M2_mmpyl_s1:
2467 di_MInst_didi_s1_sat <"vmpyweh", int_hexagon_M2_mmpyl_s1>;
2468 def HEXAGON_M2_mmpyl_rs0:
2469 di_MInst_didi_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs0>;
2470 def HEXAGON_M2_mmpyl_s0:
2471 di_MInst_didi_sat <"vmpyweh", int_hexagon_M2_mmpyl_s0>;
2472 def HEXAGON_M2_mmpyh_rs1:
2473 di_MInst_didi_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs1>;
2474 def HEXAGON_M2_mmpyh_s1:
2475 di_MInst_didi_s1_sat <"vmpywoh", int_hexagon_M2_mmpyh_s1>;
2476 def HEXAGON_M2_mmpyh_rs0:
2477 di_MInst_didi_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs0>;
2478 def HEXAGON_M2_mmpyh_s0:
2479 di_MInst_didi_sat <"vmpywoh", int_hexagon_M2_mmpyh_s0>;
2480 def HEXAGON_M2_mmacls_rs1:
2481 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs1>;
2482 def HEXAGON_M2_mmacls_s1:
2483 di_MInst_dididi_acc_s1_sat <"vmpyweh", int_hexagon_M2_mmacls_s1>;
2484 def HEXAGON_M2_mmacls_rs0:
2485 di_MInst_dididi_acc_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs0>;
2486 def HEXAGON_M2_mmacls_s0:
2487 di_MInst_dididi_acc_sat <"vmpyweh", int_hexagon_M2_mmacls_s0>;
2488 def HEXAGON_M2_mmachs_rs1:
2489 di_MInst_dididi_acc_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs1>;
2490 def HEXAGON_M2_mmachs_s1:
2491 di_MInst_dididi_acc_s1_sat <"vmpywoh", int_hexagon_M2_mmachs_s1>;
2492 def HEXAGON_M2_mmachs_rs0:
2493 di_MInst_dididi_acc_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs0>;
2494 def HEXAGON_M2_mmachs_s0:
2495 di_MInst_dididi_acc_sat <"vmpywoh", int_hexagon_M2_mmachs_s0>;
2497 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2498 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2499 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2500 def HEXAGON_M2_mmpyul_rs1:
2501 di_MInst_didi_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2502 def HEXAGON_M2_mmpyul_s1:
2503 di_MInst_didi_s1_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2504 def HEXAGON_M2_mmpyul_rs0:
2505 di_MInst_didi_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2506 def HEXAGON_M2_mmpyul_s0:
2507 di_MInst_didi_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2508 def HEXAGON_M2_mmpyuh_rs1:
2509 di_MInst_didi_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2510 def HEXAGON_M2_mmpyuh_s1:
2511 di_MInst_didi_s1_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2512 def HEXAGON_M2_mmpyuh_rs0:
2513 di_MInst_didi_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2514 def HEXAGON_M2_mmpyuh_s0:
2515 di_MInst_didi_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2516 def HEXAGON_M2_mmaculs_rs1:
2517 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2518 def HEXAGON_M2_mmaculs_s1:
2519 di_MInst_dididi_acc_s1_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2520 def HEXAGON_M2_mmaculs_rs0:
2521 di_MInst_dididi_acc_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2522 def HEXAGON_M2_mmaculs_s0:
2523 di_MInst_dididi_acc_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2524 def HEXAGON_M2_mmacuhs_rs1:
2525 di_MInst_dididi_acc_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2526 def HEXAGON_M2_mmacuhs_s1:
2527 di_MInst_dididi_acc_s1_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2528 def HEXAGON_M2_mmacuhs_rs0:
2529 di_MInst_dididi_acc_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2530 def HEXAGON_M2_mmacuhs_s0:
2531 di_MInst_dididi_acc_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2533 // MTYPE / MPYH / Multiply and use upper result.
2534 def HEXAGON_M2_hmmpyh_rs1:
2535 si_MInst_sisi_h_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyh_rs1>;
2536 def HEXAGON_M2_hmmpyl_rs1:
2537 si_MInst_sisi_l_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyl_rs1>;
2538 def HEXAGON_M2_mpy_up:
2539 si_MInst_sisi <"mpy", int_hexagon_M2_mpy_up>;
2540 def HEXAGON_M2_dpmpyss_rnd_s0:
2541 si_MInst_sisi_rnd <"mpy", int_hexagon_M2_dpmpyss_rnd_s0>;
2542 def HEXAGON_M2_mpyu_up:
2543 si_MInst_sisi <"mpyu", int_hexagon_M2_mpyu_up>;
2545 // MTYPE / MPYH / Multiply and use full result.
2546 def HEXAGON_M2_dpmpyuu_s0:
2547 di_MInst_sisi <"mpyu", int_hexagon_M2_dpmpyuu_s0>;
2548 def HEXAGON_M2_dpmpyuu_acc_s0:
2549 di_MInst_disisi_acc <"mpyu", int_hexagon_M2_dpmpyuu_acc_s0>;
2550 def HEXAGON_M2_dpmpyuu_nac_s0:
2551 di_MInst_disisi_nac <"mpyu", int_hexagon_M2_dpmpyuu_nac_s0>;
2552 def HEXAGON_M2_dpmpyss_s0:
2553 di_MInst_sisi <"mpy", int_hexagon_M2_dpmpyss_s0>;
2554 def HEXAGON_M2_dpmpyss_acc_s0:
2555 di_MInst_disisi_acc <"mpy", int_hexagon_M2_dpmpyss_acc_s0>;
2556 def HEXAGON_M2_dpmpyss_nac_s0:
2557 di_MInst_disisi_nac <"mpy", int_hexagon_M2_dpmpyss_nac_s0>;
2560 /********************************************************************
2562 *********************************************************************/
2564 // MTYPE / MPYS / Scalar 16x16 multiply signed.
2565 //Rd=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]|
2566 // [:<<0[:rnd|:sat|:rnd:sat]|:<<1[:rnd|:sat|:rnd:sat]]]
2567 def HEXAGON_M2_mpy_hh_s0:
2568 si_MInst_sisi_hh <"mpy", int_hexagon_M2_mpy_hh_s0>;
2569 def HEXAGON_M2_mpy_hh_s1:
2570 si_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpy_hh_s1>;
2571 def HEXAGON_M2_mpy_rnd_hh_s1:
2572 si_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_rnd_hh_s1>;
2573 def HEXAGON_M2_mpy_sat_rnd_hh_s1:
2574 si_MInst_sisi_sat_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s1>;
2575 def HEXAGON_M2_mpy_sat_hh_s1:
2576 si_MInst_sisi_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_hh_s1>;
2577 def HEXAGON_M2_mpy_rnd_hh_s0:
2578 si_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpy_rnd_hh_s0>;
2579 def HEXAGON_M2_mpy_sat_rnd_hh_s0:
2580 si_MInst_sisi_sat_rnd_hh <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s0>;
2581 def HEXAGON_M2_mpy_sat_hh_s0:
2582 si_MInst_sisi_sat_hh <"mpy", int_hexagon_M2_mpy_sat_hh_s0>;
2584 def HEXAGON_M2_mpy_hl_s0:
2585 si_MInst_sisi_hl <"mpy", int_hexagon_M2_mpy_hl_s0>;
2586 def HEXAGON_M2_mpy_hl_s1:
2587 si_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpy_hl_s1>;
2588 def HEXAGON_M2_mpy_rnd_hl_s1:
2589 si_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_rnd_hl_s1>;
2590 def HEXAGON_M2_mpy_sat_rnd_hl_s1:
2591 si_MInst_sisi_sat_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s1>;
2592 def HEXAGON_M2_mpy_sat_hl_s1:
2593 si_MInst_sisi_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_hl_s1>;
2594 def HEXAGON_M2_mpy_rnd_hl_s0:
2595 si_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpy_rnd_hl_s0>;
2596 def HEXAGON_M2_mpy_sat_rnd_hl_s0:
2597 si_MInst_sisi_sat_rnd_hl <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s0>;
2598 def HEXAGON_M2_mpy_sat_hl_s0:
2599 si_MInst_sisi_sat_hl <"mpy", int_hexagon_M2_mpy_sat_hl_s0>;
2601 def HEXAGON_M2_mpy_lh_s0:
2602 si_MInst_sisi_lh <"mpy", int_hexagon_M2_mpy_lh_s0>;
2603 def HEXAGON_M2_mpy_lh_s1:
2604 si_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpy_lh_s1>;
2605 def HEXAGON_M2_mpy_rnd_lh_s1:
2606 si_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_rnd_lh_s1>;
2607 def HEXAGON_M2_mpy_sat_rnd_lh_s1:
2608 si_MInst_sisi_sat_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s1>;
2609 def HEXAGON_M2_mpy_sat_lh_s1:
2610 si_MInst_sisi_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_lh_s1>;
2611 def HEXAGON_M2_mpy_rnd_lh_s0:
2612 si_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpy_rnd_lh_s0>;
2613 def HEXAGON_M2_mpy_sat_rnd_lh_s0:
2614 si_MInst_sisi_sat_rnd_lh <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s0>;
2615 def HEXAGON_M2_mpy_sat_lh_s0:
2616 si_MInst_sisi_sat_lh <"mpy", int_hexagon_M2_mpy_sat_lh_s0>;
2618 def HEXAGON_M2_mpy_ll_s0:
2619 si_MInst_sisi_ll <"mpy", int_hexagon_M2_mpy_ll_s0>;
2620 def HEXAGON_M2_mpy_ll_s1:
2621 si_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpy_ll_s1>;
2622 def HEXAGON_M2_mpy_rnd_ll_s1:
2623 si_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_rnd_ll_s1>;
2624 def HEXAGON_M2_mpy_sat_rnd_ll_s1:
2625 si_MInst_sisi_sat_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s1>;
2626 def HEXAGON_M2_mpy_sat_ll_s1:
2627 si_MInst_sisi_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_ll_s1>;
2628 def HEXAGON_M2_mpy_rnd_ll_s0:
2629 si_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpy_rnd_ll_s0>;
2630 def HEXAGON_M2_mpy_sat_rnd_ll_s0:
2631 si_MInst_sisi_sat_rnd_ll <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s0>;
2632 def HEXAGON_M2_mpy_sat_ll_s0:
2633 si_MInst_sisi_sat_ll <"mpy", int_hexagon_M2_mpy_sat_ll_s0>;
2635 //Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]]
2636 def HEXAGON_M2_mpyd_hh_s0:
2637 di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>;
2638 def HEXAGON_M2_mpyd_hh_s1:
2639 di_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpyd_hh_s1>;
2640 def HEXAGON_M2_mpyd_rnd_hh_s1:
2641 di_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hh_s1>;
2642 def HEXAGON_M2_mpyd_rnd_hh_s0:
2643 di_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpyd_rnd_hh_s0>;
2645 def HEXAGON_M2_mpyd_hl_s0:
2646 di_MInst_sisi_hl <"mpy", int_hexagon_M2_mpyd_hl_s0>;
2647 def HEXAGON_M2_mpyd_hl_s1:
2648 di_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpyd_hl_s1>;
2649 def HEXAGON_M2_mpyd_rnd_hl_s1:
2650 di_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hl_s1>;
2651 def HEXAGON_M2_mpyd_rnd_hl_s0:
2652 di_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpyd_rnd_hl_s0>;
2654 def HEXAGON_M2_mpyd_lh_s0:
2655 di_MInst_sisi_lh <"mpy", int_hexagon_M2_mpyd_lh_s0>;
2656 def HEXAGON_M2_mpyd_lh_s1:
2657 di_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpyd_lh_s1>;
2658 def HEXAGON_M2_mpyd_rnd_lh_s1:
2659 di_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_lh_s1>;
2660 def HEXAGON_M2_mpyd_rnd_lh_s0:
2661 di_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpyd_rnd_lh_s0>;
2663 def HEXAGON_M2_mpyd_ll_s0:
2664 di_MInst_sisi_ll <"mpy", int_hexagon_M2_mpyd_ll_s0>;
2665 def HEXAGON_M2_mpyd_ll_s1:
2666 di_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpyd_ll_s1>;
2667 def HEXAGON_M2_mpyd_rnd_ll_s1:
2668 di_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpyd_rnd_ll_s1>;
2669 def HEXAGON_M2_mpyd_rnd_ll_s0:
2670 di_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpyd_rnd_ll_s0>;
2672 //Rx+=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2673 def HEXAGON_M2_mpy_acc_hh_s0:
2674 si_MInst_sisisi_acc_hh <"mpy", int_hexagon_M2_mpy_acc_hh_s0>;
2675 def HEXAGON_M2_mpy_acc_hh_s1:
2676 si_MInst_sisisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_hh_s1>;
2677 def HEXAGON_M2_mpy_acc_sat_hh_s1:
2678 si_MInst_sisisi_acc_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s1>;
2679 def HEXAGON_M2_mpy_acc_sat_hh_s0:
2680 si_MInst_sisisi_acc_sat_hh <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s0>;
2682 def HEXAGON_M2_mpy_acc_hl_s0:
2683 si_MInst_sisisi_acc_hl <"mpy", int_hexagon_M2_mpy_acc_hl_s0>;
2684 def HEXAGON_M2_mpy_acc_hl_s1:
2685 si_MInst_sisisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_hl_s1>;
2686 def HEXAGON_M2_mpy_acc_sat_hl_s1:
2687 si_MInst_sisisi_acc_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s1>;
2688 def HEXAGON_M2_mpy_acc_sat_hl_s0:
2689 si_MInst_sisisi_acc_sat_hl <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s0>;
2691 def HEXAGON_M2_mpy_acc_lh_s0:
2692 si_MInst_sisisi_acc_lh <"mpy", int_hexagon_M2_mpy_acc_lh_s0>;
2693 def HEXAGON_M2_mpy_acc_lh_s1:
2694 si_MInst_sisisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_lh_s1>;
2695 def HEXAGON_M2_mpy_acc_sat_lh_s1:
2696 si_MInst_sisisi_acc_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s1>;
2697 def HEXAGON_M2_mpy_acc_sat_lh_s0:
2698 si_MInst_sisisi_acc_sat_lh <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s0>;
2700 def HEXAGON_M2_mpy_acc_ll_s0:
2701 si_MInst_sisisi_acc_ll <"mpy", int_hexagon_M2_mpy_acc_ll_s0>;
2702 def HEXAGON_M2_mpy_acc_ll_s1:
2703 si_MInst_sisisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_ll_s1>;
2704 def HEXAGON_M2_mpy_acc_sat_ll_s1:
2705 si_MInst_sisisi_acc_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s1>;
2706 def HEXAGON_M2_mpy_acc_sat_ll_s0:
2707 si_MInst_sisisi_acc_sat_ll <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s0>;
2709 //Rx-=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2710 def HEXAGON_M2_mpy_nac_hh_s0:
2711 si_MInst_sisisi_nac_hh <"mpy", int_hexagon_M2_mpy_nac_hh_s0>;
2712 def HEXAGON_M2_mpy_nac_hh_s1:
2713 si_MInst_sisisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_hh_s1>;
2714 def HEXAGON_M2_mpy_nac_sat_hh_s1:
2715 si_MInst_sisisi_nac_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s1>;
2716 def HEXAGON_M2_mpy_nac_sat_hh_s0:
2717 si_MInst_sisisi_nac_sat_hh <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s0>;
2719 def HEXAGON_M2_mpy_nac_hl_s0:
2720 si_MInst_sisisi_nac_hl <"mpy", int_hexagon_M2_mpy_nac_hl_s0>;
2721 def HEXAGON_M2_mpy_nac_hl_s1:
2722 si_MInst_sisisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_hl_s1>;
2723 def HEXAGON_M2_mpy_nac_sat_hl_s1:
2724 si_MInst_sisisi_nac_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s1>;
2725 def HEXAGON_M2_mpy_nac_sat_hl_s0:
2726 si_MInst_sisisi_nac_sat_hl <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s0>;
2728 def HEXAGON_M2_mpy_nac_lh_s0:
2729 si_MInst_sisisi_nac_lh <"mpy", int_hexagon_M2_mpy_nac_lh_s0>;
2730 def HEXAGON_M2_mpy_nac_lh_s1:
2731 si_MInst_sisisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_lh_s1>;
2732 def HEXAGON_M2_mpy_nac_sat_lh_s1:
2733 si_MInst_sisisi_nac_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s1>;
2734 def HEXAGON_M2_mpy_nac_sat_lh_s0:
2735 si_MInst_sisisi_nac_sat_lh <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s0>;
2737 def HEXAGON_M2_mpy_nac_ll_s0:
2738 si_MInst_sisisi_nac_ll <"mpy", int_hexagon_M2_mpy_nac_ll_s0>;
2739 def HEXAGON_M2_mpy_nac_ll_s1:
2740 si_MInst_sisisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_ll_s1>;
2741 def HEXAGON_M2_mpy_nac_sat_ll_s1:
2742 si_MInst_sisisi_nac_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s1>;
2743 def HEXAGON_M2_mpy_nac_sat_ll_s0:
2744 si_MInst_sisisi_nac_sat_ll <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s0>;
2746 //Rx+=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2747 def HEXAGON_M2_mpyd_acc_hh_s0:
2748 di_MInst_disisi_acc_hh <"mpy", int_hexagon_M2_mpyd_acc_hh_s0>;
2749 def HEXAGON_M2_mpyd_acc_hh_s1:
2750 di_MInst_disisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpyd_acc_hh_s1>;
2752 def HEXAGON_M2_mpyd_acc_hl_s0:
2753 di_MInst_disisi_acc_hl <"mpy", int_hexagon_M2_mpyd_acc_hl_s0>;
2754 def HEXAGON_M2_mpyd_acc_hl_s1:
2755 di_MInst_disisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpyd_acc_hl_s1>;
2757 def HEXAGON_M2_mpyd_acc_lh_s0:
2758 di_MInst_disisi_acc_lh <"mpy", int_hexagon_M2_mpyd_acc_lh_s0>;
2759 def HEXAGON_M2_mpyd_acc_lh_s1:
2760 di_MInst_disisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpyd_acc_lh_s1>;
2762 def HEXAGON_M2_mpyd_acc_ll_s0:
2763 di_MInst_disisi_acc_ll <"mpy", int_hexagon_M2_mpyd_acc_ll_s0>;
2764 def HEXAGON_M2_mpyd_acc_ll_s1:
2765 di_MInst_disisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpyd_acc_ll_s1>;
2767 //Rx-=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2768 def HEXAGON_M2_mpyd_nac_hh_s0:
2769 di_MInst_disisi_nac_hh <"mpy", int_hexagon_M2_mpyd_nac_hh_s0>;
2770 def HEXAGON_M2_mpyd_nac_hh_s1:
2771 di_MInst_disisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpyd_nac_hh_s1>;
2773 def HEXAGON_M2_mpyd_nac_hl_s0:
2774 di_MInst_disisi_nac_hl <"mpy", int_hexagon_M2_mpyd_nac_hl_s0>;
2775 def HEXAGON_M2_mpyd_nac_hl_s1:
2776 di_MInst_disisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpyd_nac_hl_s1>;
2778 def HEXAGON_M2_mpyd_nac_lh_s0:
2779 di_MInst_disisi_nac_lh <"mpy", int_hexagon_M2_mpyd_nac_lh_s0>;
2780 def HEXAGON_M2_mpyd_nac_lh_s1:
2781 di_MInst_disisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpyd_nac_lh_s1>;
2783 def HEXAGON_M2_mpyd_nac_ll_s0:
2784 di_MInst_disisi_nac_ll <"mpy", int_hexagon_M2_mpyd_nac_ll_s0>;
2785 def HEXAGON_M2_mpyd_nac_ll_s1:
2786 di_MInst_disisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpyd_nac_ll_s1>;
2788 // MTYPE / MPYS / Scalar 16x16 multiply unsigned.
2789 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2790 def HEXAGON_M2_mpyu_hh_s0:
2791 si_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyu_hh_s0>;
2792 def HEXAGON_M2_mpyu_hh_s1:
2793 si_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyu_hh_s1>;
2794 def HEXAGON_M2_mpyu_hl_s0:
2795 si_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyu_hl_s0>;
2796 def HEXAGON_M2_mpyu_hl_s1:
2797 si_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyu_hl_s1>;
2798 def HEXAGON_M2_mpyu_lh_s0:
2799 si_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyu_lh_s0>;
2800 def HEXAGON_M2_mpyu_lh_s1:
2801 si_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyu_lh_s1>;
2802 def HEXAGON_M2_mpyu_ll_s0:
2803 si_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyu_ll_s0>;
2804 def HEXAGON_M2_mpyu_ll_s1:
2805 si_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyu_ll_s1>;
2807 //Rdd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2808 def HEXAGON_M2_mpyud_hh_s0:
2809 di_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyud_hh_s0>;
2810 def HEXAGON_M2_mpyud_hh_s1:
2811 di_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyud_hh_s1>;
2812 def HEXAGON_M2_mpyud_hl_s0:
2813 di_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyud_hl_s0>;
2814 def HEXAGON_M2_mpyud_hl_s1:
2815 di_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyud_hl_s1>;
2816 def HEXAGON_M2_mpyud_lh_s0:
2817 di_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyud_lh_s0>;
2818 def HEXAGON_M2_mpyud_lh_s1:
2819 di_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyud_lh_s1>;
2820 def HEXAGON_M2_mpyud_ll_s0:
2821 di_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyud_ll_s0>;
2822 def HEXAGON_M2_mpyud_ll_s1:
2823 di_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyud_ll_s1>;
2825 //Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2826 def HEXAGON_M2_mpyu_acc_hh_s0:
2827 si_MInst_sisisi_acc_hh <"mpyu", int_hexagon_M2_mpyu_acc_hh_s0>;
2828 def HEXAGON_M2_mpyu_acc_hh_s1:
2829 si_MInst_sisisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hh_s1>;
2830 def HEXAGON_M2_mpyu_acc_hl_s0:
2831 si_MInst_sisisi_acc_hl <"mpyu", int_hexagon_M2_mpyu_acc_hl_s0>;
2832 def HEXAGON_M2_mpyu_acc_hl_s1:
2833 si_MInst_sisisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hl_s1>;
2834 def HEXAGON_M2_mpyu_acc_lh_s0:
2835 si_MInst_sisisi_acc_lh <"mpyu", int_hexagon_M2_mpyu_acc_lh_s0>;
2836 def HEXAGON_M2_mpyu_acc_lh_s1:
2837 si_MInst_sisisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_lh_s1>;
2838 def HEXAGON_M2_mpyu_acc_ll_s0:
2839 si_MInst_sisisi_acc_ll <"mpyu", int_hexagon_M2_mpyu_acc_ll_s0>;
2840 def HEXAGON_M2_mpyu_acc_ll_s1:
2841 si_MInst_sisisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyu_acc_ll_s1>;
2843 //Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2844 def HEXAGON_M2_mpyu_nac_hh_s0:
2845 si_MInst_sisisi_nac_hh <"mpyu", int_hexagon_M2_mpyu_nac_hh_s0>;
2846 def HEXAGON_M2_mpyu_nac_hh_s1:
2847 si_MInst_sisisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hh_s1>;
2848 def HEXAGON_M2_mpyu_nac_hl_s0:
2849 si_MInst_sisisi_nac_hl <"mpyu", int_hexagon_M2_mpyu_nac_hl_s0>;
2850 def HEXAGON_M2_mpyu_nac_hl_s1:
2851 si_MInst_sisisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hl_s1>;
2852 def HEXAGON_M2_mpyu_nac_lh_s0:
2853 si_MInst_sisisi_nac_lh <"mpyu", int_hexagon_M2_mpyu_nac_lh_s0>;
2854 def HEXAGON_M2_mpyu_nac_lh_s1:
2855 si_MInst_sisisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_lh_s1>;
2856 def HEXAGON_M2_mpyu_nac_ll_s0:
2857 si_MInst_sisisi_nac_ll <"mpyu", int_hexagon_M2_mpyu_nac_ll_s0>;
2858 def HEXAGON_M2_mpyu_nac_ll_s1:
2859 si_MInst_sisisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyu_nac_ll_s1>;
2861 //Rdd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2862 def HEXAGON_M2_mpyud_acc_hh_s0:
2863 di_MInst_disisi_acc_hh <"mpyu", int_hexagon_M2_mpyud_acc_hh_s0>;
2864 def HEXAGON_M2_mpyud_acc_hh_s1:
2865 di_MInst_disisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hh_s1>;
2866 def HEXAGON_M2_mpyud_acc_hl_s0:
2867 di_MInst_disisi_acc_hl <"mpyu", int_hexagon_M2_mpyud_acc_hl_s0>;
2868 def HEXAGON_M2_mpyud_acc_hl_s1:
2869 di_MInst_disisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hl_s1>;
2870 def HEXAGON_M2_mpyud_acc_lh_s0:
2871 di_MInst_disisi_acc_lh <"mpyu", int_hexagon_M2_mpyud_acc_lh_s0>;
2872 def HEXAGON_M2_mpyud_acc_lh_s1:
2873 di_MInst_disisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_lh_s1>;
2874 def HEXAGON_M2_mpyud_acc_ll_s0:
2875 di_MInst_disisi_acc_ll <"mpyu", int_hexagon_M2_mpyud_acc_ll_s0>;
2876 def HEXAGON_M2_mpyud_acc_ll_s1:
2877 di_MInst_disisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyud_acc_ll_s1>;
2879 //Rdd-=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2880 def HEXAGON_M2_mpyud_nac_hh_s0:
2881 di_MInst_disisi_nac_hh <"mpyu", int_hexagon_M2_mpyud_nac_hh_s0>;
2882 def HEXAGON_M2_mpyud_nac_hh_s1:
2883 di_MInst_disisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hh_s1>;
2884 def HEXAGON_M2_mpyud_nac_hl_s0:
2885 di_MInst_disisi_nac_hl <"mpyu", int_hexagon_M2_mpyud_nac_hl_s0>;
2886 def HEXAGON_M2_mpyud_nac_hl_s1:
2887 di_MInst_disisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hl_s1>;
2888 def HEXAGON_M2_mpyud_nac_lh_s0:
2889 di_MInst_disisi_nac_lh <"mpyu", int_hexagon_M2_mpyud_nac_lh_s0>;
2890 def HEXAGON_M2_mpyud_nac_lh_s1:
2891 di_MInst_disisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_lh_s1>;
2892 def HEXAGON_M2_mpyud_nac_ll_s0:
2893 di_MInst_disisi_nac_ll <"mpyu", int_hexagon_M2_mpyud_nac_ll_s0>;
2894 def HEXAGON_M2_mpyud_nac_ll_s1:
2895 di_MInst_disisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyud_nac_ll_s1>;
2898 /********************************************************************
2900 *********************************************************************/
2902 // MTYPE / VB / Vector reduce add unsigned bytes.
2903 def HEXAGON_A2_vraddub:
2904 di_MInst_didi <"vraddub", int_hexagon_A2_vraddub>;
2905 def HEXAGON_A2_vraddub_acc:
2906 di_MInst_dididi_acc <"vraddub", int_hexagon_A2_vraddub_acc>;
2908 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2909 def HEXAGON_A2_vrsadub:
2910 di_MInst_didi <"vrsadub", int_hexagon_A2_vrsadub>;
2911 def HEXAGON_A2_vrsadub_acc:
2912 di_MInst_dididi_acc <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2914 /********************************************************************
2916 *********************************************************************/
2918 // MTYPE / VH / Vector dual multiply.
2919 def HEXAGON_M2_vdmpys_s1:
2920 di_MInst_didi_s1_sat <"vdmpy", int_hexagon_M2_vdmpys_s1>;
2921 def HEXAGON_M2_vdmpys_s0:
2922 di_MInst_didi_sat <"vdmpy", int_hexagon_M2_vdmpys_s0>;
2923 def HEXAGON_M2_vdmacs_s1:
2924 di_MInst_dididi_acc_s1_sat <"vdmpy", int_hexagon_M2_vdmacs_s1>;
2925 def HEXAGON_M2_vdmacs_s0:
2926 di_MInst_dididi_acc_sat <"vdmpy", int_hexagon_M2_vdmacs_s0>;
2928 // MTYPE / VH / Vector dual multiply with round and pack.
2929 def HEXAGON_M2_vdmpyrs_s0:
2930 si_MInst_didi_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s0>;
2931 def HEXAGON_M2_vdmpyrs_s1:
2932 si_MInst_didi_s1_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s1>;
2934 // MTYPE / VH / Vector multiply even halfwords.
2935 def HEXAGON_M2_vmpy2es_s1:
2936 di_MInst_didi_s1_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s1>;
2937 def HEXAGON_M2_vmpy2es_s0:
2938 di_MInst_didi_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s0>;
2939 def HEXAGON_M2_vmac2es:
2940 di_MInst_dididi_acc <"vmpyeh", int_hexagon_M2_vmac2es>;
2941 def HEXAGON_M2_vmac2es_s1:
2942 di_MInst_dididi_acc_s1_sat <"vmpyeh", int_hexagon_M2_vmac2es_s1>;
2943 def HEXAGON_M2_vmac2es_s0:
2944 di_MInst_dididi_acc_sat <"vmpyeh", int_hexagon_M2_vmac2es_s0>;
2946 // MTYPE / VH / Vector multiply halfwords.
2947 def HEXAGON_M2_vmpy2s_s0:
2948 di_MInst_sisi_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0>;
2949 def HEXAGON_M2_vmpy2s_s1:
2950 di_MInst_sisi_s1_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1>;
2951 def HEXAGON_M2_vmac2:
2952 di_MInst_disisi_acc <"vmpyh", int_hexagon_M2_vmac2>;
2953 def HEXAGON_M2_vmac2s_s0:
2954 di_MInst_disisi_acc_sat <"vmpyh", int_hexagon_M2_vmac2s_s0>;
2955 def HEXAGON_M2_vmac2s_s1:
2956 di_MInst_disisi_acc_s1_sat <"vmpyh", int_hexagon_M2_vmac2s_s1>;
2958 // MTYPE / VH / Vector multiply halfwords with round and pack.
2959 def HEXAGON_M2_vmpy2s_s0pack:
2960 si_MInst_sisi_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0pack>;
2961 def HEXAGON_M2_vmpy2s_s1pack:
2962 si_MInst_sisi_s1_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1pack>;
2964 // MTYPE / VH / Vector reduce multiply halfwords.
2965 // Rxx32+=vrmpyh(Rss32,Rtt32)
2966 def HEXAGON_M2_vrmpy_s0:
2967 di_MInst_didi <"vrmpyh", int_hexagon_M2_vrmpy_s0>;
2968 def HEXAGON_M2_vrmac_s0:
2969 di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>;
2972 /********************************************************************
2974 *********************************************************************/
2976 // STYPE / ALU / Absolute value.
2978 si_SInst_si <"abs", int_hexagon_A2_abs>;
2979 def HEXAGON_A2_absp:
2980 di_SInst_di <"abs", int_hexagon_A2_absp>;
2981 def HEXAGON_A2_abssat:
2982 si_SInst_si_sat <"abs", int_hexagon_A2_abssat>;
2984 // STYPE / ALU / Negate.
2985 def HEXAGON_A2_negp:
2986 di_SInst_di <"neg", int_hexagon_A2_negp>;
2987 def HEXAGON_A2_negsat:
2988 si_SInst_si_sat <"neg", int_hexagon_A2_negsat>;
2990 // STYPE / ALU / Logical Not.
2991 def HEXAGON_A2_notp:
2992 di_SInst_di <"not", int_hexagon_A2_notp>;
2994 // STYPE / ALU / Sign extend word to doubleword.
2995 def HEXAGON_A2_sxtw:
2996 di_SInst_si <"sxtw", int_hexagon_A2_sxtw>;
2999 /********************************************************************
3001 *********************************************************************/
3003 // STYPE / BIT / Count leading.
3005 si_SInst_si <"cl0", int_hexagon_S2_cl0>;
3006 def HEXAGON_S2_cl0p:
3007 si_SInst_di <"cl0", int_hexagon_S2_cl0p>;
3009 si_SInst_si <"cl1", int_hexagon_S2_cl1>;
3010 def HEXAGON_S2_cl1p:
3011 si_SInst_di <"cl1", int_hexagon_S2_cl1p>;
3013 si_SInst_si <"clb", int_hexagon_S2_clb>;
3014 def HEXAGON_S2_clbp:
3015 si_SInst_di <"clb", int_hexagon_S2_clbp>;
3016 def HEXAGON_S2_clbnorm:
3017 si_SInst_si <"normamt", int_hexagon_S2_clbnorm>;
3019 // STYPE / BIT / Count trailing.
3021 si_SInst_si <"ct0", int_hexagon_S2_ct0>;
3023 si_SInst_si <"ct1", int_hexagon_S2_ct1>;
3025 // STYPE / BIT / Compare bit mask.
3026 def Hexagon_C2_bitsclr:
3027 qi_SInst_sisi <"bitsclr", int_hexagon_C2_bitsclr>;
3028 def Hexagon_C2_bitsclri:
3029 qi_SInst_siu6 <"bitsclr", int_hexagon_C2_bitsclri>;
3030 def Hexagon_C2_bitsset:
3031 qi_SInst_sisi <"bitsset", int_hexagon_C2_bitsset>;
3033 // STYPE / BIT / Extract unsigned.
3034 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
3035 def HEXAGON_S2_extractu:
3036 si_SInst_siu5u5 <"extractu",int_hexagon_S2_extractu>;
3037 def HEXAGON_S2_extractu_rp:
3038 si_SInst_sidi <"extractu",int_hexagon_S2_extractu_rp>;
3039 def HEXAGON_S2_extractup:
3040 di_SInst_diu6u6 <"extractu",int_hexagon_S2_extractup>;
3041 def HEXAGON_S2_extractup_rp:
3042 di_SInst_didi <"extractu",int_hexagon_S2_extractup_rp>;
3044 // STYPE / BIT / Insert bitfield.
3045 def Hexagon_S2_insert:
3046 si_SInst_sisiu5u5 <"insert", int_hexagon_S2_insert>;
3047 def Hexagon_S2_insert_rp:
3048 si_SInst_sisidi <"insert", int_hexagon_S2_insert_rp>;
3049 def Hexagon_S2_insertp:
3050 di_SInst_didiu6u6 <"insert", int_hexagon_S2_insertp>;
3051 def Hexagon_S2_insertp_rp:
3052 di_SInst_dididi <"insert", int_hexagon_S2_insertp_rp>;
3054 // STYPE / BIT / Innterleave/deinterleave.
3055 def Hexagon_S2_interleave:
3056 di_SInst_di <"interleave", int_hexagon_S2_interleave>;
3057 def Hexagon_S2_deinterleave:
3058 di_SInst_di <"deinterleave", int_hexagon_S2_deinterleave>;
3060 // STYPE / BIT / Linear feedback-shift Iteration.
3061 def Hexagon_S2_lfsp:
3062 di_SInst_didi <"lfs", int_hexagon_S2_lfsp>;
3064 // STYPE / BIT / Bit reverse.
3065 def Hexagon_S2_brev:
3066 si_SInst_si <"brev", int_hexagon_S2_brev>;
3068 // STYPE / BIT / Set/Clear/Toggle Bit.
3069 def HEXAGON_S2_setbit_i:
3070 si_SInst_siu5 <"setbit", int_hexagon_S2_setbit_i>;
3071 def HEXAGON_S2_togglebit_i:
3072 si_SInst_siu5 <"togglebit", int_hexagon_S2_togglebit_i>;
3073 def HEXAGON_S2_clrbit_i:
3074 si_SInst_siu5 <"clrbit", int_hexagon_S2_clrbit_i>;
3075 def HEXAGON_S2_setbit_r:
3076 si_SInst_sisi <"setbit", int_hexagon_S2_setbit_r>;
3077 def HEXAGON_S2_togglebit_r:
3078 si_SInst_sisi <"togglebit", int_hexagon_S2_togglebit_r>;
3079 def HEXAGON_S2_clrbit_r:
3080 si_SInst_sisi <"clrbit", int_hexagon_S2_clrbit_r>;
3082 // STYPE / BIT / Test Bit.
3083 def HEXAGON_S2_tstbit_i:
3084 qi_SInst_siu5 <"tstbit", int_hexagon_S2_tstbit_i>;
3085 def HEXAGON_S2_tstbit_r:
3086 qi_SInst_sisi <"tstbit", int_hexagon_S2_tstbit_r>;
3089 /********************************************************************
3091 *********************************************************************/
3093 // STYPE / COMPLEX / Vector Complex conjugate.
3094 def HEXAGON_A2_vconj:
3095 di_SInst_di_sat <"vconj", int_hexagon_A2_vconj>;
3097 // STYPE / COMPLEX / Vector Complex rotate.
3098 def HEXAGON_S2_vcrotate:
3099 di_SInst_disi <"vcrotate",int_hexagon_S2_vcrotate>;
3102 /********************************************************************
3104 *********************************************************************/
3106 // STYPE / PERM / Saturate.
3108 si_SInst_di <"sat", int_hexagon_A2_sat>;
3109 def HEXAGON_A2_satb:
3110 si_SInst_si <"satb", int_hexagon_A2_satb>;
3111 def HEXAGON_A2_sath:
3112 si_SInst_si <"sath", int_hexagon_A2_sath>;
3113 def HEXAGON_A2_satub:
3114 si_SInst_si <"satub", int_hexagon_A2_satub>;
3115 def HEXAGON_A2_satuh:
3116 si_SInst_si <"satuh", int_hexagon_A2_satuh>;
3118 // STYPE / PERM / Swizzle bytes.
3119 def HEXAGON_A2_swiz:
3120 si_SInst_si <"swiz", int_hexagon_A2_swiz>;
3122 // STYPE / PERM / Vector align.
3123 // Need custom lowering
3124 def HEXAGON_S2_valignib:
3125 di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
3126 def HEXAGON_S2_valignrb:
3127 di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
3129 // STYPE / PERM / Vector round and pack.
3130 def HEXAGON_S2_vrndpackwh:
3131 si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
3132 def HEXAGON_S2_vrndpackwhs:
3133 si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
3135 // STYPE / PERM / Vector saturate and pack.
3136 def HEXAGON_S2_svsathb:
3137 si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
3138 def HEXAGON_S2_vsathb:
3139 si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
3140 def HEXAGON_S2_svsathub:
3141 si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
3142 def HEXAGON_S2_vsathub:
3143 si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
3144 def HEXAGON_S2_vsatwh:
3145 si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
3146 def HEXAGON_S2_vsatwuh:
3147 si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
3149 // STYPE / PERM / Vector saturate without pack.
3150 def HEXAGON_S2_vsathb_nopack:
3151 di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
3152 def HEXAGON_S2_vsathub_nopack:
3153 di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
3154 def HEXAGON_S2_vsatwh_nopack:
3155 di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
3156 def HEXAGON_S2_vsatwuh_nopack:
3157 di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3159 // STYPE / PERM / Vector shuffle.
3160 def HEXAGON_S2_shuffeb:
3161 di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
3162 def HEXAGON_S2_shuffeh:
3163 di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
3164 def HEXAGON_S2_shuffob:
3165 di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
3166 def HEXAGON_S2_shuffoh:
3167 di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
3169 // STYPE / PERM / Vector splat bytes.
3170 def HEXAGON_S2_vsplatrb:
3171 si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
3173 // STYPE / PERM / Vector splat halfwords.
3174 def HEXAGON_S2_vsplatrh:
3175 di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
3177 // STYPE / PERM / Vector splice.
3178 def Hexagon_S2_vsplicerb:
3179 di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
3180 def Hexagon_S2_vspliceib:
3181 di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
3183 // STYPE / PERM / Sign extend.
3184 def HEXAGON_S2_vsxtbh:
3185 di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
3186 def HEXAGON_S2_vsxthw:
3187 di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
3189 // STYPE / PERM / Truncate.
3190 def HEXAGON_S2_vtrunehb:
3191 si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
3192 def HEXAGON_S2_vtrunohb:
3193 si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
3194 def HEXAGON_S2_vtrunewh:
3195 di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
3196 def HEXAGON_S2_vtrunowh:
3197 di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
3199 // STYPE / PERM / Zero extend.
3200 def HEXAGON_S2_vzxtbh:
3201 di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
3202 def HEXAGON_S2_vzxthw:
3203 di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
3206 /********************************************************************
3208 *********************************************************************/
3210 // STYPE / PRED / Mask generate from predicate.
3211 def HEXAGON_C2_mask:
3212 di_SInst_qi <"mask", int_hexagon_C2_mask>;
3214 // STYPE / PRED / Predicate transfer.
3215 def HEXAGON_C2_tfrpr:
3216 si_SInst_qi <"", int_hexagon_C2_tfrpr>;
3217 def HEXAGON_C2_tfrrp:
3218 qi_SInst_si <"", int_hexagon_C2_tfrrp>;
3220 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3221 def HEXAGON_C2_vitpack:
3222 si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
3225 /********************************************************************
3227 *********************************************************************/
3229 // STYPE / SHIFT / Shift by immediate.
3230 def HEXAGON_S2_asl_i_r:
3231 si_SInst_siu5 <"asl", int_hexagon_S2_asl_i_r>;
3232 def HEXAGON_S2_asr_i_r:
3233 si_SInst_siu5 <"asr", int_hexagon_S2_asr_i_r>;
3234 def HEXAGON_S2_lsr_i_r:
3235 si_SInst_siu5 <"lsr", int_hexagon_S2_lsr_i_r>;
3236 def HEXAGON_S2_asl_i_p:
3237 di_SInst_diu6 <"asl", int_hexagon_S2_asl_i_p>;
3238 def HEXAGON_S2_asr_i_p:
3239 di_SInst_diu6 <"asr", int_hexagon_S2_asr_i_p>;
3240 def HEXAGON_S2_lsr_i_p:
3241 di_SInst_diu6 <"lsr", int_hexagon_S2_lsr_i_p>;
3243 // STYPE / SHIFT / Shift by immediate and accumulate.
3244 def HEXAGON_S2_asl_i_r_acc:
3245 si_SInst_sisiu5_acc <"asl", int_hexagon_S2_asl_i_r_acc>;
3246 def HEXAGON_S2_asr_i_r_acc:
3247 si_SInst_sisiu5_acc <"asr", int_hexagon_S2_asr_i_r_acc>;
3248 def HEXAGON_S2_lsr_i_r_acc:
3249 si_SInst_sisiu5_acc <"lsr", int_hexagon_S2_lsr_i_r_acc>;
3250 def HEXAGON_S2_asl_i_r_nac:
3251 si_SInst_sisiu5_nac <"asl", int_hexagon_S2_asl_i_r_nac>;
3252 def HEXAGON_S2_asr_i_r_nac:
3253 si_SInst_sisiu5_nac <"asr", int_hexagon_S2_asr_i_r_nac>;
3254 def HEXAGON_S2_lsr_i_r_nac:
3255 si_SInst_sisiu5_nac <"lsr", int_hexagon_S2_lsr_i_r_nac>;
3256 def HEXAGON_S2_asl_i_p_acc:
3257 di_SInst_didiu6_acc <"asl", int_hexagon_S2_asl_i_p_acc>;
3258 def HEXAGON_S2_asr_i_p_acc:
3259 di_SInst_didiu6_acc <"asr", int_hexagon_S2_asr_i_p_acc>;
3260 def HEXAGON_S2_lsr_i_p_acc:
3261 di_SInst_didiu6_acc <"lsr", int_hexagon_S2_lsr_i_p_acc>;
3262 def HEXAGON_S2_asl_i_p_nac:
3263 di_SInst_didiu6_nac <"asl", int_hexagon_S2_asl_i_p_nac>;
3264 def HEXAGON_S2_asr_i_p_nac:
3265 di_SInst_didiu6_nac <"asr", int_hexagon_S2_asr_i_p_nac>;
3266 def HEXAGON_S2_lsr_i_p_nac:
3267 di_SInst_didiu6_nac <"lsr", int_hexagon_S2_lsr_i_p_nac>;
3269 // STYPE / SHIFT / Shift by immediate and add.
3270 def HEXAGON_S2_addasl_rrri:
3271 si_SInst_sisiu3 <"addasl", int_hexagon_S2_addasl_rrri>;
3273 // STYPE / SHIFT / Shift by immediate and logical.
3274 def HEXAGON_S2_asl_i_r_and:
3275 si_SInst_sisiu5_and <"asl", int_hexagon_S2_asl_i_r_and>;
3276 def HEXAGON_S2_asr_i_r_and:
3277 si_SInst_sisiu5_and <"asr", int_hexagon_S2_asr_i_r_and>;
3278 def HEXAGON_S2_lsr_i_r_and:
3279 si_SInst_sisiu5_and <"lsr", int_hexagon_S2_lsr_i_r_and>;
3281 def HEXAGON_S2_asl_i_r_xacc:
3282 si_SInst_sisiu5_xor <"asl", int_hexagon_S2_asl_i_r_xacc>;
3283 def HEXAGON_S2_lsr_i_r_xacc:
3284 si_SInst_sisiu5_xor <"lsr", int_hexagon_S2_lsr_i_r_xacc>;
3286 def HEXAGON_S2_asl_i_r_or:
3287 si_SInst_sisiu5_or <"asl", int_hexagon_S2_asl_i_r_or>;
3288 def HEXAGON_S2_asr_i_r_or:
3289 si_SInst_sisiu5_or <"asr", int_hexagon_S2_asr_i_r_or>;
3290 def HEXAGON_S2_lsr_i_r_or:
3291 si_SInst_sisiu5_or <"lsr", int_hexagon_S2_lsr_i_r_or>;
3293 def HEXAGON_S2_asl_i_p_and:
3294 di_SInst_didiu6_and <"asl", int_hexagon_S2_asl_i_p_and>;
3295 def HEXAGON_S2_asr_i_p_and:
3296 di_SInst_didiu6_and <"asr", int_hexagon_S2_asr_i_p_and>;
3297 def HEXAGON_S2_lsr_i_p_and:
3298 di_SInst_didiu6_and <"lsr", int_hexagon_S2_lsr_i_p_and>;
3300 def HEXAGON_S2_asl_i_p_xacc:
3301 di_SInst_didiu6_xor <"asl", int_hexagon_S2_asl_i_p_xacc>;
3302 def HEXAGON_S2_lsr_i_p_xacc:
3303 di_SInst_didiu6_xor <"lsr", int_hexagon_S2_lsr_i_p_xacc>;
3305 def HEXAGON_S2_asl_i_p_or:
3306 di_SInst_didiu6_or <"asl", int_hexagon_S2_asl_i_p_or>;
3307 def HEXAGON_S2_asr_i_p_or:
3308 di_SInst_didiu6_or <"asr", int_hexagon_S2_asr_i_p_or>;
3309 def HEXAGON_S2_lsr_i_p_or:
3310 di_SInst_didiu6_or <"lsr", int_hexagon_S2_lsr_i_p_or>;
3312 // STYPE / SHIFT / Shift right by immediate with rounding.
3313 def HEXAGON_S2_asr_i_r_rnd:
3314 si_SInst_siu5_rnd <"asr", int_hexagon_S2_asr_i_r_rnd>;
3315 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3316 si_SInst_siu5 <"asrrnd", int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3318 // STYPE / SHIFT / Shift left by immediate with saturation.
3319 def HEXAGON_S2_asl_i_r_sat:
3320 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_i_r_sat>;
3322 // STYPE / SHIFT / Shift by register.
3323 def HEXAGON_S2_asl_r_r:
3324 si_SInst_sisi <"asl", int_hexagon_S2_asl_r_r>;
3325 def HEXAGON_S2_asr_r_r:
3326 si_SInst_sisi <"asr", int_hexagon_S2_asr_r_r>;
3327 def HEXAGON_S2_lsl_r_r:
3328 si_SInst_sisi <"lsl", int_hexagon_S2_lsl_r_r>;
3329 def HEXAGON_S2_lsr_r_r:
3330 si_SInst_sisi <"lsr", int_hexagon_S2_lsr_r_r>;
3331 def HEXAGON_S2_asl_r_p:
3332 di_SInst_disi <"asl", int_hexagon_S2_asl_r_p>;
3333 def HEXAGON_S2_asr_r_p:
3334 di_SInst_disi <"asr", int_hexagon_S2_asr_r_p>;
3335 def HEXAGON_S2_lsl_r_p:
3336 di_SInst_disi <"lsl", int_hexagon_S2_lsl_r_p>;
3337 def HEXAGON_S2_lsr_r_p:
3338 di_SInst_disi <"lsr", int_hexagon_S2_lsr_r_p>;
3340 // STYPE / SHIFT / Shift by register and accumulate.
3341 def HEXAGON_S2_asl_r_r_acc:
3342 si_SInst_sisisi_acc <"asl", int_hexagon_S2_asl_r_r_acc>;
3343 def HEXAGON_S2_asr_r_r_acc:
3344 si_SInst_sisisi_acc <"asr", int_hexagon_S2_asr_r_r_acc>;
3345 def HEXAGON_S2_lsl_r_r_acc:
3346 si_SInst_sisisi_acc <"lsl", int_hexagon_S2_lsl_r_r_acc>;
3347 def HEXAGON_S2_lsr_r_r_acc:
3348 si_SInst_sisisi_acc <"lsr", int_hexagon_S2_lsr_r_r_acc>;
3349 def HEXAGON_S2_asl_r_p_acc:
3350 di_SInst_didisi_acc <"asl", int_hexagon_S2_asl_r_p_acc>;
3351 def HEXAGON_S2_asr_r_p_acc:
3352 di_SInst_didisi_acc <"asr", int_hexagon_S2_asr_r_p_acc>;
3353 def HEXAGON_S2_lsl_r_p_acc:
3354 di_SInst_didisi_acc <"lsl", int_hexagon_S2_lsl_r_p_acc>;
3355 def HEXAGON_S2_lsr_r_p_acc:
3356 di_SInst_didisi_acc <"lsr", int_hexagon_S2_lsr_r_p_acc>;
3358 def HEXAGON_S2_asl_r_r_nac:
3359 si_SInst_sisisi_nac <"asl", int_hexagon_S2_asl_r_r_nac>;
3360 def HEXAGON_S2_asr_r_r_nac:
3361 si_SInst_sisisi_nac <"asr", int_hexagon_S2_asr_r_r_nac>;
3362 def HEXAGON_S2_lsl_r_r_nac:
3363 si_SInst_sisisi_nac <"lsl", int_hexagon_S2_lsl_r_r_nac>;
3364 def HEXAGON_S2_lsr_r_r_nac:
3365 si_SInst_sisisi_nac <"lsr", int_hexagon_S2_lsr_r_r_nac>;
3366 def HEXAGON_S2_asl_r_p_nac:
3367 di_SInst_didisi_nac <"asl", int_hexagon_S2_asl_r_p_nac>;
3368 def HEXAGON_S2_asr_r_p_nac:
3369 di_SInst_didisi_nac <"asr", int_hexagon_S2_asr_r_p_nac>;
3370 def HEXAGON_S2_lsl_r_p_nac:
3371 di_SInst_didisi_nac <"lsl", int_hexagon_S2_lsl_r_p_nac>;
3372 def HEXAGON_S2_lsr_r_p_nac:
3373 di_SInst_didisi_nac <"lsr", int_hexagon_S2_lsr_r_p_nac>;
3375 // STYPE / SHIFT / Shift by register and logical.
3376 def HEXAGON_S2_asl_r_r_and:
3377 si_SInst_sisisi_and <"asl", int_hexagon_S2_asl_r_r_and>;
3378 def HEXAGON_S2_asr_r_r_and:
3379 si_SInst_sisisi_and <"asr", int_hexagon_S2_asr_r_r_and>;
3380 def HEXAGON_S2_lsl_r_r_and:
3381 si_SInst_sisisi_and <"lsl", int_hexagon_S2_lsl_r_r_and>;
3382 def HEXAGON_S2_lsr_r_r_and:
3383 si_SInst_sisisi_and <"lsr", int_hexagon_S2_lsr_r_r_and>;
3385 def HEXAGON_S2_asl_r_r_or:
3386 si_SInst_sisisi_or <"asl", int_hexagon_S2_asl_r_r_or>;
3387 def HEXAGON_S2_asr_r_r_or:
3388 si_SInst_sisisi_or <"asr", int_hexagon_S2_asr_r_r_or>;
3389 def HEXAGON_S2_lsl_r_r_or:
3390 si_SInst_sisisi_or <"lsl", int_hexagon_S2_lsl_r_r_or>;
3391 def HEXAGON_S2_lsr_r_r_or:
3392 si_SInst_sisisi_or <"lsr", int_hexagon_S2_lsr_r_r_or>;
3394 def HEXAGON_S2_asl_r_p_and:
3395 di_SInst_didisi_and <"asl", int_hexagon_S2_asl_r_p_and>;
3396 def HEXAGON_S2_asr_r_p_and:
3397 di_SInst_didisi_and <"asr", int_hexagon_S2_asr_r_p_and>;
3398 def HEXAGON_S2_lsl_r_p_and:
3399 di_SInst_didisi_and <"lsl", int_hexagon_S2_lsl_r_p_and>;
3400 def HEXAGON_S2_lsr_r_p_and:
3401 di_SInst_didisi_and <"lsr", int_hexagon_S2_lsr_r_p_and>;
3403 def HEXAGON_S2_asl_r_p_or:
3404 di_SInst_didisi_or <"asl", int_hexagon_S2_asl_r_p_or>;
3405 def HEXAGON_S2_asr_r_p_or:
3406 di_SInst_didisi_or <"asr", int_hexagon_S2_asr_r_p_or>;
3407 def HEXAGON_S2_lsl_r_p_or:
3408 di_SInst_didisi_or <"lsl", int_hexagon_S2_lsl_r_p_or>;
3409 def HEXAGON_S2_lsr_r_p_or:
3410 di_SInst_didisi_or <"lsr", int_hexagon_S2_lsr_r_p_or>;
3412 // STYPE / SHIFT / Shift by register with saturation.
3413 def HEXAGON_S2_asl_r_r_sat:
3414 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_r_r_sat>;
3415 def HEXAGON_S2_asr_r_r_sat:
3416 si_SInst_sisi_sat <"asr", int_hexagon_S2_asr_r_r_sat>;
3418 // STYPE / SHIFT / Table Index.
3419 def Hexagon_S2_tableidxb_goodsyntax:
3420 si_MInst_sisiu4u5 <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3421 def Hexagon_S2_tableidxd_goodsyntax:
3422 si_MInst_sisiu4u5 <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3423 def Hexagon_S2_tableidxh_goodsyntax:
3424 si_MInst_sisiu4u5 <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3425 def Hexagon_S2_tableidxw_goodsyntax:
3426 si_MInst_sisiu4u5 <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3429 /********************************************************************
3431 *********************************************************************/
3433 // STYPE / VH / Vector absolute value halfwords.
3434 // Rdd64=vabsh(Rss64)
3435 def HEXAGON_A2_vabsh:
3436 di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
3437 def HEXAGON_A2_vabshsat:
3438 di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
3440 // STYPE / VH / Vector shift halfwords by immediate.
3441 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3442 def HEXAGON_S2_asl_i_vh:
3443 di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
3444 def HEXAGON_S2_asr_i_vh:
3445 di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
3446 def HEXAGON_S2_lsr_i_vh:
3447 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
3449 // STYPE / VH / Vector shift halfwords by register.
3450 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3451 def HEXAGON_S2_asl_r_vh:
3452 di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
3453 def HEXAGON_S2_asr_r_vh:
3454 di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
3455 def HEXAGON_S2_lsl_r_vh:
3456 di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
3457 def HEXAGON_S2_lsr_r_vh:
3458 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
3461 /********************************************************************
3463 *********************************************************************/
3465 // STYPE / VW / Vector absolute value words.
3466 def HEXAGON_A2_vabsw:
3467 di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
3468 def HEXAGON_A2_vabswsat:
3469 di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
3471 // STYPE / VW / Vector shift words by immediate.
3472 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3473 def HEXAGON_S2_asl_i_vw:
3474 di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
3475 def HEXAGON_S2_asr_i_vw:
3476 di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
3477 def HEXAGON_S2_lsr_i_vw:
3478 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
3480 // STYPE / VW / Vector shift words by register.
3481 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3482 def HEXAGON_S2_asl_r_vw:
3483 di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
3484 def HEXAGON_S2_asr_r_vw:
3485 di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
3486 def HEXAGON_S2_lsl_r_vw:
3487 di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
3488 def HEXAGON_S2_lsr_r_vw:
3489 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
3491 // STYPE / VW / Vector shift words with truncate and pack.
3492 def HEXAGON_S2_asr_r_svw_trun:
3493 si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
3494 def HEXAGON_S2_asr_i_svw_trun:
3495 si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
3497 // LD / Circular loads.
3498 def HEXAGON_circ_ldd:
3499 di_LDInstPI_diu4 <"circ_ldd", int_hexagon_circ_ldd>;
3501 include "HexagonIntrinsicsV3.td"
3502 include "HexagonIntrinsicsV4.td"
3503 include "HexagonIntrinsicsV5.td"