1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is populated based on the following specs:
10 // Hexagon V2 Architecture
11 // Application-Level Specification
14 //===----------------------------------------------------------------------===//
16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
17 : Pat <(IntID imm:$Is),
20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
21 : Pat <(IntID I32:$Rs),
24 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
25 : Pat<(IntID I32:$Rs, ImmPred:$It),
26 (MI I32:$Rs, ImmPred:$It)>;
28 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
29 : Pat<(IntID ImmPred:$Is, I32:$Rt),
30 (MI ImmPred:$Is, I32:$Rt)>;
32 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
33 : Pat <(IntID I32:$Rs, I32:$Rt),
34 (MI I32:$Rs, I32:$Rt)>;
36 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
37 : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
38 (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
40 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
41 : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
42 (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
44 //===----------------------------------------------------------------------===//
45 // MPYS / Multipy signed/unsigned halfwords
46 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
47 //===----------------------------------------------------------------------===//
49 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
50 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
51 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
52 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
53 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
54 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
55 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
56 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
58 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
59 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
60 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
61 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
62 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
63 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
64 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
65 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
67 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
68 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
69 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
70 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
71 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
72 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
73 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
74 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
76 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
77 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
78 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
79 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
80 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
81 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
82 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
83 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
85 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
86 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
87 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
88 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
89 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
90 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
91 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
92 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
95 //===----------------------------------------------------------------------===//
96 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
97 // result from the accumulator.
98 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
99 //===----------------------------------------------------------------------===//
101 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
102 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
103 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
104 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
105 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
106 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
107 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
108 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
110 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
111 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
112 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
113 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
114 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
115 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
116 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
117 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
119 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
120 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
121 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
122 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
123 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
124 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
125 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
126 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
128 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
129 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
130 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
131 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
132 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
133 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
134 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
135 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
137 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
138 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
139 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
140 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
141 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
142 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
143 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
144 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
146 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
147 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
148 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
149 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
150 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
151 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
152 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
153 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
156 //===----------------------------------------------------------------------===//
157 // Multiply signed/unsigned halfwords with and without saturation and rounding
158 // into a 64-bits destination register.
159 //===----------------------------------------------------------------------===//
161 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
162 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
163 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
164 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
165 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
166 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
167 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
168 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
170 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
171 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
172 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
173 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
174 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
175 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
176 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
177 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
179 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
180 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
181 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
182 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
183 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
184 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
185 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
186 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
188 //===----------------------------------------------------------------------===//
189 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
190 // result from the 64-bit destination register.
191 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
192 //===----------------------------------------------------------------------===//
194 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
195 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
196 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
197 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
199 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
200 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
201 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
202 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
204 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
205 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
206 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
207 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
209 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
210 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
211 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
212 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
214 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
215 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
216 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
217 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
219 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
220 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
221 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
222 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
224 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
225 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
226 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
227 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
229 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
230 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
231 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
232 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
234 /********************************************************************
236 *********************************************************************/
237 def : T_RR_pat<A2_add, int_hexagon_A2_add>;
238 def : T_RI_pat<ADD_ri, int_hexagon_A2_addi>;
239 def : T_RR_pat<A2_sub, int_hexagon_A2_sub>;
240 def : T_IR_pat<SUB_ri, int_hexagon_A2_subri>;
241 def : T_RR_pat<A2_and, int_hexagon_A2_and>;
242 def : T_RI_pat<AND_ri, int_hexagon_A2_andir>;
243 def : T_RR_pat<A2_or, int_hexagon_A2_or>;
244 def : T_RI_pat<OR_ri, int_hexagon_A2_orir>;
245 def : T_RR_pat<A2_xor, int_hexagon_A2_xor>;
246 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
248 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
249 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
250 (SUB_ri -1, IntRegs:$Rs)>;
252 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
253 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
254 (SUB_ri 0, IntRegs:$Rs)>;
256 // Transfer immediate
257 def : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
258 (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
259 def : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
260 (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
262 // Transfer Register/immediate.
263 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
264 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
266 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
267 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
268 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
274 class qi_ALU32_sisi<string opc, Intrinsic IntID>
275 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
276 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
277 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
279 class qi_ALU32_sis10<string opc, Intrinsic IntID>
280 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
281 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
282 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
284 class qi_ALU32_sis8<string opc, Intrinsic IntID>
285 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
286 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
287 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
289 class qi_ALU32_siu8<string opc, Intrinsic IntID>
290 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
291 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
292 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
294 class qi_ALU32_siu9<string opc, Intrinsic IntID>
295 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
296 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
297 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
299 class si_ALU32_qisisi<string opc, Intrinsic IntID>
300 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
302 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
303 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
306 class si_ALU32_qis8si<string opc, Intrinsic IntID>
307 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
309 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
310 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
313 class si_ALU32_qisis8<string opc, Intrinsic IntID>
314 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
316 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
317 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
320 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
321 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
322 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
323 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
325 class si_ALU32_sisi<string opc, Intrinsic IntID>
326 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
327 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
328 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
330 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
331 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
332 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
333 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
335 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
336 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
337 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
338 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
340 class si_ALU32_sis16<string opc, Intrinsic IntID>
341 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
342 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
343 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
345 class si_ALU32_sis10<string opc, Intrinsic IntID>
346 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
347 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
348 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
350 class si_ALU32_s10si<string opc, Intrinsic IntID>
351 : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
352 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
353 [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
355 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
356 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
357 !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
358 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
360 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
361 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
362 !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
363 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
365 class si_ALU32_s16<string opc, Intrinsic IntID>
366 : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
367 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
368 [(set IntRegs:$dst, (IntID imm:$src1))]>;
370 class di_ALU32_s8<string opc, Intrinsic IntID>
371 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
372 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
373 [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
375 class di_ALU64_di<string opc, Intrinsic IntID>
376 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
377 !strconcat("$dst = ", !strconcat(opc , "$src")),
378 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
380 class si_ALU32_si<string opc, Intrinsic IntID>
381 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
382 !strconcat("$dst = ", !strconcat(opc , "($src)")),
383 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
385 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
386 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
387 !strconcat("$dst = ", !strconcat(opc , "$src")),
388 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
394 class si_ALU64_si_sat<string opc, Intrinsic IntID>
395 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
396 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
397 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
399 class si_ALU64_didi<string opc, Intrinsic IntID>
400 : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
401 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
402 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
404 class di_ALU64_sidi<string opc, Intrinsic IntID>
405 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
406 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
407 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
409 class di_ALU64_didi<string opc, Intrinsic IntID>
410 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
411 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
412 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
413 DoubleRegs:$src2))]>;
415 class di_ALU64_qididi<string opc, Intrinsic IntID>
416 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
418 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
419 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
420 DoubleRegs:$src3))]>;
422 class di_ALU64_sisi<string opc, Intrinsic IntID>
423 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
424 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
425 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
427 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
428 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
429 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
430 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
431 DoubleRegs:$src2))]>;
433 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
434 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
435 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
436 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
437 DoubleRegs:$src2))]>;
439 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
440 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
441 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
442 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
443 DoubleRegs:$src2))]>;
445 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
446 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
447 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
448 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
449 DoubleRegs:$src2))]>;
451 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
452 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
453 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
454 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
455 DoubleRegs:$src2))]>;
457 class qi_ALU64_didi<string opc, Intrinsic IntID>
458 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
459 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
460 [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
462 class si_ALU64_sisi<string opc, Intrinsic IntID>
463 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
464 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
465 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
467 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
468 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
469 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
470 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
472 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
473 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
474 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
475 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
477 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
478 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
479 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
480 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
482 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
483 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
484 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
485 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
487 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
488 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
489 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
490 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
492 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
493 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
494 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
495 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
497 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
498 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
499 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
500 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
502 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
503 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
504 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
505 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
507 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
508 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
509 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
510 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
512 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
513 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
514 !strconcat("$dst = ", !strconcat(opc ,
515 "($src1.H, $src2.H):sat:<<16")),
516 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
518 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
519 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
520 !strconcat("$dst = ", !strconcat(opc ,
521 "($src1.L, $src2.H):sat:<<16")),
522 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
524 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
525 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
526 !strconcat("$dst = ", !strconcat(opc ,
527 "($src1.H, $src2.L):sat:<<16")),
528 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
530 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
531 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
532 !strconcat("$dst = ", !strconcat(opc ,
533 "($src1.L, $src2.L):sat:<<16")),
534 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
536 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
537 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
538 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
539 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
541 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
542 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
543 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
544 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
546 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
547 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
548 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
549 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
551 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
552 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
553 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
554 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
556 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
557 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
558 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
559 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
561 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
562 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
563 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
564 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
566 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
567 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
568 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
569 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
575 class qi_SInst_qi<string opc, Intrinsic IntID>
576 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
577 !strconcat("$dst = ", !strconcat(opc , "($src)")),
578 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
580 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
581 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
582 !strconcat("$dst = ", !strconcat(opc , "$src")),
583 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
585 class qi_SInst_qiqi<string opc, Intrinsic IntID>
586 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
587 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
588 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
590 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
591 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
592 !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
593 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
595 class di_SInst_di<string opc, Intrinsic IntID>
596 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
597 !strconcat("$dst = ", !strconcat(opc , "($src)")),
598 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
600 class di_SInst_di_sat<string opc, Intrinsic IntID>
601 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
602 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
603 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
605 class si_SInst_di<string opc, Intrinsic IntID>
606 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
607 !strconcat("$dst = ", !strconcat(opc , "($src)")),
608 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
610 class si_SInst_di_sat<string opc, Intrinsic IntID>
611 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
612 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
613 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
615 class di_SInst_disi<string opc, Intrinsic IntID>
616 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
617 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
618 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
620 class di_SInst_didi<string opc, Intrinsic IntID>
621 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
622 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
623 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
625 class di_SInst_si<string opc, Intrinsic IntID>
626 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
627 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
628 [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
630 class si_SInst_sisiu3<string opc, Intrinsic IntID>
631 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
632 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
633 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
636 class si_SInst_diu5<string opc, Intrinsic IntID>
637 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
638 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
639 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
641 class si_SInst_disi<string opc, Intrinsic IntID>
642 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
643 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
644 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
646 class si_SInst_sidi<string opc, Intrinsic IntID>
647 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
648 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
649 [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
651 class di_SInst_disisi<string opc, Intrinsic IntID>
652 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
654 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
655 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
658 class di_SInst_sisi<string opc, Intrinsic IntID>
659 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
660 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
661 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
663 class qi_SInst_siu5<string opc, Intrinsic IntID>
664 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
665 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
666 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
668 class qi_SInst_siu6<string opc, Intrinsic IntID>
669 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
670 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
671 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
673 class qi_SInst_sisi<string opc, Intrinsic IntID>
674 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
675 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
676 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
678 class si_SInst_si<string opc, Intrinsic IntID>
679 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
680 !strconcat("$dst = ", !strconcat(opc , "($src)")),
681 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
683 class si_SInst_si_sat<string opc, Intrinsic IntID>
684 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
685 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
686 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
688 class di_SInst_qi<string opc, Intrinsic IntID>
689 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
690 !strconcat("$dst = ", !strconcat(opc , "($src)")),
691 [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
693 class si_SInst_qi<string opc, Intrinsic IntID>
694 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
695 !strconcat("$dst = ", !strconcat(opc , "$src")),
696 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
698 class si_SInst_qiqi<string opc, Intrinsic IntID>
699 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
700 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
701 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
703 class qi_SInst_si<string opc, Intrinsic IntID>
704 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
705 !strconcat("$dst = ", !strconcat(opc , "$src")),
706 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
708 class si_SInst_sisi<string opc, Intrinsic IntID>
709 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
710 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
711 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
713 class di_SInst_diu6<string opc, Intrinsic IntID>
714 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
715 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
716 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
718 class si_SInst_siu5<string opc, Intrinsic IntID>
719 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
720 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
721 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
723 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
724 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
725 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
726 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
728 class si_SInst_siu5u5<string opc, Intrinsic IntID>
729 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
730 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
731 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
733 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
734 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
736 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
737 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
741 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
742 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
744 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
745 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
749 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
750 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
752 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
753 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
758 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
759 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
761 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
762 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
763 DoubleRegs:$src1, IntRegs:$src2))],
766 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
767 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
768 u5Imm:$src2, u5Imm:$src3),
769 !strconcat("$dst = ", !strconcat(opc ,
770 "($src1, #$src2, #$src3)")),
771 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
772 imm:$src2, imm:$src3))],
775 class si_SInst_sisidi<string opc, Intrinsic IntID>
776 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
778 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
779 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
783 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
784 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
785 u6Imm:$src2, u6Imm:$src3),
786 !strconcat("$dst = ", !strconcat(opc ,
787 "($src1, #$src2, #$src3)")),
788 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
789 imm:$src2, imm:$src3))],
792 class di_SInst_dididi<string opc, Intrinsic IntID>
793 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
795 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
796 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
801 class di_SInst_diu6u6<string opc, Intrinsic IntID>
802 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
804 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
805 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
808 class di_SInst_didiqi<string opc, Intrinsic IntID>
809 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
811 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
812 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
815 class di_SInst_didiu3<string opc, Intrinsic IntID>
816 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
818 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
819 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
822 class di_SInst_didisi_or<string opc, Intrinsic IntID>
823 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
825 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
826 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
830 class di_SInst_didisi_and<string opc, Intrinsic IntID>
831 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
833 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
834 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
838 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
839 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
841 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
842 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
846 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
847 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
849 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
850 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
854 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
855 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
857 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
858 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
862 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
863 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
865 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
866 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
870 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
871 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
873 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
874 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
879 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
880 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
882 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
883 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
887 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
888 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
890 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
891 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
895 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
896 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
898 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
899 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
903 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
904 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
906 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
907 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
911 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
912 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
914 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
915 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
919 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
920 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
922 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
923 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
924 DoubleRegs:$src1, imm:$src2))],
927 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
928 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
930 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
931 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
940 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
941 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
942 !strconcat("$dst = ", !strconcat(opc ,
943 "($src1.H, $src2.H):<<1:rnd")),
944 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
946 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
947 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
948 !strconcat("$dst = ", !strconcat(opc ,
949 "($src1.H, $src2.H):rnd")),
950 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
952 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
953 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
954 !strconcat("$dst = ", !strconcat(opc ,
955 "($src1.H, $src2.L):<<1:rnd")),
956 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
958 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
959 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
960 !strconcat("$dst = ", !strconcat(opc ,
961 "($src1.H, $src2.L):rnd")),
962 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
964 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
965 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
966 !strconcat("$dst = ", !strconcat(opc ,
967 "($src1.L, $src2.H):<<1:rnd")),
968 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
970 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
971 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
972 !strconcat("$dst = ", !strconcat(opc ,
973 "($src1.L, $src2.H):rnd")),
974 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
976 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
977 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
978 !strconcat("$dst = ", !strconcat(opc ,
979 "($src1.L, $src2.L):<<1:rnd")),
980 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
982 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
983 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
984 !strconcat("$dst = ", !strconcat(opc ,
985 "($src1.L, $src2.L):rnd")),
986 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
988 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
989 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
991 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
992 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
996 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
997 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
999 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1000 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1004 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1005 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1007 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1008 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1012 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1013 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1015 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1016 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1020 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1021 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1023 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1024 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1028 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1029 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1031 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1032 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1036 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1037 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1039 !strconcat("$dst -= ", !strconcat(opc ,
1040 "($src1, $src2):<<1:sat")),
1041 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1045 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1046 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1048 !strconcat("$dst += ", !strconcat(opc ,
1049 "($src1, $src2*):<<1:sat")),
1050 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1054 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1055 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1057 !strconcat("$dst -= ", !strconcat(opc ,
1058 "($src1, $src2*):<<1:sat")),
1059 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1063 class di_MInst_s8s8<string opc, Intrinsic IntID>
1064 : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1065 !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1066 [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1068 class si_MInst_sis9<string opc, Intrinsic IntID>
1069 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1070 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1071 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1073 class si_MInst_sisi<string opc, Intrinsic IntID>
1074 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1075 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1076 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1078 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1079 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1080 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1081 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1083 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1084 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1085 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1086 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1088 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1089 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1090 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1091 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1093 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1094 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1095 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1096 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1098 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1099 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1100 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1101 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1103 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1104 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1105 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1106 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1108 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1109 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1110 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1111 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1113 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1114 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1115 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1116 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1119 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1120 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1121 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1122 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1124 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1125 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1126 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1127 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1129 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1130 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1131 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1132 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1134 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1135 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1136 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1137 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1139 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1140 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1141 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1142 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1144 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1145 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1146 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1147 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1149 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1150 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1151 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1152 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1154 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1155 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1156 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1157 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1159 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1160 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1161 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1162 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1164 class di_MInst_didi<string opc, Intrinsic IntID>
1165 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1166 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1167 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1168 DoubleRegs:$src2))]>;
1170 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1171 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1172 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1173 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1174 DoubleRegs:$src2))]>;
1176 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1177 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1178 !strconcat("$dst = ", !strconcat(opc ,
1179 "($src1, $src2*):<<1:sat")),
1180 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1182 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1183 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1184 !strconcat("$dst = ", !strconcat(opc ,
1185 "($src1, $src2):<<1:rnd:sat")),
1186 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1187 DoubleRegs:$src2))]>;
1189 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1190 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1191 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1192 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1193 DoubleRegs:$src2))]>;
1195 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1196 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1197 !strconcat("$dst = ", !strconcat(opc ,
1198 "($src1, $src2):rnd:sat")),
1199 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1200 DoubleRegs:$src2))]>;
1202 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1203 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1204 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1205 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1207 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1208 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1209 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1210 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1212 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1213 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1214 !strconcat("$dst = ", !strconcat(opc ,
1215 "($src1, $src2):<<1:rnd:sat")),
1216 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1218 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1219 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1220 !strconcat("$dst = ", !strconcat(opc ,
1221 "($src1, $src2):<<1:rnd:sat")),
1222 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1224 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1225 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1226 !strconcat("$dst = ", !strconcat(opc ,
1227 "($src1, $src2.L):<<1:rnd:sat")),
1228 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1230 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1231 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1232 !strconcat("$dst = ", !strconcat(opc ,
1233 "($src1, $src2.H):<<1:rnd:sat")),
1234 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1236 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1237 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1238 !strconcat("$dst = ", !strconcat(opc ,
1239 "($src1, $src2*):rnd:sat")),
1240 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1242 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1243 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1244 !strconcat("$dst = ", !strconcat(opc ,
1245 "($src1, $src2*):<<1:rnd:sat")),
1246 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1248 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1249 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1250 !strconcat("$dst = ", !strconcat(opc ,
1251 "($src1, $src2):rnd:sat")),
1252 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1254 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1255 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1256 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1257 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1259 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1260 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1262 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1263 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1267 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1268 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1270 !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1271 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1275 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1276 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1278 !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1279 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1283 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1284 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1286 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1287 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1291 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1292 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1294 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1295 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1299 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1300 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1301 u4Imm:$src2, u5Imm:$src3),
1302 !strconcat("$dst = ", !strconcat(opc ,
1303 "($src1, #$src2, #$src3)")),
1304 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1305 imm:$src2, imm:$src3))],
1308 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1309 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1311 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1312 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1316 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1317 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1319 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1320 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1324 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1325 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1327 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1328 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1332 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1333 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1335 !strconcat("$dst += ", !strconcat(opc ,
1336 "($src1.L, $src2.H):sat")),
1337 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1341 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1342 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1344 !strconcat("$dst += ", !strconcat(opc ,
1345 "($src1.L, $src2.H):<<1:sat")),
1346 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1350 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1351 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1353 !strconcat("$dst += ", !strconcat(opc ,
1354 "($src1.H, $src2.H):sat")),
1355 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1359 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1360 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1362 !strconcat("$dst += ", !strconcat(opc ,
1363 "($src1.H, $src2.H):<<1:sat")),
1364 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1368 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1369 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1371 !strconcat("$dst += ", !strconcat(opc ,
1372 "($src1.H, $src2.H):<<1")),
1373 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1377 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1378 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1380 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1381 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1385 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1386 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1388 !strconcat("$dst -= ", !strconcat(opc ,
1389 "($src1.H, $src2.H):<<1:sat")),
1390 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1394 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1395 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1397 !strconcat("$dst -= ", !strconcat(opc ,
1398 "($src1.H, $src2.H):sat")),
1399 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1403 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1404 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1406 !strconcat("$dst -= ", !strconcat(opc ,
1407 "($src1.H, $src2.L):<<1:sat")),
1408 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1412 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1413 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1415 !strconcat("$dst -= ", !strconcat(opc ,
1416 "($src1.H, $src2.L):sat")),
1417 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1421 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1422 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1424 !strconcat("$dst -= ", !strconcat(opc ,
1425 "($src1.L, $src2.H):<<1:sat")),
1426 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1430 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1431 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1433 !strconcat("$dst -= ", !strconcat(opc ,
1434 "($src1.L, $src2.H):sat")),
1435 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1439 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1440 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1442 !strconcat("$dst -= ", !strconcat(opc ,
1443 "($src1.L, $src2.L):<<1:sat")),
1444 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1448 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1449 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1451 !strconcat("$dst -= ", !strconcat(opc ,
1452 "($src1.L, $src2.L):sat")),
1453 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1457 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1458 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1460 !strconcat("$dst -= ", !strconcat(opc ,
1461 "($src1.H, $src2.H):<<1")),
1462 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1466 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1467 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1469 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1470 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1474 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1475 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1477 !strconcat("$dst += ", !strconcat(opc ,
1478 "($src1.H, $src2.L):<<1")),
1479 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1483 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1484 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1486 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1487 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1491 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1492 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1494 !strconcat("$dst -= ", !strconcat(opc ,
1495 "($src1.H, $src2.L):<<1")),
1496 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1500 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1501 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1503 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1504 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1508 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1509 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1511 !strconcat("$dst += ", !strconcat(opc ,
1512 "($src1.L, $src2.H):<<1")),
1513 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1517 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1518 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1520 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1521 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1525 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1526 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1528 !strconcat("$dst -= ", !strconcat(opc ,
1529 "($src1.L, $src2.H):<<1")),
1530 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1534 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1535 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1537 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1538 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1542 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1543 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1545 !strconcat("$dst += ", !strconcat(opc ,
1546 "($src1.L, $src2.L):<<1")),
1547 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1551 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1552 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1554 !strconcat("$dst += ", !strconcat(opc ,
1555 "($src1.L, $src2.L):<<1:sat")),
1556 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1560 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1561 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1563 !strconcat("$dst += ", !strconcat(opc ,
1564 "($src1.H, $src2.L):<<1:sat")),
1565 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1569 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1570 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1572 !strconcat("$dst += ", !strconcat(opc ,
1573 "($src1.L, $src2.L):sat")),
1574 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1578 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1579 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1581 !strconcat("$dst += ", !strconcat(opc ,
1582 "($src1.H, $src2.L):sat")),
1583 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1587 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1588 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1590 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1591 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1595 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1596 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1598 !strconcat("$dst -= ", !strconcat(opc ,
1599 "($src1.L, $src2.L):<<1")),
1600 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1604 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1605 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1607 !strconcat("$dst -= ", !strconcat(opc ,
1608 "($src1.H, $src2.H):sat")),
1609 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1613 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1614 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1616 !strconcat("$dst -= ", !strconcat(opc ,
1617 "($src1.H, $src2.H):<<1:sat")),
1618 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1622 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1623 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1625 !strconcat("$dst -= ", !strconcat(opc ,
1626 "($src1.H, $src2.L):sat")),
1627 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1631 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1632 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1634 !strconcat("$dst -= ", !strconcat(opc ,
1635 "($src1.H, $src2.L):<<1:sat")),
1636 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1640 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1641 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1643 !strconcat("$dst -= ", !strconcat(opc ,
1644 "($src1.L, $src2.H):sat")),
1645 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1649 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1650 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1652 !strconcat("$dst -= ", !strconcat(opc ,
1653 "($src1.L, $src2.H):<<1:sat")),
1654 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1658 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1659 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1661 !strconcat("$dst -= ", !strconcat(opc ,
1662 "($src1.L, $src2.L):sat")),
1663 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1667 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1668 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1670 !strconcat("$dst -= ", !strconcat(opc ,
1671 "($src1.L, $src2.L):<<1:sat")),
1672 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1676 class di_ALU32_sisi<string opc, Intrinsic IntID>
1677 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1678 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1679 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1681 class di_MInst_sisi<string opc, Intrinsic IntID>
1682 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1683 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1684 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1686 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1687 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1688 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1689 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1691 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1692 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1693 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1694 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1696 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1697 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1698 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1699 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1701 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1702 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1703 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1704 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1705 DoubleRegs:$src2))]>;
1707 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1708 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1709 !strconcat("$dst = ", !strconcat(opc ,
1710 "($src1, $src2):<<1:rnd:sat")),
1711 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1713 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1714 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1715 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1716 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1718 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1719 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1720 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1721 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1723 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1724 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1725 !strconcat("$dst = ", !strconcat(opc ,
1726 "($src1.H, $src2.H):<<1:sat")),
1727 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1729 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1730 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1731 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1732 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1734 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1735 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1736 !strconcat("$dst = ", !strconcat(opc ,
1737 "($src1.H, $src2.L):<<1:sat")),
1738 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1740 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1741 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1742 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1743 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1745 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1746 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1747 !strconcat("$dst = ", !strconcat(opc ,
1748 "($src1.L, $src2.H):<<1:sat")),
1749 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1751 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1752 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1753 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1754 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1756 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1757 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1758 !strconcat("$dst = ", !strconcat(opc ,
1759 "($src1.L, $src2.L):<<1:sat")),
1760 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1762 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1763 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1764 !strconcat("$dst = ", !strconcat(opc ,
1765 "($src1.H, $src2.H):rnd:sat")),
1766 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1768 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1769 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1770 !strconcat("$dst = ", !strconcat(opc ,
1771 "($src1.H, $src2.H):rnd")),
1772 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1774 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1775 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1776 !strconcat("$dst = ", !strconcat(opc ,
1777 "($src1.H, $src2.H):<<1:rnd")),
1778 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1780 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1781 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1782 !strconcat("$dst = ",
1784 "($src1.H, $src2.H):<<1:rnd:sat")),
1785 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1787 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1788 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1789 !strconcat("$dst = ",
1790 !strconcat(opc , "($src1.H, $src2.L):rnd")),
1791 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1793 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1794 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1795 !strconcat("$dst = ",
1796 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1797 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1799 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1800 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1801 !strconcat("$dst = ",
1802 !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1803 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1805 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1806 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1807 !strconcat("$dst = ",
1808 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1809 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1811 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1812 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1813 !strconcat("$dst = ",
1814 !strconcat(opc , "($src1.L, $src2.H):rnd")),
1815 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1817 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1818 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1819 !strconcat("$dst = ",
1820 !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1821 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1823 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1824 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1825 !strconcat("$dst = ",
1826 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1827 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1829 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1830 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1831 !strconcat("$dst = ",
1832 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1833 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1835 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1836 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1837 !strconcat("$dst = ",
1838 !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1839 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1841 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1842 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1843 !strconcat("$dst = ",
1844 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1845 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1847 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1848 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1849 !strconcat("$dst = ",
1850 !strconcat(opc , "($src1.L, $src2.L):rnd")),
1851 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1853 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1854 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1855 !strconcat("$dst = ",
1856 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1857 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1859 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1860 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1861 DoubleRegs:$src1, DoubleRegs:$src2),
1862 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1863 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1865 DoubleRegs:$src2))],
1868 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1869 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1871 !strconcat("$dst += ",
1872 !strconcat(opc , "($src1, $src2):rnd:sat")),
1873 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1875 DoubleRegs:$src2))],
1878 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1879 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1882 !strconcat("$dst += ",
1883 !strconcat(opc , "($src1, $src2):<<1")),
1884 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1886 DoubleRegs:$src2))],
1890 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1891 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1894 !strconcat("$dst += ",
1895 !strconcat(opc , "($src1, $src2):<<1:sat")),
1896 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1898 DoubleRegs:$src2))],
1901 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1902 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1904 !strconcat("$dst += ",
1905 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1906 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1908 DoubleRegs:$src2))],
1911 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1912 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1914 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1915 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1917 DoubleRegs:$src2))],
1920 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1921 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1923 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1924 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1926 DoubleRegs:$src2))],
1929 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1930 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1932 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1933 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1937 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1938 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1940 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1941 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1945 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1946 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1948 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1949 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1953 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
1954 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1956 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1957 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1961 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
1962 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1964 !strconcat("$dst += ",
1965 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1966 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1970 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
1971 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1973 !strconcat("$dst += ",
1974 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1975 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1979 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
1980 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1982 !strconcat("$dst += ",
1983 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1984 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1988 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
1989 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1991 !strconcat("$dst += ",
1992 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1993 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1997 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
1998 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2000 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
2001 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2005 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
2006 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2008 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
2009 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2013 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
2014 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2016 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2017 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2021 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
2022 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2024 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2025 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2029 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
2030 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2032 !strconcat("$dst -= ",
2033 !strconcat(opc , "($src1.H, $src2.H):<<1")),
2034 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2038 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
2039 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2041 !strconcat("$dst -= ",
2042 !strconcat(opc , "($src1.H, $src2.L):<<1")),
2043 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2047 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
2048 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2050 !strconcat("$dst -= ",
2051 !strconcat(opc , "($src1.L, $src2.H):<<1")),
2052 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2056 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2057 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2059 !strconcat("$dst -= ",
2060 !strconcat(opc , "($src1.L, $src2.L):<<1")),
2061 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2065 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2066 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2068 !strconcat("$dst += ",
2069 !strconcat(opc , "($src1, $src2):<<1:sat")),
2070 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2074 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2075 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2076 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2077 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2079 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2080 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2082 !strconcat("$dst += ",
2083 !strconcat(opc , "($src1, $src2):<<1:sat")),
2084 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2089 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2090 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2091 !strconcat("$dst = ",
2092 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2093 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2095 class si_MInst_didi<string opc, Intrinsic IntID>
2096 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2097 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2098 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2103 let mayLoad = 1, hasSideEffects = 0 in
2104 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2105 : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2106 (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2107 "$dst2 = memd($src1++#$offset:circ($src3))",
2111 /********************************************************************
2113 *********************************************************************/
2115 // ALU32 / PERM / Combine.
2116 def HEXAGON_A2_combinew:
2117 di_ALU32_sisi <"combine", int_hexagon_A2_combinew>;
2118 def HEXAGON_A2_combine_hh:
2119 si_MInst_sisi_hh <"combine", int_hexagon_A2_combine_hh>;
2120 def HEXAGON_A2_combine_lh:
2121 si_MInst_sisi_lh <"combine", int_hexagon_A2_combine_lh>;
2122 def HEXAGON_A2_combine_hl:
2123 si_MInst_sisi_hl <"combine", int_hexagon_A2_combine_hl>;
2124 def HEXAGON_A2_combine_ll:
2125 si_MInst_sisi_ll <"combine", int_hexagon_A2_combine_ll>;
2126 def HEXAGON_A2_combineii:
2127 di_MInst_s8s8 <"combine", int_hexagon_A2_combineii>;
2129 // ALU32 / PERM / Mux.
2131 si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
2132 def HEXAGON_C2_muxri:
2133 si_ALU32_qis8si <"mux", int_hexagon_C2_muxri>;
2134 def HEXAGON_C2_muxir:
2135 si_ALU32_qisis8 <"mux", int_hexagon_C2_muxir>;
2136 def HEXAGON_C2_muxii:
2137 si_ALU32_qis8s8 <"mux", int_hexagon_C2_muxii>;
2139 // ALU32 / PERM / Shift halfword.
2140 def HEXAGON_A2_aslh:
2141 si_ALU32_si <"aslh", int_hexagon_A2_aslh>;
2142 def HEXAGON_A2_asrh:
2143 si_ALU32_si <"asrh", int_hexagon_A2_asrh>;
2144 def SI_to_SXTHI_asrh:
2145 si_ALU32_si <"asrh", int_hexagon_SI_to_SXTHI_asrh>;
2147 // ALU32 / PERM / Sign/zero extend.
2148 def HEXAGON_A2_sxth:
2149 si_ALU32_si <"sxth", int_hexagon_A2_sxth>;
2150 def HEXAGON_A2_sxtb:
2151 si_ALU32_si <"sxtb", int_hexagon_A2_sxtb>;
2152 def HEXAGON_A2_zxth:
2153 si_ALU32_si <"zxth", int_hexagon_A2_zxth>;
2154 def HEXAGON_A2_zxtb:
2155 si_ALU32_si <"zxtb", int_hexagon_A2_zxtb>;
2157 /********************************************************************
2159 *********************************************************************/
2161 // ALU32 / PRED / Compare.
2162 def HEXAGON_C2_cmpeq:
2163 qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
2164 def HEXAGON_C2_cmpeqi:
2165 qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
2166 def HEXAGON_C2_cmpgei:
2167 qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
2168 def HEXAGON_C2_cmpgeui:
2169 qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
2170 def HEXAGON_C2_cmpgt:
2171 qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
2172 def HEXAGON_C2_cmpgti:
2173 qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
2174 def HEXAGON_C2_cmpgtu:
2175 qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
2176 def HEXAGON_C2_cmpgtui:
2177 qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
2178 def HEXAGON_C2_cmplt:
2179 qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
2180 def HEXAGON_C2_cmpltu:
2181 qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
2183 /********************************************************************
2185 *********************************************************************/
2187 // ALU32 / VH / Vector add halfwords.
2188 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2189 def HEXAGON_A2_svaddh:
2190 si_ALU32_sisi <"vaddh", int_hexagon_A2_svaddh>;
2191 def HEXAGON_A2_svaddhs:
2192 si_ALU32_sisi_sat <"vaddh", int_hexagon_A2_svaddhs>;
2193 def HEXAGON_A2_svadduhs:
2194 si_ALU32_sisi_sat <"vadduh", int_hexagon_A2_svadduhs>;
2196 // ALU32 / VH / Vector average halfwords.
2197 def HEXAGON_A2_svavgh:
2198 si_ALU32_sisi <"vavgh", int_hexagon_A2_svavgh>;
2199 def HEXAGON_A2_svavghs:
2200 si_ALU32_sisi_rnd <"vavgh", int_hexagon_A2_svavghs>;
2201 def HEXAGON_A2_svnavgh:
2202 si_ALU32_sisi <"vnavgh", int_hexagon_A2_svnavgh>;
2204 // ALU32 / VH / Vector subtract halfwords.
2205 def HEXAGON_A2_svsubh:
2206 si_ALU32_sisi <"vsubh", int_hexagon_A2_svsubh>;
2207 def HEXAGON_A2_svsubhs:
2208 si_ALU32_sisi_sat <"vsubh", int_hexagon_A2_svsubhs>;
2209 def HEXAGON_A2_svsubuhs:
2210 si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
2212 /********************************************************************
2214 *********************************************************************/
2216 // ALU64 / ALU / Add.
2217 def HEXAGON_A2_addp:
2218 di_ALU64_didi <"add", int_hexagon_A2_addp>;
2219 def HEXAGON_A2_addsat:
2220 si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>;
2222 // ALU64 / ALU / Add halfword.
2223 // Even though the definition says hl, it should be lh -
2224 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2225 def HEXAGON_A2_addh_l16_hl:
2226 si_ALU64_sisi_l16_lh <"add", int_hexagon_A2_addh_l16_hl>;
2227 def HEXAGON_A2_addh_l16_ll:
2228 si_ALU64_sisi_l16_ll <"add", int_hexagon_A2_addh_l16_ll>;
2230 def HEXAGON_A2_addh_l16_sat_hl:
2231 si_ALU64_sisi_l16_sat_lh <"add", int_hexagon_A2_addh_l16_sat_hl>;
2232 def HEXAGON_A2_addh_l16_sat_ll:
2233 si_ALU64_sisi_l16_sat_ll <"add", int_hexagon_A2_addh_l16_sat_ll>;
2235 def HEXAGON_A2_addh_h16_hh:
2236 si_ALU64_sisi_h16_hh <"add", int_hexagon_A2_addh_h16_hh>;
2237 def HEXAGON_A2_addh_h16_hl:
2238 si_ALU64_sisi_h16_hl <"add", int_hexagon_A2_addh_h16_hl>;
2239 def HEXAGON_A2_addh_h16_lh:
2240 si_ALU64_sisi_h16_lh <"add", int_hexagon_A2_addh_h16_lh>;
2241 def HEXAGON_A2_addh_h16_ll:
2242 si_ALU64_sisi_h16_ll <"add", int_hexagon_A2_addh_h16_ll>;
2244 def HEXAGON_A2_addh_h16_sat_hh:
2245 si_ALU64_sisi_h16_sat_hh <"add", int_hexagon_A2_addh_h16_sat_hh>;
2246 def HEXAGON_A2_addh_h16_sat_hl:
2247 si_ALU64_sisi_h16_sat_hl <"add", int_hexagon_A2_addh_h16_sat_hl>;
2248 def HEXAGON_A2_addh_h16_sat_lh:
2249 si_ALU64_sisi_h16_sat_lh <"add", int_hexagon_A2_addh_h16_sat_lh>;
2250 def HEXAGON_A2_addh_h16_sat_ll:
2251 si_ALU64_sisi_h16_sat_ll <"add", int_hexagon_A2_addh_h16_sat_ll>;
2253 // ALU64 / ALU / Compare.
2254 def HEXAGON_C2_cmpeqp:
2255 qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
2256 def HEXAGON_C2_cmpgtp:
2257 qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
2258 def HEXAGON_C2_cmpgtup:
2259 qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
2261 // ALU64 / ALU / Logical operations.
2262 def HEXAGON_A2_andp:
2263 di_ALU64_didi <"and", int_hexagon_A2_andp>;
2265 di_ALU64_didi <"or", int_hexagon_A2_orp>;
2266 def HEXAGON_A2_xorp:
2267 di_ALU64_didi <"xor", int_hexagon_A2_xorp>;
2269 // ALU64 / ALU / Maximum.
2271 si_ALU64_sisi <"max", int_hexagon_A2_max>;
2272 def HEXAGON_A2_maxu:
2273 si_ALU64_sisi <"maxu", int_hexagon_A2_maxu>;
2275 // ALU64 / ALU / Minimum.
2277 si_ALU64_sisi <"min", int_hexagon_A2_min>;
2278 def HEXAGON_A2_minu:
2279 si_ALU64_sisi <"minu", int_hexagon_A2_minu>;
2281 // ALU64 / ALU / Subtract.
2282 def HEXAGON_A2_subp:
2283 di_ALU64_didi <"sub", int_hexagon_A2_subp>;
2284 def HEXAGON_A2_subsat:
2285 si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>;
2287 // ALU64 / ALU / Subtract halfword.
2288 // Even though the definition says hl, it should be lh -
2289 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2290 def HEXAGON_A2_subh_l16_hl:
2291 si_ALU64_sisi_l16_lh <"sub", int_hexagon_A2_subh_l16_hl>;
2292 def HEXAGON_A2_subh_l16_ll:
2293 si_ALU64_sisi_l16_ll <"sub", int_hexagon_A2_subh_l16_ll>;
2295 def HEXAGON_A2_subh_l16_sat_hl:
2296 si_ALU64_sisi_l16_sat_lh <"sub", int_hexagon_A2_subh_l16_sat_hl>;
2297 def HEXAGON_A2_subh_l16_sat_ll:
2298 si_ALU64_sisi_l16_sat_ll <"sub", int_hexagon_A2_subh_l16_sat_ll>;
2300 def HEXAGON_A2_subh_h16_hh:
2301 si_ALU64_sisi_h16_hh <"sub", int_hexagon_A2_subh_h16_hh>;
2302 def HEXAGON_A2_subh_h16_hl:
2303 si_ALU64_sisi_h16_hl <"sub", int_hexagon_A2_subh_h16_hl>;
2304 def HEXAGON_A2_subh_h16_lh:
2305 si_ALU64_sisi_h16_lh <"sub", int_hexagon_A2_subh_h16_lh>;
2306 def HEXAGON_A2_subh_h16_ll:
2307 si_ALU64_sisi_h16_ll <"sub", int_hexagon_A2_subh_h16_ll>;
2309 def HEXAGON_A2_subh_h16_sat_hh:
2310 si_ALU64_sisi_h16_sat_hh <"sub", int_hexagon_A2_subh_h16_sat_hh>;
2311 def HEXAGON_A2_subh_h16_sat_hl:
2312 si_ALU64_sisi_h16_sat_hl <"sub", int_hexagon_A2_subh_h16_sat_hl>;
2313 def HEXAGON_A2_subh_h16_sat_lh:
2314 si_ALU64_sisi_h16_sat_lh <"sub", int_hexagon_A2_subh_h16_sat_lh>;
2315 def HEXAGON_A2_subh_h16_sat_ll:
2316 si_ALU64_sisi_h16_sat_ll <"sub", int_hexagon_A2_subh_h16_sat_ll>;
2318 // ALU64 / ALU / Transfer register.
2319 def HEXAGON_A2_tfrp:
2320 di_ALU64_di <"", int_hexagon_A2_tfrp>;
2322 /********************************************************************
2324 *********************************************************************/
2326 // ALU64 / BIT / Masked parity.
2327 def HEXAGON_S2_parityp:
2328 si_ALU64_didi <"parity", int_hexagon_S2_parityp>;
2330 /********************************************************************
2332 *********************************************************************/
2334 // ALU64 / PERM / Vector pack high and low halfwords.
2335 def HEXAGON_S2_packhl:
2336 di_ALU64_sisi <"packhl", int_hexagon_S2_packhl>;
2338 /********************************************************************
2340 *********************************************************************/
2342 // ALU64 / VB / Vector add unsigned bytes.
2343 def HEXAGON_A2_vaddub:
2344 di_ALU64_didi <"vaddub", int_hexagon_A2_vaddub>;
2345 def HEXAGON_A2_vaddubs:
2346 di_ALU64_didi_sat <"vaddub", int_hexagon_A2_vaddubs>;
2348 // ALU64 / VB / Vector average unsigned bytes.
2349 def HEXAGON_A2_vavgub:
2350 di_ALU64_didi <"vavgub", int_hexagon_A2_vavgub>;
2351 def HEXAGON_A2_vavgubr:
2352 di_ALU64_didi_rnd <"vavgub", int_hexagon_A2_vavgubr>;
2354 // ALU64 / VB / Vector compare unsigned bytes.
2355 def HEXAGON_A2_vcmpbeq:
2356 qi_ALU64_didi <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2357 def HEXAGON_A2_vcmpbgtu:
2358 qi_ALU64_didi <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2360 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2361 def HEXAGON_A2_vmaxub:
2362 di_ALU64_didi <"vmaxub", int_hexagon_A2_vmaxub>;
2363 def HEXAGON_A2_vminub:
2364 di_ALU64_didi <"vminub", int_hexagon_A2_vminub>;
2366 // ALU64 / VB / Vector subtract unsigned bytes.
2367 def HEXAGON_A2_vsubub:
2368 di_ALU64_didi <"vsubub", int_hexagon_A2_vsubub>;
2369 def HEXAGON_A2_vsububs:
2370 di_ALU64_didi_sat <"vsubub", int_hexagon_A2_vsububs>;
2372 // ALU64 / VB / Vector mux.
2373 def HEXAGON_C2_vmux:
2374 di_ALU64_qididi <"vmux", int_hexagon_C2_vmux>;
2377 /********************************************************************
2379 *********************************************************************/
2381 // ALU64 / VH / Vector add halfwords.
2382 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2383 def HEXAGON_A2_vaddh:
2384 di_ALU64_didi <"vaddh", int_hexagon_A2_vaddh>;
2385 def HEXAGON_A2_vaddhs:
2386 di_ALU64_didi_sat <"vaddh", int_hexagon_A2_vaddhs>;
2387 def HEXAGON_A2_vadduhs:
2388 di_ALU64_didi_sat <"vadduh", int_hexagon_A2_vadduhs>;
2390 // ALU64 / VH / Vector average halfwords.
2391 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2392 def HEXAGON_A2_vavgh:
2393 di_ALU64_didi <"vavgh", int_hexagon_A2_vavgh>;
2394 def HEXAGON_A2_vavghcr:
2395 di_ALU64_didi_crnd <"vavgh", int_hexagon_A2_vavghcr>;
2396 def HEXAGON_A2_vavghr:
2397 di_ALU64_didi_rnd <"vavgh", int_hexagon_A2_vavghr>;
2398 def HEXAGON_A2_vavguh:
2399 di_ALU64_didi <"vavguh", int_hexagon_A2_vavguh>;
2400 def HEXAGON_A2_vavguhr:
2401 di_ALU64_didi_rnd <"vavguh", int_hexagon_A2_vavguhr>;
2402 def HEXAGON_A2_vnavgh:
2403 di_ALU64_didi <"vnavgh", int_hexagon_A2_vnavgh>;
2404 def HEXAGON_A2_vnavghcr:
2405 di_ALU64_didi_crnd_sat <"vnavgh", int_hexagon_A2_vnavghcr>;
2406 def HEXAGON_A2_vnavghr:
2407 di_ALU64_didi_rnd_sat <"vnavgh", int_hexagon_A2_vnavghr>;
2409 // ALU64 / VH / Vector compare halfwords.
2410 def HEXAGON_A2_vcmpheq:
2411 qi_ALU64_didi <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2412 def HEXAGON_A2_vcmphgt:
2413 qi_ALU64_didi <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2414 def HEXAGON_A2_vcmphgtu:
2415 qi_ALU64_didi <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2417 // ALU64 / VH / Vector maximum halfwords.
2418 def HEXAGON_A2_vmaxh:
2419 di_ALU64_didi <"vmaxh", int_hexagon_A2_vmaxh>;
2420 def HEXAGON_A2_vmaxuh:
2421 di_ALU64_didi <"vmaxuh", int_hexagon_A2_vmaxuh>;
2423 // ALU64 / VH / Vector minimum halfwords.
2424 def HEXAGON_A2_vminh:
2425 di_ALU64_didi <"vminh", int_hexagon_A2_vminh>;
2426 def HEXAGON_A2_vminuh:
2427 di_ALU64_didi <"vminuh", int_hexagon_A2_vminuh>;
2429 // ALU64 / VH / Vector subtract halfwords.
2430 def HEXAGON_A2_vsubh:
2431 di_ALU64_didi <"vsubh", int_hexagon_A2_vsubh>;
2432 def HEXAGON_A2_vsubhs:
2433 di_ALU64_didi_sat <"vsubh", int_hexagon_A2_vsubhs>;
2434 def HEXAGON_A2_vsubuhs:
2435 di_ALU64_didi_sat <"vsubuh", int_hexagon_A2_vsubuhs>;
2438 /********************************************************************
2440 *********************************************************************/
2442 // ALU64 / VW / Vector add words.
2443 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2444 def HEXAGON_A2_vaddw:
2445 di_ALU64_didi <"vaddw", int_hexagon_A2_vaddw>;
2446 def HEXAGON_A2_vaddws:
2447 di_ALU64_didi_sat <"vaddw", int_hexagon_A2_vaddws>;
2449 // ALU64 / VW / Vector average words.
2450 def HEXAGON_A2_vavguw:
2451 di_ALU64_didi <"vavguw", int_hexagon_A2_vavguw>;
2452 def HEXAGON_A2_vavguwr:
2453 di_ALU64_didi_rnd <"vavguw", int_hexagon_A2_vavguwr>;
2454 def HEXAGON_A2_vavgw:
2455 di_ALU64_didi <"vavgw", int_hexagon_A2_vavgw>;
2456 def HEXAGON_A2_vavgwcr:
2457 di_ALU64_didi_crnd <"vavgw", int_hexagon_A2_vavgwcr>;
2458 def HEXAGON_A2_vavgwr:
2459 di_ALU64_didi_rnd <"vavgw", int_hexagon_A2_vavgwr>;
2460 def HEXAGON_A2_vnavgw:
2461 di_ALU64_didi <"vnavgw", int_hexagon_A2_vnavgw>;
2462 def HEXAGON_A2_vnavgwcr:
2463 di_ALU64_didi_crnd_sat <"vnavgw", int_hexagon_A2_vnavgwcr>;
2464 def HEXAGON_A2_vnavgwr:
2465 di_ALU64_didi_rnd_sat <"vnavgw", int_hexagon_A2_vnavgwr>;
2467 // ALU64 / VW / Vector compare words.
2468 def HEXAGON_A2_vcmpweq:
2469 qi_ALU64_didi <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2470 def HEXAGON_A2_vcmpwgt:
2471 qi_ALU64_didi <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2472 def HEXAGON_A2_vcmpwgtu:
2473 qi_ALU64_didi <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2475 // ALU64 / VW / Vector maximum words.
2476 def HEXAGON_A2_vmaxw:
2477 di_ALU64_didi <"vmaxw", int_hexagon_A2_vmaxw>;
2478 def HEXAGON_A2_vmaxuw:
2479 di_ALU64_didi <"vmaxuw", int_hexagon_A2_vmaxuw>;
2481 // ALU64 / VW / Vector minimum words.
2482 def HEXAGON_A2_vminw:
2483 di_ALU64_didi <"vminw", int_hexagon_A2_vminw>;
2484 def HEXAGON_A2_vminuw:
2485 di_ALU64_didi <"vminuw", int_hexagon_A2_vminuw>;
2487 // ALU64 / VW / Vector subtract words.
2488 def HEXAGON_A2_vsubw:
2489 di_ALU64_didi <"vsubw", int_hexagon_A2_vsubw>;
2490 def HEXAGON_A2_vsubws:
2491 di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
2494 /********************************************************************
2496 *********************************************************************/
2498 // CR / Logical reductions on predicates.
2499 def HEXAGON_C2_all8:
2500 qi_SInst_qi <"all8", int_hexagon_C2_all8>;
2501 def HEXAGON_C2_any8:
2502 qi_SInst_qi <"any8", int_hexagon_C2_any8>;
2504 // CR / Logical operations on predicates.
2505 def HEXAGON_C2_pxfer_map:
2506 qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
2508 qi_SInst_qiqi <"and", int_hexagon_C2_and>;
2509 def HEXAGON_C2_andn:
2510 qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
2512 qi_SInst_qi <"not", int_hexagon_C2_not>;
2514 qi_SInst_qiqi <"or", int_hexagon_C2_or>;
2516 qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
2518 qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
2521 /********************************************************************
2523 *********************************************************************/
2525 // MTYPE / ALU / Add and accumulate.
2526 def HEXAGON_M2_acci:
2527 si_MInst_sisisi_acc <"add", int_hexagon_M2_acci>;
2528 def HEXAGON_M2_accii:
2529 si_MInst_sisis8_acc <"add", int_hexagon_M2_accii>;
2530 def HEXAGON_M2_nacci:
2531 si_MInst_sisisi_nac <"add", int_hexagon_M2_nacci>;
2532 def HEXAGON_M2_naccii:
2533 si_MInst_sisis8_nac <"add", int_hexagon_M2_naccii>;
2535 // MTYPE / ALU / Subtract and accumulate.
2536 def HEXAGON_M2_subacc:
2537 si_MInst_sisisi_acc <"sub", int_hexagon_M2_subacc>;
2539 // MTYPE / ALU / Vector absolute difference.
2540 def HEXAGON_M2_vabsdiffh:
2541 di_MInst_didi <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2542 def HEXAGON_M2_vabsdiffw:
2543 di_MInst_didi <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2545 // MTYPE / ALU / XOR and xor with destination.
2546 def HEXAGON_M2_xor_xacc:
2547 si_MInst_sisisi_xacc <"xor", int_hexagon_M2_xor_xacc>;
2550 /********************************************************************
2552 *********************************************************************/
2554 // MTYPE / COMPLEX / Complex multiply.
2555 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2556 def HEXAGON_M2_cmpys_s1:
2557 di_MInst_sisi_s1_sat <"cmpy", int_hexagon_M2_cmpys_s1>;
2558 def HEXAGON_M2_cmpys_s0:
2559 di_MInst_sisi_sat <"cmpy", int_hexagon_M2_cmpys_s0>;
2560 def HEXAGON_M2_cmpysc_s1:
2561 di_MInst_sisi_s1_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s1>;
2562 def HEXAGON_M2_cmpysc_s0:
2563 di_MInst_sisi_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s0>;
2565 def HEXAGON_M2_cmacs_s1:
2566 di_MInst_disisi_acc_s1_sat <"cmpy", int_hexagon_M2_cmacs_s1>;
2567 def HEXAGON_M2_cmacs_s0:
2568 di_MInst_disisi_acc_sat <"cmpy", int_hexagon_M2_cmacs_s0>;
2569 def HEXAGON_M2_cmacsc_s1:
2570 di_MInst_disisi_acc_s1_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s1>;
2571 def HEXAGON_M2_cmacsc_s0:
2572 di_MInst_disisi_acc_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s0>;
2574 def HEXAGON_M2_cnacs_s1:
2575 di_MInst_disisi_nac_s1_sat <"cmpy", int_hexagon_M2_cnacs_s1>;
2576 def HEXAGON_M2_cnacs_s0:
2577 di_MInst_disisi_nac_sat <"cmpy", int_hexagon_M2_cnacs_s0>;
2578 def HEXAGON_M2_cnacsc_s1:
2579 di_MInst_disisi_nac_s1_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s1>;
2580 def HEXAGON_M2_cnacsc_s0:
2581 di_MInst_disisi_nac_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s0>;
2583 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2584 def HEXAGON_M2_cmpyr_s0:
2585 di_MInst_sisi <"cmpyr", int_hexagon_M2_cmpyr_s0>;
2586 def HEXAGON_M2_cmacr_s0:
2587 di_MInst_disisi_acc <"cmpyr", int_hexagon_M2_cmacr_s0>;
2589 def HEXAGON_M2_cmpyi_s0:
2590 di_MInst_sisi <"cmpyi", int_hexagon_M2_cmpyi_s0>;
2591 def HEXAGON_M2_cmaci_s0:
2592 di_MInst_disisi_acc <"cmpyi", int_hexagon_M2_cmaci_s0>;
2594 // MTYPE / COMPLEX / Complex multiply with round and pack.
2595 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2596 def HEXAGON_M2_cmpyrs_s0:
2597 si_MInst_sisi_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s0>;
2598 def HEXAGON_M2_cmpyrs_s1:
2599 si_MInst_sisi_s1_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s1>;
2601 def HEXAGON_M2_cmpyrsc_s0:
2602 si_MInst_sisi_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s0>;
2603 def HEXAGON_M2_cmpyrsc_s1:
2604 si_MInst_sisi_s1_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s1>;
2606 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2607 def HEXAGON_M2_vcmpy_s0_sat_i:
2608 di_MInst_didi_sat <"vcmpyi", int_hexagon_M2_vcmpy_s0_sat_i>;
2609 def HEXAGON_M2_vcmpy_s1_sat_i:
2610 di_MInst_didi_s1_sat <"vcmpyi", int_hexagon_M2_vcmpy_s1_sat_i>;
2612 def HEXAGON_M2_vcmpy_s0_sat_r:
2613 di_MInst_didi_sat <"vcmpyr", int_hexagon_M2_vcmpy_s0_sat_r>;
2614 def HEXAGON_M2_vcmpy_s1_sat_r:
2615 di_MInst_didi_s1_sat <"vcmpyr", int_hexagon_M2_vcmpy_s1_sat_r>;
2617 def HEXAGON_M2_vcmac_s0_sat_i:
2618 di_MInst_dididi_acc_sat <"vcmpyi", int_hexagon_M2_vcmac_s0_sat_i>;
2619 def HEXAGON_M2_vcmac_s0_sat_r:
2620 di_MInst_dididi_acc_sat <"vcmpyr", int_hexagon_M2_vcmac_s0_sat_r>;
2622 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2623 def HEXAGON_M2_vrcmpyi_s0:
2624 di_MInst_didi <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0>;
2625 def HEXAGON_M2_vrcmpyr_s0:
2626 di_MInst_didi <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0>;
2628 def HEXAGON_M2_vrcmpyi_s0c:
2629 di_MInst_didi_conj <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0c>;
2630 def HEXAGON_M2_vrcmpyr_s0c:
2631 di_MInst_didi_conj <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0c>;
2633 def HEXAGON_M2_vrcmaci_s0:
2634 di_MInst_dididi_acc <"vrcmpyi", int_hexagon_M2_vrcmaci_s0>;
2635 def HEXAGON_M2_vrcmacr_s0:
2636 di_MInst_dididi_acc <"vrcmpyr", int_hexagon_M2_vrcmacr_s0>;
2638 def HEXAGON_M2_vrcmaci_s0c:
2639 di_MInst_dididi_acc_conj <"vrcmpyi", int_hexagon_M2_vrcmaci_s0c>;
2640 def HEXAGON_M2_vrcmacr_s0c:
2641 di_MInst_dididi_acc_conj <"vrcmpyr", int_hexagon_M2_vrcmacr_s0c>;
2644 /********************************************************************
2646 *********************************************************************/
2648 // MTYPE / MPYH / Multiply and use lower result.
2649 //def HEXAGON_M2_mpysmi:
2650 //FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
2651 // not si_MInst_sis9 - but for now, we will use s9.
2652 // def Hexagon_M2_mpysmi:
2653 // si_MInst_sim9 <"mpyi", int_hexagon_M2_mpysmi>;
2654 def Hexagon_M2_mpysmi:
2655 si_MInst_sis9 <"mpyi", int_hexagon_M2_mpysmi>;
2656 def HEXAGON_M2_mpyi:
2657 si_MInst_sisi <"mpyi", int_hexagon_M2_mpyi>;
2658 def HEXAGON_M2_mpyui:
2659 si_MInst_sisi <"mpyui", int_hexagon_M2_mpyui>;
2660 def HEXAGON_M2_macsip:
2661 si_MInst_sisiu8_acc <"mpyi", int_hexagon_M2_macsip>;
2662 def HEXAGON_M2_maci:
2663 si_MInst_sisisi_acc <"mpyi", int_hexagon_M2_maci>;
2664 def HEXAGON_M2_macsin:
2665 si_MInst_sisiu8_nac <"mpyi", int_hexagon_M2_macsin>;
2667 // MTYPE / MPYH / Multiply word by half (32x16).
2668 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2669 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2670 def HEXAGON_M2_mmpyl_rs1:
2671 di_MInst_didi_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs1>;
2672 def HEXAGON_M2_mmpyl_s1:
2673 di_MInst_didi_s1_sat <"vmpyweh", int_hexagon_M2_mmpyl_s1>;
2674 def HEXAGON_M2_mmpyl_rs0:
2675 di_MInst_didi_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs0>;
2676 def HEXAGON_M2_mmpyl_s0:
2677 di_MInst_didi_sat <"vmpyweh", int_hexagon_M2_mmpyl_s0>;
2678 def HEXAGON_M2_mmpyh_rs1:
2679 di_MInst_didi_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs1>;
2680 def HEXAGON_M2_mmpyh_s1:
2681 di_MInst_didi_s1_sat <"vmpywoh", int_hexagon_M2_mmpyh_s1>;
2682 def HEXAGON_M2_mmpyh_rs0:
2683 di_MInst_didi_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs0>;
2684 def HEXAGON_M2_mmpyh_s0:
2685 di_MInst_didi_sat <"vmpywoh", int_hexagon_M2_mmpyh_s0>;
2686 def HEXAGON_M2_mmacls_rs1:
2687 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs1>;
2688 def HEXAGON_M2_mmacls_s1:
2689 di_MInst_dididi_acc_s1_sat <"vmpyweh", int_hexagon_M2_mmacls_s1>;
2690 def HEXAGON_M2_mmacls_rs0:
2691 di_MInst_dididi_acc_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs0>;
2692 def HEXAGON_M2_mmacls_s0:
2693 di_MInst_dididi_acc_sat <"vmpyweh", int_hexagon_M2_mmacls_s0>;
2694 def HEXAGON_M2_mmachs_rs1:
2695 di_MInst_dididi_acc_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs1>;
2696 def HEXAGON_M2_mmachs_s1:
2697 di_MInst_dididi_acc_s1_sat <"vmpywoh", int_hexagon_M2_mmachs_s1>;
2698 def HEXAGON_M2_mmachs_rs0:
2699 di_MInst_dididi_acc_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs0>;
2700 def HEXAGON_M2_mmachs_s0:
2701 di_MInst_dididi_acc_sat <"vmpywoh", int_hexagon_M2_mmachs_s0>;
2703 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2704 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2705 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2706 def HEXAGON_M2_mmpyul_rs1:
2707 di_MInst_didi_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2708 def HEXAGON_M2_mmpyul_s1:
2709 di_MInst_didi_s1_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2710 def HEXAGON_M2_mmpyul_rs0:
2711 di_MInst_didi_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2712 def HEXAGON_M2_mmpyul_s0:
2713 di_MInst_didi_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2714 def HEXAGON_M2_mmpyuh_rs1:
2715 di_MInst_didi_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2716 def HEXAGON_M2_mmpyuh_s1:
2717 di_MInst_didi_s1_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2718 def HEXAGON_M2_mmpyuh_rs0:
2719 di_MInst_didi_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2720 def HEXAGON_M2_mmpyuh_s0:
2721 di_MInst_didi_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2722 def HEXAGON_M2_mmaculs_rs1:
2723 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2724 def HEXAGON_M2_mmaculs_s1:
2725 di_MInst_dididi_acc_s1_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2726 def HEXAGON_M2_mmaculs_rs0:
2727 di_MInst_dididi_acc_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2728 def HEXAGON_M2_mmaculs_s0:
2729 di_MInst_dididi_acc_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2730 def HEXAGON_M2_mmacuhs_rs1:
2731 di_MInst_dididi_acc_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2732 def HEXAGON_M2_mmacuhs_s1:
2733 di_MInst_dididi_acc_s1_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2734 def HEXAGON_M2_mmacuhs_rs0:
2735 di_MInst_dididi_acc_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2736 def HEXAGON_M2_mmacuhs_s0:
2737 di_MInst_dididi_acc_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2739 // MTYPE / MPYH / Multiply and use upper result.
2740 def HEXAGON_M2_hmmpyh_rs1:
2741 si_MInst_sisi_h_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyh_rs1>;
2742 def HEXAGON_M2_hmmpyl_rs1:
2743 si_MInst_sisi_l_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyl_rs1>;
2744 def HEXAGON_M2_mpy_up:
2745 si_MInst_sisi <"mpy", int_hexagon_M2_mpy_up>;
2746 def HEXAGON_M2_dpmpyss_rnd_s0:
2747 si_MInst_sisi_rnd <"mpy", int_hexagon_M2_dpmpyss_rnd_s0>;
2748 def HEXAGON_M2_mpyu_up:
2749 si_MInst_sisi <"mpyu", int_hexagon_M2_mpyu_up>;
2751 // MTYPE / MPYH / Multiply and use full result.
2752 def HEXAGON_M2_dpmpyuu_s0:
2753 di_MInst_sisi <"mpyu", int_hexagon_M2_dpmpyuu_s0>;
2754 def HEXAGON_M2_dpmpyuu_acc_s0:
2755 di_MInst_disisi_acc <"mpyu", int_hexagon_M2_dpmpyuu_acc_s0>;
2756 def HEXAGON_M2_dpmpyuu_nac_s0:
2757 di_MInst_disisi_nac <"mpyu", int_hexagon_M2_dpmpyuu_nac_s0>;
2758 def HEXAGON_M2_dpmpyss_s0:
2759 di_MInst_sisi <"mpy", int_hexagon_M2_dpmpyss_s0>;
2760 def HEXAGON_M2_dpmpyss_acc_s0:
2761 di_MInst_disisi_acc <"mpy", int_hexagon_M2_dpmpyss_acc_s0>;
2762 def HEXAGON_M2_dpmpyss_nac_s0:
2763 di_MInst_disisi_nac <"mpy", int_hexagon_M2_dpmpyss_nac_s0>;
2765 /********************************************************************
2767 *********************************************************************/
2769 // MTYPE / VB / Vector reduce add unsigned bytes.
2770 def HEXAGON_A2_vraddub:
2771 di_MInst_didi <"vraddub", int_hexagon_A2_vraddub>;
2772 def HEXAGON_A2_vraddub_acc:
2773 di_MInst_dididi_acc <"vraddub", int_hexagon_A2_vraddub_acc>;
2775 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2776 def HEXAGON_A2_vrsadub:
2777 di_MInst_didi <"vrsadub", int_hexagon_A2_vrsadub>;
2778 def HEXAGON_A2_vrsadub_acc:
2779 di_MInst_dididi_acc <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2781 /********************************************************************
2783 *********************************************************************/
2785 // MTYPE / VH / Vector dual multiply.
2786 def HEXAGON_M2_vdmpys_s1:
2787 di_MInst_didi_s1_sat <"vdmpy", int_hexagon_M2_vdmpys_s1>;
2788 def HEXAGON_M2_vdmpys_s0:
2789 di_MInst_didi_sat <"vdmpy", int_hexagon_M2_vdmpys_s0>;
2790 def HEXAGON_M2_vdmacs_s1:
2791 di_MInst_dididi_acc_s1_sat <"vdmpy", int_hexagon_M2_vdmacs_s1>;
2792 def HEXAGON_M2_vdmacs_s0:
2793 di_MInst_dididi_acc_sat <"vdmpy", int_hexagon_M2_vdmacs_s0>;
2795 // MTYPE / VH / Vector dual multiply with round and pack.
2796 def HEXAGON_M2_vdmpyrs_s0:
2797 si_MInst_didi_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s0>;
2798 def HEXAGON_M2_vdmpyrs_s1:
2799 si_MInst_didi_s1_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s1>;
2801 // MTYPE / VH / Vector multiply even halfwords.
2802 def HEXAGON_M2_vmpy2es_s1:
2803 di_MInst_didi_s1_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s1>;
2804 def HEXAGON_M2_vmpy2es_s0:
2805 di_MInst_didi_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s0>;
2806 def HEXAGON_M2_vmac2es:
2807 di_MInst_dididi_acc <"vmpyeh", int_hexagon_M2_vmac2es>;
2808 def HEXAGON_M2_vmac2es_s1:
2809 di_MInst_dididi_acc_s1_sat <"vmpyeh", int_hexagon_M2_vmac2es_s1>;
2810 def HEXAGON_M2_vmac2es_s0:
2811 di_MInst_dididi_acc_sat <"vmpyeh", int_hexagon_M2_vmac2es_s0>;
2813 // MTYPE / VH / Vector multiply halfwords.
2814 def HEXAGON_M2_vmpy2s_s0:
2815 di_MInst_sisi_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0>;
2816 def HEXAGON_M2_vmpy2s_s1:
2817 di_MInst_sisi_s1_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1>;
2818 def HEXAGON_M2_vmac2:
2819 di_MInst_disisi_acc <"vmpyh", int_hexagon_M2_vmac2>;
2820 def HEXAGON_M2_vmac2s_s0:
2821 di_MInst_disisi_acc_sat <"vmpyh", int_hexagon_M2_vmac2s_s0>;
2822 def HEXAGON_M2_vmac2s_s1:
2823 di_MInst_disisi_acc_s1_sat <"vmpyh", int_hexagon_M2_vmac2s_s1>;
2825 // MTYPE / VH / Vector multiply halfwords with round and pack.
2826 def HEXAGON_M2_vmpy2s_s0pack:
2827 si_MInst_sisi_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0pack>;
2828 def HEXAGON_M2_vmpy2s_s1pack:
2829 si_MInst_sisi_s1_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1pack>;
2831 // MTYPE / VH / Vector reduce multiply halfwords.
2832 // Rxx32+=vrmpyh(Rss32,Rtt32)
2833 def HEXAGON_M2_vrmpy_s0:
2834 di_MInst_didi <"vrmpyh", int_hexagon_M2_vrmpy_s0>;
2835 def HEXAGON_M2_vrmac_s0:
2836 di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>;
2839 /********************************************************************
2841 *********************************************************************/
2843 // STYPE / ALU / Absolute value.
2845 si_SInst_si <"abs", int_hexagon_A2_abs>;
2846 def HEXAGON_A2_absp:
2847 di_SInst_di <"abs", int_hexagon_A2_absp>;
2848 def HEXAGON_A2_abssat:
2849 si_SInst_si_sat <"abs", int_hexagon_A2_abssat>;
2851 // STYPE / ALU / Logical Not.
2852 def HEXAGON_A2_notp:
2853 di_SInst_di <"not", int_hexagon_A2_notp>;
2855 // STYPE / ALU / Sign extend word to doubleword.
2856 def HEXAGON_A2_sxtw:
2857 di_SInst_si <"sxtw", int_hexagon_A2_sxtw>;
2860 /********************************************************************
2862 *********************************************************************/
2864 // STYPE / BIT / Count leading.
2866 si_SInst_si <"cl0", int_hexagon_S2_cl0>;
2867 def HEXAGON_S2_cl0p:
2868 si_SInst_di <"cl0", int_hexagon_S2_cl0p>;
2870 si_SInst_si <"cl1", int_hexagon_S2_cl1>;
2871 def HEXAGON_S2_cl1p:
2872 si_SInst_di <"cl1", int_hexagon_S2_cl1p>;
2874 si_SInst_si <"clb", int_hexagon_S2_clb>;
2875 def HEXAGON_S2_clbp:
2876 si_SInst_di <"clb", int_hexagon_S2_clbp>;
2877 def HEXAGON_S2_clbnorm:
2878 si_SInst_si <"normamt", int_hexagon_S2_clbnorm>;
2880 // STYPE / BIT / Count trailing.
2882 si_SInst_si <"ct0", int_hexagon_S2_ct0>;
2884 si_SInst_si <"ct1", int_hexagon_S2_ct1>;
2886 // STYPE / BIT / Compare bit mask.
2887 def Hexagon_C2_bitsclr:
2888 qi_SInst_sisi <"bitsclr", int_hexagon_C2_bitsclr>;
2889 def Hexagon_C2_bitsclri:
2890 qi_SInst_siu6 <"bitsclr", int_hexagon_C2_bitsclri>;
2891 def Hexagon_C2_bitsset:
2892 qi_SInst_sisi <"bitsset", int_hexagon_C2_bitsset>;
2894 // STYPE / BIT / Extract unsigned.
2895 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2896 def HEXAGON_S2_extractu:
2897 si_SInst_siu5u5 <"extractu",int_hexagon_S2_extractu>;
2898 def HEXAGON_S2_extractu_rp:
2899 si_SInst_sidi <"extractu",int_hexagon_S2_extractu_rp>;
2900 def HEXAGON_S2_extractup:
2901 di_SInst_diu6u6 <"extractu",int_hexagon_S2_extractup>;
2902 def HEXAGON_S2_extractup_rp:
2903 di_SInst_didi <"extractu",int_hexagon_S2_extractup_rp>;
2905 // STYPE / BIT / Insert bitfield.
2906 def Hexagon_S2_insert:
2907 si_SInst_sisiu5u5 <"insert", int_hexagon_S2_insert>;
2908 def Hexagon_S2_insert_rp:
2909 si_SInst_sisidi <"insert", int_hexagon_S2_insert_rp>;
2910 def Hexagon_S2_insertp:
2911 di_SInst_didiu6u6 <"insert", int_hexagon_S2_insertp>;
2912 def Hexagon_S2_insertp_rp:
2913 di_SInst_dididi <"insert", int_hexagon_S2_insertp_rp>;
2915 // STYPE / BIT / Innterleave/deinterleave.
2916 def Hexagon_S2_interleave:
2917 di_SInst_di <"interleave", int_hexagon_S2_interleave>;
2918 def Hexagon_S2_deinterleave:
2919 di_SInst_di <"deinterleave", int_hexagon_S2_deinterleave>;
2921 // STYPE / BIT / Linear feedback-shift Iteration.
2922 def Hexagon_S2_lfsp:
2923 di_SInst_didi <"lfs", int_hexagon_S2_lfsp>;
2925 // STYPE / BIT / Bit reverse.
2926 def Hexagon_S2_brev:
2927 si_SInst_si <"brev", int_hexagon_S2_brev>;
2929 // STYPE / BIT / Set/Clear/Toggle Bit.
2930 def HEXAGON_S2_setbit_i:
2931 si_SInst_siu5 <"setbit", int_hexagon_S2_setbit_i>;
2932 def HEXAGON_S2_togglebit_i:
2933 si_SInst_siu5 <"togglebit", int_hexagon_S2_togglebit_i>;
2934 def HEXAGON_S2_clrbit_i:
2935 si_SInst_siu5 <"clrbit", int_hexagon_S2_clrbit_i>;
2936 def HEXAGON_S2_setbit_r:
2937 si_SInst_sisi <"setbit", int_hexagon_S2_setbit_r>;
2938 def HEXAGON_S2_togglebit_r:
2939 si_SInst_sisi <"togglebit", int_hexagon_S2_togglebit_r>;
2940 def HEXAGON_S2_clrbit_r:
2941 si_SInst_sisi <"clrbit", int_hexagon_S2_clrbit_r>;
2943 // STYPE / BIT / Test Bit.
2944 def HEXAGON_S2_tstbit_i:
2945 qi_SInst_siu5 <"tstbit", int_hexagon_S2_tstbit_i>;
2946 def HEXAGON_S2_tstbit_r:
2947 qi_SInst_sisi <"tstbit", int_hexagon_S2_tstbit_r>;
2950 /********************************************************************
2952 *********************************************************************/
2954 // STYPE / COMPLEX / Vector Complex conjugate.
2955 def HEXAGON_A2_vconj:
2956 di_SInst_di_sat <"vconj", int_hexagon_A2_vconj>;
2958 // STYPE / COMPLEX / Vector Complex rotate.
2959 def HEXAGON_S2_vcrotate:
2960 di_SInst_disi <"vcrotate",int_hexagon_S2_vcrotate>;
2963 /********************************************************************
2965 *********************************************************************/
2967 // STYPE / PERM / Saturate.
2969 si_SInst_di <"sat", int_hexagon_A2_sat>;
2970 def HEXAGON_A2_satb:
2971 si_SInst_si <"satb", int_hexagon_A2_satb>;
2972 def HEXAGON_A2_sath:
2973 si_SInst_si <"sath", int_hexagon_A2_sath>;
2974 def HEXAGON_A2_satub:
2975 si_SInst_si <"satub", int_hexagon_A2_satub>;
2976 def HEXAGON_A2_satuh:
2977 si_SInst_si <"satuh", int_hexagon_A2_satuh>;
2979 // STYPE / PERM / Swizzle bytes.
2980 def HEXAGON_A2_swiz:
2981 si_SInst_si <"swiz", int_hexagon_A2_swiz>;
2983 // STYPE / PERM / Vector align.
2984 // Need custom lowering
2985 def HEXAGON_S2_valignib:
2986 di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
2987 def HEXAGON_S2_valignrb:
2988 di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
2990 // STYPE / PERM / Vector round and pack.
2991 def HEXAGON_S2_vrndpackwh:
2992 si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
2993 def HEXAGON_S2_vrndpackwhs:
2994 si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
2996 // STYPE / PERM / Vector saturate and pack.
2997 def HEXAGON_S2_svsathb:
2998 si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
2999 def HEXAGON_S2_vsathb:
3000 si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
3001 def HEXAGON_S2_svsathub:
3002 si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
3003 def HEXAGON_S2_vsathub:
3004 si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
3005 def HEXAGON_S2_vsatwh:
3006 si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
3007 def HEXAGON_S2_vsatwuh:
3008 si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
3010 // STYPE / PERM / Vector saturate without pack.
3011 def HEXAGON_S2_vsathb_nopack:
3012 di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
3013 def HEXAGON_S2_vsathub_nopack:
3014 di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
3015 def HEXAGON_S2_vsatwh_nopack:
3016 di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
3017 def HEXAGON_S2_vsatwuh_nopack:
3018 di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3020 // STYPE / PERM / Vector shuffle.
3021 def HEXAGON_S2_shuffeb:
3022 di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
3023 def HEXAGON_S2_shuffeh:
3024 di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
3025 def HEXAGON_S2_shuffob:
3026 di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
3027 def HEXAGON_S2_shuffoh:
3028 di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
3030 // STYPE / PERM / Vector splat bytes.
3031 def HEXAGON_S2_vsplatrb:
3032 si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
3034 // STYPE / PERM / Vector splat halfwords.
3035 def HEXAGON_S2_vsplatrh:
3036 di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
3038 // STYPE / PERM / Vector splice.
3039 def Hexagon_S2_vsplicerb:
3040 di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
3041 def Hexagon_S2_vspliceib:
3042 di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
3044 // STYPE / PERM / Sign extend.
3045 def HEXAGON_S2_vsxtbh:
3046 di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
3047 def HEXAGON_S2_vsxthw:
3048 di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
3050 // STYPE / PERM / Truncate.
3051 def HEXAGON_S2_vtrunehb:
3052 si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
3053 def HEXAGON_S2_vtrunohb:
3054 si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
3055 def HEXAGON_S2_vtrunewh:
3056 di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
3057 def HEXAGON_S2_vtrunowh:
3058 di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
3060 // STYPE / PERM / Zero extend.
3061 def HEXAGON_S2_vzxtbh:
3062 di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
3063 def HEXAGON_S2_vzxthw:
3064 di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
3067 /********************************************************************
3069 *********************************************************************/
3071 // STYPE / PRED / Mask generate from predicate.
3072 def HEXAGON_C2_mask:
3073 di_SInst_qi <"mask", int_hexagon_C2_mask>;
3075 // STYPE / PRED / Predicate transfer.
3076 def HEXAGON_C2_tfrpr:
3077 si_SInst_qi <"", int_hexagon_C2_tfrpr>;
3078 def HEXAGON_C2_tfrrp:
3079 qi_SInst_si <"", int_hexagon_C2_tfrrp>;
3081 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3082 def HEXAGON_C2_vitpack:
3083 si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
3086 /********************************************************************
3088 *********************************************************************/
3090 // STYPE / SHIFT / Shift by immediate.
3091 def HEXAGON_S2_asl_i_r:
3092 si_SInst_siu5 <"asl", int_hexagon_S2_asl_i_r>;
3093 def HEXAGON_S2_asr_i_r:
3094 si_SInst_siu5 <"asr", int_hexagon_S2_asr_i_r>;
3095 def HEXAGON_S2_lsr_i_r:
3096 si_SInst_siu5 <"lsr", int_hexagon_S2_lsr_i_r>;
3097 def HEXAGON_S2_asl_i_p:
3098 di_SInst_diu6 <"asl", int_hexagon_S2_asl_i_p>;
3099 def HEXAGON_S2_asr_i_p:
3100 di_SInst_diu6 <"asr", int_hexagon_S2_asr_i_p>;
3101 def HEXAGON_S2_lsr_i_p:
3102 di_SInst_diu6 <"lsr", int_hexagon_S2_lsr_i_p>;
3104 // STYPE / SHIFT / Shift by immediate and accumulate.
3105 def HEXAGON_S2_asl_i_r_acc:
3106 si_SInst_sisiu5_acc <"asl", int_hexagon_S2_asl_i_r_acc>;
3107 def HEXAGON_S2_asr_i_r_acc:
3108 si_SInst_sisiu5_acc <"asr", int_hexagon_S2_asr_i_r_acc>;
3109 def HEXAGON_S2_lsr_i_r_acc:
3110 si_SInst_sisiu5_acc <"lsr", int_hexagon_S2_lsr_i_r_acc>;
3111 def HEXAGON_S2_asl_i_r_nac:
3112 si_SInst_sisiu5_nac <"asl", int_hexagon_S2_asl_i_r_nac>;
3113 def HEXAGON_S2_asr_i_r_nac:
3114 si_SInst_sisiu5_nac <"asr", int_hexagon_S2_asr_i_r_nac>;
3115 def HEXAGON_S2_lsr_i_r_nac:
3116 si_SInst_sisiu5_nac <"lsr", int_hexagon_S2_lsr_i_r_nac>;
3117 def HEXAGON_S2_asl_i_p_acc:
3118 di_SInst_didiu6_acc <"asl", int_hexagon_S2_asl_i_p_acc>;
3119 def HEXAGON_S2_asr_i_p_acc:
3120 di_SInst_didiu6_acc <"asr", int_hexagon_S2_asr_i_p_acc>;
3121 def HEXAGON_S2_lsr_i_p_acc:
3122 di_SInst_didiu6_acc <"lsr", int_hexagon_S2_lsr_i_p_acc>;
3123 def HEXAGON_S2_asl_i_p_nac:
3124 di_SInst_didiu6_nac <"asl", int_hexagon_S2_asl_i_p_nac>;
3125 def HEXAGON_S2_asr_i_p_nac:
3126 di_SInst_didiu6_nac <"asr", int_hexagon_S2_asr_i_p_nac>;
3127 def HEXAGON_S2_lsr_i_p_nac:
3128 di_SInst_didiu6_nac <"lsr", int_hexagon_S2_lsr_i_p_nac>;
3130 // STYPE / SHIFT / Shift by immediate and add.
3131 def HEXAGON_S2_addasl_rrri:
3132 si_SInst_sisiu3 <"addasl", int_hexagon_S2_addasl_rrri>;
3134 // STYPE / SHIFT / Shift by immediate and logical.
3135 def HEXAGON_S2_asl_i_r_and:
3136 si_SInst_sisiu5_and <"asl", int_hexagon_S2_asl_i_r_and>;
3137 def HEXAGON_S2_asr_i_r_and:
3138 si_SInst_sisiu5_and <"asr", int_hexagon_S2_asr_i_r_and>;
3139 def HEXAGON_S2_lsr_i_r_and:
3140 si_SInst_sisiu5_and <"lsr", int_hexagon_S2_lsr_i_r_and>;
3142 def HEXAGON_S2_asl_i_r_xacc:
3143 si_SInst_sisiu5_xor <"asl", int_hexagon_S2_asl_i_r_xacc>;
3144 def HEXAGON_S2_lsr_i_r_xacc:
3145 si_SInst_sisiu5_xor <"lsr", int_hexagon_S2_lsr_i_r_xacc>;
3147 def HEXAGON_S2_asl_i_r_or:
3148 si_SInst_sisiu5_or <"asl", int_hexagon_S2_asl_i_r_or>;
3149 def HEXAGON_S2_asr_i_r_or:
3150 si_SInst_sisiu5_or <"asr", int_hexagon_S2_asr_i_r_or>;
3151 def HEXAGON_S2_lsr_i_r_or:
3152 si_SInst_sisiu5_or <"lsr", int_hexagon_S2_lsr_i_r_or>;
3154 def HEXAGON_S2_asl_i_p_and:
3155 di_SInst_didiu6_and <"asl", int_hexagon_S2_asl_i_p_and>;
3156 def HEXAGON_S2_asr_i_p_and:
3157 di_SInst_didiu6_and <"asr", int_hexagon_S2_asr_i_p_and>;
3158 def HEXAGON_S2_lsr_i_p_and:
3159 di_SInst_didiu6_and <"lsr", int_hexagon_S2_lsr_i_p_and>;
3161 def HEXAGON_S2_asl_i_p_xacc:
3162 di_SInst_didiu6_xor <"asl", int_hexagon_S2_asl_i_p_xacc>;
3163 def HEXAGON_S2_lsr_i_p_xacc:
3164 di_SInst_didiu6_xor <"lsr", int_hexagon_S2_lsr_i_p_xacc>;
3166 def HEXAGON_S2_asl_i_p_or:
3167 di_SInst_didiu6_or <"asl", int_hexagon_S2_asl_i_p_or>;
3168 def HEXAGON_S2_asr_i_p_or:
3169 di_SInst_didiu6_or <"asr", int_hexagon_S2_asr_i_p_or>;
3170 def HEXAGON_S2_lsr_i_p_or:
3171 di_SInst_didiu6_or <"lsr", int_hexagon_S2_lsr_i_p_or>;
3173 // STYPE / SHIFT / Shift right by immediate with rounding.
3174 def HEXAGON_S2_asr_i_r_rnd:
3175 si_SInst_siu5_rnd <"asr", int_hexagon_S2_asr_i_r_rnd>;
3176 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3177 si_SInst_siu5 <"asrrnd", int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3179 // STYPE / SHIFT / Shift left by immediate with saturation.
3180 def HEXAGON_S2_asl_i_r_sat:
3181 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_i_r_sat>;
3183 // STYPE / SHIFT / Shift by register.
3184 def HEXAGON_S2_asl_r_r:
3185 si_SInst_sisi <"asl", int_hexagon_S2_asl_r_r>;
3186 def HEXAGON_S2_asr_r_r:
3187 si_SInst_sisi <"asr", int_hexagon_S2_asr_r_r>;
3188 def HEXAGON_S2_lsl_r_r:
3189 si_SInst_sisi <"lsl", int_hexagon_S2_lsl_r_r>;
3190 def HEXAGON_S2_lsr_r_r:
3191 si_SInst_sisi <"lsr", int_hexagon_S2_lsr_r_r>;
3192 def HEXAGON_S2_asl_r_p:
3193 di_SInst_disi <"asl", int_hexagon_S2_asl_r_p>;
3194 def HEXAGON_S2_asr_r_p:
3195 di_SInst_disi <"asr", int_hexagon_S2_asr_r_p>;
3196 def HEXAGON_S2_lsl_r_p:
3197 di_SInst_disi <"lsl", int_hexagon_S2_lsl_r_p>;
3198 def HEXAGON_S2_lsr_r_p:
3199 di_SInst_disi <"lsr", int_hexagon_S2_lsr_r_p>;
3201 // STYPE / SHIFT / Shift by register and accumulate.
3202 def HEXAGON_S2_asl_r_r_acc:
3203 si_SInst_sisisi_acc <"asl", int_hexagon_S2_asl_r_r_acc>;
3204 def HEXAGON_S2_asr_r_r_acc:
3205 si_SInst_sisisi_acc <"asr", int_hexagon_S2_asr_r_r_acc>;
3206 def HEXAGON_S2_lsl_r_r_acc:
3207 si_SInst_sisisi_acc <"lsl", int_hexagon_S2_lsl_r_r_acc>;
3208 def HEXAGON_S2_lsr_r_r_acc:
3209 si_SInst_sisisi_acc <"lsr", int_hexagon_S2_lsr_r_r_acc>;
3210 def HEXAGON_S2_asl_r_p_acc:
3211 di_SInst_didisi_acc <"asl", int_hexagon_S2_asl_r_p_acc>;
3212 def HEXAGON_S2_asr_r_p_acc:
3213 di_SInst_didisi_acc <"asr", int_hexagon_S2_asr_r_p_acc>;
3214 def HEXAGON_S2_lsl_r_p_acc:
3215 di_SInst_didisi_acc <"lsl", int_hexagon_S2_lsl_r_p_acc>;
3216 def HEXAGON_S2_lsr_r_p_acc:
3217 di_SInst_didisi_acc <"lsr", int_hexagon_S2_lsr_r_p_acc>;
3219 def HEXAGON_S2_asl_r_r_nac:
3220 si_SInst_sisisi_nac <"asl", int_hexagon_S2_asl_r_r_nac>;
3221 def HEXAGON_S2_asr_r_r_nac:
3222 si_SInst_sisisi_nac <"asr", int_hexagon_S2_asr_r_r_nac>;
3223 def HEXAGON_S2_lsl_r_r_nac:
3224 si_SInst_sisisi_nac <"lsl", int_hexagon_S2_lsl_r_r_nac>;
3225 def HEXAGON_S2_lsr_r_r_nac:
3226 si_SInst_sisisi_nac <"lsr", int_hexagon_S2_lsr_r_r_nac>;
3227 def HEXAGON_S2_asl_r_p_nac:
3228 di_SInst_didisi_nac <"asl", int_hexagon_S2_asl_r_p_nac>;
3229 def HEXAGON_S2_asr_r_p_nac:
3230 di_SInst_didisi_nac <"asr", int_hexagon_S2_asr_r_p_nac>;
3231 def HEXAGON_S2_lsl_r_p_nac:
3232 di_SInst_didisi_nac <"lsl", int_hexagon_S2_lsl_r_p_nac>;
3233 def HEXAGON_S2_lsr_r_p_nac:
3234 di_SInst_didisi_nac <"lsr", int_hexagon_S2_lsr_r_p_nac>;
3236 // STYPE / SHIFT / Shift by register and logical.
3237 def HEXAGON_S2_asl_r_r_and:
3238 si_SInst_sisisi_and <"asl", int_hexagon_S2_asl_r_r_and>;
3239 def HEXAGON_S2_asr_r_r_and:
3240 si_SInst_sisisi_and <"asr", int_hexagon_S2_asr_r_r_and>;
3241 def HEXAGON_S2_lsl_r_r_and:
3242 si_SInst_sisisi_and <"lsl", int_hexagon_S2_lsl_r_r_and>;
3243 def HEXAGON_S2_lsr_r_r_and:
3244 si_SInst_sisisi_and <"lsr", int_hexagon_S2_lsr_r_r_and>;
3246 def HEXAGON_S2_asl_r_r_or:
3247 si_SInst_sisisi_or <"asl", int_hexagon_S2_asl_r_r_or>;
3248 def HEXAGON_S2_asr_r_r_or:
3249 si_SInst_sisisi_or <"asr", int_hexagon_S2_asr_r_r_or>;
3250 def HEXAGON_S2_lsl_r_r_or:
3251 si_SInst_sisisi_or <"lsl", int_hexagon_S2_lsl_r_r_or>;
3252 def HEXAGON_S2_lsr_r_r_or:
3253 si_SInst_sisisi_or <"lsr", int_hexagon_S2_lsr_r_r_or>;
3255 def HEXAGON_S2_asl_r_p_and:
3256 di_SInst_didisi_and <"asl", int_hexagon_S2_asl_r_p_and>;
3257 def HEXAGON_S2_asr_r_p_and:
3258 di_SInst_didisi_and <"asr", int_hexagon_S2_asr_r_p_and>;
3259 def HEXAGON_S2_lsl_r_p_and:
3260 di_SInst_didisi_and <"lsl", int_hexagon_S2_lsl_r_p_and>;
3261 def HEXAGON_S2_lsr_r_p_and:
3262 di_SInst_didisi_and <"lsr", int_hexagon_S2_lsr_r_p_and>;
3264 def HEXAGON_S2_asl_r_p_or:
3265 di_SInst_didisi_or <"asl", int_hexagon_S2_asl_r_p_or>;
3266 def HEXAGON_S2_asr_r_p_or:
3267 di_SInst_didisi_or <"asr", int_hexagon_S2_asr_r_p_or>;
3268 def HEXAGON_S2_lsl_r_p_or:
3269 di_SInst_didisi_or <"lsl", int_hexagon_S2_lsl_r_p_or>;
3270 def HEXAGON_S2_lsr_r_p_or:
3271 di_SInst_didisi_or <"lsr", int_hexagon_S2_lsr_r_p_or>;
3273 // STYPE / SHIFT / Shift by register with saturation.
3274 def HEXAGON_S2_asl_r_r_sat:
3275 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_r_r_sat>;
3276 def HEXAGON_S2_asr_r_r_sat:
3277 si_SInst_sisi_sat <"asr", int_hexagon_S2_asr_r_r_sat>;
3279 // STYPE / SHIFT / Table Index.
3280 def Hexagon_S2_tableidxb_goodsyntax:
3281 si_MInst_sisiu4u5 <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3282 def Hexagon_S2_tableidxd_goodsyntax:
3283 si_MInst_sisiu4u5 <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3284 def Hexagon_S2_tableidxh_goodsyntax:
3285 si_MInst_sisiu4u5 <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3286 def Hexagon_S2_tableidxw_goodsyntax:
3287 si_MInst_sisiu4u5 <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3290 /********************************************************************
3292 *********************************************************************/
3294 // STYPE / VH / Vector absolute value halfwords.
3295 // Rdd64=vabsh(Rss64)
3296 def HEXAGON_A2_vabsh:
3297 di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
3298 def HEXAGON_A2_vabshsat:
3299 di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
3301 // STYPE / VH / Vector shift halfwords by immediate.
3302 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3303 def HEXAGON_S2_asl_i_vh:
3304 di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
3305 def HEXAGON_S2_asr_i_vh:
3306 di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
3307 def HEXAGON_S2_lsr_i_vh:
3308 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
3310 // STYPE / VH / Vector shift halfwords by register.
3311 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3312 def HEXAGON_S2_asl_r_vh:
3313 di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
3314 def HEXAGON_S2_asr_r_vh:
3315 di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
3316 def HEXAGON_S2_lsl_r_vh:
3317 di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
3318 def HEXAGON_S2_lsr_r_vh:
3319 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
3322 /********************************************************************
3324 *********************************************************************/
3326 // STYPE / VW / Vector absolute value words.
3327 def HEXAGON_A2_vabsw:
3328 di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
3329 def HEXAGON_A2_vabswsat:
3330 di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
3332 // STYPE / VW / Vector shift words by immediate.
3333 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3334 def HEXAGON_S2_asl_i_vw:
3335 di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
3336 def HEXAGON_S2_asr_i_vw:
3337 di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
3338 def HEXAGON_S2_lsr_i_vw:
3339 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
3341 // STYPE / VW / Vector shift words by register.
3342 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3343 def HEXAGON_S2_asl_r_vw:
3344 di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
3345 def HEXAGON_S2_asr_r_vw:
3346 di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
3347 def HEXAGON_S2_lsl_r_vw:
3348 di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
3349 def HEXAGON_S2_lsr_r_vw:
3350 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
3352 // STYPE / VW / Vector shift words with truncate and pack.
3353 def HEXAGON_S2_asr_r_svw_trun:
3354 si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
3355 def HEXAGON_S2_asr_i_svw_trun:
3356 si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
3358 // LD / Circular loads.
3359 def HEXAGON_circ_ldd:
3360 di_LDInstPI_diu4 <"circ_ldd", int_hexagon_circ_ldd>;
3362 include "HexagonIntrinsicsV3.td"
3363 include "HexagonIntrinsicsV4.td"
3364 include "HexagonIntrinsicsV5.td"