1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is populated based on the following specs:
10 // Hexagon V2 Architecture
11 // Application-Level Specification
14 //===----------------------------------------------------------------------===//
16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
17 : Pat <(IntID imm:$Is),
20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
21 : Pat <(IntID I32:$Rs),
24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
25 : Pat <(IntID I64:$Rs),
28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
29 : Pat<(IntID Imm1:$Is, Imm2:$It),
30 (MI Imm1:$Is, Imm2:$It)>;
32 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
33 : Pat<(IntID I32:$Rs, ImmPred:$It),
34 (MI I32:$Rs, ImmPred:$It)>;
36 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
37 : Pat<(IntID ImmPred:$Is, I32:$Rt),
38 (MI ImmPred:$Is, I32:$Rt)>;
40 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
41 : Pat<(IntID I64:$Rs, imm:$It),
42 (MI DoubleRegs:$Rs, imm:$It)>;
44 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
45 : Pat<(IntID I32:$Rs, I64:$Rt),
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
48 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
49 : Pat <(IntID I32:$Rs, I32:$Rt),
50 (MI I32:$Rs, I32:$Rt)>;
52 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
53 : Pat <(IntID I64:$Rs, I64:$Rt),
54 (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
56 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
57 : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
58 (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
60 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
61 : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
62 (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
64 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
65 : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
66 (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
68 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
69 : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
70 (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
72 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
73 : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
74 (MI I32:$Rs, imm:$It, imm:$Iu)>;
76 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
77 : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
78 (MI imm:$It, I32:$Rs, imm:$Iu)>;
80 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
81 : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
82 (MI imm:$Is, I32:$Rs, I32:$Rt)>;
84 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
85 : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
86 (MI I32:$Rs, imm:$Is, I32:$Rt)>;
88 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
89 : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
90 (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
92 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
93 : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
94 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
96 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
97 : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
98 (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
100 class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
101 : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
102 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
104 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
105 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
106 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
108 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
109 : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
110 (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
112 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
113 : Pat <(IntID I64:$Rs, I32:$Rt),
114 (MI DoubleRegs:$Rs, I32:$Rt)>;
116 class T_D_pat <InstHexagon MI, Intrinsic IntID>
117 : Pat<(IntID (F64:$Rs)),
120 class T_DI_pat <InstHexagon MI, Intrinsic IntID,
121 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
122 : Pat<(IntID F64:$Rs, ImmPred:$It),
123 (MI F64:$Rs, ImmPred:$It)>;
125 class T_F_pat <InstHexagon MI, Intrinsic IntID>
126 : Pat<(IntID F32:$Rs),
129 class T_FI_pat <InstHexagon MI, Intrinsic IntID,
130 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
131 : Pat<(IntID F32:$Rs, ImmPred:$It),
132 (MI F32:$Rs, ImmPred:$It)>;
134 class T_FF_pat <InstHexagon MI, Intrinsic IntID>
135 : Pat<(IntID F32:$Rs, F32:$Rt),
136 (MI F32:$Rs, F32:$Rt)>;
138 class T_DD_pat <InstHexagon MI, Intrinsic IntID>
139 : Pat<(IntID F64:$Rs, F64:$Rt),
140 (MI F64:$Rs, F64:$Rt)>;
142 class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
143 : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
144 (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
146 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
147 : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)),
148 (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>;
150 //===----------------------------------------------------------------------===//
151 // MPYS / Multipy signed/unsigned halfwords
152 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
153 //===----------------------------------------------------------------------===//
155 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
156 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
157 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
158 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
159 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
160 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
161 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
162 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
164 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
165 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
166 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
167 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
168 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
169 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
170 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
171 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
173 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
174 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
175 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
176 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
177 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
178 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
179 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
180 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
182 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
183 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
184 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
185 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
186 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
187 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
188 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
189 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
191 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
192 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
193 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
194 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
195 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
196 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
197 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
198 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
201 //===----------------------------------------------------------------------===//
202 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
203 // result from the accumulator.
204 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
205 //===----------------------------------------------------------------------===//
207 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
208 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
209 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
210 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
211 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
212 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
213 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
214 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
216 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
217 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
218 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
219 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
220 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
221 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
222 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
223 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
225 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
226 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
227 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
228 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
229 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
230 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
231 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
232 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
234 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
235 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
236 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
237 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
238 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
239 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
240 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
241 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
243 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
244 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
245 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
246 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
247 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
248 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
249 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
250 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
252 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
253 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
254 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
255 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
256 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
257 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
258 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
259 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
262 //===----------------------------------------------------------------------===//
263 // Multiply signed/unsigned halfwords with and without saturation and rounding
264 // into a 64-bits destination register.
265 //===----------------------------------------------------------------------===//
267 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
268 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
269 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
270 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
271 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
272 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
273 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
274 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
276 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
277 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
278 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
279 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
280 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
281 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
282 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
283 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
285 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
286 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
287 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
288 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
289 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
290 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
291 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
292 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
294 //===----------------------------------------------------------------------===//
295 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
296 // result from the 64-bit destination register.
297 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
298 //===----------------------------------------------------------------------===//
300 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
301 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
302 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
303 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
305 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
306 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
307 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
308 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
310 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
311 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
312 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
313 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
315 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
316 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
317 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
318 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
320 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
321 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
322 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
323 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
325 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
326 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
327 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
328 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
330 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
331 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
332 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
333 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
335 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
336 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
337 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
338 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
340 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
341 def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>;
342 def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>;
344 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
345 def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>;
346 def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>;
348 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
349 def : T_PP_pat <M2_vdmpys_s1, int_hexagon_M2_vdmpys_s1>;
350 def : T_PP_pat <M2_vdmpys_s0, int_hexagon_M2_vdmpys_s0>;
352 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
353 def : T_PP_pat <M2_vmpy2es_s1, int_hexagon_M2_vmpy2es_s1>;
354 def : T_PP_pat <M2_vmpy2es_s0, int_hexagon_M2_vmpy2es_s0>;
356 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
357 def : T_PP_pat <M2_mmpyh_s0, int_hexagon_M2_mmpyh_s0>;
358 def : T_PP_pat <M2_mmpyh_s1, int_hexagon_M2_mmpyh_s1>;
359 def : T_PP_pat <M2_mmpyh_rs0, int_hexagon_M2_mmpyh_rs0>;
360 def : T_PP_pat <M2_mmpyh_rs1, int_hexagon_M2_mmpyh_rs1>;
362 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
363 def : T_PP_pat <M2_mmpyl_s0, int_hexagon_M2_mmpyl_s0>;
364 def : T_PP_pat <M2_mmpyl_s1, int_hexagon_M2_mmpyl_s1>;
365 def : T_PP_pat <M2_mmpyl_rs0, int_hexagon_M2_mmpyl_rs0>;
366 def : T_PP_pat <M2_mmpyl_rs1, int_hexagon_M2_mmpyl_rs1>;
368 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
369 def : T_PP_pat <M2_mmpyuh_s0, int_hexagon_M2_mmpyuh_s0>;
370 def : T_PP_pat <M2_mmpyuh_s1, int_hexagon_M2_mmpyuh_s1>;
371 def : T_PP_pat <M2_mmpyuh_rs0, int_hexagon_M2_mmpyuh_rs0>;
372 def : T_PP_pat <M2_mmpyuh_rs1, int_hexagon_M2_mmpyuh_rs1>;
374 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
375 def : T_PP_pat <M2_mmpyul_s0, int_hexagon_M2_mmpyul_s0>;
376 def : T_PP_pat <M2_mmpyul_s1, int_hexagon_M2_mmpyul_s1>;
377 def : T_PP_pat <M2_mmpyul_rs0, int_hexagon_M2_mmpyul_rs0>;
378 def : T_PP_pat <M2_mmpyul_rs1, int_hexagon_M2_mmpyul_rs1>;
380 // Vector reduce add unsigned bytes: Rdd32[+]=vrmpybu(Rss32,Rtt32)
381 def : T_PP_pat <A2_vraddub, int_hexagon_A2_vraddub>;
382 def : T_PPP_pat <A2_vraddub_acc, int_hexagon_A2_vraddub_acc>;
384 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
385 def : T_PP_pat <A2_vrsadub, int_hexagon_A2_vrsadub>;
386 def : T_PPP_pat <A2_vrsadub_acc, int_hexagon_A2_vrsadub_acc>;
388 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
389 def : T_PP_pat <M2_vabsdiffh, int_hexagon_M2_vabsdiffh>;
391 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
392 def : T_PP_pat <M2_vabsdiffw, int_hexagon_M2_vabsdiffw>;
394 // Vector reduce complex multiply real or imaginary:
395 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
396 def : T_PP_pat <M2_vrcmpyi_s0, int_hexagon_M2_vrcmpyi_s0>;
397 def : T_PP_pat <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>;
398 def : T_PPP_pat <M2_vrcmaci_s0, int_hexagon_M2_vrcmaci_s0>;
399 def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>;
401 def : T_PP_pat <M2_vrcmpyr_s0, int_hexagon_M2_vrcmpyr_s0>;
402 def : T_PP_pat <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>;
403 def : T_PPP_pat <M2_vrcmacr_s0, int_hexagon_M2_vrcmacr_s0>;
404 def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>;
406 // Vector reduce halfwords
407 // Rdd[+]=vrmpyh(Rss,Rtt)
408 def : T_PP_pat <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>;
409 def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>;
411 //===----------------------------------------------------------------------===//
412 // Vector Multipy with accumulation
413 //===----------------------------------------------------------------------===//
415 // Vector multiply word by signed half with accumulation
416 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
417 def : T_PPP_pat <M2_mmacls_s1, int_hexagon_M2_mmacls_s1>;
418 def : T_PPP_pat <M2_mmacls_s0, int_hexagon_M2_mmacls_s0>;
419 def : T_PPP_pat <M2_mmacls_rs1, int_hexagon_M2_mmacls_rs1>;
420 def : T_PPP_pat <M2_mmacls_rs0, int_hexagon_M2_mmacls_rs0>;
421 def : T_PPP_pat <M2_mmachs_s1, int_hexagon_M2_mmachs_s1>;
422 def : T_PPP_pat <M2_mmachs_s0, int_hexagon_M2_mmachs_s0>;
423 def : T_PPP_pat <M2_mmachs_rs1, int_hexagon_M2_mmachs_rs1>;
424 def : T_PPP_pat <M2_mmachs_rs0, int_hexagon_M2_mmachs_rs0>;
426 // Vector multiply word by unsigned half with accumulation
427 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
428 def : T_PPP_pat <M2_mmaculs_s1, int_hexagon_M2_mmaculs_s1>;
429 def : T_PPP_pat <M2_mmaculs_s0, int_hexagon_M2_mmaculs_s0>;
430 def : T_PPP_pat <M2_mmaculs_rs1, int_hexagon_M2_mmaculs_rs1>;
431 def : T_PPP_pat <M2_mmaculs_rs0, int_hexagon_M2_mmaculs_rs0>;
432 def : T_PPP_pat <M2_mmacuhs_s1, int_hexagon_M2_mmacuhs_s1>;
433 def : T_PPP_pat <M2_mmacuhs_s0, int_hexagon_M2_mmacuhs_s0>;
434 def : T_PPP_pat <M2_mmacuhs_rs1, int_hexagon_M2_mmacuhs_rs1>;
435 def : T_PPP_pat <M2_mmacuhs_rs0, int_hexagon_M2_mmacuhs_rs0>;
437 // Vector multiply even halfwords with accumulation
438 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
439 def : T_PPP_pat <M2_vmac2es, int_hexagon_M2_vmac2es>;
440 def : T_PPP_pat <M2_vmac2es_s1, int_hexagon_M2_vmac2es_s1>;
441 def : T_PPP_pat <M2_vmac2es_s0, int_hexagon_M2_vmac2es_s0>;
443 // Vector dual multiply with accumulation
444 // Rxx+=vdmpy(Rss,Rtt)[:sat]
445 def : T_PPP_pat <M2_vdmacs_s1, int_hexagon_M2_vdmacs_s1>;
446 def : T_PPP_pat <M2_vdmacs_s0, int_hexagon_M2_vdmacs_s0>;
448 // Vector complex multiply real or imaginary with accumulation
449 // Rxx+=vcmpy[ir](Rss,Rtt):sat
450 def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>;
451 def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>;
453 //===----------------------------------------------------------------------===//
454 // Add/Subtract halfword
455 // Rd=add(Rt.L,Rs.[HL])[:sat]
456 // Rd=sub(Rt.L,Rs.[HL])[:sat]
457 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
458 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
459 //===----------------------------------------------------------------------===//
461 //Rd=add(Rt.L,Rs.[LH])
462 def : T_RR_pat <A2_addh_l16_ll, int_hexagon_A2_addh_l16_ll>;
463 def : T_RR_pat <A2_addh_l16_hl, int_hexagon_A2_addh_l16_hl>;
465 //Rd=add(Rt.L,Rs.[LH]):sat
466 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
467 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
469 //Rd=sub(Rt.L,Rs.[LH])
470 def : T_RR_pat <A2_subh_l16_ll, int_hexagon_A2_subh_l16_ll>;
471 def : T_RR_pat <A2_subh_l16_hl, int_hexagon_A2_subh_l16_hl>;
473 //Rd=sub(Rt.L,Rs.[LH]):sat
474 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
475 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
477 //Rd=add(Rt.[LH],Rs.[LH]):<<16
478 def : T_RR_pat <A2_addh_h16_ll, int_hexagon_A2_addh_h16_ll>;
479 def : T_RR_pat <A2_addh_h16_lh, int_hexagon_A2_addh_h16_lh>;
480 def : T_RR_pat <A2_addh_h16_hl, int_hexagon_A2_addh_h16_hl>;
481 def : T_RR_pat <A2_addh_h16_hh, int_hexagon_A2_addh_h16_hh>;
483 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
484 def : T_RR_pat <A2_subh_h16_ll, int_hexagon_A2_subh_h16_ll>;
485 def : T_RR_pat <A2_subh_h16_lh, int_hexagon_A2_subh_h16_lh>;
486 def : T_RR_pat <A2_subh_h16_hl, int_hexagon_A2_subh_h16_hl>;
487 def : T_RR_pat <A2_subh_h16_hh, int_hexagon_A2_subh_h16_hh>;
489 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
490 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
491 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
492 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
493 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
495 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
496 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
497 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
498 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
499 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
501 // ALU64 / ALU / min max
502 def : T_RR_pat<A2_max, int_hexagon_A2_max>;
503 def : T_RR_pat<A2_min, int_hexagon_A2_min>;
504 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
505 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
507 // Shift and accumulate
508 def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>;
509 def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>;
510 def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>;
511 def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>;
512 def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>;
513 def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>;
515 def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>;
516 def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>;
517 def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>;
518 def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>;
519 def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>;
520 def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>;
521 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
522 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
524 def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>;
525 def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>;
526 def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>;
527 def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>;
528 def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>;
529 def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>;
531 def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>;
532 def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>;
533 def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>;
534 def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>;
535 def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>;
536 def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>;
537 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
538 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
540 def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>;
541 def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>;
542 def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>;
543 def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>;
544 def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>;
545 def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>;
546 def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>;
547 def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>;
549 def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>;
550 def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>;
551 def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>;
552 def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>;
553 def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>;
554 def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>;
555 def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>;
556 def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>;
558 def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>;
559 def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>;
560 def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>;
561 def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>;
562 def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>;
563 def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>;
564 def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>;
565 def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>;
567 def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>;
568 def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>;
569 def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>;
570 def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>;
571 def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>;
572 def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>;
573 def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>;
574 def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
576 def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>;
577 def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>;
578 def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>;
579 def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>;
580 def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>;
581 def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>;
583 def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>;
584 def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>;
585 def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>;
586 def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>;
587 def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>;
588 def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>;
589 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
590 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
592 def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>;
593 def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>;
594 def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>;
595 def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>;
596 def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>;
597 def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>;
599 def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>;
600 def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>;
601 def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>;
602 def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>;
603 def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>;
604 def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>;
605 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
606 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
608 def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>;
609 def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>;
610 def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>;
611 def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>;
612 def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>;
613 def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>;
614 def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>;
615 def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>;
617 def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>;
618 def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>;
619 def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>;
620 def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>;
621 def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>;
622 def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>;
623 def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>;
624 def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>;
626 def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>;
627 def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>;
628 def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>;
629 def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>;
630 def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>;
631 def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>;
632 def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>;
633 def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>;
635 def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>;
636 def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>;
637 def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>;
638 def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>;
639 def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>;
640 def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>;
641 def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>;
642 def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
644 /********************************************************************
646 *********************************************************************/
647 def : T_RR_pat<A2_add, int_hexagon_A2_add>;
648 def : T_RI_pat<ADD_ri, int_hexagon_A2_addi>;
649 def : T_RR_pat<A2_sub, int_hexagon_A2_sub>;
650 def : T_IR_pat<SUB_ri, int_hexagon_A2_subri>;
651 def : T_RR_pat<A2_and, int_hexagon_A2_and>;
652 def : T_RI_pat<AND_ri, int_hexagon_A2_andir>;
653 def : T_RR_pat<A2_or, int_hexagon_A2_or>;
654 def : T_RI_pat<OR_ri, int_hexagon_A2_orir>;
655 def : T_RR_pat<A2_xor, int_hexagon_A2_xor>;
656 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
658 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
659 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
660 (SUB_ri -1, IntRegs:$Rs)>;
662 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
663 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
664 (SUB_ri 0, IntRegs:$Rs)>;
666 // Transfer immediate
667 def : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
668 (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
669 def : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
670 (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
672 // Transfer Register/immediate.
673 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
674 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
676 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
677 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
678 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
680 /********************************************************************
682 *********************************************************************/
684 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
685 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
686 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
687 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
689 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
691 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
693 (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
696 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
697 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
698 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
701 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
702 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
703 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
706 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
707 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
708 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
709 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
711 /********************************************************************
713 *********************************************************************/
715 def : T_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>;
716 def : T_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>;
717 def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
719 def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
720 def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
721 def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
723 def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
724 (i32 (C2_cmpgti (I32:$src1),
725 (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
727 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
728 (i32 (C2_cmpgtui (I32:$src1),
729 (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
731 // The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
732 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
733 (i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>;
735 def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1),
737 (i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>;
739 def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1),
741 (i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>;
743 /********************************************************************
745 *********************************************************************/
746 // Vector add, subtract, average halfwords
747 def: T_RR_pat<A2_svaddh, int_hexagon_A2_svaddh>;
748 def: T_RR_pat<A2_svaddhs, int_hexagon_A2_svaddhs>;
749 def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>;
751 def: T_RR_pat<A2_svsubh, int_hexagon_A2_svsubh>;
752 def: T_RR_pat<A2_svsubhs, int_hexagon_A2_svsubhs>;
753 def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>;
755 def: T_RR_pat<A2_svavgh, int_hexagon_A2_svavgh>;
756 def: T_RR_pat<A2_svavghs, int_hexagon_A2_svavghs>;
757 def: T_RR_pat<A2_svnavgh, int_hexagon_A2_svnavgh>;
759 /********************************************************************
761 *********************************************************************/
762 def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>;
763 def: T_RR_pat<A2_subsat, int_hexagon_A2_subsat>;
764 def: T_PP_pat<A2_addp, int_hexagon_A2_addp>;
765 def: T_PP_pat<A2_subp, int_hexagon_A2_subp>;
767 def: T_PP_pat<A2_andp, int_hexagon_A2_andp>;
768 def: T_PP_pat<A2_orp, int_hexagon_A2_orp>;
769 def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>;
771 def: T_PP_pat<C2_cmpeqp, int_hexagon_C2_cmpeqp>;
772 def: T_PP_pat<C2_cmpgtp, int_hexagon_C2_cmpgtp>;
773 def: T_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>;
775 def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
776 def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
778 /********************************************************************
780 *********************************************************************/
781 // ALU64 - Vector add
782 def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddub>;
783 def : T_PP_pat <A2_vaddubs, int_hexagon_A2_vaddubs>;
784 def : T_PP_pat <A2_vaddh, int_hexagon_A2_vaddh>;
785 def : T_PP_pat <A2_vaddhs, int_hexagon_A2_vaddhs>;
786 def : T_PP_pat <A2_vadduhs, int_hexagon_A2_vadduhs>;
787 def : T_PP_pat <A2_vaddw, int_hexagon_A2_vaddw>;
788 def : T_PP_pat <A2_vaddws, int_hexagon_A2_vaddws>;
790 // ALU64 - Vector average
791 def : T_PP_pat <A2_vavgub, int_hexagon_A2_vavgub>;
792 def : T_PP_pat <A2_vavgubr, int_hexagon_A2_vavgubr>;
793 def : T_PP_pat <A2_vavgh, int_hexagon_A2_vavgh>;
794 def : T_PP_pat <A2_vavghr, int_hexagon_A2_vavghr>;
795 def : T_PP_pat <A2_vavghcr, int_hexagon_A2_vavghcr>;
796 def : T_PP_pat <A2_vavguh, int_hexagon_A2_vavguh>;
797 def : T_PP_pat <A2_vavguhr, int_hexagon_A2_vavguhr>;
799 def : T_PP_pat <A2_vavgw, int_hexagon_A2_vavgw>;
800 def : T_PP_pat <A2_vavgwr, int_hexagon_A2_vavgwr>;
801 def : T_PP_pat <A2_vavgwcr, int_hexagon_A2_vavgwcr>;
802 def : T_PP_pat <A2_vavguw, int_hexagon_A2_vavguw>;
803 def : T_PP_pat <A2_vavguwr, int_hexagon_A2_vavguwr>;
805 // ALU64 - Vector negative average
806 def : T_PP_pat <A2_vnavgh, int_hexagon_A2_vnavgh>;
807 def : T_PP_pat <A2_vnavghr, int_hexagon_A2_vnavghr>;
808 def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>;
809 def : T_PP_pat <A2_vnavgw, int_hexagon_A2_vnavgw>;
810 def : T_PP_pat <A2_vnavgwr, int_hexagon_A2_vnavgwr>;
811 def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>;
813 // ALU64 - Vector max
814 def : T_PP_pat <A2_vmaxh, int_hexagon_A2_vmaxh>;
815 def : T_PP_pat <A2_vmaxw, int_hexagon_A2_vmaxw>;
816 def : T_PP_pat <A2_vmaxub, int_hexagon_A2_vmaxub>;
817 def : T_PP_pat <A2_vmaxuh, int_hexagon_A2_vmaxuh>;
818 def : T_PP_pat <A2_vmaxuw, int_hexagon_A2_vmaxuw>;
820 // ALU64 - Vector min
821 def : T_PP_pat <A2_vminh, int_hexagon_A2_vminh>;
822 def : T_PP_pat <A2_vminw, int_hexagon_A2_vminw>;
823 def : T_PP_pat <A2_vminub, int_hexagon_A2_vminub>;
824 def : T_PP_pat <A2_vminuh, int_hexagon_A2_vminuh>;
825 def : T_PP_pat <A2_vminuw, int_hexagon_A2_vminuw>;
827 // ALU64 - Vector sub
828 def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubub>;
829 def : T_PP_pat <A2_vsububs, int_hexagon_A2_vsububs>;
830 def : T_PP_pat <A2_vsubh, int_hexagon_A2_vsubh>;
831 def : T_PP_pat <A2_vsubhs, int_hexagon_A2_vsubhs>;
832 def : T_PP_pat <A2_vsubuhs, int_hexagon_A2_vsubuhs>;
833 def : T_PP_pat <A2_vsubw, int_hexagon_A2_vsubw>;
834 def : T_PP_pat <A2_vsubws, int_hexagon_A2_vsubws>;
836 // ALU64 - Vector compare bytes
837 def : T_PP_pat <A2_vcmpbeq, int_hexagon_A2_vcmpbeq>;
838 def : T_PP_pat <A4_vcmpbgt, int_hexagon_A4_vcmpbgt>;
839 def : T_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>;
841 // ALU64 - Vector compare halfwords
842 def : T_PP_pat <A2_vcmpheq, int_hexagon_A2_vcmpheq>;
843 def : T_PP_pat <A2_vcmphgt, int_hexagon_A2_vcmphgt>;
844 def : T_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>;
846 // ALU64 - Vector compare words
847 def : T_PP_pat <A2_vcmpweq, int_hexagon_A2_vcmpweq>;
848 def : T_PP_pat <A2_vcmpwgt, int_hexagon_A2_vcmpwgt>;
849 def : T_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>;
851 // ALU64 / VB / Vector mux.
852 def : Pat<(int_hexagon_C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
853 (C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt)>;
855 // MPY - Multiply and use full result
856 // Rdd = mpy[u](Rs, Rt)
857 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
858 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
860 // Complex multiply real or imaginary
861 def : T_RR_pat <M2_cmpyi_s0, int_hexagon_M2_cmpyi_s0>;
862 def : T_RR_pat <M2_cmpyr_s0, int_hexagon_M2_cmpyr_s0>;
865 def : T_RR_pat <M2_cmpys_s0, int_hexagon_M2_cmpys_s0>;
866 def : T_RR_pat <M2_cmpysc_s0, int_hexagon_M2_cmpysc_s0>;
867 def : T_RR_pat <M2_cmpys_s1, int_hexagon_M2_cmpys_s1>;
868 def : T_RR_pat <M2_cmpysc_s1, int_hexagon_M2_cmpysc_s1>;
870 // Vector multiply halfwords
871 // Rdd=vmpyh(Rs,Rt)[:<<1]:sat
872 def : T_RR_pat <M2_vmpy2s_s0, int_hexagon_M2_vmpy2s_s0>;
873 def : T_RR_pat <M2_vmpy2s_s1, int_hexagon_M2_vmpy2s_s1>;
875 // Rxx[+-]= mpy[u](Rs,Rt)
876 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
877 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
878 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
879 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
881 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
882 def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>;
883 def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>;
884 def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>;
885 def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>;
887 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
888 def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>;
889 def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>;
890 def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>;
891 def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>;
893 // Rxx+=cmpy[ir](Rs,Rt)
894 def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>;
895 def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>;
897 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
898 def : T_PRR_pat <M2_vmac2, int_hexagon_M2_vmac2>;
899 def : T_PRR_pat <M2_vmac2s_s0, int_hexagon_M2_vmac2s_s0>;
900 def : T_PRR_pat <M2_vmac2s_s1, int_hexagon_M2_vmac2s_s1>;
902 /********************************************************************
904 *********************************************************************/
905 class qi_CRInst_qi_pat<InstHexagon Inst, Intrinsic IntID> :
906 Pat<(i32 (IntID IntRegs:$Rs)),
907 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>;
909 class qi_CRInst_qiqi_pat<InstHexagon Inst, Intrinsic IntID> :
910 Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)),
911 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>;
913 def: qi_CRInst_qi_pat<C2_not, int_hexagon_C2_not>;
914 def: qi_CRInst_qi_pat<C2_all8, int_hexagon_C2_all8>;
915 def: qi_CRInst_qi_pat<C2_any8, int_hexagon_C2_any8>;
917 def: qi_CRInst_qiqi_pat<C2_and, int_hexagon_C2_and>;
918 def: qi_CRInst_qiqi_pat<C2_andn, int_hexagon_C2_andn>;
919 def: qi_CRInst_qiqi_pat<C2_or, int_hexagon_C2_or>;
920 def: qi_CRInst_qiqi_pat<C2_orn, int_hexagon_C2_orn>;
921 def: qi_CRInst_qiqi_pat<C2_xor, int_hexagon_C2_xor>;
923 // Multiply 32x32 and use lower result
924 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
925 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
926 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
928 // Subtract and accumulate
929 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
931 // Add and accumulate
932 def : T_RRR_pat <M2_acci, int_hexagon_M2_acci>;
933 def : T_RRR_pat <M2_nacci, int_hexagon_M2_nacci>;
934 def : T_RRI_pat <M2_accii, int_hexagon_M2_accii>;
935 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
937 // XOR and XOR with destination
938 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
940 class MType_R32_pat <Intrinsic IntID, InstHexagon OutputInst> :
941 Pat <(IntID IntRegs:$src1, IntRegs:$src2),
942 (OutputInst IntRegs:$src1, IntRegs:$src2)>;
944 // Vector dual multiply with round and pack
946 def : Pat <(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2),
947 (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>;
949 def : Pat <(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2),
950 (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>;
952 // Vector multiply halfwords with round and pack
954 def : MType_R32_pat <int_hexagon_M2_vmpy2s_s0pack, M2_vmpy2s_s0pack>;
955 def : MType_R32_pat <int_hexagon_M2_vmpy2s_s1pack, M2_vmpy2s_s1pack>;
957 // Multiply and use lower result
958 def : MType_R32_pat <int_hexagon_M2_mpyi, M2_mpyi>;
959 def : T_RI_pat<M2_mpysmi, int_hexagon_M2_mpysmi>;
961 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
962 def : MType_R32_pat <int_hexagon_M2_mpyui, M2_mpyi>;
964 // Multiply and use upper result
965 def : MType_R32_pat <int_hexagon_M2_mpy_up, M2_mpy_up>;
966 def : MType_R32_pat <int_hexagon_M2_mpyu_up, M2_mpyu_up>;
967 def : MType_R32_pat <int_hexagon_M2_hmmpyh_rs1, M2_hmmpyh_rs1>;
968 def : MType_R32_pat <int_hexagon_M2_hmmpyl_rs1, M2_hmmpyl_rs1>;
969 def : MType_R32_pat <int_hexagon_M2_dpmpyss_rnd_s0, M2_dpmpyss_rnd_s0>;
971 // Complex multiply with round and pack
972 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
973 def : MType_R32_pat <int_hexagon_M2_cmpyrs_s0, M2_cmpyrs_s0>;
974 def : MType_R32_pat <int_hexagon_M2_cmpyrs_s1, M2_cmpyrs_s1>;
975 def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s0, M2_cmpyrsc_s0>;
976 def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s1, M2_cmpyrsc_s1>;
978 /********************************************************************
980 *********************************************************************/
981 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
982 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
983 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
985 /********************************************************************
987 *********************************************************************/
989 // Count leading/trailing
990 def: T_R_pat<S2_cl0, int_hexagon_S2_cl0>;
991 def: T_P_pat<S2_cl0p, int_hexagon_S2_cl0p>;
992 def: T_R_pat<S2_cl1, int_hexagon_S2_cl1>;
993 def: T_P_pat<S2_cl1p, int_hexagon_S2_cl1p>;
994 def: T_R_pat<S2_clb, int_hexagon_S2_clb>;
995 def: T_P_pat<S2_clbp, int_hexagon_S2_clbp>;
996 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
997 def: T_R_pat<S2_ct0, int_hexagon_S2_ct0>;
998 def: T_R_pat<S2_ct1, int_hexagon_S2_ct1>;
1001 def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>;
1002 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
1003 def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>;
1005 // Linear feedback-shift Iteration.
1006 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
1008 // Shift by immediate and add
1009 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
1012 def : T_PII_pat<S2_extractup, int_hexagon_S2_extractup>;
1013 def : T_RII_pat<S2_extractu, int_hexagon_S2_extractu>;
1014 def : T_RP_pat <S2_extractu_rp, int_hexagon_S2_extractu_rp>;
1015 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
1018 def : Pat <(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2,
1020 (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>;
1022 def : Pat<(i64 (int_hexagon_S2_insertp_rp (I64:$src1),
1023 (I64:$src2), (I64:$src3))),
1024 (i64 (S2_insertp_rp (I64:$src1), (I64:$src2),
1027 def : Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2,
1028 u5ImmPred:$src3, u5ImmPred:$src4),
1029 (S2_insert IntRegs:$src1, IntRegs:$src2,
1030 u5ImmPred:$src3, u5ImmPred:$src4)>;
1032 def : Pat<(i64 (int_hexagon_S2_insertp (I64:$src1),
1033 (I64:$src2), u6ImmPred:$src3, u6ImmPred:$src4)),
1034 (i64 (S2_insertp (I64:$src1), (I64:$src2),
1035 u6ImmPred:$src3, u6ImmPred:$src4))>;
1038 // Innterleave/deinterleave
1039 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
1040 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
1042 // Set/Clear/Toggle Bit
1043 def: T_RI_pat<S2_setbit_i, int_hexagon_S2_setbit_i>;
1044 def: T_RI_pat<S2_clrbit_i, int_hexagon_S2_clrbit_i>;
1045 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
1047 def: T_RR_pat<S2_setbit_r, int_hexagon_S2_setbit_r>;
1048 def: T_RR_pat<S2_clrbit_r, int_hexagon_S2_clrbit_r>;
1049 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
1052 def: T_RI_pat<S2_tstbit_i, int_hexagon_S2_tstbit_i>;
1053 def: T_RR_pat<S2_tstbit_r, int_hexagon_S2_tstbit_r>;
1055 /********************************************************************
1057 *********************************************************************/
1058 // Vector Complex conjugate
1059 def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>;
1061 // Vector Complex rotate
1062 def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>;
1064 /********************************************************************
1066 *********************************************************************/
1068 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
1069 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
1070 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
1072 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
1073 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
1074 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
1075 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
1077 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
1078 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
1079 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
1080 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
1082 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
1083 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
1085 def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>;
1087 def : T_R_pat <S2_brev, int_hexagon_S2_brev>;
1089 def : T_R_pat <A2_abs, int_hexagon_A2_abs>;
1090 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
1091 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
1093 def : T_R_pat <A2_swiz, int_hexagon_A2_swiz>;
1095 def : T_P_pat <A2_sat, int_hexagon_A2_sat>;
1096 def : T_R_pat <A2_sath, int_hexagon_A2_sath>;
1097 def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>;
1098 def : T_R_pat <A2_satub, int_hexagon_A2_satub>;
1099 def : T_R_pat <A2_satb, int_hexagon_A2_satb>;
1101 def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>;
1102 def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>;
1103 def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>;
1104 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
1105 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
1106 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
1108 // Shift left by immediate with saturation.
1109 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
1111 //===----------------------------------------------------------------------===//
1112 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
1113 //===----------------------------------------------------------------------===//
1114 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
1115 SDNodeXForm XformImm>
1116 : Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
1117 (OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3,
1118 (XformImm u5ImmPred:$src4))>;
1121 // Table Index : Extract and insert bits.
1122 // Map to the real hardware instructions after subtracting appropriate
1123 // values from the 4th input operand. Please note that subtraction is not
1124 // needed for int_hexagon_S2_tableidxb_goodsyntax.
1126 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2,
1127 u4ImmPred:$src3, u5ImmPred:$src4),
1128 (S2_tableidxb IntRegs:$src1, IntRegs:$src2,
1129 u4ImmPred:$src3, u5ImmPred:$src4)>;
1131 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
1133 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
1135 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
1142 class qi_ALU32_sisi<string opc, Intrinsic IntID>
1143 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1144 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1145 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1147 class qi_ALU32_sis10<string opc, Intrinsic IntID>
1148 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
1149 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1150 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1152 class qi_ALU32_sis8<string opc, Intrinsic IntID>
1153 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
1154 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1155 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1157 class qi_ALU32_siu8<string opc, Intrinsic IntID>
1158 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1159 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1160 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1162 class qi_ALU32_siu9<string opc, Intrinsic IntID>
1163 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
1164 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1165 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1167 class si_ALU32_qisisi<string opc, Intrinsic IntID>
1168 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1170 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1171 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
1174 class si_ALU32_sisi<string opc, Intrinsic IntID>
1175 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1176 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1177 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1179 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
1180 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1181 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1182 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1184 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
1185 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1186 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1187 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1189 class di_ALU64_di<string opc, Intrinsic IntID>
1190 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1191 !strconcat("$dst = ", !strconcat(opc , "$src")),
1192 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1198 class di_ALU64_didi<string opc, Intrinsic IntID>
1199 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1200 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1201 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1202 DoubleRegs:$src2))]>;
1204 class di_ALU64_qididi<string opc, Intrinsic IntID>
1205 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
1207 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1208 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
1209 DoubleRegs:$src3))]>;
1211 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
1212 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1213 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1214 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1215 DoubleRegs:$src2))]>;
1217 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
1218 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1219 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1220 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1221 DoubleRegs:$src2))]>;
1223 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
1224 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1225 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
1226 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1227 DoubleRegs:$src2))]>;
1229 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
1230 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1231 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1232 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1233 DoubleRegs:$src2))]>;
1235 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
1236 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1237 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
1238 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1239 DoubleRegs:$src2))]>;
1241 class qi_ALU64_didi<string opc, Intrinsic IntID>
1242 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1243 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1244 [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1250 class qi_SInst_qi<string opc, Intrinsic IntID>
1251 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1252 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1253 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1255 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
1256 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1257 !strconcat("$dst = ", !strconcat(opc , "$src")),
1258 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1260 class qi_SInst_qiqi<string opc, Intrinsic IntID>
1261 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1262 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1263 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1265 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
1266 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1267 !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
1268 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1270 class di_SInst_di<string opc, Intrinsic IntID>
1271 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1272 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1273 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1275 class di_SInst_di_sat<string opc, Intrinsic IntID>
1276 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1277 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1278 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1280 class si_SInst_di<string opc, Intrinsic IntID>
1281 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1282 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1283 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1285 class si_SInst_di_sat<string opc, Intrinsic IntID>
1286 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1287 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1288 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1290 class di_SInst_disi<string opc, Intrinsic IntID>
1291 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1292 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1293 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1295 class di_SInst_didi<string opc, Intrinsic IntID>
1296 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1297 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1298 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1300 class di_SInst_si<string opc, Intrinsic IntID>
1301 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1302 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
1303 [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
1305 class si_SInst_diu5<string opc, Intrinsic IntID>
1306 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
1307 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1308 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
1310 class si_SInst_disi<string opc, Intrinsic IntID>
1311 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1312 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1313 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1315 class si_SInst_si<string opc, Intrinsic IntID>
1316 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1317 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1318 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1320 class di_SInst_qi<string opc, Intrinsic IntID>
1321 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
1322 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1323 [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
1325 class si_SInst_qi<string opc, Intrinsic IntID>
1326 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1327 !strconcat("$dst = ", !strconcat(opc , "$src")),
1328 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1330 class si_SInst_qiqi<string opc, Intrinsic IntID>
1331 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1332 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1333 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1335 class qi_SInst_si<string opc, Intrinsic IntID>
1336 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1337 !strconcat("$dst = ", !strconcat(opc , "$src")),
1338 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1340 class di_SInst_didiqi<string opc, Intrinsic IntID>
1341 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1343 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1344 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1347 class di_SInst_didiu3<string opc, Intrinsic IntID>
1348 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1350 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
1351 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1359 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1360 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1362 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1363 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1367 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1368 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1370 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1371 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1375 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1376 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1378 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1379 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1383 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1384 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1386 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1387 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1391 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1392 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1394 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1395 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1399 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1400 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1402 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1403 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1407 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1408 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1410 !strconcat("$dst -= ", !strconcat(opc ,
1411 "($src1, $src2):<<1:sat")),
1412 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1416 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1417 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1419 !strconcat("$dst += ", !strconcat(opc ,
1420 "($src1, $src2*):<<1:sat")),
1421 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1425 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1426 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1428 !strconcat("$dst -= ", !strconcat(opc ,
1429 "($src1, $src2*):<<1:sat")),
1430 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1434 class di_MInst_didi<string opc, Intrinsic IntID>
1435 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1436 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1437 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1438 DoubleRegs:$src2))]>;
1440 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1441 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1442 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1443 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1444 DoubleRegs:$src2))]>;
1446 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1447 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1448 !strconcat("$dst = ", !strconcat(opc ,
1449 "($src1, $src2*):<<1:sat")),
1450 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1452 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1453 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1454 !strconcat("$dst = ", !strconcat(opc ,
1455 "($src1, $src2):<<1:rnd:sat")),
1456 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1457 DoubleRegs:$src2))]>;
1459 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1460 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1461 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1462 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1463 DoubleRegs:$src2))]>;
1465 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1466 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1467 !strconcat("$dst = ", !strconcat(opc ,
1468 "($src1, $src2):rnd:sat")),
1469 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1470 DoubleRegs:$src2))]>;
1472 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1473 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1474 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1475 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1477 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1478 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1479 !strconcat("$dst = ", !strconcat(opc ,
1480 "($src1, $src2):<<1:rnd:sat")),
1481 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1483 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1484 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1485 !strconcat("$dst = ", !strconcat(opc ,
1486 "($src1, $src2):<<1:rnd:sat")),
1487 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1489 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1490 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1491 !strconcat("$dst = ", !strconcat(opc ,
1492 "($src1, $src2*):rnd:sat")),
1493 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1495 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1496 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1497 !strconcat("$dst = ", !strconcat(opc ,
1498 "($src1, $src2*):<<1:rnd:sat")),
1499 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1501 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1502 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1503 !strconcat("$dst = ", !strconcat(opc ,
1504 "($src1, $src2):rnd:sat")),
1505 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1507 class di_MInst_sisi<string opc, Intrinsic IntID>
1508 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1509 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1510 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1512 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1513 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1514 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1515 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1517 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1518 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1519 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1520 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1522 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1523 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1524 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1525 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1527 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1528 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1529 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1530 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1531 DoubleRegs:$src2))]>;
1533 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1534 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1535 !strconcat("$dst = ", !strconcat(opc ,
1536 "($src1, $src2):<<1:rnd:sat")),
1537 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1539 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1540 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1541 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1542 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1544 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1545 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1546 DoubleRegs:$src1, DoubleRegs:$src2),
1547 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1548 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1550 DoubleRegs:$src2))],
1553 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1554 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1556 !strconcat("$dst += ",
1557 !strconcat(opc , "($src1, $src2):rnd:sat")),
1558 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1560 DoubleRegs:$src2))],
1563 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1564 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1567 !strconcat("$dst += ",
1568 !strconcat(opc , "($src1, $src2):<<1")),
1569 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1571 DoubleRegs:$src2))],
1575 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1576 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1579 !strconcat("$dst += ",
1580 !strconcat(opc , "($src1, $src2):<<1:sat")),
1581 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1583 DoubleRegs:$src2))],
1586 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1587 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1589 !strconcat("$dst += ",
1590 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1591 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1593 DoubleRegs:$src2))],
1596 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1597 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1599 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1600 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1602 DoubleRegs:$src2))],
1605 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1606 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1608 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1609 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1611 DoubleRegs:$src2))],
1614 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
1615 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1617 !strconcat("$dst += ",
1618 !strconcat(opc , "($src1, $src2):<<1:sat")),
1619 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1623 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
1624 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1625 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1626 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1628 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
1629 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1631 !strconcat("$dst += ",
1632 !strconcat(opc , "($src1, $src2):<<1:sat")),
1633 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1638 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1639 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1640 !strconcat("$dst = ",
1641 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1642 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1644 class si_MInst_didi<string opc, Intrinsic IntID>
1645 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1646 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1647 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1652 let mayLoad = 1, hasSideEffects = 0 in
1653 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
1654 : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
1655 (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
1656 "$dst2 = memd($src1++#$offset:circ($src3))",
1660 /********************************************************************
1662 *********************************************************************/
1664 // STYPE / PERM / Vector align.
1665 // Need custom lowering
1666 def HEXAGON_S2_valignib:
1667 di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
1668 def HEXAGON_S2_valignrb:
1669 di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
1671 // STYPE / PERM / Vector round and pack.
1672 def HEXAGON_S2_vrndpackwh:
1673 si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
1674 def HEXAGON_S2_vrndpackwhs:
1675 si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
1677 // STYPE / PERM / Vector saturate and pack.
1678 def HEXAGON_S2_svsathb:
1679 si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
1680 def HEXAGON_S2_vsathb:
1681 si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
1682 def HEXAGON_S2_svsathub:
1683 si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
1684 def HEXAGON_S2_vsathub:
1685 si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
1686 def HEXAGON_S2_vsatwh:
1687 si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
1688 def HEXAGON_S2_vsatwuh:
1689 si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
1691 // STYPE / PERM / Vector saturate without pack.
1692 def HEXAGON_S2_vsathb_nopack:
1693 di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
1694 def HEXAGON_S2_vsathub_nopack:
1695 di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
1696 def HEXAGON_S2_vsatwh_nopack:
1697 di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
1698 def HEXAGON_S2_vsatwuh_nopack:
1699 di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
1701 // STYPE / PERM / Vector shuffle.
1702 def HEXAGON_S2_shuffeb:
1703 di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
1704 def HEXAGON_S2_shuffeh:
1705 di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
1706 def HEXAGON_S2_shuffob:
1707 di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
1708 def HEXAGON_S2_shuffoh:
1709 di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
1711 // STYPE / PERM / Vector splat bytes.
1712 def HEXAGON_S2_vsplatrb:
1713 si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
1715 // STYPE / PERM / Vector splat halfwords.
1716 def HEXAGON_S2_vsplatrh:
1717 di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
1719 // STYPE / PERM / Vector splice.
1720 def Hexagon_S2_vsplicerb:
1721 di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
1722 def Hexagon_S2_vspliceib:
1723 di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
1725 // STYPE / PERM / Sign extend.
1726 def HEXAGON_S2_vsxtbh:
1727 di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
1728 def HEXAGON_S2_vsxthw:
1729 di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
1731 // STYPE / PERM / Truncate.
1732 def HEXAGON_S2_vtrunehb:
1733 si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
1734 def HEXAGON_S2_vtrunohb:
1735 si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
1736 def HEXAGON_S2_vtrunewh:
1737 di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
1738 def HEXAGON_S2_vtrunowh:
1739 di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
1741 // STYPE / PERM / Zero extend.
1742 def HEXAGON_S2_vzxtbh:
1743 di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
1744 def HEXAGON_S2_vzxthw:
1745 di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
1748 /********************************************************************
1750 *********************************************************************/
1752 // STYPE / PRED / Mask generate from predicate.
1753 def HEXAGON_C2_mask:
1754 di_SInst_qi <"mask", int_hexagon_C2_mask>;
1756 // STYPE / PRED / Predicate transfer.
1757 def HEXAGON_C2_tfrpr:
1758 si_SInst_qi <"", int_hexagon_C2_tfrpr>;
1759 def HEXAGON_C2_tfrrp:
1760 qi_SInst_si <"", int_hexagon_C2_tfrrp>;
1762 // STYPE / PRED / Viterbi pack even and odd predicate bits.
1763 def HEXAGON_C2_vitpack:
1764 si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
1767 /********************************************************************
1769 *********************************************************************/
1771 // STYPE / VH / Vector absolute value halfwords.
1772 // Rdd64=vabsh(Rss64)
1773 def HEXAGON_A2_vabsh:
1774 di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
1775 def HEXAGON_A2_vabshsat:
1776 di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
1778 // STYPE / VH / Vector shift halfwords by immediate.
1779 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
1780 def HEXAGON_S2_asl_i_vh:
1781 di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
1782 def HEXAGON_S2_asr_i_vh:
1783 di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
1784 def HEXAGON_S2_lsr_i_vh:
1785 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
1787 // STYPE / VH / Vector shift halfwords by register.
1788 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
1789 def HEXAGON_S2_asl_r_vh:
1790 di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
1791 def HEXAGON_S2_asr_r_vh:
1792 di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
1793 def HEXAGON_S2_lsl_r_vh:
1794 di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
1795 def HEXAGON_S2_lsr_r_vh:
1796 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
1799 /********************************************************************
1801 *********************************************************************/
1803 // STYPE / VW / Vector absolute value words.
1804 def HEXAGON_A2_vabsw:
1805 di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
1806 def HEXAGON_A2_vabswsat:
1807 di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
1809 // STYPE / VW / Vector shift words by immediate.
1810 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
1811 def HEXAGON_S2_asl_i_vw:
1812 di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
1813 def HEXAGON_S2_asr_i_vw:
1814 di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
1815 def HEXAGON_S2_lsr_i_vw:
1816 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
1818 // STYPE / VW / Vector shift words by register.
1819 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
1820 def HEXAGON_S2_asl_r_vw:
1821 di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
1822 def HEXAGON_S2_asr_r_vw:
1823 di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
1824 def HEXAGON_S2_lsl_r_vw:
1825 di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
1826 def HEXAGON_S2_lsr_r_vw:
1827 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
1829 // STYPE / VW / Vector shift words with truncate and pack.
1830 def HEXAGON_S2_asr_r_svw_trun:
1831 si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
1832 def HEXAGON_S2_asr_i_svw_trun:
1833 si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
1835 // LD / Circular loads.
1836 def HEXAGON_circ_ldd:
1837 di_LDInstPI_diu4 <"circ_ldd", int_hexagon_circ_ldd>;
1839 include "HexagonIntrinsicsV3.td"
1840 include "HexagonIntrinsicsV4.td"
1841 include "HexagonIntrinsicsV5.td"