lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
  25   : Pat <(IntID I64:$Rs),
  26          (MI DoubleRegs:$Rs)>;
  27
  28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  29   : Pat<(IntID Imm1:$Is, Imm2:$It),
  30         (MI Imm1:$Is, Imm2:$It)>;
  31
  32 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  33   : Pat<(IntID I32:$Rs, ImmPred:$It),
  34         (MI I32:$Rs, ImmPred:$It)>;
  35
  36 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  37   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  38         (MI ImmPred:$Is, I32:$Rt)>;
  39
  40 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
  41   : Pat<(IntID I64:$Rs, imm:$It),
  42         (MI DoubleRegs:$Rs, imm:$It)>;
  43
  44 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
  45   : Pat<(IntID I32:$Rs, I64:$Rt),
  46         (MI I32:$Rs, DoubleRegs:$Rt)>;
  47
  48 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  49   : Pat <(IntID I32:$Rs, I32:$Rt),
  50          (MI I32:$Rs, I32:$Rt)>;
  51
  52 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
  53   : Pat <(IntID I64:$Rs, I64:$Rt),
  54          (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  55
  56 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  57   : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
  58          (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
  59
  60 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  61   : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
  62          (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
  63
  64 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  65   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
  66          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
  67
  68 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
  69   : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
  70          (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
  71
  72 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
  73   : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
  74          (MI I32:$Rs, imm:$It, imm:$Iu)>;
  75
  76 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
  77   : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
  78          (MI imm:$It, I32:$Rs, imm:$Iu)>;
  79
  80 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
  81   : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
  82          (MI imm:$Is, I32:$Rs, I32:$Rt)>;
  83
  84 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
  85   : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
  86          (MI I32:$Rs, imm:$Is, I32:$Rt)>;
  87
  88 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  89   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  90          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  91
  92 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
  93   : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
  94          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
  95
  96 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
  97   : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
  98          (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
  99
 100 class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
 101   : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
 102          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
 103
 104 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
 105   : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
 106          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
 107
 108 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
 109   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
 110          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
 111
 112 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
 113   : Pat <(IntID I64:$Rs, I32:$Rt),
 114          (MI DoubleRegs:$Rs, I32:$Rt)>;
 115
 116 class T_D_pat <InstHexagon MI, Intrinsic IntID>
 117   : Pat<(IntID (F64:$Rs)),
 118         (MI (F64:$Rs))>;
 119
 120 class T_DI_pat <InstHexagon MI, Intrinsic IntID,
 121                 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 122   : Pat<(IntID F64:$Rs, ImmPred:$It),
 123         (MI F64:$Rs, ImmPred:$It)>;
 124
 125 class T_F_pat <InstHexagon MI, Intrinsic IntID>
 126   : Pat<(IntID F32:$Rs),
 127         (MI F32:$Rs)>;
 128
 129 class T_FI_pat <InstHexagon MI, Intrinsic IntID,
 130                  PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 131   : Pat<(IntID F32:$Rs, ImmPred:$It),
 132         (MI F32:$Rs, ImmPred:$It)>;
 133
 134 class T_FF_pat <InstHexagon MI, Intrinsic IntID>
 135   : Pat<(IntID F32:$Rs, F32:$Rt),
 136         (MI F32:$Rs, F32:$Rt)>;
 137
 138 class T_DD_pat <InstHexagon MI, Intrinsic IntID>
 139   : Pat<(IntID F64:$Rs, F64:$Rt),
 140         (MI F64:$Rs, F64:$Rt)>;
 141
 142 class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
 143   : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
 144         (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
 145
 146 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
 147   : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)),
 148          (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>;
 149
 150 //===----------------------------------------------------------------------===//
 151 // MPYS / Multipy signed/unsigned halfwords
 152 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
 153 //===----------------------------------------------------------------------===//
 154
 155 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
 156 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
 157 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
 158 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
 159 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
 160 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
 161 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
 162 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
 163
 164 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
 165 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
 166 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
 167 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
 168 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
 169 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
 170 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
 171 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
 172
 173 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
 174 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
 175 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
 176 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
 177 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
 178 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
 179 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
 180 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
 181
 182 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
 183 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
 184 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
 185 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
 186 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
 187 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
 188 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
 189 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 190
 191 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 192 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 193 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 194 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 195 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 196 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 197 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 198 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 199
 200
 201 //===----------------------------------------------------------------------===//
 202 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 203 // result from the accumulator.
 204 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 205 //===----------------------------------------------------------------------===//
 206
 207 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 208 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 209 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 210 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 211 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 212 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 213 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 214 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 215
 216 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 217 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 218 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 219 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 220 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 221 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 222 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 223 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 224
 225 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 226 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 227 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 228 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 229 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 230 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 231 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 232 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 233
 234 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 235 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 236 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 237 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 238 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 239 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 240 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 241 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 242
 243 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 244 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 245 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 246 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 247 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 248 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 249 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 250 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 251
 252 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 253 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 254 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 255 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 256 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 257 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 258 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 259 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 260
 261
 262 //===----------------------------------------------------------------------===//
 263 // Multiply signed/unsigned halfwords with and without saturation and rounding
 264 // into a 64-bits destination register.
 265 //===----------------------------------------------------------------------===//
 266
 267 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 268 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 269 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 270 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 271 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 272 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 273 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 274 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 275
 276 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 277 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 278 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 279 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 280 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 281 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 282 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 283 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 284
 285 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 286 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 287 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 288 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 289 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 290 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 291 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 292 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 293
 294 //===----------------------------------------------------------------------===//
 295 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 296 // result from the 64-bit destination register.
 297 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 298 //===----------------------------------------------------------------------===//
 299
 300 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 301 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 302 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 303 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 304
 305 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 306 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 307 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 308 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 309
 310 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 311 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 312 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 313 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 314
 315 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 316 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 317 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 318 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 319
 320 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 321 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 322 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 323 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 324
 325 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 326 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 327 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 328 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 329
 330 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 331 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 332 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 333 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 334
 335 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 336 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 337 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 338 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 339
 340 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
 341 def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>;
 342 def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>;
 343
 344 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
 345 def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>;
 346 def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>;
 347
 348 // Vector reduce complex multiply real or imaginary:
 349 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
 350 def : T_PP_pat  <M2_vrcmpyi_s0,  int_hexagon_M2_vrcmpyi_s0>;
 351 def : T_PP_pat  <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>;
 352 def : T_PPP_pat <M2_vrcmaci_s0,  int_hexagon_M2_vrcmaci_s0>;
 353 def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>;
 354
 355 def : T_PP_pat  <M2_vrcmpyr_s0,  int_hexagon_M2_vrcmpyr_s0>;
 356 def : T_PP_pat  <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>;
 357 def : T_PPP_pat <M2_vrcmacr_s0,  int_hexagon_M2_vrcmacr_s0>;
 358 def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>;
 359
 360 // Vector reduce halfwords
 361 // Rdd[+]=vrmpyh(Rss,Rtt)
 362 def : T_PP_pat  <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>;
 363 def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>;
 364
 365 // Vector complex multiply real or imaginary with accumulation
 366 // Rxx+=vcmpy[ir](Rss,Rtt):sat
 367 def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>;
 368 def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>;
 369
 370 //===----------------------------------------------------------------------===//
 371 // Add/Subtract halfword
 372 // Rd=add(Rt.L,Rs.[HL])[:sat]
 373 // Rd=sub(Rt.L,Rs.[HL])[:sat]
 374 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
 375 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
 376 //===----------------------------------------------------------------------===//
 377
 378 //Rd=add(Rt.L,Rs.[LH])
 379 def : T_RR_pat <A2_addh_l16_ll,     int_hexagon_A2_addh_l16_ll>;
 380 def : T_RR_pat <A2_addh_l16_hl,     int_hexagon_A2_addh_l16_hl>;
 381
 382 //Rd=add(Rt.L,Rs.[LH]):sat
 383 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
 384 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
 385
 386 //Rd=sub(Rt.L,Rs.[LH])
 387 def : T_RR_pat <A2_subh_l16_ll,     int_hexagon_A2_subh_l16_ll>;
 388 def : T_RR_pat <A2_subh_l16_hl,     int_hexagon_A2_subh_l16_hl>;
 389
 390 //Rd=sub(Rt.L,Rs.[LH]):sat
 391 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
 392 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
 393
 394 //Rd=add(Rt.[LH],Rs.[LH]):<<16
 395 def : T_RR_pat <A2_addh_h16_ll,     int_hexagon_A2_addh_h16_ll>;
 396 def : T_RR_pat <A2_addh_h16_lh,     int_hexagon_A2_addh_h16_lh>;
 397 def : T_RR_pat <A2_addh_h16_hl,     int_hexagon_A2_addh_h16_hl>;
 398 def : T_RR_pat <A2_addh_h16_hh,     int_hexagon_A2_addh_h16_hh>;
 399
 400 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
 401 def : T_RR_pat <A2_subh_h16_ll,     int_hexagon_A2_subh_h16_ll>;
 402 def : T_RR_pat <A2_subh_h16_lh,     int_hexagon_A2_subh_h16_lh>;
 403 def : T_RR_pat <A2_subh_h16_hl,     int_hexagon_A2_subh_h16_hl>;
 404 def : T_RR_pat <A2_subh_h16_hh,     int_hexagon_A2_subh_h16_hh>;
 405
 406 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
 407 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
 408 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
 409 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
 410 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
 411
 412 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
 413 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
 414 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
 415 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
 416 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
 417
 418 // ALU64 / ALU / min max
 419 def : T_RR_pat<A2_max,  int_hexagon_A2_max>;
 420 def : T_RR_pat<A2_min,  int_hexagon_A2_min>;
 421 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
 422 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
 423
 424 // Shift and accumulate
 425 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 426 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 427 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 428 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 429 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 430 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 431
 432 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 433 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 434 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 435 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 436 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 437 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 438 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 439 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 440
 441 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 442 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 443 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 444 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 445 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 446 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 447
 448 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 449 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 450 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 451 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 452 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 453 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 454 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 455 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 456
 457 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 458 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 459 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 460 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 461 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 462 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 463 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 464 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 465
 466 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 467 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 468 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 469 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 470 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 471 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 472 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 473 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 474
 475 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 476 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 477 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 478 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 479 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 480 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 481 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 482 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 483
 484 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 485 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 486 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 487 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 488 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 489 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 490 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 491 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 492
 493 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 494 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 495 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 496 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 497 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 498 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 499
 500 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 501 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 502 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 503 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 504 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 505 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 506 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 507 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 508
 509 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 510 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 511 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 512 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 513 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 514 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 515
 516 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 517 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 518 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 519 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 520 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 521 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 522 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 523 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 524
 525 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 526 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 527 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 528 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 529 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 530 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 531 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 532 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 533
 534 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 535 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 536 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 537 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 538 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 539 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 540 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 541 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 542
 543 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 544 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 545 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 546 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 547 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 548 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 549 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 550 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 551
 552 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 553 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 554 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 555 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 556 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 557 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 558 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 559 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 560
 561 /********************************************************************
 562 *            ALU32/ALU                                              *
 563 *********************************************************************/
 564 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 565 def : T_RI_pat<ADD_ri,      int_hexagon_A2_addi>;
 566 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 567 def : T_IR_pat<SUB_ri,      int_hexagon_A2_subri>;
 568 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 569 def : T_RI_pat<AND_ri,      int_hexagon_A2_andir>;
 570 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 571 def : T_RI_pat<OR_ri,       int_hexagon_A2_orir>;
 572 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 573 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 574
 575 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 576 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
 577            (SUB_ri -1, IntRegs:$Rs)>;
 578
 579 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 580 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
 581            (SUB_ri 0, IntRegs:$Rs)>;
 582
 583 // Transfer immediate
 584 def  : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
 585             (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
 586 def  : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
 587             (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
 588
 589 //  Transfer Register/immediate.
 590 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 591 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 592
 593 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 594 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
 595           (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
 596
 597 /********************************************************************
 598 *            ALU32/PERM                                             *
 599 *********************************************************************/
 600 // Combine
 601 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 602 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 603 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 604 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 605
 606 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
 607
 608 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
 609                                                      (I32:$Rt))),
 610          (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
 611
 612 // Mux
 613 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
 614 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
 615 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
 616
 617 // Shift halfword
 618 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 619 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 620 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 621
 622 // Sign/zero extend
 623 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 624 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 625 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 626 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 627
 628 /********************************************************************
 629 *            ALU32/PRED                                             *
 630 *********************************************************************/
 631 // Compare
 632 def : T_RR_pat<C2_cmpeq,  int_hexagon_C2_cmpeq>;
 633 def : T_RR_pat<C2_cmpgt,  int_hexagon_C2_cmpgt>;
 634 def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
 635
 636 def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
 637 def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
 638 def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
 639
 640 def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
 641       (i32 (C2_cmpgti (I32:$src1),
 642                       (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
 643
 644 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
 645       (i32 (C2_cmpgtui (I32:$src1),
 646                        (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
 647
 648 // The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
 649 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
 650       (i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>;
 651
 652 def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1),
 653                                       (I32:$src2))),
 654       (i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>;
 655
 656 def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1),
 657                                        (I32:$src2))),
 658       (i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>;
 659
 660 /********************************************************************
 661 *            ALU32/VH                                               *
 662 *********************************************************************/
 663 // Vector add, subtract, average halfwords
 664 def: T_RR_pat<A2_svaddh,   int_hexagon_A2_svaddh>;
 665 def: T_RR_pat<A2_svaddhs,  int_hexagon_A2_svaddhs>;
 666 def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>;
 667
 668 def: T_RR_pat<A2_svsubh,   int_hexagon_A2_svsubh>;
 669 def: T_RR_pat<A2_svsubhs,  int_hexagon_A2_svsubhs>;
 670 def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>;
 671
 672 def: T_RR_pat<A2_svavgh,   int_hexagon_A2_svavgh>;
 673 def: T_RR_pat<A2_svavghs,  int_hexagon_A2_svavghs>;
 674 def: T_RR_pat<A2_svnavgh,  int_hexagon_A2_svnavgh>;
 675
 676 /********************************************************************
 677 *            ALU64/ALU                                              *
 678 *********************************************************************/
 679 def: T_RR_pat<A2_addsat,   int_hexagon_A2_addsat>;
 680 def: T_RR_pat<A2_subsat,   int_hexagon_A2_subsat>;
 681 def: T_PP_pat<A2_addp,     int_hexagon_A2_addp>;
 682 def: T_PP_pat<A2_subp,     int_hexagon_A2_subp>;
 683
 684 def: T_PP_pat<A2_andp,     int_hexagon_A2_andp>;
 685 def: T_PP_pat<A2_orp,      int_hexagon_A2_orp>;
 686 def: T_PP_pat<A2_xorp,     int_hexagon_A2_xorp>;
 687
 688 def: T_PP_pat<C2_cmpeqp,   int_hexagon_C2_cmpeqp>;
 689 def: T_PP_pat<C2_cmpgtp,   int_hexagon_C2_cmpgtp>;
 690 def: T_PP_pat<C2_cmpgtup,  int_hexagon_C2_cmpgtup>;
 691
 692 def: T_PP_pat<S2_parityp,  int_hexagon_S2_parityp>;
 693 def: T_RR_pat<S2_packhl,   int_hexagon_S2_packhl>;
 694
 695 /********************************************************************
 696 *            ALU64/VB                                               *
 697 *********************************************************************/
 698 // ALU64 - Vector add
 699 def : T_PP_pat <A2_vaddub,   int_hexagon_A2_vaddub>;
 700 def : T_PP_pat <A2_vaddubs,  int_hexagon_A2_vaddubs>;
 701 def : T_PP_pat <A2_vaddh,    int_hexagon_A2_vaddh>;
 702 def : T_PP_pat <A2_vaddhs,   int_hexagon_A2_vaddhs>;
 703 def : T_PP_pat <A2_vadduhs,  int_hexagon_A2_vadduhs>;
 704 def : T_PP_pat <A2_vaddw,    int_hexagon_A2_vaddw>;
 705 def : T_PP_pat <A2_vaddws,   int_hexagon_A2_vaddws>;
 706
 707 // ALU64 - Vector average
 708 def : T_PP_pat <A2_vavgub,   int_hexagon_A2_vavgub>;
 709 def : T_PP_pat <A2_vavgubr,  int_hexagon_A2_vavgubr>;
 710 def : T_PP_pat <A2_vavgh,    int_hexagon_A2_vavgh>;
 711 def : T_PP_pat <A2_vavghr,   int_hexagon_A2_vavghr>;
 712 def : T_PP_pat <A2_vavghcr,  int_hexagon_A2_vavghcr>;
 713 def : T_PP_pat <A2_vavguh,   int_hexagon_A2_vavguh>;
 714 def : T_PP_pat <A2_vavguhr,  int_hexagon_A2_vavguhr>;
 715
 716 def : T_PP_pat <A2_vavgw,    int_hexagon_A2_vavgw>;
 717 def : T_PP_pat <A2_vavgwr,   int_hexagon_A2_vavgwr>;
 718 def : T_PP_pat <A2_vavgwcr,  int_hexagon_A2_vavgwcr>;
 719 def : T_PP_pat <A2_vavguw,   int_hexagon_A2_vavguw>;
 720 def : T_PP_pat <A2_vavguwr,  int_hexagon_A2_vavguwr>;
 721
 722 // ALU64 - Vector negative average
 723 def : T_PP_pat <A2_vnavgh,   int_hexagon_A2_vnavgh>;
 724 def : T_PP_pat <A2_vnavghr,  int_hexagon_A2_vnavghr>;
 725 def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>;
 726 def : T_PP_pat <A2_vnavgw,   int_hexagon_A2_vnavgw>;
 727 def : T_PP_pat <A2_vnavgwr,  int_hexagon_A2_vnavgwr>;
 728 def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>;
 729
 730 // ALU64 - Vector max
 731 def : T_PP_pat <A2_vmaxh,    int_hexagon_A2_vmaxh>;
 732 def : T_PP_pat <A2_vmaxw,    int_hexagon_A2_vmaxw>;
 733 def : T_PP_pat <A2_vmaxub,   int_hexagon_A2_vmaxub>;
 734 def : T_PP_pat <A2_vmaxuh,   int_hexagon_A2_vmaxuh>;
 735 def : T_PP_pat <A2_vmaxuw,   int_hexagon_A2_vmaxuw>;
 736
 737 // ALU64 - Vector min
 738 def : T_PP_pat <A2_vminh,    int_hexagon_A2_vminh>;
 739 def : T_PP_pat <A2_vminw,    int_hexagon_A2_vminw>;
 740 def : T_PP_pat <A2_vminub,   int_hexagon_A2_vminub>;
 741 def : T_PP_pat <A2_vminuh,   int_hexagon_A2_vminuh>;
 742 def : T_PP_pat <A2_vminuw,   int_hexagon_A2_vminuw>;
 743
 744 // ALU64 - Vector sub
 745 def : T_PP_pat <A2_vsubub,   int_hexagon_A2_vsubub>;
 746 def : T_PP_pat <A2_vsububs,  int_hexagon_A2_vsububs>;
 747 def : T_PP_pat <A2_vsubh,    int_hexagon_A2_vsubh>;
 748 def : T_PP_pat <A2_vsubhs,   int_hexagon_A2_vsubhs>;
 749 def : T_PP_pat <A2_vsubuhs,  int_hexagon_A2_vsubuhs>;
 750 def : T_PP_pat <A2_vsubw,    int_hexagon_A2_vsubw>;
 751 def : T_PP_pat <A2_vsubws,   int_hexagon_A2_vsubws>;
 752
 753 // ALU64 - Vector compare bytes
 754 def : T_PP_pat <A2_vcmpbeq,  int_hexagon_A2_vcmpbeq>;
 755 def : T_PP_pat <A4_vcmpbgt,  int_hexagon_A4_vcmpbgt>;
 756 def : T_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>;
 757
 758 // ALU64 - Vector compare halfwords
 759 def : T_PP_pat <A2_vcmpheq,  int_hexagon_A2_vcmpheq>;
 760 def : T_PP_pat <A2_vcmphgt,  int_hexagon_A2_vcmphgt>;
 761 def : T_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>;
 762
 763 // ALU64 - Vector compare words
 764 def : T_PP_pat <A2_vcmpweq,  int_hexagon_A2_vcmpweq>;
 765 def : T_PP_pat <A2_vcmpwgt,  int_hexagon_A2_vcmpwgt>;
 766 def : T_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>;
 767
 768 // ALU64 / VB / Vector mux.
 769 def : Pat<(int_hexagon_C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
 770           (C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt)>;
 771
 772 // MPY - Multiply and use full result
 773 // Rdd = mpy[u](Rs, Rt)
 774 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
 775 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
 776
 777 // Complex multiply real or imaginary
 778 def : T_RR_pat <M2_cmpyi_s0,   int_hexagon_M2_cmpyi_s0>;
 779 def : T_RR_pat <M2_cmpyr_s0,   int_hexagon_M2_cmpyr_s0>;
 780
 781 // Complex multiply
 782 def : T_RR_pat <M2_cmpys_s0,   int_hexagon_M2_cmpys_s0>;
 783 def : T_RR_pat <M2_cmpysc_s0,  int_hexagon_M2_cmpysc_s0>;
 784 def : T_RR_pat <M2_cmpys_s1,   int_hexagon_M2_cmpys_s1>;
 785 def : T_RR_pat <M2_cmpysc_s1,  int_hexagon_M2_cmpysc_s1>;
 786
 787 // Rxx[+-]= mpy[u](Rs,Rt)
 788 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
 789 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
 790 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
 791 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
 792
 793 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
 794 def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>;
 795 def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>;
 796 def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>;
 797 def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>;
 798
 799 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
 800 def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>;
 801 def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>;
 802 def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>;
 803 def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>;
 804
 805 // Rxx+=cmpy[ir](Rs,Rt)
 806 def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>;
 807 def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>;
 808
 809 /********************************************************************
 810 *            CR                                                     *
 811 *********************************************************************/
 812 class qi_CRInst_qi_pat<InstHexagon Inst, Intrinsic IntID> :
 813   Pat<(i32 (IntID IntRegs:$Rs)),
 814       (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>;
 815
 816 class qi_CRInst_qiqi_pat<InstHexagon Inst, Intrinsic IntID> :
 817   Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)),
 818       (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>;
 819
 820 def: qi_CRInst_qi_pat<C2_not,     int_hexagon_C2_not>;
 821 def: qi_CRInst_qi_pat<C2_all8,    int_hexagon_C2_all8>;
 822 def: qi_CRInst_qi_pat<C2_any8,    int_hexagon_C2_any8>;
 823
 824 def: qi_CRInst_qiqi_pat<C2_and,   int_hexagon_C2_and>;
 825 def: qi_CRInst_qiqi_pat<C2_andn,  int_hexagon_C2_andn>;
 826 def: qi_CRInst_qiqi_pat<C2_or,    int_hexagon_C2_or>;
 827 def: qi_CRInst_qiqi_pat<C2_orn,   int_hexagon_C2_orn>;
 828 def: qi_CRInst_qiqi_pat<C2_xor,   int_hexagon_C2_xor>;
 829
 830 // Multiply 32x32 and use lower result
 831 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
 832 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
 833 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
 834
 835 // Subtract and accumulate
 836 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
 837
 838 // Add and accumulate
 839 def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
 840 def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
 841 def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
 842 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
 843
 844 // XOR and XOR with destination
 845 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
 846
 847 class MType_R32_pat <Intrinsic IntID, InstHexagon OutputInst> :
 848       Pat <(IntID IntRegs:$src1, IntRegs:$src2),
 849            (OutputInst IntRegs:$src1, IntRegs:$src2)>;
 850
 851 // Multiply and use lower result
 852 def : MType_R32_pat <int_hexagon_M2_mpyi, M2_mpyi>;
 853 def : T_RI_pat<M2_mpysmi, int_hexagon_M2_mpysmi>;
 854
 855 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
 856 def : MType_R32_pat <int_hexagon_M2_mpyui, M2_mpyi>;
 857
 858 // Multiply and use upper result
 859 def : MType_R32_pat <int_hexagon_M2_mpy_up, M2_mpy_up>;
 860 def : MType_R32_pat <int_hexagon_M2_mpyu_up, M2_mpyu_up>;
 861 def : MType_R32_pat <int_hexagon_M2_hmmpyh_rs1, M2_hmmpyh_rs1>;
 862 def : MType_R32_pat <int_hexagon_M2_hmmpyl_rs1, M2_hmmpyl_rs1>;
 863 def : MType_R32_pat <int_hexagon_M2_dpmpyss_rnd_s0, M2_dpmpyss_rnd_s0>;
 864
 865 // Complex multiply with round and pack
 866 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
 867 def : MType_R32_pat <int_hexagon_M2_cmpyrs_s0, M2_cmpyrs_s0>;
 868 def : MType_R32_pat <int_hexagon_M2_cmpyrs_s1, M2_cmpyrs_s1>;
 869 def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s0, M2_cmpyrsc_s0>;
 870 def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s1, M2_cmpyrsc_s1>;
 871
 872 /********************************************************************
 873 *            STYPE/ALU                                              *
 874 *********************************************************************/
 875 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
 876 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
 877 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
 878
 879 /********************************************************************
 880 *            STYPE/BIT                                              *
 881 *********************************************************************/
 882
 883 // Count leading/trailing
 884 def: T_R_pat<S2_cl0,     int_hexagon_S2_cl0>;
 885 def: T_P_pat<S2_cl0p,    int_hexagon_S2_cl0p>;
 886 def: T_R_pat<S2_cl1,     int_hexagon_S2_cl1>;
 887 def: T_P_pat<S2_cl1p,    int_hexagon_S2_cl1p>;
 888 def: T_R_pat<S2_clb,     int_hexagon_S2_clb>;
 889 def: T_P_pat<S2_clbp,    int_hexagon_S2_clbp>;
 890 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
 891 def: T_R_pat<S2_ct0,     int_hexagon_S2_ct0>;
 892 def: T_R_pat<S2_ct1,     int_hexagon_S2_ct1>;
 893
 894 // Compare bit mask
 895 def: T_RR_pat<C2_bitsclr,  int_hexagon_C2_bitsclr>;
 896 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
 897 def: T_RR_pat<C2_bitsset,  int_hexagon_C2_bitsset>;
 898
 899 // Linear feedback-shift Iteration.
 900 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
 901
 902 // Shift by immediate and add
 903 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
 904
 905 // Extract bitfield
 906 def : T_PII_pat<S2_extractup,    int_hexagon_S2_extractup>;
 907 def : T_RII_pat<S2_extractu,     int_hexagon_S2_extractu>;
 908 def : T_RP_pat <S2_extractu_rp,  int_hexagon_S2_extractu_rp>;
 909 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
 910
 911 // Insert bitfield
 912 def : Pat <(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2,
 913                                      DoubleRegs:$src3),
 914            (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>;
 915
 916 def : Pat<(i64 (int_hexagon_S2_insertp_rp (I64:$src1),
 917                  (I64:$src2), (I64:$src3))),
 918           (i64 (S2_insertp_rp (I64:$src1), (I64:$src2),
 919                               (I64:$src3)))>;
 920
 921 def : Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2,
 922                                  u5ImmPred:$src3, u5ImmPred:$src4),
 923           (S2_insert IntRegs:$src1, IntRegs:$src2,
 924                      u5ImmPred:$src3, u5ImmPred:$src4)>;
 925
 926 def : Pat<(i64 (int_hexagon_S2_insertp (I64:$src1),
 927                  (I64:$src2), u6ImmPred:$src3, u6ImmPred:$src4)),
 928           (i64 (S2_insertp (I64:$src1), (I64:$src2),
 929                            u6ImmPred:$src3, u6ImmPred:$src4))>;
 930
 931
 932 // Innterleave/deinterleave
 933 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
 934 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
 935
 936 // Set/Clear/Toggle Bit
 937 def: T_RI_pat<S2_setbit_i,    int_hexagon_S2_setbit_i>;
 938 def: T_RI_pat<S2_clrbit_i,    int_hexagon_S2_clrbit_i>;
 939 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
 940
 941 def: T_RR_pat<S2_setbit_r,    int_hexagon_S2_setbit_r>;
 942 def: T_RR_pat<S2_clrbit_r,    int_hexagon_S2_clrbit_r>;
 943 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
 944
 945 // Test Bit
 946 def: T_RI_pat<S2_tstbit_i,    int_hexagon_S2_tstbit_i>;
 947 def: T_RR_pat<S2_tstbit_r,    int_hexagon_S2_tstbit_r>;
 948
 949 /********************************************************************
 950 *            STYPE/SHIFT                                            *
 951 *********************************************************************/
 952
 953 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
 954 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
 955 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
 956
 957 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
 958 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
 959 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
 960 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
 961
 962 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
 963 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
 964 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
 965 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
 966
 967 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
 968 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
 969
 970 def : T_R_pat <A2_sxtw,     int_hexagon_A2_sxtw>;
 971
 972 def : T_R_pat <S2_brev,        int_hexagon_S2_brev>;
 973
 974 def : T_R_pat <A2_abs,    int_hexagon_A2_abs>;
 975 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
 976 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
 977
 978 def : T_R_pat <A2_swiz,   int_hexagon_A2_swiz>;
 979
 980 def : T_P_pat <A2_sat,    int_hexagon_A2_sat>;
 981 def : T_R_pat <A2_sath,   int_hexagon_A2_sath>;
 982 def : T_R_pat <A2_satuh,  int_hexagon_A2_satuh>;
 983 def : T_R_pat <A2_satub,  int_hexagon_A2_satub>;
 984 def : T_R_pat <A2_satb,   int_hexagon_A2_satb>;
 985
 986 def : T_RI_pat <S2_asr_i_r,     int_hexagon_S2_asr_i_r>;
 987 def : T_RI_pat <S2_lsr_i_r,     int_hexagon_S2_lsr_i_r>;
 988 def : T_RI_pat <S2_asl_i_r,     int_hexagon_S2_asl_i_r>;
 989 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
 990 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
 991                 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
 992
 993 // Shift left by immediate with saturation.
 994 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
 995
 996 //===----------------------------------------------------------------------===//
 997 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
 998 //===----------------------------------------------------------------------===//
 999 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
1000                          SDNodeXForm XformImm>
1001   : Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
1002          (OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3,
1003                      (XformImm u5ImmPred:$src4))>;
1004
1005
1006 // Table Index : Extract and insert bits.
1007 // Map to the real hardware instructions after subtracting appropriate
1008 // values from the 4th input operand. Please note that subtraction is not
1009 // needed for int_hexagon_S2_tableidxb_goodsyntax.
1010
1011 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2,
1012                                               u4ImmPred:$src3, u5ImmPred:$src4),
1013            (S2_tableidxb IntRegs:$src1, IntRegs:$src2,
1014                          u4ImmPred:$src3, u5ImmPred:$src4)>;
1015
1016 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
1017                          DEC_CONST_SIGNED>;
1018 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
1019                          DEC2_CONST_SIGNED>;
1020 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
1021                          DEC3_CONST_SIGNED>;
1022
1023 //
1024 // ALU 32 types.
1025 //
1026
1027 class qi_ALU32_sisi<string opc, Intrinsic IntID>
1028   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1029              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1030              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1031
1032 class qi_ALU32_sis10<string opc, Intrinsic IntID>
1033   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
1034              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1035              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1036
1037 class qi_ALU32_sis8<string opc, Intrinsic IntID>
1038   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
1039              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1040              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1041
1042 class qi_ALU32_siu8<string opc, Intrinsic IntID>
1043   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1044              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1045              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1046
1047 class qi_ALU32_siu9<string opc, Intrinsic IntID>
1048   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
1049              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1050              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1051
1052 class si_ALU32_qisisi<string opc, Intrinsic IntID>
1053   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1054                                       IntRegs:$src3),
1055              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1056              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
1057                                         IntRegs:$src3))]>;
1058
1059 class si_ALU32_sisi<string opc, Intrinsic IntID>
1060   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1061              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1062              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1063
1064 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
1065   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1066              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1067              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1068
1069 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
1070   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1071              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1072              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1073
1074 class di_ALU64_di<string opc, Intrinsic IntID>
1075   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1076              !strconcat("$dst = ", !strconcat(opc , "$src")),
1077              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1078
1079 //
1080 // ALU 64 types.
1081 //
1082
1083 class di_ALU64_didi<string opc, Intrinsic IntID>
1084   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1085              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1086              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1087                                            DoubleRegs:$src2))]>;
1088
1089 class di_ALU64_qididi<string opc, Intrinsic IntID>
1090   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
1091                                           DoubleRegs:$src3),
1092              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1093              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
1094                                            DoubleRegs:$src3))]>;
1095
1096 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
1097   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1098              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1099              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1100                                            DoubleRegs:$src2))]>;
1101
1102 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
1103   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1104              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1105              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1106                                            DoubleRegs:$src2))]>;
1107
1108 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
1109   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1110              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
1111              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1112                                            DoubleRegs:$src2))]>;
1113
1114 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
1115   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1116              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1117              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1118                                            DoubleRegs:$src2))]>;
1119
1120 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
1121   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1122              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
1123              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1124                                            DoubleRegs:$src2))]>;
1125
1126 class qi_ALU64_didi<string opc, Intrinsic IntID>
1127   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1128              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1129              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1130
1131 //
1132 // SInst classes.
1133 //
1134
1135 class qi_SInst_qi<string opc, Intrinsic IntID>
1136   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1137              !strconcat("$dst = ", !strconcat(opc , "($src)")),
1138              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1139
1140 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
1141   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1142              !strconcat("$dst = ", !strconcat(opc , "$src")),
1143              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1144
1145 class qi_SInst_qiqi<string opc, Intrinsic IntID>
1146   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1147              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1148              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1149
1150 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
1151   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1152              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
1153              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1154
1155 class di_SInst_di<string opc, Intrinsic IntID>
1156   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1157              !strconcat("$dst = ", !strconcat(opc , "($src)")),
1158              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1159
1160 class di_SInst_di_sat<string opc, Intrinsic IntID>
1161   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1162              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1163              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1164
1165 class si_SInst_di<string opc, Intrinsic IntID>
1166   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1167           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1168           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1169
1170 class si_SInst_di_sat<string opc, Intrinsic IntID>
1171   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1172           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1173           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1174
1175 class di_SInst_disi<string opc, Intrinsic IntID>
1176   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1177           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1178           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1179
1180 class di_SInst_didi<string opc, Intrinsic IntID>
1181   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1182           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1183           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1184
1185 class di_SInst_si<string opc, Intrinsic IntID>
1186   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1187           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
1188           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
1189
1190 class si_SInst_diu5<string opc, Intrinsic IntID>
1191   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
1192           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1193           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
1194
1195 class si_SInst_disi<string opc, Intrinsic IntID>
1196   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1197           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1198           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1199
1200 class si_SInst_si<string opc, Intrinsic IntID>
1201   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1202           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1203           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1204
1205 class di_SInst_qi<string opc, Intrinsic IntID>
1206   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
1207           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1208           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
1209
1210 class si_SInst_qi<string opc, Intrinsic IntID>
1211   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1212           !strconcat("$dst = ", !strconcat(opc , "$src")),
1213           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1214
1215 class si_SInst_qiqi<string opc, Intrinsic IntID>
1216   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1217           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1218           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1219
1220 class qi_SInst_si<string opc, Intrinsic IntID>
1221   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1222           !strconcat("$dst = ", !strconcat(opc , "$src")),
1223           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1224
1225 class di_SInst_didiqi<string opc, Intrinsic IntID>
1226   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1227                                        IntRegs:$src3),
1228           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1229           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1230                                         IntRegs:$src3))]>;
1231
1232 class di_SInst_didiu3<string opc, Intrinsic IntID>
1233   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1234                                        u3Imm:$src3),
1235           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
1236           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1237                                         imm:$src3))]>;
1238
1239
1240 //
1241 // MInst classes.
1242 //
1243
1244 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1245   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1246                                            IntRegs:$src2),
1247              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1248              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1249                                            IntRegs:$src2))],
1250              "$dst2 = $dst">;
1251
1252 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1253   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1254                                            IntRegs:$src2),
1255              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1256              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1257                                            IntRegs:$src2))],
1258              "$dst2 = $dst">;
1259
1260 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1261   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1262                                            IntRegs:$src2),
1263              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1264              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1265                                            IntRegs:$src2))],
1266              "$dst2 = $dst">;
1267
1268 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1269   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1270                                            IntRegs:$src2),
1271              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1272              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1273                                            IntRegs:$src2))],
1274              "$dst2 = $dst">;
1275
1276 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1277   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1278                                            IntRegs:$src2),
1279              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1280              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1281                                            IntRegs:$src2))],
1282              "$dst2 = $dst">;
1283
1284 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1285   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1286                                            IntRegs:$src2),
1287              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1288              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1289                                            IntRegs:$src2))],
1290              "$dst2 = $dst">;
1291
1292 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1293   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1294                                            IntRegs:$src2),
1295              !strconcat("$dst -= ", !strconcat(opc ,
1296                                                "($src1, $src2):<<1:sat")),
1297              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1298                                            IntRegs:$src2))],
1299              "$dst2 = $dst">;
1300
1301 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1302   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1303                                            IntRegs:$src2),
1304              !strconcat("$dst += ", !strconcat(opc ,
1305                                                "($src1, $src2*):<<1:sat")),
1306              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1307                                            IntRegs:$src2))],
1308              "$dst2 = $dst">;
1309
1310 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1311   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1312                                            IntRegs:$src2),
1313              !strconcat("$dst -= ", !strconcat(opc ,
1314                                                "($src1, $src2*):<<1:sat")),
1315              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1316                                            IntRegs:$src2))],
1317              "$dst2 = $dst">;
1318
1319 class di_MInst_didi<string opc, Intrinsic IntID>
1320   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1321              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1322              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1323                                            DoubleRegs:$src2))]>;
1324
1325 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1326   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1327              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1328              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1329                                            DoubleRegs:$src2))]>;
1330
1331 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1332   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1333              !strconcat("$dst = ", !strconcat(opc ,
1334                                               "($src1, $src2*):<<1:sat")),
1335              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1336
1337 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1338   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1339              !strconcat("$dst = ", !strconcat(opc ,
1340                                               "($src1, $src2):<<1:rnd:sat")),
1341              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1342                                            DoubleRegs:$src2))]>;
1343
1344 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1345   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1346              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1347              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1348                                            DoubleRegs:$src2))]>;
1349
1350 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1351   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1352              !strconcat("$dst = ", !strconcat(opc ,
1353                                               "($src1, $src2):rnd:sat")),
1354              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1355                                            DoubleRegs:$src2))]>;
1356
1357 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1358   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1359           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1360           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1361
1362 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1363   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1364              !strconcat("$dst = ", !strconcat(opc ,
1365                                               "($src1, $src2):<<1:rnd:sat")),
1366              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1367
1368 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1369   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1370              !strconcat("$dst = ", !strconcat(opc ,
1371                                               "($src1, $src2):<<1:rnd:sat")),
1372              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1373
1374 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1375   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1376              !strconcat("$dst = ", !strconcat(opc ,
1377                                               "($src1, $src2*):rnd:sat")),
1378              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1379
1380 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1381   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1382              !strconcat("$dst = ", !strconcat(opc ,
1383                                               "($src1, $src2*):<<1:rnd:sat")),
1384              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1385
1386 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1387   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1388              !strconcat("$dst = ", !strconcat(opc ,
1389                                               "($src1, $src2):rnd:sat")),
1390              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1391
1392 class di_MInst_sisi<string opc, Intrinsic IntID>
1393   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1394              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1395              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1396
1397 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1398   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1399              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1400              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1401
1402 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1403   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1404              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1405              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1406
1407 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1408   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1409              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1410              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1411
1412 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1413   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1414              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1415              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1416                                            DoubleRegs:$src2))]>;
1417
1418 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1419   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1420              !strconcat("$dst = ", !strconcat(opc ,
1421                                               "($src1, $src2):<<1:rnd:sat")),
1422              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1423
1424 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1425   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1426              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1427              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1428
1429 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1430   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1431                                            DoubleRegs:$src1, DoubleRegs:$src2),
1432                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1433                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1434                                              DoubleRegs:$src1,
1435                                              DoubleRegs:$src2))],
1436                "$dst2 = $dst">;
1437
1438 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1439   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1440                                            DoubleRegs:$src2),
1441                !strconcat("$dst += ",
1442                           !strconcat(opc , "($src1, $src2):rnd:sat")),
1443                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1444                                              DoubleRegs:$src1,
1445                                              DoubleRegs:$src2))],
1446                "$dst2 = $dst">;
1447
1448 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1449   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1450                                            DoubleRegs:$src1,
1451                                            DoubleRegs:$src2),
1452                !strconcat("$dst += ",
1453                           !strconcat(opc , "($src1, $src2):<<1")),
1454                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1455                                              DoubleRegs:$src1,
1456                                              DoubleRegs:$src2))],
1457                "$dst2 = $dst">;
1458
1459
1460 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1461   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1462                                            DoubleRegs:$src1,
1463                                            DoubleRegs:$src2),
1464                !strconcat("$dst += ",
1465                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1466                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1467                                              DoubleRegs:$src1,
1468                                              DoubleRegs:$src2))],
1469                "$dst2 = $dst">;
1470
1471 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1472   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1473                                            DoubleRegs:$src2),
1474                !strconcat("$dst += ",
1475                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1476                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1477                                              DoubleRegs:$src1,
1478                                              DoubleRegs:$src2))],
1479                "$dst2 = $dst">;
1480
1481 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1482   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1483                                            DoubleRegs:$src2),
1484                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1485                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1486                                              DoubleRegs:$src1,
1487                                              DoubleRegs:$src2))],
1488                "$dst2 = $dst">;
1489
1490 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1491   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1492                                            DoubleRegs:$src2),
1493                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1494                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1495                                              DoubleRegs:$src1,
1496                                              DoubleRegs:$src2))],
1497                "$dst2 = $dst">;
1498
1499 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
1500   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1501                                            IntRegs:$src2),
1502                !strconcat("$dst += ",
1503                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1504                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1505                                              IntRegs:$src2))],
1506                "$dst2 = $dst">;
1507
1508 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
1509   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1510              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1511              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1512
1513 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
1514   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1515                                            IntRegs:$src2),
1516                !strconcat("$dst += ",
1517                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1518                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1519                                              DoubleRegs:$src1,
1520                                              IntRegs:$src2))],
1521                "$dst2 = $dst">;
1522
1523 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1524   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1525              !strconcat("$dst = ",
1526                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1527              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1528
1529 class si_MInst_didi<string opc, Intrinsic IntID>
1530   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1531              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1532              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1533
1534 //
1535 // LDInst classes.
1536 //
1537 let mayLoad = 1, hasSideEffects = 0 in
1538 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
1539   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
1540            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
1541            "$dst2 = memd($src1++#$offset:circ($src3))",
1542            [],
1543            "$src1 = $dst">;
1544
1545
1546 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
1547 def HEXAGON_A2_vmaxub:
1548   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
1549 def HEXAGON_A2_vminub:
1550   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
1551
1552 // ALU64 / VB / Vector subtract unsigned bytes.
1553 def HEXAGON_A2_vsubub:
1554   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
1555 def HEXAGON_A2_vsububs:
1556   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
1557
1558 /********************************************************************
1559 *            MTYPE/ALU                                              *
1560 *********************************************************************/
1561
1562 // MTYPE / ALU / Vector absolute difference.
1563 def HEXAGON_M2_vabsdiffh:
1564   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
1565 def HEXAGON_M2_vabsdiffw:
1566   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
1567
1568 /********************************************************************
1569 *            MTYPE/MPYH                                             *
1570 *********************************************************************/
1571
1572 // MTYPE / MPYH / Multiply word by half (32x16).
1573 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
1574 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
1575 def HEXAGON_M2_mmpyl_rs1:
1576   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
1577 def HEXAGON_M2_mmpyl_s1:
1578   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
1579 def HEXAGON_M2_mmpyl_rs0:
1580   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
1581 def HEXAGON_M2_mmpyl_s0:
1582   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
1583 def HEXAGON_M2_mmpyh_rs1:
1584   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
1585 def HEXAGON_M2_mmpyh_s1:
1586   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
1587 def HEXAGON_M2_mmpyh_rs0:
1588   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
1589 def HEXAGON_M2_mmpyh_s0:
1590   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
1591 def HEXAGON_M2_mmacls_rs1:
1592   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
1593 def HEXAGON_M2_mmacls_s1:
1594   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
1595 def HEXAGON_M2_mmacls_rs0:
1596   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
1597 def HEXAGON_M2_mmacls_s0:
1598   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
1599 def HEXAGON_M2_mmachs_rs1:
1600   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
1601 def HEXAGON_M2_mmachs_s1:
1602   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
1603 def HEXAGON_M2_mmachs_rs0:
1604   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
1605 def HEXAGON_M2_mmachs_s0:
1606   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
1607
1608 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
1609 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
1610 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
1611 def HEXAGON_M2_mmpyul_rs1:
1612   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
1613 def HEXAGON_M2_mmpyul_s1:
1614   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
1615 def HEXAGON_M2_mmpyul_rs0:
1616   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
1617 def HEXAGON_M2_mmpyul_s0:
1618   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
1619 def HEXAGON_M2_mmpyuh_rs1:
1620   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
1621 def HEXAGON_M2_mmpyuh_s1:
1622   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
1623 def HEXAGON_M2_mmpyuh_rs0:
1624   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
1625 def HEXAGON_M2_mmpyuh_s0:
1626   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
1627 def HEXAGON_M2_mmaculs_rs1:
1628   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
1629 def HEXAGON_M2_mmaculs_s1:
1630   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
1631 def HEXAGON_M2_mmaculs_rs0:
1632   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
1633 def HEXAGON_M2_mmaculs_s0:
1634   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
1635 def HEXAGON_M2_mmacuhs_rs1:
1636   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
1637 def HEXAGON_M2_mmacuhs_s1:
1638   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
1639 def HEXAGON_M2_mmacuhs_rs0:
1640   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
1641 def HEXAGON_M2_mmacuhs_s0:
1642   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
1643
1644 /********************************************************************
1645 *            MTYPE/VB                                               *
1646 *********************************************************************/
1647
1648 // MTYPE / VB / Vector reduce add unsigned bytes.
1649 def HEXAGON_A2_vraddub:
1650   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
1651 def HEXAGON_A2_vraddub_acc:
1652   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
1653
1654 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
1655 def HEXAGON_A2_vrsadub:
1656   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
1657 def HEXAGON_A2_vrsadub_acc:
1658   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
1659
1660 /********************************************************************
1661 *            MTYPE/VH                                               *
1662 *********************************************************************/
1663
1664 // MTYPE / VH / Vector dual multiply.
1665 def HEXAGON_M2_vdmpys_s1:
1666   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
1667 def HEXAGON_M2_vdmpys_s0:
1668   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
1669 def HEXAGON_M2_vdmacs_s1:
1670   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
1671 def HEXAGON_M2_vdmacs_s0:
1672   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
1673
1674 // MTYPE / VH / Vector dual multiply with round and pack.
1675 def HEXAGON_M2_vdmpyrs_s0:
1676   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
1677 def HEXAGON_M2_vdmpyrs_s1:
1678   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
1679
1680 // MTYPE / VH / Vector multiply even halfwords.
1681 def HEXAGON_M2_vmpy2es_s1:
1682   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
1683 def HEXAGON_M2_vmpy2es_s0:
1684   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
1685 def HEXAGON_M2_vmac2es:
1686   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
1687 def HEXAGON_M2_vmac2es_s1:
1688   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
1689 def HEXAGON_M2_vmac2es_s0:
1690   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
1691
1692 // MTYPE / VH / Vector multiply halfwords.
1693 def HEXAGON_M2_vmpy2s_s0:
1694   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
1695 def HEXAGON_M2_vmpy2s_s1:
1696   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
1697 def HEXAGON_M2_vmac2:
1698   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
1699 def HEXAGON_M2_vmac2s_s0:
1700   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
1701 def HEXAGON_M2_vmac2s_s1:
1702   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
1703
1704 // MTYPE / VH / Vector multiply halfwords with round and pack.
1705 def HEXAGON_M2_vmpy2s_s0pack:
1706   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
1707 def HEXAGON_M2_vmpy2s_s1pack:
1708   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
1709
1710 // MTYPE / VH / Vector reduce multiply halfwords.
1711 // Rxx32+=vrmpyh(Rss32,Rtt32)
1712 def HEXAGON_M2_vrmpy_s0:
1713   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
1714 def HEXAGON_M2_vrmac_s0:
1715   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
1716
1717 /********************************************************************
1718 *            STYPE/COMPLEX                                          *
1719 *********************************************************************/
1720
1721 // STYPE / COMPLEX / Vector Complex conjugate.
1722 def HEXAGON_A2_vconj:
1723   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
1724
1725 // STYPE / COMPLEX / Vector Complex rotate.
1726 def HEXAGON_S2_vcrotate:
1727   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
1728
1729
1730 /********************************************************************
1731 *            STYPE/PERM                                             *
1732 *********************************************************************/
1733
1734 // STYPE / PERM / Vector align.
1735 // Need custom lowering
1736 def HEXAGON_S2_valignib:
1737   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
1738 def HEXAGON_S2_valignrb:
1739   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
1740
1741 // STYPE / PERM / Vector round and pack.
1742 def HEXAGON_S2_vrndpackwh:
1743   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
1744 def HEXAGON_S2_vrndpackwhs:
1745   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
1746
1747 // STYPE / PERM / Vector saturate and pack.
1748 def HEXAGON_S2_svsathb:
1749   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
1750 def HEXAGON_S2_vsathb:
1751   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
1752 def HEXAGON_S2_svsathub:
1753   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
1754 def HEXAGON_S2_vsathub:
1755   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
1756 def HEXAGON_S2_vsatwh:
1757   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
1758 def HEXAGON_S2_vsatwuh:
1759   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
1760
1761 // STYPE / PERM / Vector saturate without pack.
1762 def HEXAGON_S2_vsathb_nopack:
1763   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
1764 def HEXAGON_S2_vsathub_nopack:
1765   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
1766 def HEXAGON_S2_vsatwh_nopack:
1767   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
1768 def HEXAGON_S2_vsatwuh_nopack:
1769   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
1770
1771 // STYPE / PERM / Vector shuffle.
1772 def HEXAGON_S2_shuffeb:
1773   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
1774 def HEXAGON_S2_shuffeh:
1775   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
1776 def HEXAGON_S2_shuffob:
1777   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
1778 def HEXAGON_S2_shuffoh:
1779   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
1780
1781 // STYPE / PERM / Vector splat bytes.
1782 def HEXAGON_S2_vsplatrb:
1783   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
1784
1785 // STYPE / PERM / Vector splat halfwords.
1786 def HEXAGON_S2_vsplatrh:
1787   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
1788
1789 // STYPE / PERM / Vector splice.
1790 def Hexagon_S2_vsplicerb:
1791   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
1792 def Hexagon_S2_vspliceib:
1793   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
1794
1795 // STYPE / PERM / Sign extend.
1796 def HEXAGON_S2_vsxtbh:
1797   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
1798 def HEXAGON_S2_vsxthw:
1799   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
1800
1801 // STYPE / PERM / Truncate.
1802 def HEXAGON_S2_vtrunehb:
1803   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
1804 def HEXAGON_S2_vtrunohb:
1805   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
1806 def HEXAGON_S2_vtrunewh:
1807   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
1808 def HEXAGON_S2_vtrunowh:
1809   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
1810
1811 // STYPE / PERM / Zero extend.
1812 def HEXAGON_S2_vzxtbh:
1813   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
1814 def HEXAGON_S2_vzxthw:
1815   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
1816
1817
1818 /********************************************************************
1819 *            STYPE/PRED                                             *
1820 *********************************************************************/
1821
1822 // STYPE / PRED / Mask generate from predicate.
1823 def HEXAGON_C2_mask:
1824   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
1825
1826 // STYPE / PRED / Predicate transfer.
1827 def HEXAGON_C2_tfrpr:
1828   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
1829 def HEXAGON_C2_tfrrp:
1830   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
1831
1832 // STYPE / PRED / Viterbi pack even and odd predicate bits.
1833 def HEXAGON_C2_vitpack:
1834   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
1835
1836
1837 /********************************************************************
1838 *            STYPE/VH                                               *
1839 *********************************************************************/
1840
1841 // STYPE / VH / Vector absolute value halfwords.
1842 // Rdd64=vabsh(Rss64)
1843 def HEXAGON_A2_vabsh:
1844   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
1845 def HEXAGON_A2_vabshsat:
1846   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
1847
1848 // STYPE / VH / Vector shift halfwords by immediate.
1849 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
1850 def HEXAGON_S2_asl_i_vh:
1851   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
1852 def HEXAGON_S2_asr_i_vh:
1853   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
1854 def HEXAGON_S2_lsr_i_vh:
1855   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
1856
1857 // STYPE / VH / Vector shift halfwords by register.
1858 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
1859 def HEXAGON_S2_asl_r_vh:
1860   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
1861 def HEXAGON_S2_asr_r_vh:
1862   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
1863 def HEXAGON_S2_lsl_r_vh:
1864   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
1865 def HEXAGON_S2_lsr_r_vh:
1866   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
1867
1868
1869 /********************************************************************
1870 *            STYPE/VW                                               *
1871 *********************************************************************/
1872
1873 // STYPE / VW / Vector absolute value words.
1874 def HEXAGON_A2_vabsw:
1875   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
1876 def HEXAGON_A2_vabswsat:
1877   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
1878
1879 // STYPE / VW / Vector shift words by immediate.
1880 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
1881 def HEXAGON_S2_asl_i_vw:
1882   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
1883 def HEXAGON_S2_asr_i_vw:
1884   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
1885 def HEXAGON_S2_lsr_i_vw:
1886   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
1887
1888 // STYPE / VW / Vector shift words by register.
1889 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
1890 def HEXAGON_S2_asl_r_vw:
1891   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
1892 def HEXAGON_S2_asr_r_vw:
1893   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
1894 def HEXAGON_S2_lsl_r_vw:
1895   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
1896 def HEXAGON_S2_lsr_r_vw:
1897   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
1898
1899 // STYPE / VW / Vector shift words with truncate and pack.
1900 def HEXAGON_S2_asr_r_svw_trun:
1901   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
1902 def HEXAGON_S2_asr_i_svw_trun:
1903   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
1904
1905 // LD / Circular loads.
1906 def HEXAGON_circ_ldd:
1907   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
1908
1909 include "HexagonIntrinsicsV3.td"
1910 include "HexagonIntrinsicsV4.td"
1911 include "HexagonIntrinsicsV5.td"