1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is populated based on the following specs:
10 // Hexagon V2 Architecture
11 // Application-Level Specification
14 //===----------------------------------------------------------------------===//
16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
17 : Pat <(IntID imm:$Is),
20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
21 : Pat <(IntID I32:$Rs),
24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
25 : Pat <(IntID I64:$Rs),
28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
29 : Pat<(IntID Imm1:$Is, Imm2:$It),
30 (MI Imm1:$Is, Imm2:$It)>;
32 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
33 : Pat<(IntID I32:$Rs, ImmPred:$It),
34 (MI I32:$Rs, ImmPred:$It)>;
36 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
37 : Pat<(IntID ImmPred:$Is, I32:$Rt),
38 (MI ImmPred:$Is, I32:$Rt)>;
40 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
41 : Pat<(IntID I64:$Rs, imm:$It),
42 (MI DoubleRegs:$Rs, imm:$It)>;
44 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
45 : Pat<(IntID I32:$Rs, I64:$Rt),
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
48 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
49 : Pat <(IntID I32:$Rs, I32:$Rt),
50 (MI I32:$Rs, I32:$Rt)>;
52 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
53 : Pat <(IntID I64:$Rs, I64:$Rt),
54 (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
56 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
57 : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
58 (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
60 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
61 : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
62 (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
64 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
65 : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
66 (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
68 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
69 : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
70 (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
72 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
73 : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
74 (MI I32:$Rs, imm:$It, imm:$Iu)>;
76 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
77 : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
78 (MI imm:$It, I32:$Rs, imm:$Iu)>;
80 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
81 : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
82 (MI imm:$Is, I32:$Rs, I32:$Rt)>;
84 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
85 : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
86 (MI I32:$Rs, imm:$Is, I32:$Rt)>;
88 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
89 : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
90 (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
92 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
93 : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
94 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
96 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
97 : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
98 (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
100 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
101 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
102 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
104 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
105 : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
106 (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
108 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
109 : Pat <(IntID I64:$Rs, I32:$Rt),
110 (MI DoubleRegs:$Rs, I32:$Rt)>;
112 //===----------------------------------------------------------------------===//
113 // MPYS / Multipy signed/unsigned halfwords
114 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
115 //===----------------------------------------------------------------------===//
117 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
118 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
119 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
120 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
121 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
122 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
123 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
124 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
126 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
127 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
128 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
129 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
130 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
131 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
132 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
133 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
135 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
136 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
137 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
138 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
139 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
140 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
141 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
142 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
144 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
145 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
146 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
147 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
148 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
149 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
150 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
151 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
153 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
154 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
155 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
156 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
157 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
158 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
159 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
160 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
163 //===----------------------------------------------------------------------===//
164 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
165 // result from the accumulator.
166 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
167 //===----------------------------------------------------------------------===//
169 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
170 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
171 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
172 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
173 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
174 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
175 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
176 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
178 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
179 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
180 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
181 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
182 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
183 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
184 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
185 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
187 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
188 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
189 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
190 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
191 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
192 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
193 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
194 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
196 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
197 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
198 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
199 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
200 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
201 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
202 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
203 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
205 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
206 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
207 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
208 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
209 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
210 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
211 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
212 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
214 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
215 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
216 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
217 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
218 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
219 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
220 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
221 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
224 //===----------------------------------------------------------------------===//
225 // Multiply signed/unsigned halfwords with and without saturation and rounding
226 // into a 64-bits destination register.
227 //===----------------------------------------------------------------------===//
229 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
230 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
231 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
232 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
233 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
234 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
235 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
236 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
238 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
239 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
240 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
241 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
242 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
243 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
244 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
245 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
247 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
248 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
249 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
250 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
251 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
252 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
253 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
254 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
256 //===----------------------------------------------------------------------===//
257 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
258 // result from the 64-bit destination register.
259 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
260 //===----------------------------------------------------------------------===//
262 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
263 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
264 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
265 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
267 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
268 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
269 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
270 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
272 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
273 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
274 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
275 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
277 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
278 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
279 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
280 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
282 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
283 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
284 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
285 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
287 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
288 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
289 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
290 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
292 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
293 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
294 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
295 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
297 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
298 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
299 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
300 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
303 //===----------------------------------------------------------------------===//
304 // Add/Subtract halfword
305 // Rd=add(Rt.L,Rs.[HL])[:sat]
306 // Rd=sub(Rt.L,Rs.[HL])[:sat]
307 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
308 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
309 //===----------------------------------------------------------------------===//
311 //Rd=add(Rt.L,Rs.[LH])
312 def : T_RR_pat <A2_addh_l16_ll, int_hexagon_A2_addh_l16_ll>;
313 def : T_RR_pat <A2_addh_l16_hl, int_hexagon_A2_addh_l16_hl>;
315 //Rd=add(Rt.L,Rs.[LH]):sat
316 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
317 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
319 //Rd=sub(Rt.L,Rs.[LH])
320 def : T_RR_pat <A2_subh_l16_ll, int_hexagon_A2_subh_l16_ll>;
321 def : T_RR_pat <A2_subh_l16_hl, int_hexagon_A2_subh_l16_hl>;
323 //Rd=sub(Rt.L,Rs.[LH]):sat
324 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
325 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
327 //Rd=add(Rt.[LH],Rs.[LH]):<<16
328 def : T_RR_pat <A2_addh_h16_ll, int_hexagon_A2_addh_h16_ll>;
329 def : T_RR_pat <A2_addh_h16_lh, int_hexagon_A2_addh_h16_lh>;
330 def : T_RR_pat <A2_addh_h16_hl, int_hexagon_A2_addh_h16_hl>;
331 def : T_RR_pat <A2_addh_h16_hh, int_hexagon_A2_addh_h16_hh>;
333 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
334 def : T_RR_pat <A2_subh_h16_ll, int_hexagon_A2_subh_h16_ll>;
335 def : T_RR_pat <A2_subh_h16_lh, int_hexagon_A2_subh_h16_lh>;
336 def : T_RR_pat <A2_subh_h16_hl, int_hexagon_A2_subh_h16_hl>;
337 def : T_RR_pat <A2_subh_h16_hh, int_hexagon_A2_subh_h16_hh>;
339 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
340 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
341 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
342 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
343 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
345 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
346 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
347 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
348 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
349 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
351 // ALU64 / ALU / min max
352 def : T_RR_pat<A2_max, int_hexagon_A2_max>;
353 def : T_RR_pat<A2_min, int_hexagon_A2_min>;
354 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
355 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
357 // Shift and accumulate
358 def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>;
359 def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>;
360 def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>;
361 def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>;
362 def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>;
363 def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>;
365 def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>;
366 def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>;
367 def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>;
368 def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>;
369 def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>;
370 def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>;
371 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
372 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
374 def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>;
375 def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>;
376 def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>;
377 def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>;
378 def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>;
379 def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>;
381 def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>;
382 def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>;
383 def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>;
384 def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>;
385 def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>;
386 def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>;
387 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
388 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
390 def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>;
391 def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>;
392 def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>;
393 def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>;
394 def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>;
395 def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>;
396 def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>;
397 def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>;
399 def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>;
400 def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>;
401 def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>;
402 def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>;
403 def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>;
404 def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>;
405 def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>;
406 def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>;
408 def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>;
409 def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>;
410 def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>;
411 def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>;
412 def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>;
413 def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>;
414 def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>;
415 def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>;
417 def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>;
418 def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>;
419 def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>;
420 def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>;
421 def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>;
422 def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>;
423 def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>;
424 def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
426 def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>;
427 def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>;
428 def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>;
429 def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>;
430 def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>;
431 def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>;
433 def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>;
434 def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>;
435 def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>;
436 def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>;
437 def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>;
438 def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>;
439 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
440 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
442 def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>;
443 def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>;
444 def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>;
445 def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>;
446 def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>;
447 def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>;
449 def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>;
450 def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>;
451 def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>;
452 def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>;
453 def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>;
454 def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>;
455 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
456 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
458 def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>;
459 def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>;
460 def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>;
461 def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>;
462 def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>;
463 def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>;
464 def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>;
465 def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>;
467 def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>;
468 def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>;
469 def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>;
470 def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>;
471 def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>;
472 def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>;
473 def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>;
474 def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>;
476 def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>;
477 def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>;
478 def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>;
479 def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>;
480 def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>;
481 def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>;
482 def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>;
483 def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>;
485 def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>;
486 def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>;
487 def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>;
488 def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>;
489 def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>;
490 def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>;
491 def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>;
492 def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
494 /********************************************************************
496 *********************************************************************/
497 def : T_RR_pat<A2_add, int_hexagon_A2_add>;
498 def : T_RI_pat<ADD_ri, int_hexagon_A2_addi>;
499 def : T_RR_pat<A2_sub, int_hexagon_A2_sub>;
500 def : T_IR_pat<SUB_ri, int_hexagon_A2_subri>;
501 def : T_RR_pat<A2_and, int_hexagon_A2_and>;
502 def : T_RI_pat<AND_ri, int_hexagon_A2_andir>;
503 def : T_RR_pat<A2_or, int_hexagon_A2_or>;
504 def : T_RI_pat<OR_ri, int_hexagon_A2_orir>;
505 def : T_RR_pat<A2_xor, int_hexagon_A2_xor>;
506 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
508 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
509 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
510 (SUB_ri -1, IntRegs:$Rs)>;
512 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
513 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
514 (SUB_ri 0, IntRegs:$Rs)>;
516 // Transfer immediate
517 def : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
518 (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
519 def : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
520 (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
522 // Transfer Register/immediate.
523 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
524 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
526 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
527 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
528 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
530 /********************************************************************
532 *********************************************************************/
534 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
535 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
536 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
537 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
539 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
541 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
543 (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
546 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
547 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
548 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
551 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
552 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
553 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
556 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
557 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
558 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
559 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
561 /********************************************************************
563 *********************************************************************/
564 def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>;
565 def: T_RR_pat<A2_subsat, int_hexagon_A2_subsat>;
566 def: T_PP_pat<A2_addp, int_hexagon_A2_addp>;
567 def: T_PP_pat<A2_subp, int_hexagon_A2_subp>;
569 def: T_PP_pat<A2_andp, int_hexagon_A2_andp>;
570 def: T_PP_pat<A2_orp, int_hexagon_A2_orp>;
571 def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>;
573 def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
574 def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
576 // MPY - Multiply and use full result
577 // Rdd = mpy[u](Rs, Rt)
578 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
579 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
581 // Rxx[+-]= mpy[u](Rs,Rt)
582 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
583 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
584 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
585 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
587 // Multiply 32x32 and use lower result
588 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
589 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
590 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
592 // Subtract and accumulate
593 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
595 // Add and accumulate
596 def : T_RRR_pat <M2_acci, int_hexagon_M2_acci>;
597 def : T_RRR_pat <M2_nacci, int_hexagon_M2_nacci>;
598 def : T_RRI_pat <M2_accii, int_hexagon_M2_accii>;
599 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
601 // XOR and XOR with destination
602 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
604 class MType_R32_pat <Intrinsic IntID, InstHexagon OutputInst> :
605 Pat <(IntID IntRegs:$src1, IntRegs:$src2),
606 (OutputInst IntRegs:$src1, IntRegs:$src2)>;
608 // Multiply and use lower result
609 def : MType_R32_pat <int_hexagon_M2_mpyi, M2_mpyi>;
610 def : T_RI_pat<M2_mpysmi, int_hexagon_M2_mpysmi>;
612 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
613 def : MType_R32_pat <int_hexagon_M2_mpyui, M2_mpyi>;
615 // Multiply and use upper result
616 def : MType_R32_pat <int_hexagon_M2_mpy_up, M2_mpy_up>;
617 def : MType_R32_pat <int_hexagon_M2_mpyu_up, M2_mpyu_up>;
618 def : MType_R32_pat <int_hexagon_M2_hmmpyh_rs1, M2_hmmpyh_rs1>;
619 def : MType_R32_pat <int_hexagon_M2_hmmpyl_rs1, M2_hmmpyl_rs1>;
620 def : MType_R32_pat <int_hexagon_M2_dpmpyss_rnd_s0, M2_dpmpyss_rnd_s0>;
622 /********************************************************************
624 *********************************************************************/
625 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
626 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
627 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
629 /********************************************************************
631 *********************************************************************/
633 // Count leading/trailing
634 def: T_R_pat<S2_cl0, int_hexagon_S2_cl0>;
635 def: T_P_pat<S2_cl0p, int_hexagon_S2_cl0p>;
636 def: T_R_pat<S2_cl1, int_hexagon_S2_cl1>;
637 def: T_P_pat<S2_cl1p, int_hexagon_S2_cl1p>;
638 def: T_R_pat<S2_clb, int_hexagon_S2_clb>;
639 def: T_P_pat<S2_clbp, int_hexagon_S2_clbp>;
640 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
641 def: T_R_pat<S2_ct0, int_hexagon_S2_ct0>;
642 def: T_R_pat<S2_ct1, int_hexagon_S2_ct1>;
645 def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>;
646 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
647 def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>;
649 // Linear feedback-shift Iteration.
650 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
652 // Shift by immediate and add
653 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
656 def : T_PII_pat<S2_extractup, int_hexagon_S2_extractup>;
657 def : T_RII_pat<S2_extractu, int_hexagon_S2_extractu>;
658 def : T_RP_pat <S2_extractu_rp, int_hexagon_S2_extractu_rp>;
659 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
662 def : Pat <(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2,
664 (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>;
666 def : Pat<(i64 (int_hexagon_S2_insertp_rp (I64:$src1),
667 (I64:$src2), (I64:$src3))),
668 (i64 (S2_insertp_rp (I64:$src1), (I64:$src2),
671 def : Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2,
672 u5ImmPred:$src3, u5ImmPred:$src4),
673 (S2_insert IntRegs:$src1, IntRegs:$src2,
674 u5ImmPred:$src3, u5ImmPred:$src4)>;
676 def : Pat<(i64 (int_hexagon_S2_insertp (I64:$src1),
677 (I64:$src2), u6ImmPred:$src3, u6ImmPred:$src4)),
678 (i64 (S2_insertp (I64:$src1), (I64:$src2),
679 u6ImmPred:$src3, u6ImmPred:$src4))>;
682 // Innterleave/deinterleave
683 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
684 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
686 // Set/Clear/Toggle Bit
687 def: T_RI_pat<S2_setbit_i, int_hexagon_S2_setbit_i>;
688 def: T_RI_pat<S2_clrbit_i, int_hexagon_S2_clrbit_i>;
689 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
691 def: T_RR_pat<S2_setbit_r, int_hexagon_S2_setbit_r>;
692 def: T_RR_pat<S2_clrbit_r, int_hexagon_S2_clrbit_r>;
693 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
696 def: T_RI_pat<S2_tstbit_i, int_hexagon_S2_tstbit_i>;
697 def: T_RR_pat<S2_tstbit_r, int_hexagon_S2_tstbit_r>;
699 /********************************************************************
701 *********************************************************************/
703 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
704 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
705 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
707 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
708 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
709 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
710 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
712 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
713 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
714 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
715 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
717 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
718 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
720 def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>;
722 def : T_R_pat <S2_brev, int_hexagon_S2_brev>;
724 def : T_R_pat <A2_abs, int_hexagon_A2_abs>;
725 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
726 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
728 def : T_R_pat <A2_swiz, int_hexagon_A2_swiz>;
730 def : T_P_pat <A2_sat, int_hexagon_A2_sat>;
731 def : T_R_pat <A2_sath, int_hexagon_A2_sath>;
732 def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>;
733 def : T_R_pat <A2_satub, int_hexagon_A2_satub>;
734 def : T_R_pat <A2_satb, int_hexagon_A2_satb>;
736 def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>;
737 def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>;
738 def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>;
739 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
740 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
741 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
743 // Shift left by immediate with saturation.
744 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
746 //===----------------------------------------------------------------------===//
747 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
748 //===----------------------------------------------------------------------===//
749 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
750 SDNodeXForm XformImm>
751 : Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
752 (OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3,
753 (XformImm u5ImmPred:$src4))>;
756 // Table Index : Extract and insert bits.
757 // Map to the real hardware instructions after subtracting appropriate
758 // values from the 4th input operand. Please note that subtraction is not
759 // needed for int_hexagon_S2_tableidxb_goodsyntax.
761 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2,
762 u4ImmPred:$src3, u5ImmPred:$src4),
763 (S2_tableidxb IntRegs:$src1, IntRegs:$src2,
764 u4ImmPred:$src3, u5ImmPred:$src4)>;
766 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
768 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
770 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
777 class qi_ALU32_sisi<string opc, Intrinsic IntID>
778 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
779 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
780 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
782 class qi_ALU32_sis10<string opc, Intrinsic IntID>
783 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
784 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
785 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
787 class qi_ALU32_sis8<string opc, Intrinsic IntID>
788 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
789 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
790 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
792 class qi_ALU32_siu8<string opc, Intrinsic IntID>
793 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
794 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
795 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
797 class qi_ALU32_siu9<string opc, Intrinsic IntID>
798 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
799 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
800 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
802 class si_ALU32_qisisi<string opc, Intrinsic IntID>
803 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
805 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
806 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
809 class si_ALU32_qis8si<string opc, Intrinsic IntID>
810 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
812 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
813 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
816 class si_ALU32_qisis8<string opc, Intrinsic IntID>
817 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
819 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
820 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
823 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
824 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
825 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
826 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
828 class si_ALU32_sisi<string opc, Intrinsic IntID>
829 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
830 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
831 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
833 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
834 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
835 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
836 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
838 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
839 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
840 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
841 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
843 class si_ALU32_sis16<string opc, Intrinsic IntID>
844 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
845 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
846 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
848 class si_ALU32_sis10<string opc, Intrinsic IntID>
849 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
850 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
851 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
853 class si_ALU32_s10si<string opc, Intrinsic IntID>
854 : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
855 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
856 [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
858 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
859 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
860 !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
861 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
863 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
864 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
865 !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
866 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
868 class si_ALU32_s16<string opc, Intrinsic IntID>
869 : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
870 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
871 [(set IntRegs:$dst, (IntID imm:$src1))]>;
873 class di_ALU32_s8<string opc, Intrinsic IntID>
874 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
875 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
876 [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
878 class di_ALU64_di<string opc, Intrinsic IntID>
879 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
880 !strconcat("$dst = ", !strconcat(opc , "$src")),
881 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
883 class si_ALU32_si<string opc, Intrinsic IntID>
884 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
885 !strconcat("$dst = ", !strconcat(opc , "($src)")),
886 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
888 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
889 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
890 !strconcat("$dst = ", !strconcat(opc , "$src")),
891 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
897 class si_ALU64_si_sat<string opc, Intrinsic IntID>
898 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
899 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
900 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
902 class si_ALU64_didi<string opc, Intrinsic IntID>
903 : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
904 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
905 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
907 class di_ALU64_sidi<string opc, Intrinsic IntID>
908 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
909 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
910 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
912 class di_ALU64_didi<string opc, Intrinsic IntID>
913 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
914 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
915 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
916 DoubleRegs:$src2))]>;
918 class di_ALU64_qididi<string opc, Intrinsic IntID>
919 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
921 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
922 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
923 DoubleRegs:$src3))]>;
925 class di_ALU64_sisi<string opc, Intrinsic IntID>
926 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
927 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
928 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
930 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
931 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
932 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
933 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
934 DoubleRegs:$src2))]>;
936 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
937 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
938 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
939 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
940 DoubleRegs:$src2))]>;
942 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
943 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
944 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
945 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
946 DoubleRegs:$src2))]>;
948 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
949 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
950 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
951 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
952 DoubleRegs:$src2))]>;
954 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
955 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
956 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
957 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
958 DoubleRegs:$src2))]>;
960 class qi_ALU64_didi<string opc, Intrinsic IntID>
961 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
962 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
963 [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
965 class si_ALU64_sisi<string opc, Intrinsic IntID>
966 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
967 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
968 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
970 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
971 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
972 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
973 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
975 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
976 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
977 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
978 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
980 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
981 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
982 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
983 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
985 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
986 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
987 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
988 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
990 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
991 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
992 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
993 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
995 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
996 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
997 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
998 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1000 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
1001 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1002 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1003 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1005 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
1006 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1007 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1008 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1010 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
1011 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1012 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1013 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1015 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
1016 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1017 !strconcat("$dst = ", !strconcat(opc ,
1018 "($src1.H, $src2.H):sat:<<16")),
1019 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1021 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
1022 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1023 !strconcat("$dst = ", !strconcat(opc ,
1024 "($src1.L, $src2.H):sat:<<16")),
1025 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1027 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
1028 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1029 !strconcat("$dst = ", !strconcat(opc ,
1030 "($src1.H, $src2.L):sat:<<16")),
1031 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1033 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
1034 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1035 !strconcat("$dst = ", !strconcat(opc ,
1036 "($src1.L, $src2.L):sat:<<16")),
1037 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1039 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
1040 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1041 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
1042 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1044 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
1045 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1046 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
1047 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1049 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
1050 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1051 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
1052 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1054 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
1055 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1056 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
1057 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1059 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
1060 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1061 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1062 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1064 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
1065 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1066 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1067 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1069 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
1070 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1071 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1072 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1078 class qi_SInst_qi<string opc, Intrinsic IntID>
1079 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1080 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1081 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1083 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
1084 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1085 !strconcat("$dst = ", !strconcat(opc , "$src")),
1086 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1088 class qi_SInst_qiqi<string opc, Intrinsic IntID>
1089 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1090 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1091 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1093 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
1094 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1095 !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
1096 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1098 class di_SInst_di<string opc, Intrinsic IntID>
1099 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1100 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1101 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1103 class di_SInst_di_sat<string opc, Intrinsic IntID>
1104 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1105 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1106 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1108 class si_SInst_di<string opc, Intrinsic IntID>
1109 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1110 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1111 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1113 class si_SInst_di_sat<string opc, Intrinsic IntID>
1114 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1115 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1116 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1118 class di_SInst_disi<string opc, Intrinsic IntID>
1119 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1120 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1121 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1123 class di_SInst_didi<string opc, Intrinsic IntID>
1124 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1125 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1126 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1128 class di_SInst_si<string opc, Intrinsic IntID>
1129 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1130 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
1131 [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
1133 class si_SInst_sisiu3<string opc, Intrinsic IntID>
1134 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
1135 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
1136 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
1139 class si_SInst_diu5<string opc, Intrinsic IntID>
1140 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
1141 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1142 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
1144 class si_SInst_disi<string opc, Intrinsic IntID>
1145 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1146 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1147 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1149 class si_SInst_sidi<string opc, Intrinsic IntID>
1150 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
1151 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1152 [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
1154 class di_SInst_disisi<string opc, Intrinsic IntID>
1155 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
1157 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1158 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
1161 class di_SInst_sisi<string opc, Intrinsic IntID>
1162 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1163 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1164 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1166 class qi_SInst_siu5<string opc, Intrinsic IntID>
1167 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1168 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1169 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1171 class qi_SInst_siu6<string opc, Intrinsic IntID>
1172 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
1173 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1174 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1176 class qi_SInst_sisi<string opc, Intrinsic IntID>
1177 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1178 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1179 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1181 class si_SInst_si<string opc, Intrinsic IntID>
1182 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1183 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1184 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1186 class si_SInst_si_sat<string opc, Intrinsic IntID>
1187 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1188 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1189 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1191 class di_SInst_qi<string opc, Intrinsic IntID>
1192 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
1193 !strconcat("$dst = ", !strconcat(opc , "($src)")),
1194 [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
1196 class si_SInst_qi<string opc, Intrinsic IntID>
1197 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1198 !strconcat("$dst = ", !strconcat(opc , "$src")),
1199 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1201 class si_SInst_qiqi<string opc, Intrinsic IntID>
1202 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1203 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1204 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1206 class qi_SInst_si<string opc, Intrinsic IntID>
1207 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1208 !strconcat("$dst = ", !strconcat(opc , "$src")),
1209 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1211 class si_SInst_sisi<string opc, Intrinsic IntID>
1212 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1213 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1214 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1216 class di_SInst_diu6<string opc, Intrinsic IntID>
1217 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1218 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1219 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
1221 class si_SInst_siu5<string opc, Intrinsic IntID>
1222 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1223 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1224 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1226 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
1227 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1228 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
1229 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1231 class si_SInst_siu5u5<string opc, Intrinsic IntID>
1232 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
1233 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
1234 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
1236 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
1237 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1239 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1240 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1244 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
1245 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1247 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1248 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1252 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
1253 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1255 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1256 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1261 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
1262 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1264 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1265 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1266 DoubleRegs:$src1, IntRegs:$src2))],
1269 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
1270 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1271 u5Imm:$src2, u5Imm:$src3),
1272 !strconcat("$dst = ", !strconcat(opc ,
1273 "($src1, #$src2, #$src3)")),
1274 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1275 imm:$src2, imm:$src3))],
1278 class si_SInst_sisidi<string opc, Intrinsic IntID>
1279 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1281 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1282 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1283 DoubleRegs:$src2))],
1286 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
1287 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1288 u6Imm:$src2, u6Imm:$src3),
1289 !strconcat("$dst = ", !strconcat(opc ,
1290 "($src1, #$src2, #$src3)")),
1291 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1292 imm:$src2, imm:$src3))],
1295 class di_SInst_dididi<string opc, Intrinsic IntID>
1296 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1298 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1299 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1301 DoubleRegs:$src2))],
1304 class di_SInst_diu6u6<string opc, Intrinsic IntID>
1305 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
1307 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
1308 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
1311 class di_SInst_didiqi<string opc, Intrinsic IntID>
1312 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1314 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1315 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1318 class di_SInst_didiu3<string opc, Intrinsic IntID>
1319 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1321 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
1322 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1325 class di_SInst_didisi_or<string opc, Intrinsic IntID>
1326 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1328 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
1329 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1333 class di_SInst_didisi_and<string opc, Intrinsic IntID>
1334 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1336 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
1337 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1341 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
1342 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1344 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
1345 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1349 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
1350 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1352 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
1353 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1357 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
1358 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1360 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
1361 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1365 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
1366 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1368 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
1369 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1373 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
1374 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1376 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
1377 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1382 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
1383 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1385 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
1386 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1390 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
1391 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1393 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
1394 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1398 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
1399 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1401 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
1402 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1406 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
1407 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1409 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
1410 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1414 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
1415 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1417 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1418 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1422 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
1423 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1425 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
1426 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1427 DoubleRegs:$src1, imm:$src2))],
1430 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
1431 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1433 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1434 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1443 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1444 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1445 !strconcat("$dst = ", !strconcat(opc ,
1446 "($src1.H, $src2.H):<<1:rnd")),
1447 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1449 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1450 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1451 !strconcat("$dst = ", !strconcat(opc ,
1452 "($src1.H, $src2.H):rnd")),
1453 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1455 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1456 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1457 !strconcat("$dst = ", !strconcat(opc ,
1458 "($src1.H, $src2.L):<<1:rnd")),
1459 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1461 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1462 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1463 !strconcat("$dst = ", !strconcat(opc ,
1464 "($src1.H, $src2.L):rnd")),
1465 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1467 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1468 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1469 !strconcat("$dst = ", !strconcat(opc ,
1470 "($src1.L, $src2.H):<<1:rnd")),
1471 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1473 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1474 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1475 !strconcat("$dst = ", !strconcat(opc ,
1476 "($src1.L, $src2.H):rnd")),
1477 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1479 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1480 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1481 !strconcat("$dst = ", !strconcat(opc ,
1482 "($src1.L, $src2.L):<<1:rnd")),
1483 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1485 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1486 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1487 !strconcat("$dst = ", !strconcat(opc ,
1488 "($src1.L, $src2.L):rnd")),
1489 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1491 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1492 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1494 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1495 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1499 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1500 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1502 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1503 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1507 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1508 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1510 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1511 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1515 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1516 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1518 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1519 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1523 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1524 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1526 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1527 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1531 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1532 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1534 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1535 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1539 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1540 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1542 !strconcat("$dst -= ", !strconcat(opc ,
1543 "($src1, $src2):<<1:sat")),
1544 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1548 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1549 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1551 !strconcat("$dst += ", !strconcat(opc ,
1552 "($src1, $src2*):<<1:sat")),
1553 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1557 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1558 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1560 !strconcat("$dst -= ", !strconcat(opc ,
1561 "($src1, $src2*):<<1:sat")),
1562 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1566 class di_MInst_s8s8<string opc, Intrinsic IntID>
1567 : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1568 !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1569 [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1571 class si_MInst_sis9<string opc, Intrinsic IntID>
1572 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1573 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1574 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1576 class si_MInst_sisi<string opc, Intrinsic IntID>
1577 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1578 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1579 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1581 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1582 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1583 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1584 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1586 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1587 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1588 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1589 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1591 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1592 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1593 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1594 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1596 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1597 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1598 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1599 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1601 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1602 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1603 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1604 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1606 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1607 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1608 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1609 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1611 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1612 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1613 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1614 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1616 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1617 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1618 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1619 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1622 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1623 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1624 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1625 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1627 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1628 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1629 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1630 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1632 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1633 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1634 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1635 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1637 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1638 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1639 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1640 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1642 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1643 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1644 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1645 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1647 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1648 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1649 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1650 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1652 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1653 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1654 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1655 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1657 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1658 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1659 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1660 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1662 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1663 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1664 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1665 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1667 class di_MInst_didi<string opc, Intrinsic IntID>
1668 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1669 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1670 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1671 DoubleRegs:$src2))]>;
1673 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1674 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1675 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1676 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1677 DoubleRegs:$src2))]>;
1679 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1680 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1681 !strconcat("$dst = ", !strconcat(opc ,
1682 "($src1, $src2*):<<1:sat")),
1683 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1685 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1686 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1687 !strconcat("$dst = ", !strconcat(opc ,
1688 "($src1, $src2):<<1:rnd:sat")),
1689 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1690 DoubleRegs:$src2))]>;
1692 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1693 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1694 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1695 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1696 DoubleRegs:$src2))]>;
1698 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1699 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1700 !strconcat("$dst = ", !strconcat(opc ,
1701 "($src1, $src2):rnd:sat")),
1702 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1703 DoubleRegs:$src2))]>;
1705 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1706 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1707 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1708 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1710 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1711 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1712 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1713 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1715 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1716 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1717 !strconcat("$dst = ", !strconcat(opc ,
1718 "($src1, $src2):<<1:rnd:sat")),
1719 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1721 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1722 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1723 !strconcat("$dst = ", !strconcat(opc ,
1724 "($src1, $src2):<<1:rnd:sat")),
1725 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1727 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1728 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1729 !strconcat("$dst = ", !strconcat(opc ,
1730 "($src1, $src2.L):<<1:rnd:sat")),
1731 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1733 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1734 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1735 !strconcat("$dst = ", !strconcat(opc ,
1736 "($src1, $src2.H):<<1:rnd:sat")),
1737 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1739 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1740 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1741 !strconcat("$dst = ", !strconcat(opc ,
1742 "($src1, $src2*):rnd:sat")),
1743 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1745 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1746 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1747 !strconcat("$dst = ", !strconcat(opc ,
1748 "($src1, $src2*):<<1:rnd:sat")),
1749 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1751 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1752 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1753 !strconcat("$dst = ", !strconcat(opc ,
1754 "($src1, $src2):rnd:sat")),
1755 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1757 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1758 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1759 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1760 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1762 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1763 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1765 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1766 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1770 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1771 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1773 !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1774 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1778 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1779 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1781 !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1782 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1786 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1787 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1789 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1790 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1794 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1795 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1797 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1798 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1802 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1803 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1804 u4Imm:$src2, u5Imm:$src3),
1805 !strconcat("$dst = ", !strconcat(opc ,
1806 "($src1, #$src2, #$src3)")),
1807 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1808 imm:$src2, imm:$src3))],
1811 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1812 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1814 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1815 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1819 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1820 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1822 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1823 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1827 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1828 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1830 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1831 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1835 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1836 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1838 !strconcat("$dst += ", !strconcat(opc ,
1839 "($src1.L, $src2.H):sat")),
1840 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1844 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1845 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1847 !strconcat("$dst += ", !strconcat(opc ,
1848 "($src1.L, $src2.H):<<1:sat")),
1849 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1853 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1854 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1856 !strconcat("$dst += ", !strconcat(opc ,
1857 "($src1.H, $src2.H):sat")),
1858 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1862 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1863 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1865 !strconcat("$dst += ", !strconcat(opc ,
1866 "($src1.H, $src2.H):<<1:sat")),
1867 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1871 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1872 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1874 !strconcat("$dst += ", !strconcat(opc ,
1875 "($src1.H, $src2.H):<<1")),
1876 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1880 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1881 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1883 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1884 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1888 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1889 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1891 !strconcat("$dst -= ", !strconcat(opc ,
1892 "($src1.H, $src2.H):<<1:sat")),
1893 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1897 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1898 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1900 !strconcat("$dst -= ", !strconcat(opc ,
1901 "($src1.H, $src2.H):sat")),
1902 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1906 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1907 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1909 !strconcat("$dst -= ", !strconcat(opc ,
1910 "($src1.H, $src2.L):<<1:sat")),
1911 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1915 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1916 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1918 !strconcat("$dst -= ", !strconcat(opc ,
1919 "($src1.H, $src2.L):sat")),
1920 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1924 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1925 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1927 !strconcat("$dst -= ", !strconcat(opc ,
1928 "($src1.L, $src2.H):<<1:sat")),
1929 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1933 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1934 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1936 !strconcat("$dst -= ", !strconcat(opc ,
1937 "($src1.L, $src2.H):sat")),
1938 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1942 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1943 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1945 !strconcat("$dst -= ", !strconcat(opc ,
1946 "($src1.L, $src2.L):<<1:sat")),
1947 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1951 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1952 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1954 !strconcat("$dst -= ", !strconcat(opc ,
1955 "($src1.L, $src2.L):sat")),
1956 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1960 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1961 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1963 !strconcat("$dst -= ", !strconcat(opc ,
1964 "($src1.H, $src2.H):<<1")),
1965 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1969 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1970 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1972 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1973 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1977 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1978 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1980 !strconcat("$dst += ", !strconcat(opc ,
1981 "($src1.H, $src2.L):<<1")),
1982 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1986 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1987 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1989 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1990 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1994 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1995 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1997 !strconcat("$dst -= ", !strconcat(opc ,
1998 "($src1.H, $src2.L):<<1")),
1999 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2003 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
2004 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2006 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
2007 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2011 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
2012 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2014 !strconcat("$dst += ", !strconcat(opc ,
2015 "($src1.L, $src2.H):<<1")),
2016 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2020 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
2021 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2023 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2024 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2028 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
2029 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2031 !strconcat("$dst -= ", !strconcat(opc ,
2032 "($src1.L, $src2.H):<<1")),
2033 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2037 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
2038 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2040 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
2041 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2045 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
2046 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2048 !strconcat("$dst += ", !strconcat(opc ,
2049 "($src1.L, $src2.L):<<1")),
2050 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2054 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
2055 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2057 !strconcat("$dst += ", !strconcat(opc ,
2058 "($src1.L, $src2.L):<<1:sat")),
2059 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2063 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
2064 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2066 !strconcat("$dst += ", !strconcat(opc ,
2067 "($src1.H, $src2.L):<<1:sat")),
2068 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2072 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
2073 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2075 !strconcat("$dst += ", !strconcat(opc ,
2076 "($src1.L, $src2.L):sat")),
2077 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2081 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
2082 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2084 !strconcat("$dst += ", !strconcat(opc ,
2085 "($src1.H, $src2.L):sat")),
2086 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2090 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
2091 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2093 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2094 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2098 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
2099 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2101 !strconcat("$dst -= ", !strconcat(opc ,
2102 "($src1.L, $src2.L):<<1")),
2103 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2107 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
2108 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2110 !strconcat("$dst -= ", !strconcat(opc ,
2111 "($src1.H, $src2.H):sat")),
2112 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2116 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
2117 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2119 !strconcat("$dst -= ", !strconcat(opc ,
2120 "($src1.H, $src2.H):<<1:sat")),
2121 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2125 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
2126 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2128 !strconcat("$dst -= ", !strconcat(opc ,
2129 "($src1.H, $src2.L):sat")),
2130 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2134 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
2135 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2137 !strconcat("$dst -= ", !strconcat(opc ,
2138 "($src1.H, $src2.L):<<1:sat")),
2139 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2143 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
2144 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2146 !strconcat("$dst -= ", !strconcat(opc ,
2147 "($src1.L, $src2.H):sat")),
2148 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2152 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
2153 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2155 !strconcat("$dst -= ", !strconcat(opc ,
2156 "($src1.L, $src2.H):<<1:sat")),
2157 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2161 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
2162 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2164 !strconcat("$dst -= ", !strconcat(opc ,
2165 "($src1.L, $src2.L):sat")),
2166 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2170 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
2171 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2173 !strconcat("$dst -= ", !strconcat(opc ,
2174 "($src1.L, $src2.L):<<1:sat")),
2175 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2179 class di_ALU32_sisi<string opc, Intrinsic IntID>
2180 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2181 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2182 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2184 class di_MInst_sisi<string opc, Intrinsic IntID>
2185 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2186 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2187 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2189 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
2190 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2191 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
2192 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2194 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
2195 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2196 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
2197 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2199 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
2200 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2201 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2202 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2204 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
2205 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2206 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2207 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
2208 DoubleRegs:$src2))]>;
2210 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
2211 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2212 !strconcat("$dst = ", !strconcat(opc ,
2213 "($src1, $src2):<<1:rnd:sat")),
2214 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2216 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
2217 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2218 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
2219 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2221 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
2222 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2223 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
2224 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2226 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
2227 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2228 !strconcat("$dst = ", !strconcat(opc ,
2229 "($src1.H, $src2.H):<<1:sat")),
2230 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2232 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
2233 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2234 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
2235 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2237 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
2238 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2239 !strconcat("$dst = ", !strconcat(opc ,
2240 "($src1.H, $src2.L):<<1:sat")),
2241 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2243 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
2244 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2245 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
2246 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2248 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
2249 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2250 !strconcat("$dst = ", !strconcat(opc ,
2251 "($src1.L, $src2.H):<<1:sat")),
2252 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2254 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
2255 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2256 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
2257 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2259 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
2260 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2261 !strconcat("$dst = ", !strconcat(opc ,
2262 "($src1.L, $src2.L):<<1:sat")),
2263 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2265 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
2266 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2267 !strconcat("$dst = ", !strconcat(opc ,
2268 "($src1.H, $src2.H):rnd:sat")),
2269 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2271 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
2272 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2273 !strconcat("$dst = ", !strconcat(opc ,
2274 "($src1.H, $src2.H):rnd")),
2275 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2277 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
2278 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2279 !strconcat("$dst = ", !strconcat(opc ,
2280 "($src1.H, $src2.H):<<1:rnd")),
2281 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2283 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
2284 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2285 !strconcat("$dst = ",
2287 "($src1.H, $src2.H):<<1:rnd:sat")),
2288 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2290 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
2291 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2292 !strconcat("$dst = ",
2293 !strconcat(opc , "($src1.H, $src2.L):rnd")),
2294 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2296 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
2297 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2298 !strconcat("$dst = ",
2299 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
2300 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2302 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
2303 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2304 !strconcat("$dst = ",
2305 !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
2306 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2308 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
2309 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2310 !strconcat("$dst = ",
2311 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
2312 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2314 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
2315 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2316 !strconcat("$dst = ",
2317 !strconcat(opc , "($src1.L, $src2.H):rnd")),
2318 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2320 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
2321 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2322 !strconcat("$dst = ",
2323 !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
2324 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2326 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
2327 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2328 !strconcat("$dst = ",
2329 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
2330 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2332 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
2333 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2334 !strconcat("$dst = ",
2335 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
2336 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2338 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
2339 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2340 !strconcat("$dst = ",
2341 !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
2342 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2344 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
2345 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2346 !strconcat("$dst = ",
2347 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
2348 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2350 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
2351 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2352 !strconcat("$dst = ",
2353 !strconcat(opc , "($src1.L, $src2.L):rnd")),
2354 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2356 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
2357 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2358 !strconcat("$dst = ",
2359 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
2360 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2362 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
2363 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2364 DoubleRegs:$src1, DoubleRegs:$src2),
2365 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
2366 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2368 DoubleRegs:$src2))],
2371 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
2372 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2374 !strconcat("$dst += ",
2375 !strconcat(opc , "($src1, $src2):rnd:sat")),
2376 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2378 DoubleRegs:$src2))],
2381 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
2382 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2385 !strconcat("$dst += ",
2386 !strconcat(opc , "($src1, $src2):<<1")),
2387 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2389 DoubleRegs:$src2))],
2393 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
2394 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2397 !strconcat("$dst += ",
2398 !strconcat(opc , "($src1, $src2):<<1:sat")),
2399 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2401 DoubleRegs:$src2))],
2404 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
2405 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2407 !strconcat("$dst += ",
2408 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2409 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2411 DoubleRegs:$src2))],
2414 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
2415 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2417 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
2418 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2420 DoubleRegs:$src2))],
2423 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
2424 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2426 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
2427 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2429 DoubleRegs:$src2))],
2432 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
2433 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2435 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
2436 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2440 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
2441 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2443 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
2444 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2448 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
2449 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2451 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
2452 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2456 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
2457 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2459 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
2460 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2464 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
2465 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2467 !strconcat("$dst += ",
2468 !strconcat(opc , "($src1.H, $src2.H):<<1")),
2469 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2473 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
2474 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2476 !strconcat("$dst += ",
2477 !strconcat(opc , "($src1.H, $src2.L):<<1")),
2478 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2482 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
2483 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2485 !strconcat("$dst += ",
2486 !strconcat(opc , "($src1.L, $src2.H):<<1")),
2487 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2491 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
2492 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2494 !strconcat("$dst += ",
2495 !strconcat(opc , "($src1.L, $src2.L):<<1")),
2496 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2500 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
2501 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2503 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
2504 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2508 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
2509 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2511 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
2512 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2516 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
2517 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2519 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2520 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2524 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
2525 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2527 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2528 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2532 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
2533 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2535 !strconcat("$dst -= ",
2536 !strconcat(opc , "($src1.H, $src2.H):<<1")),
2537 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2541 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
2542 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2544 !strconcat("$dst -= ",
2545 !strconcat(opc , "($src1.H, $src2.L):<<1")),
2546 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2550 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
2551 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2553 !strconcat("$dst -= ",
2554 !strconcat(opc , "($src1.L, $src2.H):<<1")),
2555 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2559 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2560 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2562 !strconcat("$dst -= ",
2563 !strconcat(opc , "($src1.L, $src2.L):<<1")),
2564 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2568 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2569 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2571 !strconcat("$dst += ",
2572 !strconcat(opc , "($src1, $src2):<<1:sat")),
2573 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2577 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2578 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2579 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2580 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2582 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2583 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2585 !strconcat("$dst += ",
2586 !strconcat(opc , "($src1, $src2):<<1:sat")),
2587 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2592 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2593 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2594 !strconcat("$dst = ",
2595 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2596 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2598 class si_MInst_didi<string opc, Intrinsic IntID>
2599 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2600 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2601 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2606 let mayLoad = 1, hasSideEffects = 0 in
2607 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2608 : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2609 (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2610 "$dst2 = memd($src1++#$offset:circ($src3))",
2614 /********************************************************************
2616 *********************************************************************/
2618 // ALU32 / PERM / Mux.
2620 si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
2622 /********************************************************************
2624 *********************************************************************/
2626 // ALU32 / PRED / Compare.
2627 def HEXAGON_C2_cmpeq:
2628 qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
2629 def HEXAGON_C2_cmpeqi:
2630 qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
2631 def HEXAGON_C2_cmpgei:
2632 qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
2633 def HEXAGON_C2_cmpgeui:
2634 qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
2635 def HEXAGON_C2_cmpgt:
2636 qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
2637 def HEXAGON_C2_cmpgti:
2638 qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
2639 def HEXAGON_C2_cmpgtu:
2640 qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
2641 def HEXAGON_C2_cmpgtui:
2642 qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
2643 def HEXAGON_C2_cmplt:
2644 qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
2645 def HEXAGON_C2_cmpltu:
2646 qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
2648 /********************************************************************
2650 *********************************************************************/
2652 // ALU32 / VH / Vector add halfwords.
2653 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2654 def HEXAGON_A2_svaddh:
2655 si_ALU32_sisi <"vaddh", int_hexagon_A2_svaddh>;
2656 def HEXAGON_A2_svaddhs:
2657 si_ALU32_sisi_sat <"vaddh", int_hexagon_A2_svaddhs>;
2658 def HEXAGON_A2_svadduhs:
2659 si_ALU32_sisi_sat <"vadduh", int_hexagon_A2_svadduhs>;
2661 // ALU32 / VH / Vector average halfwords.
2662 def HEXAGON_A2_svavgh:
2663 si_ALU32_sisi <"vavgh", int_hexagon_A2_svavgh>;
2664 def HEXAGON_A2_svavghs:
2665 si_ALU32_sisi_rnd <"vavgh", int_hexagon_A2_svavghs>;
2666 def HEXAGON_A2_svnavgh:
2667 si_ALU32_sisi <"vnavgh", int_hexagon_A2_svnavgh>;
2669 // ALU32 / VH / Vector subtract halfwords.
2670 def HEXAGON_A2_svsubh:
2671 si_ALU32_sisi <"vsubh", int_hexagon_A2_svsubh>;
2672 def HEXAGON_A2_svsubhs:
2673 si_ALU32_sisi_sat <"vsubh", int_hexagon_A2_svsubhs>;
2674 def HEXAGON_A2_svsubuhs:
2675 si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
2677 /********************************************************************
2679 *********************************************************************/
2681 // ALU64 / ALU / Compare.
2682 def HEXAGON_C2_cmpeqp:
2683 qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
2684 def HEXAGON_C2_cmpgtp:
2685 qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
2686 def HEXAGON_C2_cmpgtup:
2687 qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
2689 // ALU64 / ALU / Transfer register.
2690 def HEXAGON_A2_tfrp:
2691 di_ALU64_di <"", int_hexagon_A2_tfrp>;
2693 /********************************************************************
2695 *********************************************************************/
2697 // ALU64 / VB / Vector add unsigned bytes.
2698 def HEXAGON_A2_vaddub:
2699 di_ALU64_didi <"vaddub", int_hexagon_A2_vaddub>;
2700 def HEXAGON_A2_vaddubs:
2701 di_ALU64_didi_sat <"vaddub", int_hexagon_A2_vaddubs>;
2703 // ALU64 / VB / Vector average unsigned bytes.
2704 def HEXAGON_A2_vavgub:
2705 di_ALU64_didi <"vavgub", int_hexagon_A2_vavgub>;
2706 def HEXAGON_A2_vavgubr:
2707 di_ALU64_didi_rnd <"vavgub", int_hexagon_A2_vavgubr>;
2709 // ALU64 / VB / Vector compare unsigned bytes.
2710 def HEXAGON_A2_vcmpbeq:
2711 qi_ALU64_didi <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2712 def HEXAGON_A2_vcmpbgtu:
2713 qi_ALU64_didi <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2715 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2716 def HEXAGON_A2_vmaxub:
2717 di_ALU64_didi <"vmaxub", int_hexagon_A2_vmaxub>;
2718 def HEXAGON_A2_vminub:
2719 di_ALU64_didi <"vminub", int_hexagon_A2_vminub>;
2721 // ALU64 / VB / Vector subtract unsigned bytes.
2722 def HEXAGON_A2_vsubub:
2723 di_ALU64_didi <"vsubub", int_hexagon_A2_vsubub>;
2724 def HEXAGON_A2_vsububs:
2725 di_ALU64_didi_sat <"vsubub", int_hexagon_A2_vsububs>;
2727 // ALU64 / VB / Vector mux.
2728 def HEXAGON_C2_vmux:
2729 di_ALU64_qididi <"vmux", int_hexagon_C2_vmux>;
2732 /********************************************************************
2734 *********************************************************************/
2736 // ALU64 / VH / Vector add halfwords.
2737 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2738 def HEXAGON_A2_vaddh:
2739 di_ALU64_didi <"vaddh", int_hexagon_A2_vaddh>;
2740 def HEXAGON_A2_vaddhs:
2741 di_ALU64_didi_sat <"vaddh", int_hexagon_A2_vaddhs>;
2742 def HEXAGON_A2_vadduhs:
2743 di_ALU64_didi_sat <"vadduh", int_hexagon_A2_vadduhs>;
2745 // ALU64 / VH / Vector average halfwords.
2746 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2747 def HEXAGON_A2_vavgh:
2748 di_ALU64_didi <"vavgh", int_hexagon_A2_vavgh>;
2749 def HEXAGON_A2_vavghcr:
2750 di_ALU64_didi_crnd <"vavgh", int_hexagon_A2_vavghcr>;
2751 def HEXAGON_A2_vavghr:
2752 di_ALU64_didi_rnd <"vavgh", int_hexagon_A2_vavghr>;
2753 def HEXAGON_A2_vavguh:
2754 di_ALU64_didi <"vavguh", int_hexagon_A2_vavguh>;
2755 def HEXAGON_A2_vavguhr:
2756 di_ALU64_didi_rnd <"vavguh", int_hexagon_A2_vavguhr>;
2757 def HEXAGON_A2_vnavgh:
2758 di_ALU64_didi <"vnavgh", int_hexagon_A2_vnavgh>;
2759 def HEXAGON_A2_vnavghcr:
2760 di_ALU64_didi_crnd_sat <"vnavgh", int_hexagon_A2_vnavghcr>;
2761 def HEXAGON_A2_vnavghr:
2762 di_ALU64_didi_rnd_sat <"vnavgh", int_hexagon_A2_vnavghr>;
2764 // ALU64 / VH / Vector compare halfwords.
2765 def HEXAGON_A2_vcmpheq:
2766 qi_ALU64_didi <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2767 def HEXAGON_A2_vcmphgt:
2768 qi_ALU64_didi <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2769 def HEXAGON_A2_vcmphgtu:
2770 qi_ALU64_didi <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2772 // ALU64 / VH / Vector maximum halfwords.
2773 def HEXAGON_A2_vmaxh:
2774 di_ALU64_didi <"vmaxh", int_hexagon_A2_vmaxh>;
2775 def HEXAGON_A2_vmaxuh:
2776 di_ALU64_didi <"vmaxuh", int_hexagon_A2_vmaxuh>;
2778 // ALU64 / VH / Vector minimum halfwords.
2779 def HEXAGON_A2_vminh:
2780 di_ALU64_didi <"vminh", int_hexagon_A2_vminh>;
2781 def HEXAGON_A2_vminuh:
2782 di_ALU64_didi <"vminuh", int_hexagon_A2_vminuh>;
2784 // ALU64 / VH / Vector subtract halfwords.
2785 def HEXAGON_A2_vsubh:
2786 di_ALU64_didi <"vsubh", int_hexagon_A2_vsubh>;
2787 def HEXAGON_A2_vsubhs:
2788 di_ALU64_didi_sat <"vsubh", int_hexagon_A2_vsubhs>;
2789 def HEXAGON_A2_vsubuhs:
2790 di_ALU64_didi_sat <"vsubuh", int_hexagon_A2_vsubuhs>;
2793 /********************************************************************
2795 *********************************************************************/
2797 // ALU64 / VW / Vector add words.
2798 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2799 def HEXAGON_A2_vaddw:
2800 di_ALU64_didi <"vaddw", int_hexagon_A2_vaddw>;
2801 def HEXAGON_A2_vaddws:
2802 di_ALU64_didi_sat <"vaddw", int_hexagon_A2_vaddws>;
2804 // ALU64 / VW / Vector average words.
2805 def HEXAGON_A2_vavguw:
2806 di_ALU64_didi <"vavguw", int_hexagon_A2_vavguw>;
2807 def HEXAGON_A2_vavguwr:
2808 di_ALU64_didi_rnd <"vavguw", int_hexagon_A2_vavguwr>;
2809 def HEXAGON_A2_vavgw:
2810 di_ALU64_didi <"vavgw", int_hexagon_A2_vavgw>;
2811 def HEXAGON_A2_vavgwcr:
2812 di_ALU64_didi_crnd <"vavgw", int_hexagon_A2_vavgwcr>;
2813 def HEXAGON_A2_vavgwr:
2814 di_ALU64_didi_rnd <"vavgw", int_hexagon_A2_vavgwr>;
2815 def HEXAGON_A2_vnavgw:
2816 di_ALU64_didi <"vnavgw", int_hexagon_A2_vnavgw>;
2817 def HEXAGON_A2_vnavgwcr:
2818 di_ALU64_didi_crnd_sat <"vnavgw", int_hexagon_A2_vnavgwcr>;
2819 def HEXAGON_A2_vnavgwr:
2820 di_ALU64_didi_rnd_sat <"vnavgw", int_hexagon_A2_vnavgwr>;
2822 // ALU64 / VW / Vector compare words.
2823 def HEXAGON_A2_vcmpweq:
2824 qi_ALU64_didi <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2825 def HEXAGON_A2_vcmpwgt:
2826 qi_ALU64_didi <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2827 def HEXAGON_A2_vcmpwgtu:
2828 qi_ALU64_didi <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2830 // ALU64 / VW / Vector maximum words.
2831 def HEXAGON_A2_vmaxw:
2832 di_ALU64_didi <"vmaxw", int_hexagon_A2_vmaxw>;
2833 def HEXAGON_A2_vmaxuw:
2834 di_ALU64_didi <"vmaxuw", int_hexagon_A2_vmaxuw>;
2836 // ALU64 / VW / Vector minimum words.
2837 def HEXAGON_A2_vminw:
2838 di_ALU64_didi <"vminw", int_hexagon_A2_vminw>;
2839 def HEXAGON_A2_vminuw:
2840 di_ALU64_didi <"vminuw", int_hexagon_A2_vminuw>;
2842 // ALU64 / VW / Vector subtract words.
2843 def HEXAGON_A2_vsubw:
2844 di_ALU64_didi <"vsubw", int_hexagon_A2_vsubw>;
2845 def HEXAGON_A2_vsubws:
2846 di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
2849 /********************************************************************
2851 *********************************************************************/
2853 // CR / Logical reductions on predicates.
2854 def HEXAGON_C2_all8:
2855 qi_SInst_qi <"all8", int_hexagon_C2_all8>;
2856 def HEXAGON_C2_any8:
2857 qi_SInst_qi <"any8", int_hexagon_C2_any8>;
2859 // CR / Logical operations on predicates.
2860 def HEXAGON_C2_pxfer_map:
2861 qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
2863 qi_SInst_qiqi <"and", int_hexagon_C2_and>;
2864 def HEXAGON_C2_andn:
2865 qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
2867 qi_SInst_qi <"not", int_hexagon_C2_not>;
2869 qi_SInst_qiqi <"or", int_hexagon_C2_or>;
2871 qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
2873 qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
2876 /********************************************************************
2878 *********************************************************************/
2880 // MTYPE / ALU / Vector absolute difference.
2881 def HEXAGON_M2_vabsdiffh:
2882 di_MInst_didi <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2883 def HEXAGON_M2_vabsdiffw:
2884 di_MInst_didi <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2887 /********************************************************************
2889 *********************************************************************/
2891 // MTYPE / COMPLEX / Complex multiply.
2892 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2893 def HEXAGON_M2_cmpys_s1:
2894 di_MInst_sisi_s1_sat <"cmpy", int_hexagon_M2_cmpys_s1>;
2895 def HEXAGON_M2_cmpys_s0:
2896 di_MInst_sisi_sat <"cmpy", int_hexagon_M2_cmpys_s0>;
2897 def HEXAGON_M2_cmpysc_s1:
2898 di_MInst_sisi_s1_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s1>;
2899 def HEXAGON_M2_cmpysc_s0:
2900 di_MInst_sisi_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s0>;
2902 def HEXAGON_M2_cmacs_s1:
2903 di_MInst_disisi_acc_s1_sat <"cmpy", int_hexagon_M2_cmacs_s1>;
2904 def HEXAGON_M2_cmacs_s0:
2905 di_MInst_disisi_acc_sat <"cmpy", int_hexagon_M2_cmacs_s0>;
2906 def HEXAGON_M2_cmacsc_s1:
2907 di_MInst_disisi_acc_s1_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s1>;
2908 def HEXAGON_M2_cmacsc_s0:
2909 di_MInst_disisi_acc_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s0>;
2911 def HEXAGON_M2_cnacs_s1:
2912 di_MInst_disisi_nac_s1_sat <"cmpy", int_hexagon_M2_cnacs_s1>;
2913 def HEXAGON_M2_cnacs_s0:
2914 di_MInst_disisi_nac_sat <"cmpy", int_hexagon_M2_cnacs_s0>;
2915 def HEXAGON_M2_cnacsc_s1:
2916 di_MInst_disisi_nac_s1_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s1>;
2917 def HEXAGON_M2_cnacsc_s0:
2918 di_MInst_disisi_nac_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s0>;
2920 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2921 def HEXAGON_M2_cmpyr_s0:
2922 di_MInst_sisi <"cmpyr", int_hexagon_M2_cmpyr_s0>;
2923 def HEXAGON_M2_cmacr_s0:
2924 di_MInst_disisi_acc <"cmpyr", int_hexagon_M2_cmacr_s0>;
2926 def HEXAGON_M2_cmpyi_s0:
2927 di_MInst_sisi <"cmpyi", int_hexagon_M2_cmpyi_s0>;
2928 def HEXAGON_M2_cmaci_s0:
2929 di_MInst_disisi_acc <"cmpyi", int_hexagon_M2_cmaci_s0>;
2931 // MTYPE / COMPLEX / Complex multiply with round and pack.
2932 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2933 def HEXAGON_M2_cmpyrs_s0:
2934 si_MInst_sisi_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s0>;
2935 def HEXAGON_M2_cmpyrs_s1:
2936 si_MInst_sisi_s1_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s1>;
2938 def HEXAGON_M2_cmpyrsc_s0:
2939 si_MInst_sisi_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s0>;
2940 def HEXAGON_M2_cmpyrsc_s1:
2941 si_MInst_sisi_s1_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s1>;
2943 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2944 def HEXAGON_M2_vcmpy_s0_sat_i:
2945 di_MInst_didi_sat <"vcmpyi", int_hexagon_M2_vcmpy_s0_sat_i>;
2946 def HEXAGON_M2_vcmpy_s1_sat_i:
2947 di_MInst_didi_s1_sat <"vcmpyi", int_hexagon_M2_vcmpy_s1_sat_i>;
2949 def HEXAGON_M2_vcmpy_s0_sat_r:
2950 di_MInst_didi_sat <"vcmpyr", int_hexagon_M2_vcmpy_s0_sat_r>;
2951 def HEXAGON_M2_vcmpy_s1_sat_r:
2952 di_MInst_didi_s1_sat <"vcmpyr", int_hexagon_M2_vcmpy_s1_sat_r>;
2954 def HEXAGON_M2_vcmac_s0_sat_i:
2955 di_MInst_dididi_acc_sat <"vcmpyi", int_hexagon_M2_vcmac_s0_sat_i>;
2956 def HEXAGON_M2_vcmac_s0_sat_r:
2957 di_MInst_dididi_acc_sat <"vcmpyr", int_hexagon_M2_vcmac_s0_sat_r>;
2959 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2960 def HEXAGON_M2_vrcmpyi_s0:
2961 di_MInst_didi <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0>;
2962 def HEXAGON_M2_vrcmpyr_s0:
2963 di_MInst_didi <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0>;
2965 def HEXAGON_M2_vrcmpyi_s0c:
2966 di_MInst_didi_conj <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0c>;
2967 def HEXAGON_M2_vrcmpyr_s0c:
2968 di_MInst_didi_conj <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0c>;
2970 def HEXAGON_M2_vrcmaci_s0:
2971 di_MInst_dididi_acc <"vrcmpyi", int_hexagon_M2_vrcmaci_s0>;
2972 def HEXAGON_M2_vrcmacr_s0:
2973 di_MInst_dididi_acc <"vrcmpyr", int_hexagon_M2_vrcmacr_s0>;
2975 def HEXAGON_M2_vrcmaci_s0c:
2976 di_MInst_dididi_acc_conj <"vrcmpyi", int_hexagon_M2_vrcmaci_s0c>;
2977 def HEXAGON_M2_vrcmacr_s0c:
2978 di_MInst_dididi_acc_conj <"vrcmpyr", int_hexagon_M2_vrcmacr_s0c>;
2981 /********************************************************************
2983 *********************************************************************/
2985 // MTYPE / MPYH / Multiply word by half (32x16).
2986 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2987 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2988 def HEXAGON_M2_mmpyl_rs1:
2989 di_MInst_didi_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs1>;
2990 def HEXAGON_M2_mmpyl_s1:
2991 di_MInst_didi_s1_sat <"vmpyweh", int_hexagon_M2_mmpyl_s1>;
2992 def HEXAGON_M2_mmpyl_rs0:
2993 di_MInst_didi_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs0>;
2994 def HEXAGON_M2_mmpyl_s0:
2995 di_MInst_didi_sat <"vmpyweh", int_hexagon_M2_mmpyl_s0>;
2996 def HEXAGON_M2_mmpyh_rs1:
2997 di_MInst_didi_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs1>;
2998 def HEXAGON_M2_mmpyh_s1:
2999 di_MInst_didi_s1_sat <"vmpywoh", int_hexagon_M2_mmpyh_s1>;
3000 def HEXAGON_M2_mmpyh_rs0:
3001 di_MInst_didi_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs0>;
3002 def HEXAGON_M2_mmpyh_s0:
3003 di_MInst_didi_sat <"vmpywoh", int_hexagon_M2_mmpyh_s0>;
3004 def HEXAGON_M2_mmacls_rs1:
3005 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs1>;
3006 def HEXAGON_M2_mmacls_s1:
3007 di_MInst_dididi_acc_s1_sat <"vmpyweh", int_hexagon_M2_mmacls_s1>;
3008 def HEXAGON_M2_mmacls_rs0:
3009 di_MInst_dididi_acc_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs0>;
3010 def HEXAGON_M2_mmacls_s0:
3011 di_MInst_dididi_acc_sat <"vmpyweh", int_hexagon_M2_mmacls_s0>;
3012 def HEXAGON_M2_mmachs_rs1:
3013 di_MInst_dididi_acc_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs1>;
3014 def HEXAGON_M2_mmachs_s1:
3015 di_MInst_dididi_acc_s1_sat <"vmpywoh", int_hexagon_M2_mmachs_s1>;
3016 def HEXAGON_M2_mmachs_rs0:
3017 di_MInst_dididi_acc_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs0>;
3018 def HEXAGON_M2_mmachs_s0:
3019 di_MInst_dididi_acc_sat <"vmpywoh", int_hexagon_M2_mmachs_s0>;
3021 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
3022 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
3023 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
3024 def HEXAGON_M2_mmpyul_rs1:
3025 di_MInst_didi_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
3026 def HEXAGON_M2_mmpyul_s1:
3027 di_MInst_didi_s1_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
3028 def HEXAGON_M2_mmpyul_rs0:
3029 di_MInst_didi_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
3030 def HEXAGON_M2_mmpyul_s0:
3031 di_MInst_didi_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
3032 def HEXAGON_M2_mmpyuh_rs1:
3033 di_MInst_didi_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
3034 def HEXAGON_M2_mmpyuh_s1:
3035 di_MInst_didi_s1_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
3036 def HEXAGON_M2_mmpyuh_rs0:
3037 di_MInst_didi_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
3038 def HEXAGON_M2_mmpyuh_s0:
3039 di_MInst_didi_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
3040 def HEXAGON_M2_mmaculs_rs1:
3041 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
3042 def HEXAGON_M2_mmaculs_s1:
3043 di_MInst_dididi_acc_s1_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
3044 def HEXAGON_M2_mmaculs_rs0:
3045 di_MInst_dididi_acc_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
3046 def HEXAGON_M2_mmaculs_s0:
3047 di_MInst_dididi_acc_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
3048 def HEXAGON_M2_mmacuhs_rs1:
3049 di_MInst_dididi_acc_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
3050 def HEXAGON_M2_mmacuhs_s1:
3051 di_MInst_dididi_acc_s1_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
3052 def HEXAGON_M2_mmacuhs_rs0:
3053 di_MInst_dididi_acc_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
3054 def HEXAGON_M2_mmacuhs_s0:
3055 di_MInst_dididi_acc_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
3057 /********************************************************************
3059 *********************************************************************/
3061 // MTYPE / VB / Vector reduce add unsigned bytes.
3062 def HEXAGON_A2_vraddub:
3063 di_MInst_didi <"vraddub", int_hexagon_A2_vraddub>;
3064 def HEXAGON_A2_vraddub_acc:
3065 di_MInst_dididi_acc <"vraddub", int_hexagon_A2_vraddub_acc>;
3067 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
3068 def HEXAGON_A2_vrsadub:
3069 di_MInst_didi <"vrsadub", int_hexagon_A2_vrsadub>;
3070 def HEXAGON_A2_vrsadub_acc:
3071 di_MInst_dididi_acc <"vrsadub", int_hexagon_A2_vrsadub_acc>;
3073 /********************************************************************
3075 *********************************************************************/
3077 // MTYPE / VH / Vector dual multiply.
3078 def HEXAGON_M2_vdmpys_s1:
3079 di_MInst_didi_s1_sat <"vdmpy", int_hexagon_M2_vdmpys_s1>;
3080 def HEXAGON_M2_vdmpys_s0:
3081 di_MInst_didi_sat <"vdmpy", int_hexagon_M2_vdmpys_s0>;
3082 def HEXAGON_M2_vdmacs_s1:
3083 di_MInst_dididi_acc_s1_sat <"vdmpy", int_hexagon_M2_vdmacs_s1>;
3084 def HEXAGON_M2_vdmacs_s0:
3085 di_MInst_dididi_acc_sat <"vdmpy", int_hexagon_M2_vdmacs_s0>;
3087 // MTYPE / VH / Vector dual multiply with round and pack.
3088 def HEXAGON_M2_vdmpyrs_s0:
3089 si_MInst_didi_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s0>;
3090 def HEXAGON_M2_vdmpyrs_s1:
3091 si_MInst_didi_s1_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s1>;
3093 // MTYPE / VH / Vector multiply even halfwords.
3094 def HEXAGON_M2_vmpy2es_s1:
3095 di_MInst_didi_s1_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s1>;
3096 def HEXAGON_M2_vmpy2es_s0:
3097 di_MInst_didi_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s0>;
3098 def HEXAGON_M2_vmac2es:
3099 di_MInst_dididi_acc <"vmpyeh", int_hexagon_M2_vmac2es>;
3100 def HEXAGON_M2_vmac2es_s1:
3101 di_MInst_dididi_acc_s1_sat <"vmpyeh", int_hexagon_M2_vmac2es_s1>;
3102 def HEXAGON_M2_vmac2es_s0:
3103 di_MInst_dididi_acc_sat <"vmpyeh", int_hexagon_M2_vmac2es_s0>;
3105 // MTYPE / VH / Vector multiply halfwords.
3106 def HEXAGON_M2_vmpy2s_s0:
3107 di_MInst_sisi_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0>;
3108 def HEXAGON_M2_vmpy2s_s1:
3109 di_MInst_sisi_s1_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1>;
3110 def HEXAGON_M2_vmac2:
3111 di_MInst_disisi_acc <"vmpyh", int_hexagon_M2_vmac2>;
3112 def HEXAGON_M2_vmac2s_s0:
3113 di_MInst_disisi_acc_sat <"vmpyh", int_hexagon_M2_vmac2s_s0>;
3114 def HEXAGON_M2_vmac2s_s1:
3115 di_MInst_disisi_acc_s1_sat <"vmpyh", int_hexagon_M2_vmac2s_s1>;
3117 // MTYPE / VH / Vector multiply halfwords with round and pack.
3118 def HEXAGON_M2_vmpy2s_s0pack:
3119 si_MInst_sisi_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0pack>;
3120 def HEXAGON_M2_vmpy2s_s1pack:
3121 si_MInst_sisi_s1_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1pack>;
3123 // MTYPE / VH / Vector reduce multiply halfwords.
3124 // Rxx32+=vrmpyh(Rss32,Rtt32)
3125 def HEXAGON_M2_vrmpy_s0:
3126 di_MInst_didi <"vrmpyh", int_hexagon_M2_vrmpy_s0>;
3127 def HEXAGON_M2_vrmac_s0:
3128 di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>;
3130 /********************************************************************
3132 *********************************************************************/
3134 // STYPE / COMPLEX / Vector Complex conjugate.
3135 def HEXAGON_A2_vconj:
3136 di_SInst_di_sat <"vconj", int_hexagon_A2_vconj>;
3138 // STYPE / COMPLEX / Vector Complex rotate.
3139 def HEXAGON_S2_vcrotate:
3140 di_SInst_disi <"vcrotate",int_hexagon_S2_vcrotate>;
3143 /********************************************************************
3145 *********************************************************************/
3147 // STYPE / PERM / Vector align.
3148 // Need custom lowering
3149 def HEXAGON_S2_valignib:
3150 di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
3151 def HEXAGON_S2_valignrb:
3152 di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
3154 // STYPE / PERM / Vector round and pack.
3155 def HEXAGON_S2_vrndpackwh:
3156 si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
3157 def HEXAGON_S2_vrndpackwhs:
3158 si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
3160 // STYPE / PERM / Vector saturate and pack.
3161 def HEXAGON_S2_svsathb:
3162 si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
3163 def HEXAGON_S2_vsathb:
3164 si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
3165 def HEXAGON_S2_svsathub:
3166 si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
3167 def HEXAGON_S2_vsathub:
3168 si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
3169 def HEXAGON_S2_vsatwh:
3170 si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
3171 def HEXAGON_S2_vsatwuh:
3172 si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
3174 // STYPE / PERM / Vector saturate without pack.
3175 def HEXAGON_S2_vsathb_nopack:
3176 di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
3177 def HEXAGON_S2_vsathub_nopack:
3178 di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
3179 def HEXAGON_S2_vsatwh_nopack:
3180 di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
3181 def HEXAGON_S2_vsatwuh_nopack:
3182 di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3184 // STYPE / PERM / Vector shuffle.
3185 def HEXAGON_S2_shuffeb:
3186 di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
3187 def HEXAGON_S2_shuffeh:
3188 di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
3189 def HEXAGON_S2_shuffob:
3190 di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
3191 def HEXAGON_S2_shuffoh:
3192 di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
3194 // STYPE / PERM / Vector splat bytes.
3195 def HEXAGON_S2_vsplatrb:
3196 si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
3198 // STYPE / PERM / Vector splat halfwords.
3199 def HEXAGON_S2_vsplatrh:
3200 di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
3202 // STYPE / PERM / Vector splice.
3203 def Hexagon_S2_vsplicerb:
3204 di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
3205 def Hexagon_S2_vspliceib:
3206 di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
3208 // STYPE / PERM / Sign extend.
3209 def HEXAGON_S2_vsxtbh:
3210 di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
3211 def HEXAGON_S2_vsxthw:
3212 di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
3214 // STYPE / PERM / Truncate.
3215 def HEXAGON_S2_vtrunehb:
3216 si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
3217 def HEXAGON_S2_vtrunohb:
3218 si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
3219 def HEXAGON_S2_vtrunewh:
3220 di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
3221 def HEXAGON_S2_vtrunowh:
3222 di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
3224 // STYPE / PERM / Zero extend.
3225 def HEXAGON_S2_vzxtbh:
3226 di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
3227 def HEXAGON_S2_vzxthw:
3228 di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
3231 /********************************************************************
3233 *********************************************************************/
3235 // STYPE / PRED / Mask generate from predicate.
3236 def HEXAGON_C2_mask:
3237 di_SInst_qi <"mask", int_hexagon_C2_mask>;
3239 // STYPE / PRED / Predicate transfer.
3240 def HEXAGON_C2_tfrpr:
3241 si_SInst_qi <"", int_hexagon_C2_tfrpr>;
3242 def HEXAGON_C2_tfrrp:
3243 qi_SInst_si <"", int_hexagon_C2_tfrrp>;
3245 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3246 def HEXAGON_C2_vitpack:
3247 si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
3250 /********************************************************************
3252 *********************************************************************/
3254 // STYPE / VH / Vector absolute value halfwords.
3255 // Rdd64=vabsh(Rss64)
3256 def HEXAGON_A2_vabsh:
3257 di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
3258 def HEXAGON_A2_vabshsat:
3259 di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
3261 // STYPE / VH / Vector shift halfwords by immediate.
3262 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3263 def HEXAGON_S2_asl_i_vh:
3264 di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
3265 def HEXAGON_S2_asr_i_vh:
3266 di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
3267 def HEXAGON_S2_lsr_i_vh:
3268 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
3270 // STYPE / VH / Vector shift halfwords by register.
3271 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3272 def HEXAGON_S2_asl_r_vh:
3273 di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
3274 def HEXAGON_S2_asr_r_vh:
3275 di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
3276 def HEXAGON_S2_lsl_r_vh:
3277 di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
3278 def HEXAGON_S2_lsr_r_vh:
3279 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
3282 /********************************************************************
3284 *********************************************************************/
3286 // STYPE / VW / Vector absolute value words.
3287 def HEXAGON_A2_vabsw:
3288 di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
3289 def HEXAGON_A2_vabswsat:
3290 di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
3292 // STYPE / VW / Vector shift words by immediate.
3293 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3294 def HEXAGON_S2_asl_i_vw:
3295 di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
3296 def HEXAGON_S2_asr_i_vw:
3297 di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
3298 def HEXAGON_S2_lsr_i_vw:
3299 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
3301 // STYPE / VW / Vector shift words by register.
3302 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3303 def HEXAGON_S2_asl_r_vw:
3304 di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
3305 def HEXAGON_S2_asr_r_vw:
3306 di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
3307 def HEXAGON_S2_lsl_r_vw:
3308 di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
3309 def HEXAGON_S2_lsr_r_vw:
3310 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
3312 // STYPE / VW / Vector shift words with truncate and pack.
3313 def HEXAGON_S2_asr_r_svw_trun:
3314 si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
3315 def HEXAGON_S2_asr_i_svw_trun:
3316 si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
3318 // LD / Circular loads.
3319 def HEXAGON_circ_ldd:
3320 di_LDInstPI_diu4 <"circ_ldd", int_hexagon_circ_ldd>;
3322 include "HexagonIntrinsicsV3.td"
3323 include "HexagonIntrinsicsV4.td"
3324 include "HexagonIntrinsicsV5.td"