1 //=- HexagonIntrinsicsV3.td - Target Description for Hexagon -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 Compiler Intrinsics in TableGen format.
12 //===----------------------------------------------------------------------===//
17 // MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
18 def Hexagon_M2_vrcmpys_s1:
19 di_MInst_disi_s1_sat <"vrcmpys", int_hexagon_M2_vrcmpys_s1>;
20 def Hexagon_M2_vrcmpys_acc_s1:
21 di_MInst_didisi_acc_s1_sat <"vrcmpys", int_hexagon_M2_vrcmpys_acc_s1>;
22 def Hexagon_M2_vrcmpys_s1rp:
23 si_MInst_disi_s1_rnd_sat <"vrcmpys", int_hexagon_M2_vrcmpys_s1rp>;
28 /********************************************************************
30 *********************************************************************/
32 // MTYPE / VB / Vector reduce add unsigned bytes.
33 def Hexagon_M2_vradduh:
34 si_MInst_didi <"vradduh", int_hexagon_M2_vradduh>;
37 /********************************************************************
39 *********************************************************************/
43 di_ALU64_sidi <"add", int_hexagon_A2_addsp>;
44 def Hexagon_A2_addpsat:
45 di_ALU64_didi <"add", int_hexagon_A2_addpsat>;
48 di_ALU64_didi <"max", int_hexagon_A2_maxp>;
50 di_ALU64_didi <"maxu", int_hexagon_A2_maxup>;