lib/Target/Hexagon/HexagonIntrinsicsV4.td

   1 //===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V4 Architecture Extensions
  11 // Application-Level Specification
  12 // 80-V9418-12 Rev. A
  13 // June 15, 2010
  14
  15 // Polynomial multiply words
  16 // Rdd=pmpyw(Rs,Rt)
  17 def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
  18 // Rxx^=pmpyw(Rs,Rt)
  19 def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
  20
  21 //Rxx^=asr(Rss,Rt)
  22 def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
  23 //Rxx^=asl(Rss,Rt)
  24 def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
  25 //Rxx^=lsr(Rss,Rt)
  26 def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
  27 //Rxx^=lsl(Rss,Rt)
  28 def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
  29
  30 // Multiply and use upper result
  31 def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
  32 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
  33 def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
  34 def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
  35 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
  36
  37 def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
  38
  39 def: T_P_pat  <S2_ct0p,      int_hexagon_S2_ct0p>;
  40 def: T_P_pat  <S2_ct1p,      int_hexagon_S2_ct1p>;
  41 def: T_RR_pat<C4_nbitsset,  int_hexagon_C4_nbitsset>;
  42 def: T_RR_pat<C4_nbitsclr,  int_hexagon_C4_nbitsclr>;
  43 def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
  44
  45 def : T_RP_pat <A4_boundscheck, int_hexagon_A4_boundscheck>;
  46
  47 def : T_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
  48
  49 def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
  50                                       IntRegs:$src3),
  51            (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
  52
  53 def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
  54 def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
  55 def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
  56 def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
  57 // Multiply 32x32 and use upper result
  58 def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
  59 def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
  60
  61 def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
  62 def : T_PP_pat<A4_ornp,  int_hexagon_A4_ornp>;
  63
  64 // Extract bitfield
  65 def : T_PP_pat  <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
  66 def : T_RP_pat  <S4_extract_rp, int_hexagon_S4_extract_rp>;
  67 def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
  68 def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
  69
  70 // Shift an immediate left by register amount
  71 def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
  72
  73 // Logical xor with xor accumulation
  74 def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
  75
  76 // Shift and add/sub/and/or
  77 def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
  78 def : T_IRI_pat <S4_ori_asl_ri,  int_hexagon_S4_ori_asl_ri>;
  79 def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
  80 def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
  81 def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
  82 def : T_IRI_pat <S4_ori_lsr_ri,  int_hexagon_S4_ori_lsr_ri>;
  83 def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
  84 def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
  85
  86 // Split bitfield
  87 def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
  88 def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
  89
  90 def: T_RR_pat<S4_parity,   int_hexagon_S4_parity>;
  91
  92 def: T_RI_pat<S4_ntstbit_i,  int_hexagon_S4_ntstbit_i>;
  93 def: T_RR_pat<S4_ntstbit_r,  int_hexagon_S4_ntstbit_r>;
  94
  95 def: T_RI_pat<S4_clbaddi,  int_hexagon_S4_clbaddi>;
  96 def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
  97 def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
  98
  99 /********************************************************************
 100 *            ALU32/ALU                                              *
 101 *********************************************************************/
 102
 103 // ALU32 / ALU / Logical Operations.
 104 def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
 105 def: T_RR_pat<A4_orn,  int_hexagon_A4_orn>;
 106
 107 /********************************************************************
 108 *            ALU32/PERM                                             *
 109 *********************************************************************/
 110
 111 // Combine Words Into Doublewords.
 112 def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
 113 def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
 114
 115 /********************************************************************
 116 *            ALU32/PRED                                             *
 117 *********************************************************************/
 118
 119 def: T_RR_pat<A4_rcmpeq,  int_hexagon_A4_rcmpeq>;
 120 def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
 121
 122 def: T_RI_pat<A4_rcmpeqi,  int_hexagon_A4_rcmpeqi>;
 123 def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
 124
 125 /********************************************************************
 126 *            XTYPE/ALU                                              *
 127 *********************************************************************/
 128
 129 // Add And Accumulate.
 130
 131 def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
 132 def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
 133
 134
 135 // XTYPE / ALU / Logical-logical Words.
 136 def : T_RRR_pat <M4_or_xor,   int_hexagon_M4_or_xor>;
 137 def : T_RRR_pat <M4_and_xor,  int_hexagon_M4_and_xor>;
 138 def : T_RRR_pat <M4_or_and,   int_hexagon_M4_or_and>;
 139 def : T_RRR_pat <M4_and_and,  int_hexagon_M4_and_and>;
 140 def : T_RRR_pat <M4_xor_and,  int_hexagon_M4_xor_and>;
 141 def : T_RRR_pat <M4_or_or,    int_hexagon_M4_or_or>;
 142 def : T_RRR_pat <M4_and_or,   int_hexagon_M4_and_or>;
 143 def : T_RRR_pat <M4_xor_or,   int_hexagon_M4_xor_or>;
 144 def : T_RRR_pat <M4_or_andn,  int_hexagon_M4_or_andn>;
 145 def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
 146 def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
 147
 148 def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
 149 def : T_RRI_pat <S4_or_andix,  int_hexagon_S4_or_andix>;
 150 def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
 151
 152 // Modulo wrap.
 153 def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
 154
 155 // Arithmetic/Convergent round
 156 // Rd=[cround|round](Rs,Rt)[:sat]
 157 // Rd=[cround|round](Rs,#u5)[:sat]
 158 def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
 159 def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
 160
 161 def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
 162 def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
 163
 164 def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
 165 def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
 166
 167 def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
 168
 169 class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
 170   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 171              !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
 172              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 173
 174 class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
 175   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 176              !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
 177              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 178
 179 class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
 180   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 181              !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
 182              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 183
 184 //
 185 // SInst Classes.
 186 //
 187 class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
 188   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 189              !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
 190              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 191
 192 class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
 193   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 194                                      IntRegs:$src3),
 195              !strconcat("$dst = ", !strconcat(opc ,
 196                                               "($src1, and($src2, !$src3)")),
 197              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 198                                          IntRegs:$src3))]>;
 199
 200 class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
 201   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 202                                      IntRegs:$src3),
 203              !strconcat("$dst = ", !strconcat(opc ,
 204                                               "($src1, and($src2, $src3)")),
 205              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 206                                          IntRegs:$src3))]>;
 207
 208 class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
 209   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 210                                      IntRegs:$src3),
 211              !strconcat("$dst = ", !strconcat(opc ,
 212                                               "($src1, or($src2, !$src3)")),
 213              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 214                                          IntRegs:$src3))]>;
 215
 216 class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
 217   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 218                                      IntRegs:$src3),
 219              !strconcat("$dst = ", !strconcat(opc ,
 220                                               "($src1, or($src2, $src3)")),
 221              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 222                                          IntRegs:$src3))]>;
 223
 224 /********************************************************************
 225 *            ALU32/PRED                                             *
 226 *********************************************************************/
 227
 228 // ALU32 / PRED / Conditional Shift Halfword.
 229 // ALU32 / PRED / Conditional Sign Extend.
 230 // ALU32 / PRED / Conditional Zero Extend.
 231 // ALU32 / PRED / Compare.
 232 def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
 233 def Hexagon_C4_cmplte  : qi_neg_ALU32_sisi  <"cmp.gt", int_hexagon_C4_cmplte>;
 234 def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi  <"cmp.gtu",int_hexagon_C4_cmplteu>;
 235
 236 def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
 237 def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
 238 def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
 239
 240
 241 /********************************************************************
 242 *            CR                                                     *
 243 *********************************************************************/
 244
 245 // CR / Corner Detection Acceleration.
 246 def Hexagon_C4_fastcorner9:
 247   qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
 248 def Hexagon_C4_fastcorner9_not:
 249   qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
 250
 251 // CR / Logical Operations On Predicates.
 252 def Hexagon_C4_and_andn:
 253   qi_SInst_qi_andqiqi_neg         <"and",      int_hexagon_C4_and_andn>;
 254 def Hexagon_C4_and_and:
 255   qi_SInst_qi_andqiqi             <"and",      int_hexagon_C4_and_and>;
 256 def Hexagon_C4_and_orn:
 257   qi_SInst_qi_orqiqi_neg          <"and",      int_hexagon_C4_and_orn>;
 258 def Hexagon_C4_and_or:
 259   qi_SInst_qi_orqiqi              <"and",      int_hexagon_C4_and_or>;
 260 def Hexagon_C4_or_andn:
 261   qi_SInst_qi_andqiqi_neg         <"or",       int_hexagon_C4_or_andn>;
 262 def Hexagon_C4_or_and:
 263   qi_SInst_qi_andqiqi             <"or",       int_hexagon_C4_or_and>;
 264 def Hexagon_C4_or_orn:
 265   qi_SInst_qi_orqiqi_neg          <"or",       int_hexagon_C4_or_orn>;
 266 def Hexagon_C4_or_or:
 267   qi_SInst_qi_orqiqi              <"or",       int_hexagon_C4_or_or>;