lib/Target/Hexagon/HexagonIntrinsicsV4.td

   1 //===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V4 Architecture Extensions
  11 // Application-Level Specification
  12 // 80-V9418-12 Rev. A
  13 // June 15, 2010
  14
  15 // Polynomial multiply words
  16 // Rdd=pmpyw(Rs,Rt)
  17 def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
  18 // Rxx^=pmpyw(Rs,Rt)
  19 def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
  20
  21 //Rxx^=asr(Rss,Rt)
  22 def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
  23 //Rxx^=asl(Rss,Rt)
  24 def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
  25 //Rxx^=lsr(Rss,Rt)
  26 def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
  27 //Rxx^=lsl(Rss,Rt)
  28 def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
  29
  30 // Multiply and use upper result
  31 def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
  32 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
  33 def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
  34 def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
  35 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
  36
  37 def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
  38
  39 def: T_P_pat  <S2_ct0p,      int_hexagon_S2_ct0p>;
  40 def: T_P_pat  <S2_ct1p,      int_hexagon_S2_ct1p>;
  41 def: T_RR_pat<C4_nbitsset,  int_hexagon_C4_nbitsset>;
  42 def: T_RR_pat<C4_nbitsclr,  int_hexagon_C4_nbitsclr>;
  43 def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
  44
  45 def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
  46                                       IntRegs:$src3),
  47            (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
  48
  49 def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
  50 def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
  51 def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
  52 def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
  53 // Multiply 32x32 and use upper result
  54 def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
  55 def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
  56
  57 // Extract bitfield
  58 def : T_PP_pat  <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
  59 def : T_RP_pat  <S4_extract_rp, int_hexagon_S4_extract_rp>;
  60 def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
  61 def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
  62
  63 // Shift an immediate left by register amount
  64 def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
  65
  66 // Shift and add/sub/and/or
  67 def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
  68 def : T_IRI_pat <S4_ori_asl_ri,  int_hexagon_S4_ori_asl_ri>;
  69 def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
  70 def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
  71 def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
  72 def : T_IRI_pat <S4_ori_lsr_ri,  int_hexagon_S4_ori_lsr_ri>;
  73 def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
  74 def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
  75
  76 // Split bitfield
  77 def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
  78 def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
  79
  80 def: T_RR_pat<S4_parity,   int_hexagon_S4_parity>;
  81
  82 def: T_RI_pat<S4_ntstbit_i,  int_hexagon_S4_ntstbit_i>;
  83 def: T_RR_pat<S4_ntstbit_r,  int_hexagon_S4_ntstbit_r>;
  84
  85 def: T_RI_pat<S4_clbaddi,  int_hexagon_S4_clbaddi>;
  86 def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
  87 def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
  88
  89 //
  90 // ALU 32 types.
  91 //
  92
  93 class si_ALU32_sisi_not<string opc, Intrinsic IntID>
  94   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
  95              !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
  96              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
  97
  98 class di_ALU32_s8si<string opc, Intrinsic IntID>
  99   : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
 100              !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
 101              [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
 102
 103 class di_ALU32_sis8<string opc, Intrinsic IntID>
 104   : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 105              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 106              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 107
 108 class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
 109   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 110              !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
 111              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 112
 113 class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
 114   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 115              !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
 116              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 117
 118 class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
 119   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 120              !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
 121              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 122
 123 class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
 124   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 125              !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
 126              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 127
 128 class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
 129   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 130              !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
 131              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 132
 133 class si_ALU32_sis8<string opc, Intrinsic IntID>
 134   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 135              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 136              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 137
 138
 139 //
 140 // SInst Classes.
 141 //
 142 class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
 143   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 144              !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
 145              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 146
 147 class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
 148   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 149                                      IntRegs:$src3),
 150              !strconcat("$dst = ", !strconcat(opc ,
 151                                               "($src1, and($src2, !$src3)")),
 152              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 153                                          IntRegs:$src3))]>;
 154
 155 class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
 156   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 157                                      IntRegs:$src3),
 158              !strconcat("$dst = ", !strconcat(opc ,
 159                                               "($src1, and($src2, $src3)")),
 160              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 161                                          IntRegs:$src3))]>;
 162
 163 class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
 164   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 165                                      IntRegs:$src3),
 166              !strconcat("$dst = ", !strconcat(opc ,
 167                                               "($src1, or($src2, !$src3)")),
 168              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 169                                          IntRegs:$src3))]>;
 170
 171 class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
 172   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 173                                      IntRegs:$src3),
 174              !strconcat("$dst = ", !strconcat(opc ,
 175                                               "($src1, or($src2, $src3)")),
 176              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 177                                          IntRegs:$src3))]>;
 178
 179 class si_SInst_si_addsis6<string opc, Intrinsic IntID>
 180   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
 181              !strconcat("$dst = ", !strconcat(opc ,
 182                                               "($src1, add($src2, #$src3)")),
 183              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 184                                         imm:$src3))]>;
 185
 186 class si_SInst_si_subs6si<string opc, Intrinsic IntID>
 187   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
 188              !strconcat("$dst = ", !strconcat(opc ,
 189                                               "($src1, sub(#$src2, $src3)")),
 190              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
 191                                         IntRegs:$src3))]>;
 192
 193 class di_ALU64_didi_neg<string opc, Intrinsic IntID>
 194   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 195           !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
 196           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 197
 198 class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
 199   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 200                                            DoubleRegs:$src2),
 201                !strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")),
 202                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 203                                              DoubleRegs:$src2))],
 204                "$dst2 = $dst">;
 205
 206 class si_MInst_sisisi_and<string opc, Intrinsic IntID>
 207   : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
 208                                     IntRegs:$src3),
 209              !strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")),
 210              [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
 211                                         IntRegs:$src3))]>;
 212
 213 class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
 214   : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
 215                                     IntRegs:$src3),
 216              !strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")),
 217              [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
 218                                         IntRegs:$src3))]>;
 219
 220 class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
 221   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3),
 222              !strconcat("$dst = ", !strconcat(opc ,
 223                                               "($src1, and($src2, #$src3))")),
 224              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 225                                         imm:$src3))]>;
 226
 227 class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
 228   : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
 229                                     IntRegs:$src3),
 230              !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
 231              [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
 232                                         IntRegs:$src3))]>;
 233
 234 class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
 235   : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
 236                                     IntRegs:$src3),
 237              !strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")),
 238              [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
 239                                         IntRegs:$src3))]>;
 240
 241 class si_SInst_sisis10_or<string opc, Intrinsic IntID>
 242   : SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3),
 243              !strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")),
 244              [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
 245                                         imm:$src3))]>;
 246
 247 class si_MInst_sisisi_or<string opc, Intrinsic IntID>
 248   : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
 249                                     IntRegs:$src3),
 250              !strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")),
 251              [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
 252                                         IntRegs:$src3))]>;
 253
 254 class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
 255   : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
 256                                     IntRegs:$src3),
 257              !strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")),
 258              [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
 259                                         IntRegs:$src3))]>;
 260
 261 class si_SInst_siu5_sat<string opc, Intrinsic IntID>
 262   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 263           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")),
 264           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 265
 266
 267 /********************************************************************
 268 *            ALU32/ALU                                              *
 269 *********************************************************************/
 270
 271 // ALU32 / ALU / Logical Operations.
 272 def Hexagon_A4_orn  : si_ALU32_sisi_not <"or",  int_hexagon_A4_orn>;
 273 def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>;
 274
 275
 276 /********************************************************************
 277 *            ALU32/PERM                                             *
 278 *********************************************************************/
 279
 280 // ALU32 / PERM / Combine Words Into Doublewords.
 281 def Hexagon_A4_combineir : di_ALU32_s8si  <"combine", int_hexagon_A4_combineir>;
 282 def Hexagon_A4_combineri : di_ALU32_sis8  <"combine", int_hexagon_A4_combineri>;
 283
 284
 285 /********************************************************************
 286 *            ALU32/PRED                                             *
 287 *********************************************************************/
 288
 289 // ALU32 / PRED / Conditional Shift Halfword.
 290 // ALU32 / PRED / Conditional Sign Extend.
 291 // ALU32 / PRED / Conditional Zero Extend.
 292 // ALU32 / PRED / Compare.
 293 def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
 294 def Hexagon_C4_cmplte  : qi_neg_ALU32_sisi  <"cmp.gt", int_hexagon_C4_cmplte>;
 295 def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi  <"cmp.gtu",int_hexagon_C4_cmplteu>;
 296
 297 def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
 298 def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
 299 def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
 300
 301 // ALU32 / PRED / cmpare To General Register.
 302 def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>;
 303 def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>;
 304 def Hexagon_A4_rcmpeq  : si_ALU32_sisi     <"cmp.eq", int_hexagon_A4_rcmpeq>;
 305 def Hexagon_A4_rcmpeqi : si_ALU32_sis8     <"cmp.eq", int_hexagon_A4_rcmpeqi>;
 306
 307
 308 /********************************************************************
 309 *            CR                                                     *
 310 *********************************************************************/
 311
 312 // CR / Corner Detection Acceleration.
 313 def Hexagon_C4_fastcorner9:
 314   qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
 315 def Hexagon_C4_fastcorner9_not:
 316   qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
 317
 318 // CR / Logical Operations On Predicates.
 319 def Hexagon_C4_and_andn:
 320   qi_SInst_qi_andqiqi_neg         <"and",      int_hexagon_C4_and_andn>;
 321 def Hexagon_C4_and_and:
 322   qi_SInst_qi_andqiqi             <"and",      int_hexagon_C4_and_and>;
 323 def Hexagon_C4_and_orn:
 324   qi_SInst_qi_orqiqi_neg          <"and",      int_hexagon_C4_and_orn>;
 325 def Hexagon_C4_and_or:
 326   qi_SInst_qi_orqiqi              <"and",      int_hexagon_C4_and_or>;
 327 def Hexagon_C4_or_andn:
 328   qi_SInst_qi_andqiqi_neg         <"or",       int_hexagon_C4_or_andn>;
 329 def Hexagon_C4_or_and:
 330   qi_SInst_qi_andqiqi             <"or",       int_hexagon_C4_or_and>;
 331 def Hexagon_C4_or_orn:
 332   qi_SInst_qi_orqiqi_neg          <"or",       int_hexagon_C4_or_orn>;
 333 def Hexagon_C4_or_or:
 334   qi_SInst_qi_orqiqi              <"or",       int_hexagon_C4_or_or>;
 335
 336
 337 /********************************************************************
 338 *            XTYPE/ALU                                              *
 339 *********************************************************************/
 340
 341 // XTYPE / ALU / Add And Accumulate.
 342 def Hexagon_S4_addaddi:
 343   si_SInst_si_addsis6             <"add",      int_hexagon_S4_addaddi>;
 344 def Hexagon_S4_subaddi:
 345   si_SInst_si_subs6si             <"add",      int_hexagon_S4_subaddi>;
 346
 347 // XTYPE / ALU / Logical Doublewords.
 348 def Hexagon_S4_andnp:
 349   di_ALU64_didi_neg               <"and",      int_hexagon_A4_andnp>;
 350 def Hexagon_S4_ornp:
 351   di_ALU64_didi_neg               <"or",       int_hexagon_A4_ornp>;
 352
 353 // XTYPE / ALU / Logical-logical Doublewords.
 354 def Hexagon_M4_xor_xacc:
 355   di_MInst_dididi_xacc            <"xor",      int_hexagon_M4_xor_xacc>;
 356
 357 // XTYPE / ALU / Logical-logical Words.
 358 def HEXAGON_M4_and_and:
 359   si_MInst_sisisi_and             <"and",      int_hexagon_M4_and_and>;
 360 def HEXAGON_M4_and_or:
 361   si_MInst_sisisi_and             <"or",       int_hexagon_M4_and_or>;
 362 def HEXAGON_M4_and_xor:
 363   si_MInst_sisisi_and             <"xor",      int_hexagon_M4_and_xor>;
 364 def HEXAGON_M4_and_andn:
 365   si_MInst_sisisi_andn            <"and",      int_hexagon_M4_and_andn>;
 366 def HEXAGON_M4_xor_and:
 367   si_MInst_sisisi_xor             <"and",      int_hexagon_M4_xor_and>;
 368 def HEXAGON_M4_xor_or:
 369   si_MInst_sisisi_xor             <"or",       int_hexagon_M4_xor_or>;
 370 def HEXAGON_M4_xor_andn:
 371   si_MInst_sisisi_xorn            <"and",      int_hexagon_M4_xor_andn>;
 372 def HEXAGON_M4_or_and:
 373   si_MInst_sisisi_or              <"and",      int_hexagon_M4_or_and>;
 374 def HEXAGON_M4_or_or:
 375   si_MInst_sisisi_or              <"or",       int_hexagon_M4_or_or>;
 376 def HEXAGON_M4_or_xor:
 377   si_MInst_sisisi_or              <"xor",      int_hexagon_M4_or_xor>;
 378 def HEXAGON_M4_or_andn:
 379   si_MInst_sisisi_orn             <"and",      int_hexagon_M4_or_andn>;
 380 def HEXAGON_S4_or_andix:
 381   si_SInst_sisis10_andi           <"or",       int_hexagon_S4_or_andix>;
 382 def HEXAGON_S4_or_andi:
 383   si_SInst_sisis10_or             <"and",      int_hexagon_S4_or_andi>;
 384 def HEXAGON_S4_or_ori:
 385   si_SInst_sisis10_or             <"or",       int_hexagon_S4_or_ori>;
 386
 387 // XTYPE / ALU / Modulo wrap.
 388 def HEXAGON_A4_modwrapu:
 389   si_ALU64_sisi                   <"modwrap",  int_hexagon_A4_modwrapu>;
 390
 391 // XTYPE / ALU / Round.
 392 def HEXAGON_A4_cround_ri:
 393   si_SInst_siu5                   <"cround",   int_hexagon_A4_cround_ri>;
 394 def HEXAGON_A4_cround_rr:
 395   si_SInst_sisi                   <"cround",   int_hexagon_A4_cround_rr>;
 396 def HEXAGON_A4_round_ri:
 397   si_SInst_siu5                   <"round",    int_hexagon_A4_round_ri>;
 398 def HEXAGON_A4_round_rr:
 399   si_SInst_sisi                   <"round",    int_hexagon_A4_round_rr>;
 400 def HEXAGON_A4_round_ri_sat:
 401   si_SInst_siu5_sat               <"round",    int_hexagon_A4_round_ri_sat>;
 402 def HEXAGON_A4_round_rr_sat:
 403   si_SInst_sisi_sat               <"round",    int_hexagon_A4_round_rr_sat>;
 404
 405 // XTYPE / ALU / Vector reduce add unsigned halfwords.
 406 // XTYPE / ALU / Vector add bytes.
 407 // XTYPE / ALU / Vector conditional negate.
 408 // XTYPE / ALU / Vector maximum bytes.
 409 // XTYPE / ALU / Vector reduce maximum halfwords.
 410 // XTYPE / ALU / Vector reduce maximum words.
 411 // XTYPE / ALU / Vector minimum bytes.
 412 // XTYPE / ALU / Vector reduce minimum halfwords.
 413 // XTYPE / ALU / Vector reduce minimum words.
 414 // XTYPE / ALU / Vector subtract bytes.
 415
 416
 417 /********************************************************************
 418 *            XTYPE/BIT                                              *
 419 *********************************************************************/
 420
 421 // XTYPE / BIT / Count leading.
 422 // XTYPE / BIT / Count trailing.
 423 // XTYPE / BIT / Extract bitfield.
 424 // XTYPE / BIT / Masked parity.
 425 // XTYPE / BIT / Bit reverse.
 426 // XTYPE / BIT / Split bitfield.
 427
 428
 429 /********************************************************************
 430 *            XTYPE/COMPLEX                                          *
 431 *********************************************************************/
 432
 433 // XTYPE / COMPLEX / Complex add/sub halfwords.
 434 // XTYPE / COMPLEX / Complex add/sub words.
 435 // XTYPE / COMPLEX / Complex multiply 32x16.
 436 // XTYPE / COMPLEX / Vector reduce complex rotate.
 437
 438
 439 /********************************************************************
 440 *            XTYPE/MPY                                              *
 441 *********************************************************************/
 442
 443 // XTYPE / COMPLEX / Complex add/sub halfwords.