1 //=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V60 Compiler Intrinsics in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let isCodeGenOnly = 1 in {
15 def HEXAGON_V6_vd0_pseudo : CVI_VA_Resource<(outs VectorRegs:$dst),
18 [(set VectorRegs:$dst, (int_hexagon_V6_vd0 ))]>;
20 def HEXAGON_V6_vd0_pseudo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst),
23 [(set VectorRegs128B:$dst, (int_hexagon_V6_vd0_128B ))]>;
26 def HEXAGON_V6_vassignp : CVI_VA_Resource<(outs VecDblRegs:$dst),
27 (ins VecDblRegs:$src1),
28 "$dst=vassignp_W($src1)",
29 [(set VecDblRegs:$dst, (int_hexagon_V6_vassignp VecDblRegs:$src1))]>;
32 def HEXAGON_V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst),
33 (ins VecDblRegs128B:$src1),
34 "$dst=vassignp_W_128B($src1)",
35 [(set VecDblRegs128B:$dst, (int_hexagon_V6_vassignp_128B
36 VecDblRegs128B:$src1))]>;
39 def HEXAGON_V6_lo : CVI_VA_Resource<(outs VectorRegs:$dst),
40 (ins VecDblRegs:$src1),
42 [(set VectorRegs:$dst, (int_hexagon_V6_lo VecDblRegs:$src1))]>;
45 def HEXAGON_V6_hi : CVI_VA_Resource<(outs VectorRegs:$dst),
46 (ins VecDblRegs:$src1),
48 [(set VectorRegs:$dst, (int_hexagon_V6_hi VecDblRegs:$src1))]>;
51 def HEXAGON_V6_lo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst),
52 (ins VecDblRegs128B:$src1),
54 [(set VectorRegs128B:$dst, (int_hexagon_V6_lo_128B VecDblRegs128B:$src1))]>;
57 def HEXAGON_V6_hi_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst),
58 (ins VecDblRegs128B:$src1),
60 [(set VectorRegs128B:$dst, (int_hexagon_V6_hi_128B VecDblRegs128B:$src1))]>;
62 let AddedComplexity = 100 in {
63 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
64 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
65 Requires<[UseHVXSgl]>;
67 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
68 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
69 Requires<[UseHVXSgl]>;
71 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
72 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
74 Requires<[UseHVXDbl]>;
76 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
77 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
79 Requires<[UseHVXDbl]>;
82 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
83 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
84 (A2_tfrsi 0x01010101)))>,
85 Requires<[UseHVXSgl]>;
87 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
88 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
89 (A2_tfrsi 0x01010101)))>,
90 Requires<[UseHVXSgl]>;
92 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
93 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
94 (A2_tfrsi 0x01010101)))>,
95 Requires<[UseHVXSgl]>;
97 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
98 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
99 (A2_tfrsi 0x01010101)))>,
100 Requires<[UseHVXSgl]>;
102 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
103 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
104 (A2_tfrsi 0x01010101)))>,
105 Requires<[UseHVXSgl]>;
107 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
108 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),
109 (A2_tfrsi 0x01010101)))>,
110 Requires<[UseHVXSgl]>;
112 def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))),
113 (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1),
114 (A2_tfrsi 0x01010101)))>,
115 Requires<[UseHVXSgl]>;
117 def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))),
118 (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1),
119 (A2_tfrsi 0x01010101)))>,
120 Requires<[UseHVXSgl]>;
122 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
123 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
124 (A2_tfrsi 0x01010101)))>,
125 Requires<[UseHVXDbl]>;
127 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
128 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
129 (A2_tfrsi 0x01010101)))>,
130 Requires<[UseHVXDbl]>;
132 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
133 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
134 (A2_tfrsi 0x01010101)))>,
135 Requires<[UseHVXDbl]>;
137 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
138 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
139 (A2_tfrsi 0x01010101)))>,
140 Requires<[UseHVXDbl]>;
142 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
143 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
144 (A2_tfrsi 0x01010101)))>,
145 Requires<[UseHVXDbl]>;
147 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
148 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
149 (A2_tfrsi 0x01010101)))>,
150 Requires<[UseHVXDbl]>;
152 def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
153 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
154 (A2_tfrsi 0x01010101)))>,
155 Requires<[UseHVXDbl]>;
157 def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
158 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
159 (A2_tfrsi 0x01010101)))>,
160 Requires<[UseHVXDbl]>;
162 let AddedComplexity = 140 in {
163 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
164 (V6_vS32b_ai IntRegs:$addr, 0,
165 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
166 (A2_tfrsi 0x01010101))))>,
167 Requires<[UseHVXSgl]>;
169 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
171 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
172 Requires<[UseHVXSgl]>;
174 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
175 (V6_vS32b_ai_128B IntRegs:$addr, 0,
176 (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1),
177 (A2_tfrsi 0x01010101))))>,
178 Requires<[UseHVXDbl]>;
180 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
181 (v1024i1 (V6_vandvrt_128B
182 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
183 (A2_tfrsi 0x01010101)))>,
184 Requires<[UseHVXDbl]>;
187 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
188 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
189 Requires<[UseHVXSgl]>;
190 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
191 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
192 Requires<[UseHVXDbl]>;
195 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
196 def: Pat<(IntID VectorRegs:$src1),
197 (MI VectorRegs:$src1)>,
198 Requires<[UseHVXSgl]>;
200 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1),
201 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1)>,
202 Requires<[UseHVXDbl]>;
205 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
206 def: Pat<(IntID VecPredRegs:$src1),
207 (MI VecPredRegs:$src1)>,
208 Requires<[UseHVXSgl]>;
210 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1),
211 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1)>,
212 Requires<[UseHVXDbl]>;
215 multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> {
216 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
217 (MI VecDblRegs:$src1, IntRegs:$src2)>,
218 Requires<[UseHVXSgl]>;
220 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
221 (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>,
222 Requires<[UseHVXDbl]>;
225 multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> {
226 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
227 (MI VectorRegs:$src1, IntRegs:$src2)>,
228 Requires<[UseHVXSgl]>;
230 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
231 (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>,
232 Requires<[UseHVXDbl]>;
235 multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> {
236 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2),
237 (MI VecDblRegs:$src1, VectorRegs:$src2)>,
238 Requires<[UseHVXSgl]>;
240 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
241 VectorRegs128B:$src2),
242 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
243 VectorRegs128B:$src2)>,
244 Requires<[UseHVXDbl]>;
247 multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> {
248 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
249 (MI VecDblRegs:$src1, VecDblRegs:$src2)>,
250 Requires<[UseHVXSgl]>;
252 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
253 VecDblRegs128B:$src2),
254 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
255 VecDblRegs128B:$src2)>,
256 Requires<[UseHVXDbl]>;
259 multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> {
260 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
261 (MI VectorRegs:$src1, VectorRegs:$src2)>,
262 Requires<[UseHVXSgl]>;
264 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
265 VectorRegs128B:$src2),
266 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
267 VectorRegs128B:$src2)>,
268 Requires<[UseHVXDbl]>;
271 multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> {
272 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
273 (MI VecPredRegs:$src1, IntRegs:$src2)>,
274 Requires<[UseHVXSgl]>;
276 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
278 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
280 Requires<[UseHVXDbl]>;
283 multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> {
284 def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
285 (MI VecPredRegs:$src1, VecPredRegs:$src2)>,
286 Requires<[UseHVXSgl]>;
288 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
289 VecPredRegs128B:$src2),
290 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
291 VecPredRegs128B:$src2)>,
292 Requires<[UseHVXDbl]>;
295 multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> {
296 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
297 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
298 Requires<[UseHVXSgl]>;
300 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
301 VecDblRegs128B:$src2,
303 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
304 VecDblRegs128B:$src2,
306 Requires<[UseHVXDbl]>;
309 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
310 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
311 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
312 Requires<[UseHVXSgl]>;
314 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
315 VectorRegs128B:$src2,
317 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
318 VectorRegs128B:$src2,
320 Requires<[UseHVXDbl]>;
323 multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> {
324 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
325 (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
326 Requires<[UseHVXSgl]>;
328 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
329 VectorRegs128B:$src2,
331 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
332 VectorRegs128B:$src2,
334 Requires<[UseHVXDbl]>;
337 multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> {
338 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
339 (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
340 Requires<[UseHVXSgl]>;
342 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
343 VecDblRegs128B:$src2,
345 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
346 VecDblRegs128B:$src2,
348 Requires<[UseHVXDbl]>;
351 multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> {
352 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
353 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
354 Requires<[UseHVXSgl]>;
356 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
357 VectorRegs128B:$src2,
358 VectorRegs128B:$src3),
359 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
360 VectorRegs128B:$src2,
361 VectorRegs128B:$src3)>,
362 Requires<[UseHVXDbl]>;
365 multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> {
366 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
367 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
368 Requires<[UseHVXSgl]>;
370 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
371 VectorRegs128B:$src2,
372 VectorRegs128B:$src3),
373 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
374 VectorRegs128B:$src2,
375 VectorRegs128B:$src3)>,
376 Requires<[UseHVXDbl]>;
379 multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> {
380 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
381 (MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
382 Requires<[UseHVXSgl]>;
384 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
385 VectorRegs128B:$src2,
386 VectorRegs128B:$src3),
387 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
388 VectorRegs128B:$src2,
389 VectorRegs128B:$src3)>,
390 Requires<[UseHVXDbl]>;
393 multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> {
394 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
395 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
396 Requires<[UseHVXSgl]>;
398 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
399 VecPredRegs128B:$src2,
401 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
402 VecPredRegs128B:$src2,
404 Requires<[UseHVXDbl]>;
408 multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> {
409 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
410 (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
411 Requires<[UseHVXSgl]>;
413 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
414 VectorRegs128B:$src2,
416 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
417 VectorRegs128B:$src2,
419 Requires<[UseHVXDbl]>;
422 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
423 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
424 (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
425 Requires<[UseHVXSgl]>;
427 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
428 VectorRegs128B:$src2, imm:$src3),
429 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
430 VectorRegs128B:$src2, imm:$src3)>,
431 Requires<[UseHVXDbl]>;
434 multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> {
435 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
436 (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>,
437 Requires<[UseHVXSgl]>;
439 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
440 IntRegs:$src2, imm:$src3),
441 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
442 IntRegs:$src2, imm:$src3)>,
443 Requires<[UseHVXDbl]>;
446 multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> {
447 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
448 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>,
449 Requires<[UseHVXSgl]>;
451 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
452 VecDblRegs128B:$src2,
453 IntRegs:$src3, imm:$src4),
454 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
455 VecDblRegs128B:$src2,
456 IntRegs:$src3, imm:$src4)>,
457 Requires<[UseHVXDbl]>;
460 multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> {
461 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
463 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
465 Requires<[UseHVXSgl]>;
467 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
468 VectorRegs128B:$src2,
469 VectorRegs128B:$src3,
471 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
472 VectorRegs128B:$src2,
473 VectorRegs128B:$src3,
475 Requires<[UseHVXDbl]>;
478 multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> {
479 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
481 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
483 Requires<[UseHVXSgl]>;
485 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
486 VectorRegs128B:$src2,
487 VectorRegs128B:$src3,
489 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
490 VectorRegs128B:$src2,
491 VectorRegs128B:$src3,
493 Requires<[UseHVXDbl]>;
496 defm : T_WR_pat<V6_vtmpyb, int_hexagon_V6_vtmpyb>;
497 defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>;
498 defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>;
499 defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>;
500 defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>;
501 defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>;
502 defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>;
503 defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>;
504 defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>;
505 defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>;
506 defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>;
507 defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>;
508 defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>;
509 defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>;
510 defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>;
511 defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>;
512 defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>;
513 defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>;
514 defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>;
515 defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>;
516 defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>;
517 defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>;
518 defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>;
519 defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>;
520 defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>;
521 defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>;
522 defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>;
523 defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>;
524 defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>;
525 defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>;
526 defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>;
527 defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>;
529 defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>;
530 defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>;
531 defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>;
532 defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>;
533 defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>;
534 defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>;
535 defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>;
536 defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>;
537 defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>;
538 defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>;
539 defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>;
540 defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>;
541 defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>;
542 defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>;
543 defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>;
544 defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>;
545 defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>;
546 defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>;
547 defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>;
548 defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>;
549 defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>;
550 defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>;
551 defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>;
552 defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>;
553 defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>;
554 defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>;
555 defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>;
556 defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>;
557 defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>;
558 defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>;
559 defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>;
560 defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>;
561 defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>;
562 defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>;
563 defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>;
564 defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>;
565 defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>;
566 defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>;
567 defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>;
568 defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>;
569 defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>;
570 defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>;
571 defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>;
572 defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>;
573 defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>;
574 defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>;
575 defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>;
576 defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>;
577 defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>;
578 defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>;
579 defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>;
580 defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>;
581 defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>;
582 defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>;
583 defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>;
584 defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>;
585 defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>;
586 defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>;
587 defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>;
588 defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>;
589 defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>;
590 defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>;
591 defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>;
592 defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>;
594 defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>;
595 defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>;
596 defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>;
597 defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>;
598 defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>;
599 defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>;
600 defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>;
601 defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>;
602 defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>;
603 defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>;
604 defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>;
606 defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>;
607 defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>;
609 defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>;
610 defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>;
611 defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>;
612 defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>;
614 defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>;
615 defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>;
616 defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>;
617 defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>;
618 defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>;
619 defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>;
620 defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>;
621 defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>;
623 defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>;
624 defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>;
625 defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>;
626 defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>;
627 defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>;
628 defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>;
629 defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>;
630 defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>;
631 defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>;
632 defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>;
633 defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>;
634 defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>;
635 defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>;
636 defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>;
637 defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>;
639 // Compare instructions
640 defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>;
641 defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>;
642 defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>;
643 defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>;
644 defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>;
645 defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>;
646 defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>;
647 defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>;
648 defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>;
649 defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>;
650 defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>;
651 defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>;
652 defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>;
653 defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>;
654 defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>;
655 defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>;
656 defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>;
657 defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>;
658 defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>;
659 defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>;
660 defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>;
661 defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>;
662 defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>;
663 defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>;
664 defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>;
665 defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>;
666 defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>;
668 defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>;
669 defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>;
670 defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>;
671 defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>;
672 defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>;
673 defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>;
674 defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>;
675 defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>;
676 defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>;
677 defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>;
678 defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>;
679 defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>;
680 defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>;
681 defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>;
682 defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>;
683 defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>;
684 defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>;
685 defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>;
686 defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>;
687 defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>;
688 defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>;
689 defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>;
690 defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>;
691 defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>;
692 defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>;
693 defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>;
694 defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>;
695 defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>;
696 defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>;
697 defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>;
698 defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>;
699 defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>;
700 defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>;
701 defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>;
702 defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>;
703 defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>;
704 defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>;
705 defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>;
706 defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>;
707 defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>;
708 defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>;
709 defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>;
710 defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>;
711 defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>;
712 defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>;
713 defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>;
715 defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>;
716 defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>;
717 defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>;
718 defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>;
719 defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>;
720 defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>;
721 defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>;
722 defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>;
723 defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>;
724 defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>;
725 defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>;
726 defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>;
728 defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>;
729 defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>;
730 defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>;
731 defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>;
732 defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>;
733 defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>;
734 defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>;
735 defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>;
736 defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>;
737 defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>;
738 defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>;
739 defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>;
740 defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>;
741 defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>;
742 defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>;
743 defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>;
744 defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>;
745 defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>;
746 defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>;
747 defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>;
748 defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>;
749 defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>;
750 defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>;
752 defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>;
753 defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>;
754 defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>;
756 defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>;
757 defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>;
758 defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>;
761 //defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>;
762 // not present earlier.. need to add intrinsic
763 defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>;
764 defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>;
765 defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>;
766 defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>;
767 defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>;
768 defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>;
769 defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>;
770 defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>;
771 defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>;
773 defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>;
774 defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>;
776 defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>;
777 defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>;
778 defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>;
779 defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>;
781 defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>;
782 defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>;
783 defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>;
784 defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>;
785 defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>;
786 defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>;
787 defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>;
788 defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>;
789 defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>;
790 defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>;
791 defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>;
792 defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>;
793 defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>;
794 defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>;
795 defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>;
796 defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>;
797 defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>;
799 defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>;
800 defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
801 defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>;
802 defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>;
803 defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>;
804 defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>;
806 defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>;
807 defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>;
808 defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>;
809 defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>;
811 defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
812 def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>;
813 def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>;
814 def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>;
815 def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>;
816 def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>;
817 def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>;
818 def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>;
819 def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>;
820 def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>;
821 def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>;
822 def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>;
823 def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>;
825 defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>;
826 defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>;
828 def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
830 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
831 (v64i16 (V6_vpackwh_sat_128B
832 (v32i32 (HEXAGON_V6_hi_128B VecDblRegs128B:$Vdd)),
833 (v32i32 (HEXAGON_V6_lo_128B VecDblRegs128B:$Vdd))))>,
834 Requires<[UseHVXDbl]>;