1 //=- HexagonIsetDx.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon duplex instructions.
12 //===----------------------------------------------------------------------===//
14 // SA1_combine1i: Combines.
15 let isCodeGenOnly = 1, hasSideEffects = 0 in
16 def V4_SA1_combine1i: SUBInst <
17 (outs DoubleRegs:$Rdd),
19 "$Rdd = combine(#1, #$u2)"> {
23 let Inst{12-10} = 0b111;
30 // SL2_jumpr31_f: Indirect conditional jump if false.
31 // SL2_jumpr31_f -> SL2_jumpr31_fnew
32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
33 def V4_SL2_jumpr31_f: SUBInst <
36 "if (!p0) jumpr r31"> {
37 let Inst{12-6} = 0b1111111;
38 let Inst{2-0} = 0b101;
41 // SL2_deallocframe: Deallocate stack frame.
42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
43 def V4_SL2_deallocframe: SUBInst <
47 let Inst{12-6} = 0b1111100;
51 // SL2_return_f: Deallocate stack frame and return.
52 // SL2_return_f -> SL2_return_fnew
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
54 def V4_SL2_return_f: SUBInst <
57 "if (!p0) dealloc_return"> {
58 let Inst{12-6} = 0b1111101;
59 let Inst{2-0} = 0b101;
62 // SA1_combine3i: Combines.
63 let isCodeGenOnly = 1, hasSideEffects = 0 in
64 def V4_SA1_combine3i: SUBInst <
65 (outs DoubleRegs:$Rdd),
67 "$Rdd = combine(#3, #$u2)"> {
71 let Inst{12-10} = 0b111;
78 // SS2_storebi0: Store byte.
79 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
80 def V4_SS2_storebi0: SUBInst <
82 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
83 "memb($Rs + #$u4_0)=#0"> {
87 let Inst{12-8} = 0b10010;
92 // SA1_clrtnew: Clear if true.
93 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
94 def V4_SA1_clrtnew: SUBInst <
97 "if (p0.new) $Rd = #0"> {
100 let Inst{12-9} = 0b1101;
101 let Inst{6-4} = 0b100;
105 // SL2_loadruh_io: Load half.
106 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
107 def V4_SL2_loadruh_io: SUBInst <
109 (ins IntRegs:$Rs, u3_1Imm:$u3_1),
110 "$Rd = memuh($Rs + #$u3_1)"> {
115 let Inst{12-11} = 0b01;
118 let Inst{10-8} = u3_1{3-1};
121 // SL2_jumpr31_tnew: Indirect conditional jump if true.
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
123 def V4_SL2_jumpr31_tnew: SUBInst <
126 "if (p0.new) jumpr:nt r31"> {
127 let Inst{12-6} = 0b1111111;
128 let Inst{2-0} = 0b110;
132 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in
133 def V4_SA1_addi: SUBInst <
135 (ins IntRegs:$_src_, s7Ext:$s7),
136 "$Rx = add($_src_, #$s7)" ,
142 let Inst{12-11} = 0b00;
147 // SL1_loadrub_io: Load byte.
148 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
149 def V4_SL1_loadrub_io: SUBInst <
151 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
152 "$Rd = memub($Rs + #$u4_0)"> {
160 let Inst{11-8} = u4_0;
163 // SL1_loadri_io: Load word.
164 let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
165 def V4_SL1_loadri_io: SUBInst <
167 (ins IntRegs:$Rs, u4_2Imm:$u4_2),
168 "$Rd = memw($Rs + #$u4_2)"> {
176 let Inst{11-8} = u4_2{5-2};
179 // SA1_cmpeqi: Compareimmed.
180 let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
181 def V4_SA1_cmpeqi: SUBInst <
183 (ins IntRegs:$Rs, u2Imm:$u2),
184 "p0 = cmp.eq($Rs, #$u2)"> {
188 let Inst{12-8} = 0b11001;
193 // SA1_combinerz: Combines.
194 let isCodeGenOnly = 1, hasSideEffects = 0 in
195 def V4_SA1_combinerz: SUBInst <
196 (outs DoubleRegs:$Rdd),
198 "$Rdd = combine($Rs, #0)"> {
202 let Inst{12-10} = 0b111;
209 // SL2_return_t: Deallocate stack frame and return.
210 // SL2_return_t -> SL2_return_tnew
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
212 def V4_SL2_return_t: SUBInst <
215 "if (p0) dealloc_return"> {
216 let Inst{12-6} = 0b1111101;
217 let Inst{2-0} = 0b100;
220 // SS2_allocframe: Allocate stack frame.
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
222 def V4_SS2_allocframe: SUBInst <
225 "allocframe(#$u5_3)"> {
228 let Inst{12-9} = 0b1110;
229 let Inst{8-4} = u5_3{7-3};
232 // SS2_storeh_io: Store half.
233 let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in
234 def V4_SS2_storeh_io: SUBInst <
236 (ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt),
237 "memh($Rs + #$u3_1) = $Rt"> {
242 let Inst{12-11} = 0b00;
244 let Inst{10-8} = u3_1{3-1};
248 // SS2_storewi0: Store word.
249 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
250 def V4_SS2_storewi0: SUBInst <
252 (ins IntRegs:$Rs, u4_2Imm:$u4_2),
253 "memw($Rs + #$u4_2)=#0"> {
257 let Inst{12-8} = 0b10000;
259 let Inst{3-0} = u4_2{5-2};
262 // SS2_storewi1: Store word.
263 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
264 def V4_SS2_storewi1: SUBInst <
266 (ins IntRegs:$Rs, u4_2Imm:$u4_2),
267 "memw($Rs + #$u4_2)=#1"> {
271 let Inst{12-8} = 0b10001;
273 let Inst{3-0} = u4_2{5-2};
276 // SL2_jumpr31: Indirect conditional jump if true.
277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
278 def V4_SL2_jumpr31: SUBInst <
282 let Inst{12-6} = 0b1111111;
286 // SA1_combinezr: Combines.
287 let isCodeGenOnly = 1, hasSideEffects = 0 in
288 def V4_SA1_combinezr: SUBInst <
289 (outs DoubleRegs:$Rdd),
291 "$Rdd = combine(#0, $Rs)"> {
295 let Inst{12-10} = 0b111;
302 // SL2_loadrh_io: Load half.
303 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
304 def V4_SL2_loadrh_io: SUBInst <
306 (ins IntRegs:$Rs, u3_1Imm:$u3_1),
307 "$Rd = memh($Rs + #$u3_1)"> {
312 let Inst{12-11} = 0b00;
315 let Inst{10-8} = u3_1{3-1};
319 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
320 def V4_SA1_addrx: SUBInst <
322 (ins IntRegs:$_src_, IntRegs:$Rs),
323 "$Rx = add($_src_, $Rs)" ,
329 let Inst{12-8} = 0b11000;
334 // SA1_setin1: Set to -1.
335 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
336 def V4_SA1_setin1: SUBInst <
342 let Inst{12-9} = 0b1101;
348 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
349 def V4_SA1_sxth: SUBInst <
356 let Inst{12-8} = 0b10100;
361 // SA1_combine0i: Combines.
362 let isCodeGenOnly = 1, hasSideEffects = 0 in
363 def V4_SA1_combine0i: SUBInst <
364 (outs DoubleRegs:$Rdd),
366 "$Rdd = combine(#0, #$u2)"> {
370 let Inst{12-10} = 0b111;
372 let Inst{4-3} = 0b00;
377 // SA1_combine2i: Combines.
378 let isCodeGenOnly = 1, hasSideEffects = 0 in
379 def V4_SA1_combine2i: SUBInst <
380 (outs DoubleRegs:$Rdd),
382 "$Rdd = combine(#2, #$u2)"> {
386 let Inst{12-10} = 0b111;
388 let Inst{4-3} = 0b10;
394 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
395 def V4_SA1_sxtb: SUBInst <
402 let Inst{12-8} = 0b10101;
407 // SA1_clrf: Clear if false.
408 // SA1_clrf -> SA1_clrfnew
409 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
410 def V4_SA1_clrf: SUBInst <
413 "if (!p0) $Rd = #0"> {
416 let Inst{12-9} = 0b1101;
417 let Inst{6-4} = 0b111;
421 // SL2_loadrb_io: Load byte.
422 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
423 def V4_SL2_loadrb_io: SUBInst <
425 (ins IntRegs:$Rs, u3_0Imm:$u3_0),
426 "$Rd = memb($Rs + #$u3_0)"> {
431 let Inst{12-11} = 0b10;
434 let Inst{10-8} = u3_0;
438 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
439 def V4_SA1_tfr: SUBInst <
446 let Inst{12-8} = 0b10000;
451 // SL2_loadrd_sp: Load dword.
452 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
453 def V4_SL2_loadrd_sp: SUBInst <
454 (outs DoubleRegs:$Rdd),
456 "$Rdd = memd(r29 + #$u5_3)"> {
460 let Inst{12-8} = 0b11110;
462 let Inst{7-3} = u5_3{7-3};
466 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
467 def V4_SA1_and1: SUBInst <
470 "$Rd = and($Rs, #1)"> {
474 let Inst{12-8} = 0b10010;
479 // SS2_storebi1: Store byte.
480 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
481 def V4_SS2_storebi1: SUBInst <
483 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
484 "memb($Rs + #$u4_0)=#1"> {
488 let Inst{12-8} = 0b10011;
490 let Inst{3-0} = u4_0;
494 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
495 def V4_SA1_inc: SUBInst <
498 "$Rd = add($Rs, #1)"> {
502 let Inst{12-8} = 0b10001;
507 // SS2_stored_sp: Store dword.
508 let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
509 def V4_SS2_stored_sp: SUBInst <
511 (ins s6_3Imm:$s6_3, DoubleRegs:$Rtt),
512 "memd(r29 + #$s6_3) = $Rtt"> {
516 let Inst{12-9} = 0b0101;
517 let Inst{8-3} = s6_3{8-3};
521 // SS2_storew_sp: Store word.
522 let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
523 def V4_SS2_storew_sp: SUBInst <
525 (ins u5_2Imm:$u5_2, IntRegs:$Rt),
526 "memw(r29 + #$u5_2) = $Rt"> {
530 let Inst{12-9} = 0b0100;
531 let Inst{8-4} = u5_2{6-2};
535 // SL2_jumpr31_fnew: Indirect conditional jump if false.
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
537 def V4_SL2_jumpr31_fnew: SUBInst <
540 "if (!p0.new) jumpr:nt r31"> {
541 let Inst{12-6} = 0b1111111;
542 let Inst{2-0} = 0b111;
545 // SA1_clrt: Clear if true.
546 // SA1_clrt -> SA1_clrtnew
547 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
548 def V4_SA1_clrt: SUBInst <
551 "if (p0) $Rd = #0"> {
554 let Inst{12-9} = 0b1101;
555 let Inst{6-4} = 0b110;
559 // SL2_return: Deallocate stack frame and return.
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
561 def V4_SL2_return: SUBInst <
565 let Inst{12-6} = 0b1111101;
570 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
571 def V4_SA1_dec: SUBInst <
574 "$Rd = add($Rs,#-1)"> {
578 let Inst{12-8} = 0b10011;
583 // SA1_seti: Set immed.
584 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in
585 def V4_SA1_seti: SUBInst <
592 let Inst{12-10} = 0b010;
597 // SL2_jumpr31_t: Indirect conditional jump if true.
598 // SL2_jumpr31_t -> SL2_jumpr31_tnew
599 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
600 def V4_SL2_jumpr31_t: SUBInst <
603 "if (p0) jumpr r31"> {
604 let Inst{12-6} = 0b1111111;
605 let Inst{2-0} = 0b100;
608 // SA1_clrfnew: Clear if false.
609 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
610 def V4_SA1_clrfnew: SUBInst <
613 "if (!p0.new) $Rd = #0"> {
616 let Inst{12-9} = 0b1101;
617 let Inst{6-4} = 0b101;
621 // SS1_storew_io: Store word.
622 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
623 def V4_SS1_storew_io: SUBInst <
625 (ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt),
626 "memw($Rs + #$u4_2) = $Rt"> {
633 let Inst{11-8} = u4_2{5-2};
638 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
639 def V4_SA1_zxtb: SUBInst <
642 "$Rd = and($Rs, #255)"> {
646 let Inst{12-8} = 0b10111;
652 let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
653 def V4_SA1_addsp: SUBInst <
656 "$Rd = add(r29, #$u6_2)"> {
660 let Inst{12-10} = 0b011;
662 let Inst{9-4} = u6_2{7-2};
665 // SL2_loadri_sp: Load word.
666 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
667 def V4_SL2_loadri_sp: SUBInst <
670 "$Rd = memw(r29 + #$u5_2)"> {
674 let Inst{12-9} = 0b1110;
676 let Inst{8-4} = u5_2{6-2};
679 // SS1_storeb_io: Store byte.
680 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
681 def V4_SS1_storeb_io: SUBInst <
683 (ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt),
684 "memb($Rs + #$u4_0) = $Rt"> {
691 let Inst{11-8} = u4_0;
695 // SL2_return_tnew: Deallocate stack frame and return.
696 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
697 def V4_SL2_return_tnew: SUBInst <
700 "if (p0.new) dealloc_return:nt"> {
701 let Inst{12-6} = 0b1111101;
702 let Inst{2-0} = 0b110;
705 // SL2_return_fnew: Deallocate stack frame and return.
706 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
707 def V4_SL2_return_fnew: SUBInst <
710 "if (!p0.new) dealloc_return:nt"> {
711 let Inst{12-6} = 0b1111101;
712 let Inst{2-0} = 0b111;
716 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
717 def V4_SA1_zxth: SUBInst <
724 let Inst{12-8} = 0b10110;