1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
23 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "hexagon-nvj"
25 #include "llvm/PassSupport.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/LiveVariables.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "HexagonTargetMachine.h"
42 #include "HexagonRegisterInfo.h"
43 #include "HexagonSubtarget.h"
44 #include "HexagonInstrInfo.h"
45 #include "HexagonMachineFunctionInfo.h"
49 #include "llvm/Support/CommandLine.h"
52 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
55 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
56 "Maximum number of predicated jumps to be converted to New Value Jump"));
58 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
59 cl::ZeroOrMore, cl::init(false),
60 cl::desc("Disable New Value Jumps"));
63 struct HexagonNewValueJump : public MachineFunctionPass {
64 const HexagonInstrInfo *QII;
65 const HexagonRegisterInfo *QRI;
70 HexagonNewValueJump() : MachineFunctionPass(ID) { }
72 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
73 MachineFunctionPass::getAnalysisUsage(AU);
76 const char *getPassName() const {
77 return "Hexagon NewValueJump";
80 virtual bool runOnMachineFunction(MachineFunction &Fn);
86 } // end of anonymous namespace
88 char HexagonNewValueJump::ID = 0;
90 // We have identified this II could be feeder to NVJ,
91 // verify that it can be.
92 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
93 const TargetRegisterInfo *TRI,
94 MachineBasicBlock::iterator II,
95 MachineBasicBlock::iterator end,
96 MachineBasicBlock::iterator skip,
97 MachineFunction &MF) {
99 // Predicated instruction can not be feeder to NVJ.
100 if (QII->isPredicated(II))
103 // Bail out if feederReg is a paired register (double regs in
104 // our case). One would think that we can check to see if a given
105 // register cmpReg1 or cmpReg2 is a sub register of feederReg
106 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
107 // before the callsite of this function
108 // But we can not as it comes in the following fashion.
109 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
110 // %R0<def> = KILL %R0, %D0<imp-use,kill>
111 // %P0<def> = CMPEQri %R0<kill>, 0
112 // Hence, we need to check if it's a KILL instruction.
113 if (II->getOpcode() == TargetOpcode::KILL)
117 // Make sure there there is no 'def' or 'use' of any of the uses of
118 // feeder insn between it's definition, this MI and jump, jmpInst
119 // skipping compare, cmpInst.
120 // Here's the example.
121 // r21=memub(r22+r24<<#0)
122 // p0 = cmp.eq(r21, #0)
123 // r4=memub(r3+r21<<#0)
124 // if (p0.new) jump:t .LBB29_45
125 // Without this check, it will be converted into
126 // r4=memub(r3+r21<<#0)
127 // r21=memub(r22+r24<<#0)
128 // p0 = cmp.eq(r21, #0)
129 // if (p0.new) jump:t .LBB29_45
130 // and result WAR hazards if converted to New Value Jump.
132 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
133 if (II->getOperand(i).isReg() &&
134 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
135 MachineBasicBlock::iterator localII = II;
137 unsigned Reg = II->getOperand(i).getReg();
138 for (MachineBasicBlock::iterator localBegin = localII;
139 localBegin != end; ++localBegin) {
140 if (localBegin == skip ) continue;
141 // Check for Subregisters too.
142 if (localBegin->modifiesRegister(Reg, TRI) ||
143 localBegin->readsRegister(Reg, TRI))
151 // These are the common checks that need to performed
153 // 1. compare instruction can be moved before jump.
154 // 2. feeder to the compare instruction can be moved before jump.
155 static bool commonChecksToProhibitNewValueJump(bool afterRA,
156 MachineBasicBlock::iterator MII) {
158 // If store in path, bail out.
159 if (MII->getDesc().mayStore())
162 // if call in path, bail out.
163 if (MII->getOpcode() == Hexagon::CALLv3)
166 // if NVJ is running prior to RA, do the following checks.
168 // The following Target Opcode instructions are spurious
169 // to new value jump. If they are in the path, bail out.
170 // KILL sets kill flag on the opcode. It also sets up a
171 // single register, out of pair.
172 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
173 // %R0<def> = KILL %R0, %D0<imp-use,kill>
174 // %P0<def> = CMPEQri %R0<kill>, 0
175 // PHI can be anything after RA.
176 // COPY can remateriaze things in between feeder, compare and nvj.
177 if (MII->getOpcode() == TargetOpcode::KILL ||
178 MII->getOpcode() == TargetOpcode::PHI ||
179 MII->getOpcode() == TargetOpcode::COPY)
182 // The following pseudo Hexagon instructions sets "use" and "def"
183 // of registers by individual passes in the backend. At this time,
184 // we don't know the scope of usage and definitions of these
186 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
187 MII->getOpcode() == Hexagon::TFR_condset_ii ||
188 MII->getOpcode() == Hexagon::TFR_condset_ri ||
189 MII->getOpcode() == Hexagon::TFR_condset_ir ||
190 MII->getOpcode() == Hexagon::LDriw_pred ||
191 MII->getOpcode() == Hexagon::STriw_pred)
198 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
199 const TargetRegisterInfo *TRI,
200 MachineBasicBlock::iterator II,
204 MachineBasicBlock::iterator end,
205 MachineFunction &MF) {
207 MachineInstr *MI = II;
209 // If the second operand of the compare is an imm, make sure it's in the
210 // range specified by the arch.
212 int64_t v = MI->getOperand(2).getImm();
213 if (MI->getOpcode() == Hexagon::CMPGEri ||
214 (MI->getOpcode() == Hexagon::CMPGEUri && v > 0))
217 if (!(isUInt<5>(v) ||
218 ((MI->getOpcode() == Hexagon::CMPEQri ||
219 MI->getOpcode() == Hexagon::CMPGTri ||
220 MI->getOpcode() == Hexagon::CMPGEri) &&
225 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
226 cmpReg1 = MI->getOperand(1).getReg();
229 cmpOp2 = MI->getOperand(2).getReg();
231 // Make sure that that second register is not from COPY
232 // At machine code level, we don't need this, but if we decide
233 // to move new value jump prior to RA, we would be needing this.
234 MachineRegisterInfo &MRI = MF.getRegInfo();
235 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
236 MachineInstr *def = MRI.getVRegDef(cmpOp2);
237 if (def->getOpcode() == TargetOpcode::COPY)
242 // Walk the instructions after the compare (predicate def) to the jump,
243 // and satisfy the following conditions.
245 for (MachineBasicBlock::iterator localII = II; localII != end;
249 // If "common" checks fail, bail out.
250 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
254 // If there is a def or use of predicate (result of compare), bail out.
255 if (localII->modifiesRegister(pReg, TRI) ||
256 localII->readsRegister(pReg, TRI))
260 // If there is a def of any of the use of the compare (operands of compare),
263 // p0 = cmp.eq(r2, r0)
265 // if (p0.new) jump:t .LBB28_3
266 if (localII->modifiesRegister(cmpReg1, TRI) ||
267 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
273 // Given a compare operator, return a matching New Value Jump
274 // compare operator. Make sure that MI here is included in
275 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
276 static unsigned getNewValueJumpOpcode(const MachineInstr *MI, int reg,
277 bool secondRegNewified) {
278 switch (MI->getOpcode()) {
279 case Hexagon::CMPEQrr:
280 return Hexagon::JMP_EQrrPt_nv_V4;
282 case Hexagon::CMPEQri: {
284 return Hexagon::JMP_EQriPt_nv_V4;
286 return Hexagon::JMP_EQriPtneg_nv_V4;
289 case Hexagon::CMPLTrr:
290 case Hexagon::CMPGTrr: {
291 if (secondRegNewified)
292 return Hexagon::JMP_GTrrdnPt_nv_V4;
294 return Hexagon::JMP_GTrrPt_nv_V4;
297 case Hexagon::CMPGEri: {
299 return Hexagon::JMP_GTriPt_nv_V4;
301 return Hexagon::JMP_GTriPtneg_nv_V4;
304 case Hexagon::CMPGTri: {
306 return Hexagon::JMP_GTriPt_nv_V4;
308 return Hexagon::JMP_GTriPtneg_nv_V4;
311 case Hexagon::CMPLTUrr:
312 case Hexagon::CMPGTUrr: {
313 if (secondRegNewified)
314 return Hexagon::JMP_GTUrrdnPt_nv_V4;
316 return Hexagon::JMP_GTUrrPt_nv_V4;
319 case Hexagon::CMPGTUri:
320 return Hexagon::JMP_GTUriPt_nv_V4;
322 case Hexagon::CMPGEUri: {
324 return Hexagon::JMP_EQrrPt_nv_V4;
326 return Hexagon::JMP_GTUriPt_nv_V4;
330 llvm_unreachable("Could not find matching New Value Jump instruction.");
332 // return *some value* to avoid compiler warning
336 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
338 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
339 << "********** Function: "
340 << MF.getFunction()->getName() << "\n");
343 // for now disable this, if we move NewValueJump before register
344 // allocation we need this information.
345 LiveVariables &LVs = getAnalysis<LiveVariables>();
348 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
350 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
352 if (!QRI->Subtarget.hasV4TOps() ||
353 DisableNewValueJumps) {
357 int nvjCount = DbgNVJCount;
358 int nvjGenerated = 0;
360 // Loop through all the bb's of the function
361 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
362 MBBb != MBBe; ++MBBb) {
363 MachineBasicBlock* MBB = MBBb;
365 DEBUG(dbgs() << "** dumping bb ** "
366 << MBB->getNumber() << "\n");
368 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
369 bool foundJump = false;
370 bool foundCompare = false;
371 bool invertPredicate = false;
372 unsigned predReg = 0; // predicate reg of the jump.
373 unsigned cmpReg1 = 0;
375 bool MO1IsKill = false;
376 bool MO2IsKill = false;
377 MachineBasicBlock::iterator jmpPos;
378 MachineBasicBlock::iterator cmpPos;
379 MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
380 MachineBasicBlock *jmpTarget = NULL;
381 bool afterRA = false;
382 bool isSecondOpReg = false;
383 bool isSecondOpNewified = false;
384 // Traverse the basic block - bottom up
385 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
387 MachineInstr *MI = --MII;
388 if (MI->isDebugValue()) {
392 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
395 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
398 (MI->getOpcode() == Hexagon::JMP_c ||
399 MI->getOpcode() == Hexagon::JMP_cNot ||
400 MI->getOpcode() == Hexagon::JMP_cdnPt ||
401 MI->getOpcode() == Hexagon::JMP_cdnPnt ||
402 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
403 MI->getOpcode() == Hexagon::JMP_cdnNotPnt)) {
404 // This is where you would insert your compare and
405 // instr that feeds compare
408 predReg = MI->getOperand(0).getReg();
409 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
411 // If ifconverter had not messed up with the kill flags of the
412 // operands, the following check on the kill flag would suffice.
413 // if(!jmpInstr->getOperand(0).isKill()) break;
415 // This predicate register is live out out of BB
416 // this would only work if we can actually use Live
417 // variable analysis on phy regs - but LLVM does not
418 // provide LV analysis on phys regs.
419 //if(LVs.isLiveOut(predReg, *MBB)) break;
421 // Get all the successors of this block - which will always
422 // be 2. Check if the predicate register is live in in those
423 // successor. If yes, we can not delete the predicate -
424 // I am doing this only because LLVM does not provide LiveOut
426 bool predLive = false;
427 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
428 SIE = MBB->succ_end(); SI != SIE; ++SI) {
429 MachineBasicBlock* succMBB = *SI;
430 if (succMBB->isLiveIn(predReg)) {
437 jmpTarget = MI->getOperand(1).getMBB();
439 if (MI->getOpcode() == Hexagon::JMP_cNot ||
440 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
441 MI->getOpcode() == Hexagon::JMP_cdnNotPnt) {
442 invertPredicate = true;
447 // No new value jump if there is a barrier. A barrier has to be in its
448 // own packet. A barrier has zero operands. We conservatively bail out
449 // here if we see any instruction with zero operands.
450 if (foundJump && MI->getNumOperands() == 0)
455 MI->getOperand(0).isReg() &&
456 MI->getOperand(0).getReg() == predReg) {
458 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
459 if (QII->isNewValueJumpCandidate(MI)) {
461 assert((MI->getDesc().isCompare()) &&
462 "Only compare instruction can be collapsed into New Value Jump");
463 isSecondOpReg = MI->getOperand(2).isReg();
465 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
466 afterRA, jmpPos, MF))
473 // We need cmpReg1 and cmpOp2(imm or reg) while building
474 // new value jump instruction.
475 cmpReg1 = MI->getOperand(1).getReg();
476 if (MI->getOperand(1).isKill())
480 cmpOp2 = MI->getOperand(2).getReg();
481 if (MI->getOperand(2).isKill())
484 cmpOp2 = MI->getOperand(2).getImm();
489 if (foundCompare && foundJump) {
491 // If "common" checks fail, bail out on this BB.
492 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
495 bool foundFeeder = false;
496 MachineBasicBlock::iterator feederPos = MII;
497 if (MI->getOperand(0).isReg() &&
498 MI->getOperand(0).isDef() &&
499 (MI->getOperand(0).getReg() == cmpReg1 ||
501 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
503 unsigned feederReg = MI->getOperand(0).getReg();
505 // First try to see if we can get the feeder from the first operand
506 // of the compare. If we can not, and if secondOpReg is true
507 // (second operand of the compare is also register), try that one.
508 // TODO: Try to come up with some heuristic to figure out which
509 // feeder would benefit.
511 if (feederReg == cmpReg1) {
512 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
523 feederReg == (unsigned) cmpOp2)
524 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
528 // In case of CMPLT, or CMPLTU, or EQ with the second register
529 // to newify, swap the operands.
530 if (cmpInstr->getOpcode() == Hexagon::CMPLTrr ||
531 cmpInstr->getOpcode() == Hexagon::CMPLTUrr ||
532 (cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
533 feederReg == (unsigned) cmpOp2)) {
534 unsigned tmp = cmpReg1;
535 bool tmpIsKill = MO1IsKill;
537 MO1IsKill = MO2IsKill;
539 MO2IsKill = tmpIsKill;
542 // Now we have swapped the operands, all we need to check is,
543 // if the second operand (after swap) is the feeder.
544 // And if it is, make a note.
545 if (feederReg == (unsigned)cmpOp2)
546 isSecondOpNewified = true;
549 // Now that we are moving feeder close the jump,
550 // make sure we are respecting the kill values of
551 // the operands of the feeder.
553 bool updatedIsKill = false;
554 for (unsigned i = 0; i < MI->getNumOperands(); i++) {
555 MachineOperand &MO = MI->getOperand(i);
556 if (MO.isReg() && MO.isUse()) {
557 unsigned feederReg = MO.getReg();
558 for (MachineBasicBlock::iterator localII = feederPos,
559 end = jmpPos; localII != end; localII++) {
560 MachineInstr *localMI = localII;
561 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
562 MachineOperand &localMO = localMI->getOperand(j);
563 if (localMO.isReg() && localMO.isUse() &&
564 localMO.isKill() && feederReg == localMO.getReg()) {
565 // We found that there is kill of a use register
566 // Set up a kill flag on the register
567 localMO.setIsKill(false);
569 updatedIsKill = true;
573 if (updatedIsKill) break;
576 if (updatedIsKill) break;
579 MBB->splice(jmpPos, MI->getParent(), MI);
580 MBB->splice(jmpPos, MI->getParent(), cmpInstr);
581 DebugLoc dl = MI->getDebugLoc();
584 assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
585 "This compare is not a New Value Jump candidate.");
586 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
589 opc = QII->getInvertedPredicatedOpcode(opc);
591 // Manage the conversions from CMPGEUri to either CMPEQrr
592 // or CMPGTUri properly. See Arch spec for CMPGEUri instructions.
593 // This has to be after the getNewValueJumpOpcode function call as
594 // second operand of the compare could be modified in this logic.
595 if (cmpInstr->getOpcode() == Hexagon::CMPGEUri) {
598 MO2IsKill = MO1IsKill;
599 isSecondOpReg = true;
604 // Manage the conversions from CMPGEri to CMPGTUri properly.
605 // See Arch spec for CMPGEri instructions.
606 if (cmpInstr->getOpcode() == Hexagon::CMPGEri)
610 NewMI = BuildMI(*MBB, jmpPos, dl,
612 .addReg(cmpReg1, getKillRegState(MO1IsKill))
613 .addReg(cmpOp2, getKillRegState(MO2IsKill))
617 NewMI = BuildMI(*MBB, jmpPos, dl,
619 .addReg(cmpReg1, getKillRegState(MO1IsKill))
624 assert(NewMI && "New Value Jump Instruction Not created!");
625 if (cmpInstr->getOperand(0).isReg() &&
626 cmpInstr->getOperand(0).isKill())
627 cmpInstr->getOperand(0).setIsKill(false);
628 if (cmpInstr->getOperand(1).isReg() &&
629 cmpInstr->getOperand(1).isKill())
630 cmpInstr->getOperand(1).setIsKill(false);
631 cmpInstr->eraseFromParent();
632 jmpInstr->eraseFromParent();
645 FunctionPass *llvm::createHexagonNewValueJump() {
646 return new HexagonNewValueJump();