1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
23 //===----------------------------------------------------------------------===//
24 #include "llvm/PassSupport.h"
26 #include "HexagonInstrInfo.h"
27 #include "HexagonMachineFunctionInfo.h"
28 #include "HexagonRegisterInfo.h"
29 #include "HexagonSubtarget.h"
30 #include "HexagonTargetMachine.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
49 #define DEBUG_TYPE "hexagon-nvj"
51 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
54 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
55 "Maximum number of predicated jumps to be converted to New Value Jump"));
57 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
58 cl::ZeroOrMore, cl::init(false),
59 cl::desc("Disable New Value Jumps"));
62 void initializeHexagonNewValueJumpPass(PassRegistry&);
67 struct HexagonNewValueJump : public MachineFunctionPass {
68 const HexagonInstrInfo *QII;
69 const HexagonRegisterInfo *QRI;
74 HexagonNewValueJump() : MachineFunctionPass(ID) {
75 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
78 void getAnalysisUsage(AnalysisUsage &AU) const override {
79 AU.addRequired<MachineBranchProbabilityInfo>();
80 MachineFunctionPass::getAnalysisUsage(AU);
83 const char *getPassName() const override {
84 return "Hexagon NewValueJump";
87 bool runOnMachineFunction(MachineFunction &Fn) override;
90 /// \brief A handle to the branch probability pass.
91 const MachineBranchProbabilityInfo *MBPI;
95 } // end of anonymous namespace
97 char HexagonNewValueJump::ID = 0;
99 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
100 "Hexagon NewValueJump", false, false)
101 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
102 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
103 "Hexagon NewValueJump", false, false)
106 // We have identified this II could be feeder to NVJ,
107 // verify that it can be.
108 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
109 const TargetRegisterInfo *TRI,
110 MachineBasicBlock::iterator II,
111 MachineBasicBlock::iterator end,
112 MachineBasicBlock::iterator skip,
113 MachineFunction &MF) {
115 // Predicated instruction can not be feeder to NVJ.
116 if (QII->isPredicated(II))
119 // Bail out if feederReg is a paired register (double regs in
120 // our case). One would think that we can check to see if a given
121 // register cmpReg1 or cmpReg2 is a sub register of feederReg
122 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
123 // before the callsite of this function
124 // But we can not as it comes in the following fashion.
125 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
126 // %R0<def> = KILL %R0, %D0<imp-use,kill>
127 // %P0<def> = CMPEQri %R0<kill>, 0
128 // Hence, we need to check if it's a KILL instruction.
129 if (II->getOpcode() == TargetOpcode::KILL)
133 // Make sure there there is no 'def' or 'use' of any of the uses of
134 // feeder insn between it's definition, this MI and jump, jmpInst
135 // skipping compare, cmpInst.
136 // Here's the example.
137 // r21=memub(r22+r24<<#0)
138 // p0 = cmp.eq(r21, #0)
139 // r4=memub(r3+r21<<#0)
140 // if (p0.new) jump:t .LBB29_45
141 // Without this check, it will be converted into
142 // r4=memub(r3+r21<<#0)
143 // r21=memub(r22+r24<<#0)
144 // p0 = cmp.eq(r21, #0)
145 // if (p0.new) jump:t .LBB29_45
146 // and result WAR hazards if converted to New Value Jump.
148 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
149 if (II->getOperand(i).isReg() &&
150 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
151 MachineBasicBlock::iterator localII = II;
153 unsigned Reg = II->getOperand(i).getReg();
154 for (MachineBasicBlock::iterator localBegin = localII;
155 localBegin != end; ++localBegin) {
156 if (localBegin == skip ) continue;
157 // Check for Subregisters too.
158 if (localBegin->modifiesRegister(Reg, TRI) ||
159 localBegin->readsRegister(Reg, TRI))
167 // These are the common checks that need to performed
169 // 1. compare instruction can be moved before jump.
170 // 2. feeder to the compare instruction can be moved before jump.
171 static bool commonChecksToProhibitNewValueJump(bool afterRA,
172 MachineBasicBlock::iterator MII) {
174 // If store in path, bail out.
175 if (MII->getDesc().mayStore())
178 // if call in path, bail out.
179 if (MII->getOpcode() == Hexagon::J2_call)
182 // if NVJ is running prior to RA, do the following checks.
184 // The following Target Opcode instructions are spurious
185 // to new value jump. If they are in the path, bail out.
186 // KILL sets kill flag on the opcode. It also sets up a
187 // single register, out of pair.
188 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
189 // %R0<def> = KILL %R0, %D0<imp-use,kill>
190 // %P0<def> = CMPEQri %R0<kill>, 0
191 // PHI can be anything after RA.
192 // COPY can remateriaze things in between feeder, compare and nvj.
193 if (MII->getOpcode() == TargetOpcode::KILL ||
194 MII->getOpcode() == TargetOpcode::PHI ||
195 MII->getOpcode() == TargetOpcode::COPY)
198 // The following pseudo Hexagon instructions sets "use" and "def"
199 // of registers by individual passes in the backend. At this time,
200 // we don't know the scope of usage and definitions of these
202 if (MII->getOpcode() == Hexagon::TFR_condset_ii ||
203 MII->getOpcode() == Hexagon::TFR_condset_ri ||
204 MII->getOpcode() == Hexagon::TFR_condset_ir ||
205 MII->getOpcode() == Hexagon::LDriw_pred ||
206 MII->getOpcode() == Hexagon::STriw_pred)
213 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
214 const TargetRegisterInfo *TRI,
215 MachineBasicBlock::iterator II,
219 MachineBasicBlock::iterator end,
220 MachineFunction &MF) {
222 MachineInstr *MI = II;
224 // If the second operand of the compare is an imm, make sure it's in the
225 // range specified by the arch.
227 int64_t v = MI->getOperand(2).getImm();
229 if (!(isUInt<5>(v) ||
230 ((MI->getOpcode() == Hexagon::C2_cmpeqi ||
231 MI->getOpcode() == Hexagon::C2_cmpgti) &&
236 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
237 cmpReg1 = MI->getOperand(1).getReg();
240 cmpOp2 = MI->getOperand(2).getReg();
242 // Make sure that that second register is not from COPY
243 // At machine code level, we don't need this, but if we decide
244 // to move new value jump prior to RA, we would be needing this.
245 MachineRegisterInfo &MRI = MF.getRegInfo();
246 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
247 MachineInstr *def = MRI.getVRegDef(cmpOp2);
248 if (def->getOpcode() == TargetOpcode::COPY)
253 // Walk the instructions after the compare (predicate def) to the jump,
254 // and satisfy the following conditions.
256 for (MachineBasicBlock::iterator localII = II; localII != end;
260 // If "common" checks fail, bail out.
261 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
265 // If there is a def or use of predicate (result of compare), bail out.
266 if (localII->modifiesRegister(pReg, TRI) ||
267 localII->readsRegister(pReg, TRI))
271 // If there is a def of any of the use of the compare (operands of compare),
274 // p0 = cmp.eq(r2, r0)
276 // if (p0.new) jump:t .LBB28_3
277 if (localII->modifiesRegister(cmpReg1, TRI) ||
278 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
284 // Given a compare operator, return a matching New Value Jump
285 // compare operator. Make sure that MI here is included in
286 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
287 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
288 bool secondRegNewified,
289 MachineBasicBlock *jmpTarget,
290 const MachineBranchProbabilityInfo
293 MachineBasicBlock *Src = MI->getParent();
294 const BranchProbability Prediction =
295 MBPI->getEdgeProbability(Src, jmpTarget);
297 if (Prediction >= BranchProbability(1,2))
300 switch (MI->getOpcode()) {
301 case Hexagon::C2_cmpeq:
302 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
303 : Hexagon::J4_cmpeq_t_jumpnv_nt;
305 case Hexagon::C2_cmpeqi: {
307 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
308 : Hexagon::J4_cmpeqi_t_jumpnv_nt;
310 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
311 : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
314 case Hexagon::C2_cmpgt: {
315 if (secondRegNewified)
316 return taken ? Hexagon::J4_cmplt_t_jumpnv_t
317 : Hexagon::J4_cmplt_t_jumpnv_nt;
319 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
320 : Hexagon::J4_cmpgt_t_jumpnv_nt;
323 case Hexagon::C2_cmpgti: {
325 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
326 : Hexagon::J4_cmpgti_t_jumpnv_nt;
328 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
329 : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
332 case Hexagon::C2_cmpgtu: {
333 if (secondRegNewified)
334 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
335 : Hexagon::J4_cmpltu_t_jumpnv_nt;
337 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
338 : Hexagon::J4_cmpgtu_t_jumpnv_nt;
341 case Hexagon::C2_cmpgtui:
342 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
343 : Hexagon::J4_cmpgtui_t_jumpnv_nt;
346 llvm_unreachable("Could not find matching New Value Jump instruction.");
348 // return *some value* to avoid compiler warning
352 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
354 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
355 << "********** Function: "
356 << MF.getName() << "\n");
358 // If we move NewValueJump before register allocation we'll need live variable
359 // analysis here too.
361 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
362 QRI = static_cast<const HexagonRegisterInfo *>(
363 MF.getSubtarget().getRegisterInfo());
364 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
366 if (!QRI->Subtarget.hasV4TOps() ||
367 DisableNewValueJumps) {
371 int nvjCount = DbgNVJCount;
372 int nvjGenerated = 0;
374 // Loop through all the bb's of the function
375 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
376 MBBb != MBBe; ++MBBb) {
377 MachineBasicBlock* MBB = MBBb;
379 DEBUG(dbgs() << "** dumping bb ** "
380 << MBB->getNumber() << "\n");
382 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
383 bool foundJump = false;
384 bool foundCompare = false;
385 bool invertPredicate = false;
386 unsigned predReg = 0; // predicate reg of the jump.
387 unsigned cmpReg1 = 0;
389 bool MO1IsKill = false;
390 bool MO2IsKill = false;
391 MachineBasicBlock::iterator jmpPos;
392 MachineBasicBlock::iterator cmpPos;
393 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
394 MachineBasicBlock *jmpTarget = nullptr;
395 bool afterRA = false;
396 bool isSecondOpReg = false;
397 bool isSecondOpNewified = false;
398 // Traverse the basic block - bottom up
399 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
401 MachineInstr *MI = --MII;
402 if (MI->isDebugValue()) {
406 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
409 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
412 (MI->getOpcode() == Hexagon::J2_jumpt ||
413 MI->getOpcode() == Hexagon::J2_jumpf ||
414 MI->getOpcode() == Hexagon::J2_jumptnewpt ||
415 MI->getOpcode() == Hexagon::J2_jumptnew ||
416 MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
417 MI->getOpcode() == Hexagon::J2_jumpfnew)) {
418 // This is where you would insert your compare and
419 // instr that feeds compare
422 predReg = MI->getOperand(0).getReg();
423 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
425 // If ifconverter had not messed up with the kill flags of the
426 // operands, the following check on the kill flag would suffice.
427 // if(!jmpInstr->getOperand(0).isKill()) break;
429 // This predicate register is live out out of BB
430 // this would only work if we can actually use Live
431 // variable analysis on phy regs - but LLVM does not
432 // provide LV analysis on phys regs.
433 //if(LVs.isLiveOut(predReg, *MBB)) break;
435 // Get all the successors of this block - which will always
436 // be 2. Check if the predicate register is live in in those
437 // successor. If yes, we can not delete the predicate -
438 // I am doing this only because LLVM does not provide LiveOut
440 bool predLive = false;
441 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
442 SIE = MBB->succ_end(); SI != SIE; ++SI) {
443 MachineBasicBlock* succMBB = *SI;
444 if (succMBB->isLiveIn(predReg)) {
451 jmpTarget = MI->getOperand(1).getMBB();
453 if (MI->getOpcode() == Hexagon::J2_jumpf ||
454 MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
455 MI->getOpcode() == Hexagon::J2_jumpfnew) {
456 invertPredicate = true;
461 // No new value jump if there is a barrier. A barrier has to be in its
462 // own packet. A barrier has zero operands. We conservatively bail out
463 // here if we see any instruction with zero operands.
464 if (foundJump && MI->getNumOperands() == 0)
469 MI->getOperand(0).isReg() &&
470 MI->getOperand(0).getReg() == predReg) {
472 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
473 if (QII->isNewValueJumpCandidate(MI)) {
475 assert((MI->getDesc().isCompare()) &&
476 "Only compare instruction can be collapsed into New Value Jump");
477 isSecondOpReg = MI->getOperand(2).isReg();
479 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
480 afterRA, jmpPos, MF))
487 // We need cmpReg1 and cmpOp2(imm or reg) while building
488 // new value jump instruction.
489 cmpReg1 = MI->getOperand(1).getReg();
490 if (MI->getOperand(1).isKill())
494 cmpOp2 = MI->getOperand(2).getReg();
495 if (MI->getOperand(2).isKill())
498 cmpOp2 = MI->getOperand(2).getImm();
503 if (foundCompare && foundJump) {
505 // If "common" checks fail, bail out on this BB.
506 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
509 bool foundFeeder = false;
510 MachineBasicBlock::iterator feederPos = MII;
511 if (MI->getOperand(0).isReg() &&
512 MI->getOperand(0).isDef() &&
513 (MI->getOperand(0).getReg() == cmpReg1 ||
515 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
517 unsigned feederReg = MI->getOperand(0).getReg();
519 // First try to see if we can get the feeder from the first operand
520 // of the compare. If we can not, and if secondOpReg is true
521 // (second operand of the compare is also register), try that one.
522 // TODO: Try to come up with some heuristic to figure out which
523 // feeder would benefit.
525 if (feederReg == cmpReg1) {
526 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
537 feederReg == (unsigned) cmpOp2)
538 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
542 // In case of CMPLT, or CMPLTU, or EQ with the second register
543 // to newify, swap the operands.
544 if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq &&
545 feederReg == (unsigned) cmpOp2) {
546 unsigned tmp = cmpReg1;
547 bool tmpIsKill = MO1IsKill;
549 MO1IsKill = MO2IsKill;
551 MO2IsKill = tmpIsKill;
554 // Now we have swapped the operands, all we need to check is,
555 // if the second operand (after swap) is the feeder.
556 // And if it is, make a note.
557 if (feederReg == (unsigned)cmpOp2)
558 isSecondOpNewified = true;
561 // Now that we are moving feeder close the jump,
562 // make sure we are respecting the kill values of
563 // the operands of the feeder.
565 bool updatedIsKill = false;
566 for (unsigned i = 0; i < MI->getNumOperands(); i++) {
567 MachineOperand &MO = MI->getOperand(i);
568 if (MO.isReg() && MO.isUse()) {
569 unsigned feederReg = MO.getReg();
570 for (MachineBasicBlock::iterator localII = feederPos,
571 end = jmpPos; localII != end; localII++) {
572 MachineInstr *localMI = localII;
573 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
574 MachineOperand &localMO = localMI->getOperand(j);
575 if (localMO.isReg() && localMO.isUse() &&
576 localMO.isKill() && feederReg == localMO.getReg()) {
577 // We found that there is kill of a use register
578 // Set up a kill flag on the register
579 localMO.setIsKill(false);
581 updatedIsKill = true;
585 if (updatedIsKill) break;
588 if (updatedIsKill) break;
591 MBB->splice(jmpPos, MI->getParent(), MI);
592 MBB->splice(jmpPos, MI->getParent(), cmpInstr);
593 DebugLoc dl = MI->getDebugLoc();
596 assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
597 "This compare is not a New Value Jump candidate.");
598 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
602 opc = QII->getInvertedPredicatedOpcode(opc);
605 NewMI = BuildMI(*MBB, jmpPos, dl,
607 .addReg(cmpReg1, getKillRegState(MO1IsKill))
608 .addReg(cmpOp2, getKillRegState(MO2IsKill))
611 else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi ||
612 cmpInstr->getOpcode() == Hexagon::C2_cmpgti) &&
614 // Corresponding new-value compare jump instructions don't have the
615 // operand for -1 immediate value.
616 NewMI = BuildMI(*MBB, jmpPos, dl,
618 .addReg(cmpReg1, getKillRegState(MO1IsKill))
622 NewMI = BuildMI(*MBB, jmpPos, dl,
624 .addReg(cmpReg1, getKillRegState(MO1IsKill))
628 assert(NewMI && "New Value Jump Instruction Not created!");
630 if (cmpInstr->getOperand(0).isReg() &&
631 cmpInstr->getOperand(0).isKill())
632 cmpInstr->getOperand(0).setIsKill(false);
633 if (cmpInstr->getOperand(1).isReg() &&
634 cmpInstr->getOperand(1).isKill())
635 cmpInstr->getOperand(1).setIsKill(false);
636 cmpInstr->eraseFromParent();
637 jmpInstr->eraseFromParent();
650 FunctionPass *llvm::createHexagonNewValueJump() {
651 return new HexagonNewValueJump();