1 //===- HexagonOperands.td - Hexagon immediate processing -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illnois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }
11 def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }
12 def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }
13 def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }
15 // Immediate operands.
17 let PrintMethod = "printImmOperand" in {
18 def s32Imm : Operand<i32>;
19 def s8Imm : Operand<i32>;
20 def s8Imm64 : Operand<i64>;
21 def s6Imm : Operand<i32>;
22 def s6_3Imm : Operand<i32>;
23 def s4Imm : Operand<i32>;
24 def s4_0Imm : Operand<i32> { let DecoderMethod = "s4_0ImmDecoder"; }
25 def s4_1Imm : Operand<i32> { let DecoderMethod = "s4_1ImmDecoder"; }
26 def s4_2Imm : Operand<i32> { let DecoderMethod = "s4_2ImmDecoder"; }
27 def s4_3Imm : Operand<i32> { let DecoderMethod = "s4_3ImmDecoder"; }
28 def u64Imm : Operand<i64>;
29 def u32Imm : Operand<i32>;
30 def u26_6Imm : Operand<i32>;
31 def u16Imm : Operand<i32>;
32 def u16_0Imm : Operand<i32>;
33 def u16_1Imm : Operand<i32>;
34 def u16_2Imm : Operand<i32>;
35 def u16_3Imm : Operand<i32>;
36 def u11_3Imm : Operand<i32>;
37 def u10Imm : Operand<i32>;
38 def u9Imm : Operand<i32>;
39 def u8Imm : Operand<i32>;
40 def u7Imm : Operand<i32>;
41 def u6Imm : Operand<i32>;
42 def u6_0Imm : Operand<i32>;
43 def u6_1Imm : Operand<i32>;
44 def u6_2Imm : Operand<i32>;
45 def u6_3Imm : Operand<i32>;
46 def u5Imm : Operand<i32>;
47 def u5_2Imm : Operand<i32>;
48 def u5_3Imm : Operand<i32>;
49 def u4Imm : Operand<i32>;
50 def u4_0Imm : Operand<i32>;
51 def u4_2Imm : Operand<i32>;
52 def u3Imm : Operand<i32>;
53 def u3_0Imm : Operand<i32>;
54 def u3_1Imm : Operand<i32>;
55 def u2Imm : Operand<i32>;
56 def u1Imm : Operand<i32>;
57 def n8Imm : Operand<i32>;
58 def m6Imm : Operand<i32>;
61 let PrintMethod = "printNOneImmOperand" in
62 def nOneImm : Operand<i32>;
65 // Immediate predicates
67 def s32ImmPred : PatLeaf<(i32 imm), [{
68 int64_t v = (int64_t)N->getSExtValue();
72 def s32_0ImmPred : PatLeaf<(i32 imm), [{
73 int64_t v = (int64_t)N->getSExtValue();
77 def s31_1ImmPred : PatLeaf<(i32 imm), [{
78 int64_t v = (int64_t)N->getSExtValue();
79 return isShiftedInt<31,1>(v);
82 def s30_2ImmPred : PatLeaf<(i32 imm), [{
83 int64_t v = (int64_t)N->getSExtValue();
84 return isShiftedInt<31,1>(v);
87 def s29_3ImmPred : PatLeaf<(i32 imm), [{
88 int64_t v = (int64_t)N->getSExtValue();
89 return isShiftedInt<31,1>(v);
92 def s22_10ImmPred : PatLeaf<(i32 imm), [{
93 int64_t v = (int64_t)N->getSExtValue();
94 return isShiftedInt<22,10>(v);
97 def s8_24ImmPred : PatLeaf<(i32 imm), [{
98 int64_t v = (int64_t)N->getSExtValue();
99 return isShiftedInt<8,24>(v);
102 def s16_16ImmPred : PatLeaf<(i32 imm), [{
103 int64_t v = (int64_t)N->getSExtValue();
104 return isShiftedInt<16,16>(v);
107 def s26_6ImmPred : PatLeaf<(i32 imm), [{
108 int64_t v = (int64_t)N->getSExtValue();
109 return isShiftedInt<26,6>(v);
112 def s16ImmPred : PatLeaf<(i32 imm), [{
113 int64_t v = (int64_t)N->getSExtValue();
117 def s13ImmPred : PatLeaf<(i32 imm), [{
118 int64_t v = (int64_t)N->getSExtValue();
122 def s12ImmPred : PatLeaf<(i32 imm), [{
123 int64_t v = (int64_t)N->getSExtValue();
127 def s11_0ImmPred : PatLeaf<(i32 imm), [{
128 int64_t v = (int64_t)N->getSExtValue();
132 def s11_1ImmPred : PatLeaf<(i32 imm), [{
133 int64_t v = (int64_t)N->getSExtValue();
134 return isShiftedInt<11,1>(v);
137 def s11_2ImmPred : PatLeaf<(i32 imm), [{
138 int64_t v = (int64_t)N->getSExtValue();
139 return isShiftedInt<11,2>(v);
142 def s11_3ImmPred : PatLeaf<(i32 imm), [{
143 int64_t v = (int64_t)N->getSExtValue();
144 return isShiftedInt<11,3>(v);
147 def s10ImmPred : PatLeaf<(i32 imm), [{
148 int64_t v = (int64_t)N->getSExtValue();
152 def s9ImmPred : PatLeaf<(i32 imm), [{
153 int64_t v = (int64_t)N->getSExtValue();
157 def m9ImmPred : PatLeaf<(i32 imm), [{
158 int64_t v = (int64_t)N->getSExtValue();
159 return isInt<9>(v) && (v != -256);
162 def s8ImmPred : PatLeaf<(i32 imm), [{
163 int64_t v = (int64_t)N->getSExtValue();
167 def s8Imm64Pred : PatLeaf<(i64 imm), [{
168 int64_t v = (int64_t)N->getSExtValue();
172 def s6ImmPred : PatLeaf<(i32 imm), [{
173 int64_t v = (int64_t)N->getSExtValue();
177 def s4_0ImmPred : PatLeaf<(i32 imm), [{
178 int64_t v = (int64_t)N->getSExtValue();
182 def s4_1ImmPred : PatLeaf<(i32 imm), [{
183 int64_t v = (int64_t)N->getSExtValue();
184 return isShiftedInt<4,1>(v);
187 def s4_2ImmPred : PatLeaf<(i32 imm), [{
188 int64_t v = (int64_t)N->getSExtValue();
189 return isShiftedInt<4,2>(v);
192 def s4_3ImmPred : PatLeaf<(i32 imm), [{
193 int64_t v = (int64_t)N->getSExtValue();
194 return isShiftedInt<4,3>(v);
198 def u64ImmPred : PatLeaf<(i64 imm), [{
199 // Adding "N ||" to suppress gcc unused warning.
203 def u32ImmPred : PatLeaf<(i32 imm), [{
204 int64_t v = (int64_t)N->getSExtValue();
205 return isUInt<32>(v);
208 def u32_0ImmPred : PatLeaf<(i32 imm), [{
209 int64_t v = (int64_t)N->getSExtValue();
210 return isUInt<32>(v);
213 def u31_1ImmPred : PatLeaf<(i32 imm), [{
214 int64_t v = (int64_t)N->getSExtValue();
215 return isShiftedUInt<31,1>(v);
218 def u30_2ImmPred : PatLeaf<(i32 imm), [{
219 int64_t v = (int64_t)N->getSExtValue();
220 return isShiftedUInt<30,2>(v);
223 def u29_3ImmPred : PatLeaf<(i32 imm), [{
224 int64_t v = (int64_t)N->getSExtValue();
225 return isShiftedUInt<29,3>(v);
228 def u26_6ImmPred : PatLeaf<(i32 imm), [{
229 int64_t v = (int64_t)N->getSExtValue();
230 return isShiftedUInt<26,6>(v);
233 def u16ImmPred : PatLeaf<(i32 imm), [{
234 int64_t v = (int64_t)N->getSExtValue();
235 return isUInt<16>(v);
238 def u16_s8ImmPred : PatLeaf<(i32 imm), [{
239 int64_t v = (int64_t)N->getSExtValue();
240 return isShiftedUInt<16,8>(v);
243 def u16_0ImmPred : PatLeaf<(i32 imm), [{
244 int64_t v = (int64_t)N->getSExtValue();
245 return isUInt<16>(v);
248 def u11_3ImmPred : PatLeaf<(i32 imm), [{
249 int64_t v = (int64_t)N->getSExtValue();
250 return isShiftedUInt<11,3>(v);
253 def u9ImmPred : PatLeaf<(i32 imm), [{
254 int64_t v = (int64_t)N->getSExtValue();
258 def u8ImmPred : PatLeaf<(i32 imm), [{
259 int64_t v = (int64_t)N->getSExtValue();
263 def u7StrictPosImmPred : ImmLeaf<i32, [{
264 // u7StrictPosImmPred predicate - True if the immediate fits in an 7-bit
265 // unsigned field and is strictly greater than 0.
266 return isUInt<7>(Imm) && Imm > 0;
269 def u7ImmPred : PatLeaf<(i32 imm), [{
270 int64_t v = (int64_t)N->getSExtValue();
274 def u6ImmPred : PatLeaf<(i32 imm), [{
275 int64_t v = (int64_t)N->getSExtValue();
279 def u6_0ImmPred : PatLeaf<(i32 imm), [{
280 int64_t v = (int64_t)N->getSExtValue();
284 def u6_1ImmPred : PatLeaf<(i32 imm), [{
285 int64_t v = (int64_t)N->getSExtValue();
286 return isShiftedUInt<6,1>(v);
289 def u6_2ImmPred : PatLeaf<(i32 imm), [{
290 int64_t v = (int64_t)N->getSExtValue();
291 return isShiftedUInt<6,2>(v);
294 def u6_3ImmPred : PatLeaf<(i32 imm), [{
295 int64_t v = (int64_t)N->getSExtValue();
296 return isShiftedUInt<6,3>(v);
299 def u5ImmPred : PatLeaf<(i32 imm), [{
300 int64_t v = (int64_t)N->getSExtValue();
304 def u4ImmPred : PatLeaf<(i32 imm), [{
305 int64_t v = (int64_t)N->getSExtValue();
309 def u3ImmPred : PatLeaf<(i32 imm), [{
310 int64_t v = (int64_t)N->getSExtValue();
314 def u2ImmPred : PatLeaf<(i32 imm), [{
315 int64_t v = (int64_t)N->getSExtValue();
319 def u1ImmPred : PatLeaf<(i1 imm), [{
320 int64_t v = (int64_t)N->getSExtValue();
324 def m5BImmPred : PatLeaf<(i32 imm), [{
325 // m5BImmPred predicate - True if the (char) number is in range -1 .. -31
326 // and will fit in a 5 bit field when made positive, for use in memops.
327 // this is specific to the zero extending of a negative by CombineInstr
328 int8_t v = (int8_t)N->getSExtValue();
329 return (-31 <= v && v <= -1);
332 def m5HImmPred : PatLeaf<(i32 imm), [{
333 // m5HImmPred predicate - True if the (short) number is in range -1 .. -31
334 // and will fit in a 5 bit field when made positive, for use in memops.
335 // this is specific to the zero extending of a negative by CombineInstr
336 int16_t v = (int16_t)N->getSExtValue();
337 return (-31 <= v && v <= -1);
340 def m5ImmPred : PatLeaf<(i32 imm), [{
341 // m5ImmPred predicate - True if the number is in range -1 .. -31
342 // and will fit in a 5 bit field when made positive, for use in memops.
343 int64_t v = (int64_t)N->getSExtValue();
344 return (-31 <= v && v <= -1);
347 //InN means negative integers in [-(2^N - 1), 0]
348 def n8ImmPred : PatLeaf<(i32 imm), [{
349 // n8ImmPred predicate - True if the immediate fits in a 8-bit signed
351 int64_t v = (int64_t)N->getSExtValue();
352 return (-255 <= v && v <= 0);
355 def nOneImmPred : PatLeaf<(i32 imm), [{
356 // nOneImmPred predicate - True if the immediate is -1.
357 int64_t v = (int64_t)N->getSExtValue();
361 def Set5ImmPred : PatLeaf<(i32 imm), [{
362 // Set5ImmPred predicate - True if the number is in the series of values.
363 // [ 2^0, 2^1, ... 2^31 ]
364 // For use in setbit immediate.
365 uint32_t v = (int32_t)N->getSExtValue();
366 // Constrain to 32 bits, and then check for single bit.
367 return ImmIsSingleBit(v);
370 def Clr5ImmPred : PatLeaf<(i32 imm), [{
371 // Clr5ImmPred predicate - True if the number is in the series of
372 // bit negated values.
373 // [ 2^0, 2^1, ... 2^31 ]
374 // For use in clrbit immediate.
375 // Note: we are bit NOTing the value.
376 uint32_t v = ~ (int32_t)N->getSExtValue();
377 // Constrain to 32 bits, and then check for single bit.
378 return ImmIsSingleBit(v);
381 def SetClr5ImmPred : PatLeaf<(i32 imm), [{
382 // SetClr5ImmPred predicate - True if the immediate is in range 0..31.
383 int32_t v = (int32_t)N->getSExtValue();
384 return (v >= 0 && v <= 31);
387 def Set4ImmPred : PatLeaf<(i32 imm), [{
388 // Set4ImmPred predicate - True if the number is in the series of values:
389 // [ 2^0, 2^1, ... 2^15 ].
390 // For use in setbit immediate.
391 uint16_t v = (int16_t)N->getSExtValue();
392 // Constrain to 16 bits, and then check for single bit.
393 return ImmIsSingleBit(v);
396 def Clr4ImmPred : PatLeaf<(i32 imm), [{
397 // Clr4ImmPred predicate - True if the number is in the series of
398 // bit negated values:
399 // [ 2^0, 2^1, ... 2^15 ].
400 // For use in setbit and clrbit immediate.
401 uint16_t v = ~ (int16_t)N->getSExtValue();
402 // Constrain to 16 bits, and then check for single bit.
403 return ImmIsSingleBit(v);
406 def SetClr4ImmPred : PatLeaf<(i32 imm), [{
407 // SetClr4ImmPred predicate - True if the immediate is in the range 0..15.
408 int16_t v = (int16_t)N->getSExtValue();
409 return (v >= 0 && v <= 15);
412 def Set3ImmPred : PatLeaf<(i32 imm), [{
413 // Set3ImmPred predicate - True if the number is in the series of values:
414 // [ 2^0, 2^1, ... 2^7 ].
415 // For use in setbit immediate.
416 uint8_t v = (int8_t)N->getSExtValue();
417 // Constrain to 8 bits, and then check for single bit.
418 return ImmIsSingleBit(v);
421 def Clr3ImmPred : PatLeaf<(i32 imm), [{
422 // Clr3ImmPred predicate - True if the number is in the series of
423 // bit negated values:
424 // [ 2^0, 2^1, ... 2^7 ].
425 // For use in setbit and clrbit immediate.
426 uint8_t v = ~ (int8_t)N->getSExtValue();
427 // Constrain to 8 bits, and then check for single bit.
428 return ImmIsSingleBit(v);
431 def SetClr3ImmPred : PatLeaf<(i32 imm), [{
432 // SetClr3ImmPred predicate - True if the immediate is in the range 0..7.
433 int8_t v = (int8_t)N->getSExtValue();
434 return (v >= 0 && v <= 7);
438 // Extendable immediate operands.
440 let PrintMethod = "printExtOperand" in {
441 def f32Ext : Operand<f32>;
442 def s16Ext : Operand<i32> { let DecoderMethod = "s16ImmDecoder"; }
443 def s12Ext : Operand<i32> { let DecoderMethod = "s12ImmDecoder"; }
444 def s11_0Ext : Operand<i32> { let DecoderMethod = "s11_0ImmDecoder"; }
445 def s11_1Ext : Operand<i32> { let DecoderMethod = "s11_1ImmDecoder"; }
446 def s11_2Ext : Operand<i32> { let DecoderMethod = "s11_2ImmDecoder"; }
447 def s11_3Ext : Operand<i32> { let DecoderMethod = "s11_3ImmDecoder"; }
448 def s10Ext : Operand<i32> { let DecoderMethod = "s10ImmDecoder"; }
449 def s9Ext : Operand<i32> { let DecoderMethod = "s90ImmDecoder"; }
450 def s8Ext : Operand<i32> { let DecoderMethod = "s8ImmDecoder"; }
451 def s7Ext : Operand<i32>;
452 def s6Ext : Operand<i32> { let DecoderMethod = "s6_0ImmDecoder"; }
453 def u6Ext : Operand<i32>;
454 def u7Ext : Operand<i32>;
455 def u8Ext : Operand<i32>;
456 def u9Ext : Operand<i32>;
457 def u10Ext : Operand<i32>;
458 def u6_0Ext : Operand<i32>;
459 def u6_1Ext : Operand<i32>;
460 def u6_2Ext : Operand<i32>;
461 def u6_3Ext : Operand<i32>;
464 def s10ExtPred : PatLeaf<(i32 imm), [{
465 int64_t v = (int64_t)N->getSExtValue();
469 // Return true if extending this immediate is profitable and the value
470 // can fit in a 32-bit signed field.
471 return isConstExtProfitable(Node) && isInt<32>(v);
474 def s8ExtPred : PatLeaf<(i32 imm), [{
475 int64_t v = (int64_t)N->getSExtValue();
479 // Return true if extending this immediate is profitable and the value
480 // can fit in a 32-bit signed field.
481 return isConstExtProfitable(Node) && isInt<32>(v);
484 def u8ExtPred : PatLeaf<(i32 imm), [{
485 int64_t v = (int64_t)N->getSExtValue();
489 // Return true if extending this immediate is profitable and the value
490 // can fit in a 32-bit unsigned field.
491 return isConstExtProfitable(Node) && isUInt<32>(v);
494 def u9ExtPred : PatLeaf<(i32 imm), [{
495 int64_t v = (int64_t)N->getSExtValue();
499 // Return true if extending this immediate is profitable and the value
500 // can fit in a 32-bit unsigned field.
501 return isConstExtProfitable(Node) && isUInt<32>(v);
505 // This complex pattern exists only to create a machine instruction operand
506 // of type "frame index". There doesn't seem to be a way to do that directly
508 def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
510 // These complex patterns are not strictly necessary, since global address
511 // folding will happen during DAG combining. For distinguishing between GA
512 // and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
513 def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
514 def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
518 let PrintMethod = "printGlobalOperand" in {
519 def globaladdress : Operand<i32>;
520 def globaladdressExt : Operand<i32>;
523 let PrintMethod = "printJumpTable" in
524 def jumptablebase : Operand<i32>;
526 def brtarget : Operand<OtherVT>;
527 def brtargetExt : Operand<OtherVT> {
528 let PrintMethod = "printExtBrtarget";
530 def calltarget : Operand<i32>;
532 def bblabel : Operand<i32>;
533 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
535 def symbolHi32 : Operand<i32> {
536 let PrintMethod = "printSymbolHi";
538 def symbolLo32 : Operand<i32> {
539 let PrintMethod = "printSymbolLo";
542 // Return true if for a 32 to 64-bit sign-extended load.
543 def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{
544 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
547 return LD->getExtensionType() == ISD::SEXTLOAD &&
548 LD->getMemoryVT().getScalarType() == MVT::i32;