1 //===- HexagonOperands.td - Hexagon immediate processing -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illnois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }
11 def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }
12 def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }
13 def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }
14 def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
15 def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
17 // Immediate operands.
19 let PrintMethod = "printImmOperand" in {
20 def s32Imm : Operand<i32>;
21 def s8Imm : Operand<i32>;
22 def s8Imm64 : Operand<i64>;
23 def s6Imm : Operand<i32>;
24 def s6_3Imm : Operand<i32>;
25 def s4Imm : Operand<i32>;
26 def s4_0Imm : Operand<i32> { let DecoderMethod = "s4_0ImmDecoder"; }
27 def s4_1Imm : Operand<i32> { let DecoderMethod = "s4_1ImmDecoder"; }
28 def s4_2Imm : Operand<i32> { let DecoderMethod = "s4_2ImmDecoder"; }
29 def s4_3Imm : Operand<i32> { let DecoderMethod = "s4_3ImmDecoder"; }
30 def u64Imm : Operand<i64>;
31 def u32Imm : Operand<i32>;
32 def u26_6Imm : Operand<i32>;
33 def u16Imm : Operand<i32>;
34 def u16_0Imm : Operand<i32>;
35 def u16_1Imm : Operand<i32>;
36 def u16_2Imm : Operand<i32>;
37 def u16_3Imm : Operand<i32>;
38 def u11_3Imm : Operand<i32>;
39 def u10Imm : Operand<i32>;
40 def u9Imm : Operand<i32>;
41 def u8Imm : Operand<i32>;
42 def u7Imm : Operand<i32>;
43 def u6Imm : Operand<i32>;
44 def u6_0Imm : Operand<i32>;
45 def u6_1Imm : Operand<i32>;
46 def u6_2Imm : Operand<i32>;
47 def u6_3Imm : Operand<i32>;
48 def u5Imm : Operand<i32>;
49 def u5_2Imm : Operand<i32>;
50 def u5_3Imm : Operand<i32>;
51 def u4Imm : Operand<i32>;
52 def u4_0Imm : Operand<i32>;
53 def u4_2Imm : Operand<i32>;
54 def u3Imm : Operand<i32>;
55 def u3_0Imm : Operand<i32>;
56 def u3_1Imm : Operand<i32>;
57 def u2Imm : Operand<i32>;
58 def u1Imm : Operand<i32>;
59 def n8Imm : Operand<i32>;
60 def m6Imm : Operand<i32>;
63 let OperandType = "OPERAND_IMMEDIATE" in {
64 def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand;
65 let PrintMethod = "prints4_6ImmOperand";
66 let DecoderMethod = "s4_6ImmDecoder";}
67 def s4_7Imm : Operand<i32> { let PrintMethod = "prints4_7ImmOperand";
68 let DecoderMethod = "s4_6ImmDecoder";}
69 def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand;
70 let PrintMethod = "prints3_6ImmOperand";
71 let DecoderMethod = "s3_6ImmDecoder";}
72 def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand";
73 let DecoderMethod = "s3_6ImmDecoder";}
76 let PrintMethod = "printNOneImmOperand" in
77 def nOneImm : Operand<i32>;
80 // Immediate predicates
82 def s32ImmPred : PatLeaf<(i32 imm), [{
83 int64_t v = (int64_t)N->getSExtValue();
87 def s32_0ImmPred : PatLeaf<(i32 imm), [{
88 int64_t v = (int64_t)N->getSExtValue();
92 def s31_1ImmPred : PatLeaf<(i32 imm), [{
93 int64_t v = (int64_t)N->getSExtValue();
94 return isShiftedInt<31,1>(v);
97 def s30_2ImmPred : PatLeaf<(i32 imm), [{
98 int64_t v = (int64_t)N->getSExtValue();
99 return isShiftedInt<30,2>(v);
102 def s29_3ImmPred : PatLeaf<(i32 imm), [{
103 int64_t v = (int64_t)N->getSExtValue();
104 return isShiftedInt<29,3>(v);
107 def s16ImmPred : PatLeaf<(i32 imm), [{
108 int64_t v = (int64_t)N->getSExtValue();
112 def s11_0ImmPred : PatLeaf<(i32 imm), [{
113 int64_t v = (int64_t)N->getSExtValue();
117 def s11_1ImmPred : PatLeaf<(i32 imm), [{
118 int64_t v = (int64_t)N->getSExtValue();
119 return isShiftedInt<11,1>(v);
122 def s11_2ImmPred : PatLeaf<(i32 imm), [{
123 int64_t v = (int64_t)N->getSExtValue();
124 return isShiftedInt<11,2>(v);
127 def s11_3ImmPred : PatLeaf<(i32 imm), [{
128 int64_t v = (int64_t)N->getSExtValue();
129 return isShiftedInt<11,3>(v);
132 def s10ImmPred : PatLeaf<(i32 imm), [{
133 int64_t v = (int64_t)N->getSExtValue();
137 def s8ImmPred : PatLeaf<(i32 imm), [{
138 int64_t v = (int64_t)N->getSExtValue();
142 def s8Imm64Pred : PatLeaf<(i64 imm), [{
143 int64_t v = (int64_t)N->getSExtValue();
147 def s6ImmPred : PatLeaf<(i32 imm), [{
148 int64_t v = (int64_t)N->getSExtValue();
152 def s4_0ImmPred : PatLeaf<(i32 imm), [{
153 int64_t v = (int64_t)N->getSExtValue();
157 def s4_1ImmPred : PatLeaf<(i32 imm), [{
158 int64_t v = (int64_t)N->getSExtValue();
159 return isShiftedInt<4,1>(v);
162 def s4_2ImmPred : PatLeaf<(i32 imm), [{
163 int64_t v = (int64_t)N->getSExtValue();
164 return isShiftedInt<4,2>(v);
167 def s4_3ImmPred : PatLeaf<(i32 imm), [{
168 int64_t v = (int64_t)N->getSExtValue();
169 return isShiftedInt<4,3>(v);
173 def u64ImmPred : PatLeaf<(i64 imm), [{
174 // Adding "N ||" to suppress gcc unused warning.
178 def u32ImmPred : PatLeaf<(i32 imm), [{
179 int64_t v = (int64_t)N->getSExtValue();
180 return isUInt<32>(v);
183 def u32_0ImmPred : PatLeaf<(i32 imm), [{
184 int64_t v = (int64_t)N->getSExtValue();
185 return isUInt<32>(v);
188 def u31_1ImmPred : PatLeaf<(i32 imm), [{
189 int64_t v = (int64_t)N->getSExtValue();
190 return isShiftedUInt<31,1>(v);
193 def u30_2ImmPred : PatLeaf<(i32 imm), [{
194 int64_t v = (int64_t)N->getSExtValue();
195 return isShiftedUInt<30,2>(v);
198 def u29_3ImmPred : PatLeaf<(i32 imm), [{
199 int64_t v = (int64_t)N->getSExtValue();
200 return isShiftedUInt<29,3>(v);
203 def u26_6ImmPred : PatLeaf<(i32 imm), [{
204 int64_t v = (int64_t)N->getSExtValue();
205 return isShiftedUInt<26,6>(v);
208 def u16_0ImmPred : PatLeaf<(i32 imm), [{
209 int64_t v = (int64_t)N->getSExtValue();
210 return isUInt<16>(v);
213 def u16_1ImmPred : PatLeaf<(i32 imm), [{
214 int64_t v = (int64_t)N->getSExtValue();
215 return isShiftedUInt<16,1>(v);
218 def u16_2ImmPred : PatLeaf<(i32 imm), [{
219 int64_t v = (int64_t)N->getSExtValue();
220 return isShiftedUInt<16,2>(v);
223 def u11_3ImmPred : PatLeaf<(i32 imm), [{
224 int64_t v = (int64_t)N->getSExtValue();
225 return isShiftedUInt<11,3>(v);
228 def u9ImmPred : PatLeaf<(i32 imm), [{
229 int64_t v = (int64_t)N->getSExtValue();
233 def u8ImmPred : PatLeaf<(i32 imm), [{
234 int64_t v = (int64_t)N->getSExtValue();
238 def u7StrictPosImmPred : ImmLeaf<i32, [{
239 // u7StrictPosImmPred predicate - True if the immediate fits in an 7-bit
240 // unsigned field and is strictly greater than 0.
241 return isUInt<7>(Imm) && Imm > 0;
244 def u7ImmPred : PatLeaf<(i32 imm), [{
245 int64_t v = (int64_t)N->getSExtValue();
249 def u6ImmPred : PatLeaf<(i32 imm), [{
250 int64_t v = (int64_t)N->getSExtValue();
254 def u6_0ImmPred : PatLeaf<(i32 imm), [{
255 int64_t v = (int64_t)N->getSExtValue();
259 def u6_1ImmPred : PatLeaf<(i32 imm), [{
260 int64_t v = (int64_t)N->getSExtValue();
261 return isShiftedUInt<6,1>(v);
264 def u6_2ImmPred : PatLeaf<(i32 imm), [{
265 int64_t v = (int64_t)N->getSExtValue();
266 return isShiftedUInt<6,2>(v);
269 def u6_3ImmPred : PatLeaf<(i32 imm), [{
270 int64_t v = (int64_t)N->getSExtValue();
271 return isShiftedUInt<6,3>(v);
274 def u5ImmPred : PatLeaf<(i32 imm), [{
275 int64_t v = (int64_t)N->getSExtValue();
279 def u4ImmPred : PatLeaf<(i32 imm), [{
280 int64_t v = (int64_t)N->getSExtValue();
284 def u3ImmPred : PatLeaf<(i32 imm), [{
285 int64_t v = (int64_t)N->getSExtValue();
289 def u2ImmPred : PatLeaf<(i32 imm), [{
290 int64_t v = (int64_t)N->getSExtValue();
294 def u1ImmPred : PatLeaf<(i1 imm), [{
295 int64_t v = (int64_t)N->getSExtValue();
299 def m5BImmPred : PatLeaf<(i32 imm), [{
300 // m5BImmPred predicate - True if the (char) number is in range -1 .. -31
301 // and will fit in a 5 bit field when made positive, for use in memops.
302 // this is specific to the zero extending of a negative by CombineInstr
303 int8_t v = (int8_t)N->getSExtValue();
304 return (-31 <= v && v <= -1);
307 def m5HImmPred : PatLeaf<(i32 imm), [{
308 // m5HImmPred predicate - True if the (short) number is in range -1 .. -31
309 // and will fit in a 5 bit field when made positive, for use in memops.
310 // this is specific to the zero extending of a negative by CombineInstr
311 int16_t v = (int16_t)N->getSExtValue();
312 return (-31 <= v && v <= -1);
315 def m5ImmPred : PatLeaf<(i32 imm), [{
316 // m5ImmPred predicate - True if the number is in range -1 .. -31
317 // and will fit in a 5 bit field when made positive, for use in memops.
318 int64_t v = (int64_t)N->getSExtValue();
319 return (-31 <= v && v <= -1);
322 //InN means negative integers in [-(2^N - 1), 0]
323 def n8ImmPred : PatLeaf<(i32 imm), [{
324 // n8ImmPred predicate - True if the immediate fits in a 8-bit signed
326 int64_t v = (int64_t)N->getSExtValue();
327 return (-255 <= v && v <= 0);
330 def nOneImmPred : PatLeaf<(i32 imm), [{
331 // nOneImmPred predicate - True if the immediate is -1.
332 int64_t v = (int64_t)N->getSExtValue();
336 def Set5ImmPred : PatLeaf<(i32 imm), [{
337 // Set5ImmPred predicate - True if the number is in the series of values.
338 // [ 2^0, 2^1, ... 2^31 ]
339 // For use in setbit immediate.
340 uint32_t v = (int32_t)N->getSExtValue();
341 // Constrain to 32 bits, and then check for single bit.
342 return ImmIsSingleBit(v);
345 def Clr5ImmPred : PatLeaf<(i32 imm), [{
346 // Clr5ImmPred predicate - True if the number is in the series of
347 // bit negated values.
348 // [ 2^0, 2^1, ... 2^31 ]
349 // For use in clrbit immediate.
350 // Note: we are bit NOTing the value.
351 uint32_t v = ~ (int32_t)N->getSExtValue();
352 // Constrain to 32 bits, and then check for single bit.
353 return ImmIsSingleBit(v);
356 def SetClr5ImmPred : PatLeaf<(i32 imm), [{
357 // True if the immediate is in range 0..31.
358 int32_t v = (int32_t)N->getSExtValue();
359 return (v >= 0 && v <= 31);
362 def Set4ImmPred : PatLeaf<(i32 imm), [{
363 // Set4ImmPred predicate - True if the number is in the series of values:
364 // [ 2^0, 2^1, ... 2^15 ].
365 // For use in setbit immediate.
366 uint16_t v = (int16_t)N->getSExtValue();
367 // Constrain to 16 bits, and then check for single bit.
368 return ImmIsSingleBit(v);
371 def Clr4ImmPred : PatLeaf<(i32 imm), [{
372 // Clr4ImmPred predicate - True if the number is in the series of
373 // bit negated values:
374 // [ 2^0, 2^1, ... 2^15 ].
375 // For use in setbit and clrbit immediate.
376 uint16_t v = ~ (int16_t)N->getSExtValue();
377 // Constrain to 16 bits, and then check for single bit.
378 return ImmIsSingleBit(v);
381 def SetClr4ImmPred : PatLeaf<(i32 imm), [{
382 // True if the immediate is in the range 0..15.
383 int16_t v = (int16_t)N->getSExtValue();
384 return (v >= 0 && v <= 15);
387 def Set3ImmPred : PatLeaf<(i32 imm), [{
388 // True if the number is in the series of values: [ 2^0, 2^1, ... 2^7 ].
389 // For use in setbit immediate.
390 uint8_t v = (int8_t)N->getSExtValue();
391 // Constrain to 8 bits, and then check for single bit.
392 return ImmIsSingleBit(v);
395 def Clr3ImmPred : PatLeaf<(i32 imm), [{
396 // True if the number is in the series of bit negated values: [ 2^0, 2^1, ... 2^7 ].
397 // For use in setbit and clrbit immediate.
398 uint8_t v = ~ (int8_t)N->getSExtValue();
399 // Constrain to 8 bits, and then check for single bit.
400 return ImmIsSingleBit(v);
403 def SetClr3ImmPred : PatLeaf<(i32 imm), [{
404 // True if the immediate is in the range 0..7.
405 int8_t v = (int8_t)N->getSExtValue();
406 return (v >= 0 && v <= 7);
410 // Extendable immediate operands.
412 let PrintMethod = "printExtOperand" in {
413 def f32Ext : Operand<f32>;
414 def s16Ext : Operand<i32> { let DecoderMethod = "s16ImmDecoder"; }
415 def s12Ext : Operand<i32> { let DecoderMethod = "s12ImmDecoder"; }
416 def s11_0Ext : Operand<i32> { let DecoderMethod = "s11_0ImmDecoder"; }
417 def s11_1Ext : Operand<i32> { let DecoderMethod = "s11_1ImmDecoder"; }
418 def s11_2Ext : Operand<i32> { let DecoderMethod = "s11_2ImmDecoder"; }
419 def s11_3Ext : Operand<i32> { let DecoderMethod = "s11_3ImmDecoder"; }
420 def s10Ext : Operand<i32> { let DecoderMethod = "s10ImmDecoder"; }
421 def s9Ext : Operand<i32> { let DecoderMethod = "s90ImmDecoder"; }
422 def s8Ext : Operand<i32> { let DecoderMethod = "s8ImmDecoder"; }
423 def s7Ext : Operand<i32>;
424 def s6Ext : Operand<i32> { let DecoderMethod = "s6_0ImmDecoder"; }
425 def u6Ext : Operand<i32>;
426 def u7Ext : Operand<i32>;
427 def u8Ext : Operand<i32>;
428 def u9Ext : Operand<i32>;
429 def u10Ext : Operand<i32>;
430 def u6_0Ext : Operand<i32>;
431 def u6_1Ext : Operand<i32>;
432 def u6_2Ext : Operand<i32>;
433 def u6_3Ext : Operand<i32>;
437 def s4_7ImmPred : PatLeaf<(i32 imm), [{
438 int64_t v = (int64_t)N->getSExtValue();
439 if (HST->hasV60TOps())
440 // Return true if the immediate can fit in a 10-bit sign extended field and
441 // is 128-byte aligned.
442 return isShiftedInt<4,7>(v);
446 def s3_7ImmPred : PatLeaf<(i32 imm), [{
447 int64_t v = (int64_t)N->getSExtValue();
448 if (HST->hasV60TOps())
449 // Return true if the immediate can fit in a 9-bit sign extended field and
450 // is 128-byte aligned.
451 return isShiftedInt<3,7>(v);
455 def s4_6ImmPred : PatLeaf<(i32 imm), [{
456 int64_t v = (int64_t)N->getSExtValue();
457 if (HST->hasV60TOps())
458 // Return true if the immediate can fit in a 10-bit sign extended field and
459 // is 64-byte aligned.
460 return isShiftedInt<4,6>(v);
464 def s3_6ImmPred : PatLeaf<(i32 imm), [{
465 int64_t v = (int64_t)N->getSExtValue();
466 if (HST->hasV60TOps())
467 // Return true if the immediate can fit in a 9-bit sign extended field and
468 // is 64-byte aligned.
469 return isShiftedInt<3,6>(v);
474 // This complex pattern exists only to create a machine instruction operand
475 // of type "frame index". There doesn't seem to be a way to do that directly
477 def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
479 // These complex patterns are not strictly necessary, since global address
480 // folding will happen during DAG combining. For distinguishing between GA
481 // and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
482 def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
483 def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
487 let PrintMethod = "printGlobalOperand" in {
488 def globaladdress : Operand<i32>;
489 def globaladdressExt : Operand<i32>;
492 let PrintMethod = "printJumpTable" in
493 def jumptablebase : Operand<i32>;
495 def brtarget : Operand<OtherVT>;
496 def brtargetExt : Operand<OtherVT> {
497 let PrintMethod = "printExtBrtarget";
499 def calltarget : Operand<i32>;
501 def bblabel : Operand<i32>;
502 def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
504 def symbolHi32 : Operand<i32> {
505 let PrintMethod = "printSymbolHi";
507 def symbolLo32 : Operand<i32> {
508 let PrintMethod = "printSymbolLo";
511 // Return true if for a 32 to 64-bit sign-extended load.
512 def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{
513 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
516 return LD->getExtensionType() == ISD::SEXTLOAD &&
517 LD->getMemoryVT().getScalarType() == MVT::i32;