1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 // Transform the following pattern
11 // %vreg170<def> = SXTW %vreg166
13 // %vreg176<def> = COPY %vreg170:subreg_loreg
16 // %vreg176<def> = COPY vreg166
18 // 2. Optimizes redundant negation of predicates.
19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2
21 // %vreg16<def> = NOT_p %vreg15<kill>
23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2;
28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instrucions, like
33 // DCE or DIE to actually eliminate them.
36 //===----------------------------------------------------------------------===//
38 #define DEBUG_TYPE "hexagon-peephole"
39 #include "llvm/Constants.h"
40 #include "llvm/PassSupport.h"
41 #include "llvm/ADT/DenseMap.h"
42 #include "llvm/ADT/Statistic.h"
43 #include "llvm/CodeGen/Passes.h"
44 #include "llvm/CodeGen/MachineFunction.h"
45 #include "llvm/CodeGen/MachineFunctionPass.h"
46 #include "llvm/CodeGen/MachineInstrBuilder.h"
47 #include "llvm/CodeGen/MachineRegisterInfo.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetMachine.h"
51 #include "llvm/Target/TargetRegisterInfo.h"
52 #include "llvm/Target/TargetInstrInfo.h"
55 #include "HexagonTargetMachine.h"
57 #include "llvm/Support/CommandLine.h"
61 cl::opt<int> DebugHexagonPeephole("debug-hexagon-peephole",
62 cl::Hidden, cl::desc(""));
64 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
65 cl::Hidden, cl::ZeroOrMore, cl::init(false),
66 cl::desc("Disable Peephole Optimization"));
69 DbgPNPCount("pnp-count", cl::init(-1), cl::Hidden,
70 cl::desc("Maximum number of P=NOT(P) to be optimized"));
72 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
73 cl::Hidden, cl::ZeroOrMore, cl::init(false),
74 cl::desc("Disable Optimization of PNotP"));
76 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
77 cl::Hidden, cl::ZeroOrMore, cl::init(false),
78 cl::desc("Disable Optimization of Sign/Zero Extends"));
81 struct HexagonPeephole : public MachineFunctionPass {
82 const HexagonInstrInfo *QII;
83 const HexagonRegisterInfo *QRI;
84 const MachineRegisterInfo *MRI;
88 HexagonPeephole() : MachineFunctionPass(ID) { }
90 bool runOnMachineFunction(MachineFunction &MF);
92 const char *getPassName() const {
93 return "Hexagon optimize redundant zero and size extends";
96 void getAnalysisUsage(AnalysisUsage &AU) const {
97 MachineFunctionPass::getAnalysisUsage(AU);
101 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
105 char HexagonPeephole::ID = 0;
107 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
109 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().
111 QRI = static_cast<const HexagonRegisterInfo *>(MF.getTarget().
113 MRI = &MF.getRegInfo();
115 DenseMap<unsigned, unsigned> PeepholeMap;
117 if (DisableHexagonPeephole) return false;
119 // Loop over all of the basic blocks.
120 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
121 MBBb != MBBe; ++MBBb) {
122 MachineBasicBlock* MBB = MBBb;
125 // Traverse the basic block.
126 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
128 MachineInstr *MI = MII;
129 // Look for sign extends:
130 // %vreg170<def> = SXTW %vreg166
131 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
132 assert (MI->getNumOperands() == 2);
133 MachineOperand &Dst = MI->getOperand(0);
134 MachineOperand &Src = MI->getOperand(1);
135 unsigned DstReg = Dst.getReg();
136 unsigned SrcReg = Src.getReg();
137 // Just handle virtual registers.
138 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
139 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
140 // Map the following:
141 // %vreg170<def> = SXTW %vreg166
142 // PeepholeMap[170] = vreg166
143 PeepholeMap[DstReg] = SrcReg;
147 // Look for P=NOT(P).
149 (MI->getOpcode() == Hexagon::NOT_p)) {
150 assert (MI->getNumOperands() == 2);
151 MachineOperand &Dst = MI->getOperand(0);
152 MachineOperand &Src = MI->getOperand(1);
153 unsigned DstReg = Dst.getReg();
154 unsigned SrcReg = Src.getReg();
155 // Just handle virtual registers.
156 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
157 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
158 // Map the following:
159 // %vreg170<def> = NOT_xx %vreg166
160 // PeepholeMap[170] = vreg166
161 PeepholeMap[DstReg] = SrcReg;
166 // %vreg176<def> = COPY %vreg170:subreg_loreg
167 if (!DisableOptSZExt && MI->isCopy()) {
168 assert (MI->getNumOperands() == 2);
169 MachineOperand &Dst = MI->getOperand(0);
170 MachineOperand &Src = MI->getOperand(1);
172 // Make sure we are copying the lower 32 bits.
173 if (Src.getSubReg() != Hexagon::subreg_loreg)
176 unsigned DstReg = Dst.getReg();
177 unsigned SrcReg = Src.getReg();
178 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
179 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
180 // Try to find in the map.
181 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
182 // Change the 1st operand.
183 MI->RemoveOperand(1);
184 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
189 // Look for Predicated instructions.
192 if (QII->isPredicated(MI)) {
193 MachineOperand &Op0 = MI->getOperand(0);
194 unsigned Reg0 = Op0.getReg();
195 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
196 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
197 // Handle instructions that have a prediate register in op0
198 // (most cases of predicable instructions).
199 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
200 // Try to find in the map.
201 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
202 // Change the 1st operand and, flip the opcode.
203 MI->getOperand(0).setReg(PeepholeSrc);
204 int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
205 MI->setDesc(QII->get(NewOp));
213 // Handle special instructions.
214 unsigned Op = MI->getOpcode();
216 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
219 case Hexagon::TFR_condset_rr:
220 case Hexagon::TFR_condset_ii:
221 case Hexagon::MUX_ii:
222 case Hexagon::MUX_rr:
225 case Hexagon::TFR_condset_ri:
226 NewOp = Hexagon::TFR_condset_ir;
228 case Hexagon::TFR_condset_ir:
229 NewOp = Hexagon::TFR_condset_ri;
231 case Hexagon::MUX_ri:
232 NewOp = Hexagon::MUX_ir;
234 case Hexagon::MUX_ir:
235 NewOp = Hexagon::MUX_ri;
239 unsigned PSrc = MI->getOperand(PR).getReg();
240 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
241 MI->getOperand(PR).setReg(POrig);
242 MI->setDesc(QII->get(NewOp));
243 // Swap operands S1 and S2.
244 MachineOperand Op1 = MI->getOperand(S1);
245 MachineOperand Op2 = MI->getOperand(S2);
246 ChangeOpInto(MI->getOperand(S1), Op2);
247 ChangeOpInto(MI->getOperand(S2), Op1);
252 } // if (!DisablePNotP)
259 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
260 assert (&Dst != &Src && "Cannot duplicate into itself");
261 switch (Dst.getType()) {
262 case MachineOperand::MO_Register:
264 Dst.setReg(Src.getReg());
265 } else if (Src.isImm()) {
266 Dst.ChangeToImmediate(Src.getImm());
268 llvm_unreachable("Unexpected src operand type");
272 case MachineOperand::MO_Immediate:
274 Dst.setImm(Src.getImm());
275 } else if (Src.isReg()) {
276 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
277 Src.isKill(), Src.isDead(), Src.isUndef(),
280 llvm_unreachable("Unexpected src operand type");
285 llvm_unreachable("Unexpected dst operand type");
290 FunctionPass *llvm::createHexagonPeephole() {
291 return new HexagonPeephole();