1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 // Transform the following pattern
11 // %vreg170<def> = SXTW %vreg166
13 // %vreg176<def> = COPY %vreg170:subreg_loreg
16 // %vreg176<def> = COPY vreg166
18 // 2. Optimizes redundant negation of predicates.
19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2
21 // %vreg16<def> = NOT_p %vreg15<kill>
23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2;
28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instrucions, like
33 // DCE or DIE to actually eliminate them.
36 //===----------------------------------------------------------------------===//
38 #define DEBUG_TYPE "hexagon-peephole"
40 #include "HexagonTargetMachine.h"
41 #include "llvm/Constants.h"
42 #include "llvm/PassSupport.h"
43 #include "llvm/ADT/DenseMap.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/CodeGen/Passes.h"
46 #include "llvm/CodeGen/MachineFunction.h"
47 #include "llvm/CodeGen/MachineFunctionPass.h"
48 #include "llvm/CodeGen/MachineInstrBuilder.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
55 #include "llvm/Target/TargetInstrInfo.h"
60 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
61 cl::Hidden, cl::ZeroOrMore, cl::init(false),
62 cl::desc("Disable Peephole Optimization"));
65 DbgPNPCount("pnp-count", cl::init(-1), cl::Hidden,
66 cl::desc("Maximum number of P=NOT(P) to be optimized"));
68 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
69 cl::Hidden, cl::ZeroOrMore, cl::init(false),
70 cl::desc("Disable Optimization of PNotP"));
72 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
73 cl::Hidden, cl::ZeroOrMore, cl::init(false),
74 cl::desc("Disable Optimization of Sign/Zero Extends"));
77 struct HexagonPeephole : public MachineFunctionPass {
78 const HexagonInstrInfo *QII;
79 const HexagonRegisterInfo *QRI;
80 const MachineRegisterInfo *MRI;
84 HexagonPeephole() : MachineFunctionPass(ID) { }
86 bool runOnMachineFunction(MachineFunction &MF);
88 const char *getPassName() const {
89 return "Hexagon optimize redundant zero and size extends";
92 void getAnalysisUsage(AnalysisUsage &AU) const {
93 MachineFunctionPass::getAnalysisUsage(AU);
97 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
101 char HexagonPeephole::ID = 0;
103 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
105 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().
107 QRI = static_cast<const HexagonRegisterInfo *>(MF.getTarget().
109 MRI = &MF.getRegInfo();
111 DenseMap<unsigned, unsigned> PeepholeMap;
113 if (DisableHexagonPeephole) return false;
115 // Loop over all of the basic blocks.
116 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
117 MBBb != MBBe; ++MBBb) {
118 MachineBasicBlock* MBB = MBBb;
121 // Traverse the basic block.
122 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
124 MachineInstr *MI = MII;
125 // Look for sign extends:
126 // %vreg170<def> = SXTW %vreg166
127 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
128 assert (MI->getNumOperands() == 2);
129 MachineOperand &Dst = MI->getOperand(0);
130 MachineOperand &Src = MI->getOperand(1);
131 unsigned DstReg = Dst.getReg();
132 unsigned SrcReg = Src.getReg();
133 // Just handle virtual registers.
134 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
135 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
136 // Map the following:
137 // %vreg170<def> = SXTW %vreg166
138 // PeepholeMap[170] = vreg166
139 PeepholeMap[DstReg] = SrcReg;
143 // Look for P=NOT(P).
145 (MI->getOpcode() == Hexagon::NOT_p)) {
146 assert (MI->getNumOperands() == 2);
147 MachineOperand &Dst = MI->getOperand(0);
148 MachineOperand &Src = MI->getOperand(1);
149 unsigned DstReg = Dst.getReg();
150 unsigned SrcReg = Src.getReg();
151 // Just handle virtual registers.
152 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
153 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
154 // Map the following:
155 // %vreg170<def> = NOT_xx %vreg166
156 // PeepholeMap[170] = vreg166
157 PeepholeMap[DstReg] = SrcReg;
162 // %vreg176<def> = COPY %vreg170:subreg_loreg
163 if (!DisableOptSZExt && MI->isCopy()) {
164 assert (MI->getNumOperands() == 2);
165 MachineOperand &Dst = MI->getOperand(0);
166 MachineOperand &Src = MI->getOperand(1);
168 // Make sure we are copying the lower 32 bits.
169 if (Src.getSubReg() != Hexagon::subreg_loreg)
172 unsigned DstReg = Dst.getReg();
173 unsigned SrcReg = Src.getReg();
174 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
175 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
176 // Try to find in the map.
177 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
178 // Change the 1st operand.
179 MI->RemoveOperand(1);
180 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
185 // Look for Predicated instructions.
188 if (QII->isPredicated(MI)) {
189 MachineOperand &Op0 = MI->getOperand(0);
190 unsigned Reg0 = Op0.getReg();
191 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
192 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
193 // Handle instructions that have a prediate register in op0
194 // (most cases of predicable instructions).
195 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
196 // Try to find in the map.
197 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
198 // Change the 1st operand and, flip the opcode.
199 MI->getOperand(0).setReg(PeepholeSrc);
200 int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
201 MI->setDesc(QII->get(NewOp));
209 // Handle special instructions.
210 unsigned Op = MI->getOpcode();
212 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
215 case Hexagon::TFR_condset_rr:
216 case Hexagon::TFR_condset_ii:
217 case Hexagon::MUX_ii:
218 case Hexagon::MUX_rr:
221 case Hexagon::TFR_condset_ri:
222 NewOp = Hexagon::TFR_condset_ir;
224 case Hexagon::TFR_condset_ir:
225 NewOp = Hexagon::TFR_condset_ri;
227 case Hexagon::MUX_ri:
228 NewOp = Hexagon::MUX_ir;
230 case Hexagon::MUX_ir:
231 NewOp = Hexagon::MUX_ri;
235 unsigned PSrc = MI->getOperand(PR).getReg();
236 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
237 MI->getOperand(PR).setReg(POrig);
238 MI->setDesc(QII->get(NewOp));
239 // Swap operands S1 and S2.
240 MachineOperand Op1 = MI->getOperand(S1);
241 MachineOperand Op2 = MI->getOperand(S2);
242 ChangeOpInto(MI->getOperand(S1), Op2);
243 ChangeOpInto(MI->getOperand(S2), Op1);
248 } // if (!DisablePNotP)
255 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
256 assert (&Dst != &Src && "Cannot duplicate into itself");
257 switch (Dst.getType()) {
258 case MachineOperand::MO_Register:
260 Dst.setReg(Src.getReg());
261 } else if (Src.isImm()) {
262 Dst.ChangeToImmediate(Src.getImm());
264 llvm_unreachable("Unexpected src operand type");
268 case MachineOperand::MO_Immediate:
270 Dst.setImm(Src.getImm());
271 } else if (Src.isReg()) {
272 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
273 Src.isKill(), Src.isDead(), Src.isUndef(),
276 llvm_unreachable("Unexpected src operand type");
281 llvm_unreachable("Unexpected dst operand type");
286 FunctionPass *llvm::createHexagonPeephole() {
287 return new HexagonPeephole();