1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 // Transform the following pattern
11 // %vreg170<def> = SXTW %vreg166
13 // %vreg176<def> = COPY %vreg170:subreg_loreg
16 // %vreg176<def> = COPY vreg166
18 // 2. Optimizes redundant negation of predicates.
19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2
21 // %vreg16<def> = NOT_p %vreg15<kill>
23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2;
28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instructions, like
33 // DCE or DIE to actually eliminate them.
36 //===----------------------------------------------------------------------===//
39 #include "HexagonTargetMachine.h"
40 #include "llvm/ADT/DenseMap.h"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/MachineFunction.h"
43 #include "llvm/CodeGen/MachineFunctionPass.h"
44 #include "llvm/CodeGen/MachineInstrBuilder.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/IR/Constants.h"
48 #include "llvm/PassSupport.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
59 #define DEBUG_TYPE "hexagon-peephole"
61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
62 cl::Hidden, cl::ZeroOrMore, cl::init(false),
63 cl::desc("Disable Peephole Optimization"));
65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
66 cl::Hidden, cl::ZeroOrMore, cl::init(false),
67 cl::desc("Disable Optimization of PNotP"));
69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
70 cl::Hidden, cl::ZeroOrMore, cl::init(false),
71 cl::desc("Disable Optimization of Sign/Zero Extends"));
73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
74 cl::Hidden, cl::ZeroOrMore, cl::init(false),
75 cl::desc("Disable Optimization of extensions to i64."));
78 void initializeHexagonPeepholePass(PassRegistry&);
82 struct HexagonPeephole : public MachineFunctionPass {
83 const HexagonInstrInfo *QII;
84 const HexagonRegisterInfo *QRI;
85 const MachineRegisterInfo *MRI;
89 HexagonPeephole() : MachineFunctionPass(ID) {
90 initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
93 bool runOnMachineFunction(MachineFunction &MF) override;
95 const char *getPassName() const override {
96 return "Hexagon optimize redundant zero and size extends";
99 void getAnalysisUsage(AnalysisUsage &AU) const override {
100 MachineFunctionPass::getAnalysisUsage(AU);
104 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
108 char HexagonPeephole::ID = 0;
110 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
113 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
114 QII = static_cast<const HexagonInstrInfo *>(
115 MF.getTarget().getSubtargetImpl()->getInstrInfo());
116 QRI = MF.getTarget().getSubtarget<HexagonSubtarget>().getRegisterInfo();
117 MRI = &MF.getRegInfo();
119 DenseMap<unsigned, unsigned> PeepholeMap;
120 DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
122 if (DisableHexagonPeephole) return false;
124 // Loop over all of the basic blocks.
125 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
126 MBBb != MBBe; ++MBBb) {
127 MachineBasicBlock* MBB = MBBb;
129 PeepholeDoubleRegsMap.clear();
131 // Traverse the basic block.
132 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
134 MachineInstr *MI = MII;
135 // Look for sign extends:
136 // %vreg170<def> = SXTW %vreg166
137 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
138 assert (MI->getNumOperands() == 2);
139 MachineOperand &Dst = MI->getOperand(0);
140 MachineOperand &Src = MI->getOperand(1);
141 unsigned DstReg = Dst.getReg();
142 unsigned SrcReg = Src.getReg();
143 // Just handle virtual registers.
144 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
145 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
146 // Map the following:
147 // %vreg170<def> = SXTW %vreg166
148 // PeepholeMap[170] = vreg166
149 PeepholeMap[DstReg] = SrcReg;
153 // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
154 // %vreg170:DoublRegs, %vreg169:IntRegs
155 if (!DisableOptExtTo64 &&
156 MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
157 assert (MI->getNumOperands() == 3);
158 MachineOperand &Dst = MI->getOperand(0);
159 MachineOperand &Src1 = MI->getOperand(1);
160 MachineOperand &Src2 = MI->getOperand(2);
161 if (Src1.getImm() != 0)
163 unsigned DstReg = Dst.getReg();
164 unsigned SrcReg = Src2.getReg();
165 PeepholeMap[DstReg] = SrcReg;
168 // Look for this sequence below
169 // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
170 // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
172 // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
173 if (MI->getOpcode() == Hexagon::LSRd_ri) {
174 assert(MI->getNumOperands() == 3);
175 MachineOperand &Dst = MI->getOperand(0);
176 MachineOperand &Src1 = MI->getOperand(1);
177 MachineOperand &Src2 = MI->getOperand(2);
178 if (Src2.getImm() != 32)
180 unsigned DstReg = Dst.getReg();
181 unsigned SrcReg = Src1.getReg();
182 PeepholeDoubleRegsMap[DstReg] =
183 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
186 // Look for P=NOT(P).
188 (MI->getOpcode() == Hexagon::NOT_p)) {
189 assert (MI->getNumOperands() == 2);
190 MachineOperand &Dst = MI->getOperand(0);
191 MachineOperand &Src = MI->getOperand(1);
192 unsigned DstReg = Dst.getReg();
193 unsigned SrcReg = Src.getReg();
194 // Just handle virtual registers.
195 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
196 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
197 // Map the following:
198 // %vreg170<def> = NOT_xx %vreg166
199 // PeepholeMap[170] = vreg166
200 PeepholeMap[DstReg] = SrcReg;
205 // %vreg176<def> = COPY %vreg170:subreg_loreg
206 if (!DisableOptSZExt && MI->isCopy()) {
207 assert (MI->getNumOperands() == 2);
208 MachineOperand &Dst = MI->getOperand(0);
209 MachineOperand &Src = MI->getOperand(1);
211 // Make sure we are copying the lower 32 bits.
212 if (Src.getSubReg() != Hexagon::subreg_loreg)
215 unsigned DstReg = Dst.getReg();
216 unsigned SrcReg = Src.getReg();
217 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
218 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
219 // Try to find in the map.
220 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
221 // Change the 1st operand.
222 MI->RemoveOperand(1);
223 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
225 DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
226 PeepholeDoubleRegsMap.find(SrcReg);
227 if (DI != PeepholeDoubleRegsMap.end()) {
228 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
229 MI->RemoveOperand(1);
230 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
236 false /*isEarlyClobber*/,
237 PeepholeSrc.second));
243 // Look for Predicated instructions.
246 if (QII->isPredicated(MI)) {
247 MachineOperand &Op0 = MI->getOperand(0);
248 unsigned Reg0 = Op0.getReg();
249 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
250 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
251 // Handle instructions that have a prediate register in op0
252 // (most cases of predicable instructions).
253 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
254 // Try to find in the map.
255 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
256 // Change the 1st operand and, flip the opcode.
257 MI->getOperand(0).setReg(PeepholeSrc);
258 int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
259 MI->setDesc(QII->get(NewOp));
267 // Handle special instructions.
268 unsigned Op = MI->getOpcode();
270 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
273 case Hexagon::TFR_condset_rr:
274 case Hexagon::TFR_condset_ii:
275 case Hexagon::MUX_ii:
276 case Hexagon::MUX_rr:
279 case Hexagon::TFR_condset_ri:
280 NewOp = Hexagon::TFR_condset_ir;
282 case Hexagon::TFR_condset_ir:
283 NewOp = Hexagon::TFR_condset_ri;
285 case Hexagon::MUX_ri:
286 NewOp = Hexagon::MUX_ir;
288 case Hexagon::MUX_ir:
289 NewOp = Hexagon::MUX_ri;
293 unsigned PSrc = MI->getOperand(PR).getReg();
294 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
295 MI->getOperand(PR).setReg(POrig);
296 MI->setDesc(QII->get(NewOp));
297 // Swap operands S1 and S2.
298 MachineOperand Op1 = MI->getOperand(S1);
299 MachineOperand Op2 = MI->getOperand(S2);
300 ChangeOpInto(MI->getOperand(S1), Op2);
301 ChangeOpInto(MI->getOperand(S2), Op1);
306 } // if (!DisablePNotP)
313 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
314 assert (&Dst != &Src && "Cannot duplicate into itself");
315 switch (Dst.getType()) {
316 case MachineOperand::MO_Register:
318 Dst.setReg(Src.getReg());
319 } else if (Src.isImm()) {
320 Dst.ChangeToImmediate(Src.getImm());
322 llvm_unreachable("Unexpected src operand type");
326 case MachineOperand::MO_Immediate:
328 Dst.setImm(Src.getImm());
329 } else if (Src.isReg()) {
330 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
331 Src.isKill(), Src.isDead(), Src.isUndef(),
334 llvm_unreachable("Unexpected src operand type");
339 llvm_unreachable("Unexpected dst operand type");
344 FunctionPass *llvm::createHexagonPeephole() {
345 return new HexagonPeephole();