1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonMachineFunctionInfo.h"
20 #include "llvm/Function.h"
21 #include "llvm/Type.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/MC/MachineLocation.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
40 HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st,
41 const HexagonInstrInfo &tii)
42 : HexagonGenRegisterInfo(Hexagon::R31),
47 const uint16_t* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
50 static const uint16_t CalleeSavedRegsV2[] = {
51 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
53 static const uint16_t CalleeSavedRegsV3[] = {
54 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
55 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
56 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
59 switch(Subtarget.getHexagonArchVersion()) {
60 case HexagonSubtarget::V1:
62 case HexagonSubtarget::V2:
63 return CalleeSavedRegsV2;
64 case HexagonSubtarget::V3:
65 case HexagonSubtarget::V4:
66 case HexagonSubtarget::V5:
67 return CalleeSavedRegsV3;
69 llvm_unreachable("Callee saved registers requested for unknown architecture "
73 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
75 BitVector Reserved(getNumRegs());
76 Reserved.set(HEXAGON_RESERVED_REG_1);
77 Reserved.set(HEXAGON_RESERVED_REG_2);
78 Reserved.set(Hexagon::R29);
79 Reserved.set(Hexagon::R30);
80 Reserved.set(Hexagon::R31);
81 Reserved.set(Hexagon::D14);
82 Reserved.set(Hexagon::D15);
83 Reserved.set(Hexagon::LC0);
84 Reserved.set(Hexagon::LC1);
85 Reserved.set(Hexagon::SA0);
86 Reserved.set(Hexagon::SA1);
91 const TargetRegisterClass* const*
92 HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
93 static const TargetRegisterClass * const CalleeSavedRegClassesV2[] = {
94 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
95 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
97 static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
98 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
99 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
100 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
101 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
102 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
103 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
106 switch(Subtarget.getHexagonArchVersion()) {
107 case HexagonSubtarget::V1:
109 case HexagonSubtarget::V2:
110 return CalleeSavedRegClassesV2;
111 case HexagonSubtarget::V3:
112 case HexagonSubtarget::V4:
113 case HexagonSubtarget::V5:
114 return CalleeSavedRegClassesV3;
116 llvm_unreachable("Callee saved register classes requested for unknown "
117 "architecture version");
120 void HexagonRegisterInfo::
121 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator I) const {
123 MachineInstr &MI = *I;
125 if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) {
126 // Hexagon_TODO: add code
127 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
128 // Hexagon_TODO: add code
130 llvm_unreachable("Cannot handle this call frame pseudo instruction");
135 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
136 int SPAdj, RegScavenger *RS) const {
139 // Hexagon_TODO: Do we need to enforce this for Hexagon?
140 assert(SPAdj == 0 && "Unexpected");
144 MachineInstr &MI = *II;
145 while (!MI.getOperand(i).isFI()) {
147 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
150 int FrameIndex = MI.getOperand(i).getIndex();
152 // Addressable stack objects are accessed using neg. offsets from %fp.
153 MachineFunction &MF = *MI.getParent()->getParent();
154 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
155 MachineFrameInfo &MFI = *MF.getFrameInfo();
157 unsigned FrameReg = getFrameRegister(MF);
158 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
159 if (!TFI->hasFP(MF)) {
160 // We will not reserve space on the stack for the lr and fp registers.
161 Offset -= 2 * Hexagon_WordSize;
164 const unsigned FrameSize = MFI.getStackSize();
166 if (!MFI.hasVarSizedObjects() &&
167 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
168 !TII.isSpillPredRegOp(&MI)) {
169 // Replace frame index with a stack pointer reference.
170 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false, true);
171 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
173 // Replace frame index with a frame pointer reference.
174 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
176 // If the offset overflows, then correct it.
178 // For loads, we do not need a reserved register
179 // r0 = memw(r30 + #10000) to:
181 // r0 = add(r30, #10000)
183 if ( (MI.getOpcode() == Hexagon::LDriw) ||
184 (MI.getOpcode() == Hexagon::LDrid) ||
185 (MI.getOpcode() == Hexagon::LDrih) ||
186 (MI.getOpcode() == Hexagon::LDriuh) ||
187 (MI.getOpcode() == Hexagon::LDrib) ||
188 (MI.getOpcode() == Hexagon::LDriub) ||
189 (MI.getOpcode() == Hexagon::LDriw_f) ||
190 (MI.getOpcode() == Hexagon::LDrid_f)) {
191 unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ?
192 getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
193 MI.getOperand(0).getReg();
195 // Check if offset can fit in addi.
196 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
197 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
198 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
199 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
200 TII.get(Hexagon::ADD_rr),
201 dstReg).addReg(FrameReg).addReg(dstReg);
203 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
204 TII.get(Hexagon::ADD_ri),
205 dstReg).addReg(FrameReg).addImm(Offset);
208 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
209 MI.getOperand(i+1).ChangeToImmediate(0);
210 } else if ((MI.getOpcode() == Hexagon::STriw_indexed) ||
211 (MI.getOpcode() == Hexagon::STriw) ||
212 (MI.getOpcode() == Hexagon::STrid) ||
213 (MI.getOpcode() == Hexagon::STrih) ||
214 (MI.getOpcode() == Hexagon::STrib) ||
215 (MI.getOpcode() == Hexagon::STrid_f) ||
216 (MI.getOpcode() == Hexagon::STriw_f)) {
217 // For stores, we need a reserved register. Change
218 // memw(r30 + #10000) = r0 to:
220 // rs = add(r30, #10000);
222 unsigned resReg = HEXAGON_RESERVED_REG_1;
224 // Check if offset can fit in addi.
225 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
226 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
227 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
228 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
229 TII.get(Hexagon::ADD_rr),
230 resReg).addReg(FrameReg).addReg(resReg);
232 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
233 TII.get(Hexagon::ADD_ri),
234 resReg).addReg(FrameReg).addImm(Offset);
236 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
237 MI.getOperand(i+1).ChangeToImmediate(0);
238 } else if (TII.isMemOp(&MI)) {
239 unsigned resReg = HEXAGON_RESERVED_REG_1;
240 if (!MFI.hasVarSizedObjects() &&
241 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset))) {
242 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false,
244 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
245 } else if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
246 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
247 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
248 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
249 TII.get(Hexagon::ADD_rr),
250 resReg).addReg(FrameReg).addReg(resReg);
251 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
252 MI.getOperand(i+1).ChangeToImmediate(0);
254 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
255 TII.get(Hexagon::ADD_ri),
256 resReg).addReg(FrameReg).addImm(Offset);
257 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
258 MI.getOperand(i+1).ChangeToImmediate(0);
261 unsigned dstReg = MI.getOperand(0).getReg();
262 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
263 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
264 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
265 TII.get(Hexagon::ADD_rr),
266 dstReg).addReg(FrameReg).addReg(dstReg);
267 // Can we delete MI??? r2 = add (r2, #0).
268 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
269 MI.getOperand(i+1).ChangeToImmediate(0);
272 // If the offset is small enough to fit in the immediate field, directly
274 MI.getOperand(i).ChangeToRegister(FrameReg, false);
275 MI.getOperand(i+1).ChangeToImmediate(Offset);
281 unsigned HexagonRegisterInfo::getRARegister() const {
285 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
287 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
288 if (TFI->hasFP(MF)) {
295 unsigned HexagonRegisterInfo::getFrameRegister() const {
299 unsigned HexagonRegisterInfo::getStackRegister() const {
303 void HexagonRegisterInfo::getInitialFrameState(std::vector<MachineMove>
306 // VirtualFP = (R30 + #0).
307 unsigned FPReg = getFrameRegister();
308 MachineLocation Dst(MachineLocation::VirtualFP);
309 MachineLocation Src(FPReg, 0);
310 Moves.push_back(MachineMove(0, Dst, Src));
313 // Get the weight in units of pressure for this register class.
314 const RegClassWeight &
315 HexagonRegisterInfo::getRegClassWeight(const TargetRegisterClass *RC) const {
316 // Each TargetRegisterClass has a per register weight, and weight
317 // limit which must be less than the limits of its pressure sets.
318 static const RegClassWeight RCWeightTable[] = {
322 {2, 16}, // DoubleRegs
324 return RCWeightTable[RC->getID()];
327 /// Get the number of dimensions of register pressure.
328 unsigned HexagonRegisterInfo::getNumRegPressureSets() const {
332 /// Get the name of this register unit pressure set.
333 const char *HexagonRegisterInfo::getRegPressureSetName(unsigned Idx) const {
334 static const char *const RegPressureSetName[] = {
340 assert((Idx < 4) && "Index out of bounds");
341 return RegPressureSetName[Idx];
344 /// Get the register unit pressure limit for this dimension.
345 /// This limit must be adjusted dynamically for reserved registers.
346 unsigned HexagonRegisterInfo::getRegPressureSetLimit(unsigned Idx) const {
347 static const int RegPressureLimit [] = { 16, 4, 2, 8 };
348 assert((Idx < 4) && "Index out of bounds");
349 return RegPressureLimit[Idx];
353 HexagonRegisterInfo::getRegClassPressureSets(const TargetRegisterClass *RC)
355 static const int RCSetsTable[] = {
361 static const unsigned RCSetStartTable[] = { 0, 2, 4, 6, 0 };
362 unsigned SetListStart = RCSetStartTable[RC->getID()];
363 return &RCSetsTable[SetListStart];
365 unsigned HexagonRegisterInfo::getEHExceptionRegister() const {
366 llvm_unreachable("What is the exception register");
369 unsigned HexagonRegisterInfo::getEHHandlerRegister() const {
370 llvm_unreachable("What is the exception handler register");
373 #define GET_REGINFO_TARGET_DESC
374 #include "HexagonGenRegisterInfo.inc"