1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "HexagonRegisterInfo.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
41 HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st)
42 : HexagonGenRegisterInfo(Hexagon::R31),
47 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
48 static const MCPhysReg CalleeSavedRegsV3[] = {
49 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
50 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
51 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
54 switch(Subtarget.getHexagonArchVersion()) {
55 case HexagonSubtarget::V4:
56 case HexagonSubtarget::V5:
57 return CalleeSavedRegsV3;
59 llvm_unreachable("Callee saved registers requested for unknown architecture "
63 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
65 BitVector Reserved(getNumRegs());
66 Reserved.set(HEXAGON_RESERVED_REG_1);
67 Reserved.set(HEXAGON_RESERVED_REG_2);
68 Reserved.set(Hexagon::R29);
69 Reserved.set(Hexagon::R30);
70 Reserved.set(Hexagon::R31);
71 Reserved.set(Hexagon::D14);
72 Reserved.set(Hexagon::D15);
73 Reserved.set(Hexagon::LC0);
74 Reserved.set(Hexagon::LC1);
75 Reserved.set(Hexagon::SA0);
76 Reserved.set(Hexagon::SA1);
81 const TargetRegisterClass* const*
82 HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
83 static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
84 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
85 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
86 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
87 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
88 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
89 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
92 switch(Subtarget.getHexagonArchVersion()) {
93 case HexagonSubtarget::V4:
94 case HexagonSubtarget::V5:
95 return CalleeSavedRegClassesV3;
97 llvm_unreachable("Callee saved register classes requested for unknown "
98 "architecture version");
101 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
102 int SPAdj, unsigned FIOperandNum,
103 RegScavenger *RS) const {
105 // Hexagon_TODO: Do we need to enforce this for Hexagon?
106 assert(SPAdj == 0 && "Unexpected");
108 MachineInstr &MI = *II;
109 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
111 // Addressable stack objects are accessed using neg. offsets from %fp.
112 MachineFunction &MF = *MI.getParent()->getParent();
113 const HexagonInstrInfo &TII =
114 *static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
115 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
116 MachineFrameInfo &MFI = *MF.getFrameInfo();
118 unsigned FrameReg = getFrameRegister(MF);
119 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
120 if (!TFI->hasFP(MF)) {
121 // We will not reserve space on the stack for the lr and fp registers.
122 Offset -= 2 * Hexagon_WordSize;
125 const unsigned FrameSize = MFI.getStackSize();
127 if (!MFI.hasVarSizedObjects() &&
128 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
129 !TII.isSpillPredRegOp(&MI)) {
130 // Replace frame index with a stack pointer reference.
131 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
133 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
135 // Replace frame index with a frame pointer reference.
136 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
138 // If the offset overflows, then correct it.
140 // For loads, we do not need a reserved register
141 // r0 = memw(r30 + #10000) to:
143 // r0 = add(r30, #10000)
145 if ( (MI.getOpcode() == Hexagon::L2_loadri_io) ||
146 (MI.getOpcode() == Hexagon::L2_loadrd_io) ||
147 (MI.getOpcode() == Hexagon::L2_loadrh_io) ||
148 (MI.getOpcode() == Hexagon::L2_loadruh_io) ||
149 (MI.getOpcode() == Hexagon::L2_loadrb_io) ||
150 (MI.getOpcode() == Hexagon::L2_loadrub_io)) {
151 unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
152 getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
153 MI.getOperand(0).getReg();
155 // Check if offset can fit in addi.
156 if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
157 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
158 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
159 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
160 TII.get(Hexagon::A2_add),
161 dstReg).addReg(FrameReg).addReg(dstReg);
163 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
164 TII.get(Hexagon::A2_addi),
165 dstReg).addReg(FrameReg).addImm(Offset);
168 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
169 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
170 } else if ((MI.getOpcode() == Hexagon::S2_storeri_io) ||
171 (MI.getOpcode() == Hexagon::S2_storerd_io) ||
172 (MI.getOpcode() == Hexagon::S2_storerh_io) ||
173 (MI.getOpcode() == Hexagon::S2_storerb_io)) {
174 // For stores, we need a reserved register. Change
175 // memw(r30 + #10000) = r0 to:
177 // rs = add(r30, #10000);
179 unsigned resReg = HEXAGON_RESERVED_REG_1;
181 // Check if offset can fit in addi.
182 if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
183 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
184 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
185 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
186 TII.get(Hexagon::A2_add),
187 resReg).addReg(FrameReg).addReg(resReg);
189 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
190 TII.get(Hexagon::A2_addi),
191 resReg).addReg(FrameReg).addImm(Offset);
193 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
194 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
195 } else if (TII.isMemOp(&MI)) {
196 // use the constant extender if the instruction provides it
197 if (TII.isConstExtended(&MI)) {
198 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
199 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
200 TII.immediateExtend(&MI);
202 llvm_unreachable("Need to implement for memops");
205 unsigned dstReg = MI.getOperand(0).getReg();
206 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
207 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
208 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
209 TII.get(Hexagon::A2_add),
210 dstReg).addReg(FrameReg).addReg(dstReg);
211 // Can we delete MI??? r2 = add (r2, #0).
212 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
213 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
216 // If the offset is small enough to fit in the immediate field, directly
218 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
219 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
225 unsigned HexagonRegisterInfo::getRARegister() const {
229 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
231 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
232 if (TFI->hasFP(MF)) {
239 unsigned HexagonRegisterInfo::getFrameRegister() const {
243 unsigned HexagonRegisterInfo::getStackRegister() const {
247 #define GET_REGINFO_TARGET_DESC
248 #include "HexagonGenRegisterInfo.inc"